From 829b1b1cc0a7dced1946500c1f27b4a7277ddb26 Mon Sep 17 00:00:00 2001 From: gdkchan <gab.dark.100@gmail.com> Date: Fri, 2 Mar 2018 20:03:28 -0300 Subject: [PATCH] Add REV64 (vector) instruction --- ChocolArm64/AOpCodeTable.cs | 1 + ChocolArm64/Instruction/AInstEmitSimdLogical.cs | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index 470b70e04e..13df4d9868 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -230,6 +230,7 @@ namespace ChocolArm64 Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd)); Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg)); Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm)); + Set("0x001110xx100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd)); Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg)); Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt)); Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd)); diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs index ea4b17b3da..f4cc66cf68 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs @@ -1,4 +1,5 @@ using ChocolArm64.Translation; +using System; using System.Reflection.Emit; using static ChocolArm64.Instruction.AInstEmitSimdHelper; @@ -65,5 +66,15 @@ namespace ChocolArm64.Instruction { EmitVectorImmBinaryOp(Context, () => Context.Emit(OpCodes.Or)); } + + public static void Rev64_V(AILEmitterCtx Context) + { + Action Emit = () => + { + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits64)); + }; + + EmitVectorUnaryOpZx(Context, Emit); + } } } \ No newline at end of file