diff --git a/ARMeilleure/Decoders/Block.cs b/ARMeilleure/Decoders/Block.cs
index ef0517c006..9d380bca6b 100644
--- a/ARMeilleure/Decoders/Block.cs
+++ b/ARMeilleure/Decoders/Block.cs
@@ -14,7 +14,7 @@ namespace ARMeilleure.Decoders
         public bool TailCall { get; set; }
         public bool Exit     { get; set; }
 
-        public List<OpCode> OpCodes { get; private set; }
+        public List<OpCode> OpCodes { get; }
 
         public Block()
         {
diff --git a/ARMeilleure/Decoders/Decoder.cs b/ARMeilleure/Decoders/Decoder.cs
index 9ec95ab691..8666cdccc2 100644
--- a/ARMeilleure/Decoders/Decoder.cs
+++ b/ARMeilleure/Decoders/Decoder.cs
@@ -339,7 +339,7 @@ namespace ARMeilleure.Decoders
 
             if (makeOp != null)
             {
-                return (OpCode)makeOp(inst, address, opCode);
+                return makeOp(inst, address, opCode);
             }
             else
             {
diff --git a/ARMeilleure/Decoders/OpCode.cs b/ARMeilleure/Decoders/OpCode.cs
index 0bfc2456bc..e0b14e662e 100644
--- a/ARMeilleure/Decoders/OpCode.cs
+++ b/ARMeilleure/Decoders/OpCode.cs
@@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCode : IOpCode
     {
-        public ulong Address   { get; private set; }
-        public int   RawOpCode { get; private set; }
+        public ulong Address   { get; }
+        public int   RawOpCode { get; }
 
         public int OpCodeSizeInBytes { get; protected set; } = 4;
 
@@ -14,6 +14,8 @@ namespace ARMeilleure.Decoders
 
         public RegisterSize RegisterSize { get; protected set; }
 
+        public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
+
         public OpCode(InstDescriptor inst, ulong address, int opCode)
         {
             Address   = address;
diff --git a/ARMeilleure/Decoders/OpCode32.cs b/ARMeilleure/Decoders/OpCode32.cs
index 20927d5e4f..0d8ad1fdb6 100644
--- a/ARMeilleure/Decoders/OpCode32.cs
+++ b/ARMeilleure/Decoders/OpCode32.cs
@@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
     {
         public Condition Cond { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32(inst, address, opCode);
+
         public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             RegisterSize = RegisterSize.Int32;
diff --git a/ARMeilleure/Decoders/OpCode32Alu.cs b/ARMeilleure/Decoders/OpCode32Alu.cs
index 8d03baddb8..6c7723bb8e 100644
--- a/ARMeilleure/Decoders/OpCode32Alu.cs
+++ b/ARMeilleure/Decoders/OpCode32Alu.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32Alu : OpCode32, IOpCode32Alu
     {
-        public int Rd { get; private set; }
-        public int Rn { get; private set; }
+        public int Rd { get; }
+        public int Rn { get; }
 
-        public bool SetFlags { get; private set; }
+        public bool SetFlags { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode);
 
         public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluBf.cs b/ARMeilleure/Decoders/OpCode32AluBf.cs
index 7ee0ee34eb..f8dc6db0d4 100644
--- a/ARMeilleure/Decoders/OpCode32AluBf.cs
+++ b/ARMeilleure/Decoders/OpCode32AluBf.cs
@@ -2,16 +2,18 @@
 {
     class OpCode32AluBf : OpCode32, IOpCode32AluBf
     {
-        public int Rd { get; private set; }
-        public int Rn { get; private set; }
+        public int Rd { get; }
+        public int Rn { get; }
 
-        public int Msb { get; private set; }
+        public int Msb { get; }
 
-        public int Lsb { get; private set; }
+        public int Lsb { get; }
 
         public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
         public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode);
+
         public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rd = (opCode >> 12) & 0xf;
diff --git a/ARMeilleure/Decoders/OpCode32AluImm.cs b/ARMeilleure/Decoders/OpCode32AluImm.cs
index bba03e4d8c..9d82db4b9a 100644
--- a/ARMeilleure/Decoders/OpCode32AluImm.cs
+++ b/ARMeilleure/Decoders/OpCode32AluImm.cs
@@ -4,9 +4,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32AluImm : OpCode32Alu
     {
-        public int Immediate { get; private set; }
+        public int Immediate { get; }
 
-        public bool IsRotated { get; private set; }
+        public bool IsRotated { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm(inst, address, opCode);
 
         public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluImm16.cs b/ARMeilleure/Decoders/OpCode32AluImm16.cs
index dbc02932a8..662482719c 100644
--- a/ARMeilleure/Decoders/OpCode32AluImm16.cs
+++ b/ARMeilleure/Decoders/OpCode32AluImm16.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32AluImm16 : OpCode32Alu
     {
-        public int Immediate { get; private set; }
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm16(inst, address, opCode);
 
         public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluMla.cs b/ARMeilleure/Decoders/OpCode32AluMla.cs
index 4570aa4e2a..4e9b25e39c 100644
--- a/ARMeilleure/Decoders/OpCode32AluMla.cs
+++ b/ARMeilleure/Decoders/OpCode32AluMla.cs
@@ -2,15 +2,17 @@
 {
     class OpCode32AluMla : OpCode32, IOpCode32AluReg
     {
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
-        public int Ra { get; private set; }
-        public int Rd { get; private set; }
+        public int Rn { get; }
+        public int Rm { get; }
+        public int Ra { get; }
+        public int Rd { get; }
 
-        public bool NHigh { get; private set; }
-        public bool MHigh { get; private set; }
-        public bool R { get; private set; }
-        public bool SetFlags { get; private set; }
+        public bool NHigh { get; }
+        public bool MHigh { get; }
+        public bool R { get; }
+        public bool SetFlags { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode);
 
         public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluReg.cs b/ARMeilleure/Decoders/OpCode32AluReg.cs
index e378dd05d7..493a977f07 100644
--- a/ARMeilleure/Decoders/OpCode32AluReg.cs
+++ b/ARMeilleure/Decoders/OpCode32AluReg.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32AluReg : OpCode32Alu, IOpCode32AluReg
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluReg(inst, address, opCode);
 
         public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluRsImm.cs b/ARMeilleure/Decoders/OpCode32AluRsImm.cs
index 68ca0d0cbe..f24e77577a 100644
--- a/ARMeilleure/Decoders/OpCode32AluRsImm.cs
+++ b/ARMeilleure/Decoders/OpCode32AluRsImm.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32AluRsImm : OpCode32Alu
     {
-        public int Rm        { get; private set; }
-        public int Immediate { get; private set; }
+        public int Rm        { get; }
+        public int Immediate { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsImm(inst, address, opCode);
 
         public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluRsReg.cs b/ARMeilleure/Decoders/OpCode32AluRsReg.cs
index d195987bf8..574588f80f 100644
--- a/ARMeilleure/Decoders/OpCode32AluRsReg.cs
+++ b/ARMeilleure/Decoders/OpCode32AluRsReg.cs
@@ -2,10 +2,12 @@
 {
     class OpCode32AluRsReg : OpCode32Alu
     {
-        public int Rm { get; private set; }
-        public int Rs { get; private set; }
+        public int Rm { get; }
+        public int Rs { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsReg(inst, address, opCode);
 
         public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluUmull.cs b/ARMeilleure/Decoders/OpCode32AluUmull.cs
index c98d9305b4..e4f0895be0 100644
--- a/ARMeilleure/Decoders/OpCode32AluUmull.cs
+++ b/ARMeilleure/Decoders/OpCode32AluUmull.cs
@@ -2,16 +2,18 @@
 {
     class OpCode32AluUmull : OpCode32
     {
-        public int RdLo { get; private set; }
-        public int RdHi { get; private set; }
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
+        public int RdLo { get; }
+        public int RdHi { get; }
+        public int Rn { get; }
+        public int Rm { get; }
 
-        public bool NHigh { get; private set; }
-        public bool MHigh { get; private set; }
+        public bool NHigh { get; }
+        public bool MHigh { get; }
 
-        public bool SetFlags { get; private set; }
-        public DataOp DataOp { get; private set; }
+        public bool SetFlags { get; }
+        public DataOp DataOp { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
 
         public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32AluUx.cs b/ARMeilleure/Decoders/OpCode32AluUx.cs
index 55c10209de..57068675df 100644
--- a/ARMeilleure/Decoders/OpCode32AluUx.cs
+++ b/ARMeilleure/Decoders/OpCode32AluUx.cs
@@ -4,10 +4,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32AluUx : OpCode32AluReg, IOpCode32AluUx
     {
-        public int Rotate { get; private set; }
+        public int Rotate { get; }
         public int RotateBits => Rotate * 8;
         public bool Add => Rn != RegisterAlias.Aarch32Pc;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUx(inst, address, opCode);
+
         public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rotate = (opCode >> 10) & 0x3;
diff --git a/ARMeilleure/Decoders/OpCode32BImm.cs b/ARMeilleure/Decoders/OpCode32BImm.cs
index ea6443bc80..f2959b3315 100644
--- a/ARMeilleure/Decoders/OpCode32BImm.cs
+++ b/ARMeilleure/Decoders/OpCode32BImm.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32BImm : OpCode32, IOpCode32BImm
     {
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BImm(inst, address, opCode);
 
         public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32BReg.cs b/ARMeilleure/Decoders/OpCode32BReg.cs
index ffb4870704..d4f5f7601f 100644
--- a/ARMeilleure/Decoders/OpCode32BReg.cs
+++ b/ARMeilleure/Decoders/OpCode32BReg.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32BReg : OpCode32, IOpCode32BReg
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BReg(inst, address, opCode);
 
         public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32Exception.cs b/ARMeilleure/Decoders/OpCode32Exception.cs
index 1acdf5b122..e963be6433 100644
--- a/ARMeilleure/Decoders/OpCode32Exception.cs
+++ b/ARMeilleure/Decoders/OpCode32Exception.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32Exception : OpCode32
     {
-        public int Id { get; private set; }
+        public int Id { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Exception(inst, address, opCode);
 
         public OpCode32Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32Mem.cs b/ARMeilleure/Decoders/OpCode32Mem.cs
index b749f3dbe5..ceb1e49f5f 100644
--- a/ARMeilleure/Decoders/OpCode32Mem.cs
+++ b/ARMeilleure/Decoders/OpCode32Mem.cs
@@ -5,16 +5,18 @@ namespace ARMeilleure.Decoders
     class OpCode32Mem : OpCode32, IOpCode32Mem
     {
         public int Rt { get; protected set; }
-        public int Rn { get; private set; }
+        public int Rn { get; }
 
         public int Immediate { get; protected set; }
 
-        public bool Index        { get; private set; }
-        public bool Add          { get; private set; }
-        public bool WBack        { get; private set; }
-        public bool Unprivileged { get; private set; }
+        public bool Index        { get; }
+        public bool Add          { get; }
+        public bool WBack        { get; }
+        public bool Unprivileged { get; }
 
-        public bool IsLoad { get; private set; }
+        public bool IsLoad { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mem(inst, address, opCode);
 
         public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32MemImm.cs b/ARMeilleure/Decoders/OpCode32MemImm.cs
index f79c63197c..3af4b6f7c6 100644
--- a/ARMeilleure/Decoders/OpCode32MemImm.cs
+++ b/ARMeilleure/Decoders/OpCode32MemImm.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32MemImm : OpCode32Mem
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm(inst, address, opCode);
+
         public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Immediate = opCode & 0xfff;
diff --git a/ARMeilleure/Decoders/OpCode32MemImm8.cs b/ARMeilleure/Decoders/OpCode32MemImm8.cs
index 08027fb758..1b8a57de47 100644
--- a/ARMeilleure/Decoders/OpCode32MemImm8.cs
+++ b/ARMeilleure/Decoders/OpCode32MemImm8.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32MemImm8 : OpCode32Mem
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm8(inst, address, opCode);
+
         public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             int imm4L = (opCode >> 0) & 0xf;
diff --git a/ARMeilleure/Decoders/OpCode32MemLdEx.cs b/ARMeilleure/Decoders/OpCode32MemLdEx.cs
index 42d1a33a02..520113f463 100644
--- a/ARMeilleure/Decoders/OpCode32MemLdEx.cs
+++ b/ARMeilleure/Decoders/OpCode32MemLdEx.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32MemLdEx : OpCode32Mem, IOpCode32MemEx
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemLdEx(inst, address, opCode);
 
         public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32MemMult.cs b/ARMeilleure/Decoders/OpCode32MemMult.cs
index b61b50ea83..cc726196d5 100644
--- a/ARMeilleure/Decoders/OpCode32MemMult.cs
+++ b/ARMeilleure/Decoders/OpCode32MemMult.cs
@@ -2,13 +2,15 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32MemMult : OpCode32, IOpCode32MemMult
     {
-        public int Rn { get; private set; }
+        public int Rn { get; }
 
-        public int RegisterMask { get; private set; }
-        public int Offset       { get; private set; }
-        public int PostOffset   { get; private set; }
+        public int RegisterMask { get; }
+        public int Offset       { get; }
+        public int PostOffset   { get; }
 
-        public bool IsLoad { get; private set; }
+        public bool IsLoad { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemMult(inst, address, opCode);
 
         public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32MemReg.cs b/ARMeilleure/Decoders/OpCode32MemReg.cs
index ccc05a875e..c9434399c6 100644
--- a/ARMeilleure/Decoders/OpCode32MemReg.cs
+++ b/ARMeilleure/Decoders/OpCode32MemReg.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32MemReg : OpCode32Mem
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemReg(inst, address, opCode);
 
         public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32MemRsImm.cs b/ARMeilleure/Decoders/OpCode32MemRsImm.cs
index 299e83e2c5..dc5f0fd357 100644
--- a/ARMeilleure/Decoders/OpCode32MemRsImm.cs
+++ b/ARMeilleure/Decoders/OpCode32MemRsImm.cs
@@ -2,8 +2,10 @@
 {
     class OpCode32MemRsImm : OpCode32Mem
     {
-        public int Rm { get; private set; }
-        public ShiftType ShiftType { get; private set; }
+        public int Rm { get; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemRsImm(inst, address, opCode);
 
         public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32MemStEx.cs b/ARMeilleure/Decoders/OpCode32MemStEx.cs
index b9c6d4f4ff..dcf93b2244 100644
--- a/ARMeilleure/Decoders/OpCode32MemStEx.cs
+++ b/ARMeilleure/Decoders/OpCode32MemStEx.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32MemStEx : OpCode32Mem, IOpCode32MemEx
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemStEx(inst, address, opCode);
 
         public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32Sat.cs b/ARMeilleure/Decoders/OpCode32Sat.cs
index b5ddab32d4..621def27c0 100644
--- a/ARMeilleure/Decoders/OpCode32Sat.cs
+++ b/ARMeilleure/Decoders/OpCode32Sat.cs
@@ -2,12 +2,14 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32Sat : OpCode32
     {
-        public int Rn { get; private set; }
-        public int Imm5 { get; private set; }
-        public int Rd { get; private set; }
-        public int SatImm { get; private set; }
+        public int Rn { get; }
+        public int Imm5 { get; }
+        public int Rd { get; }
+        public int SatImm { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat(inst, address, opCode);
 
         public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32Sat16.cs b/ARMeilleure/Decoders/OpCode32Sat16.cs
index c25f6ceee9..51061b0794 100644
--- a/ARMeilleure/Decoders/OpCode32Sat16.cs
+++ b/ARMeilleure/Decoders/OpCode32Sat16.cs
@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32Sat16 : OpCode32
     {
-        public int Rn { get; private set; }
-        public int Rd { get; private set; }
-        public int SatImm { get; private set; }
+        public int Rn { get; }
+        public int Rd { get; }
+        public int SatImm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat16(inst, address, opCode);
 
         public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32Simd.cs b/ARMeilleure/Decoders/OpCode32Simd.cs
index cda10c3c8f..51f3905616 100644
--- a/ARMeilleure/Decoders/OpCode32Simd.cs
+++ b/ARMeilleure/Decoders/OpCode32Simd.cs
@@ -5,7 +5,9 @@
         public int Opc { get; protected set; }
         public bool Q { get; protected set; }
         public bool F { get; protected set; }
-        public bool U { get; private set; }
+        public bool U { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode);
 
         public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdBase.cs b/ARMeilleure/Decoders/OpCode32SimdBase.cs
index 10b5465978..183378b977 100644
--- a/ARMeilleure/Decoders/OpCode32SimdBase.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdBase.cs
@@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders
 
         // Helpers to index doublewords within quad words. Essentially, looping over the vector starts at quadword Q and index Fx or Ix within it,
         // depending on instruction type.
-        // 
+        //
         // Qx: The quadword register that the target vector is contained in.
         // Ix: The starting index of the target vector within the quadword, with size treated as integer.
         // Fx: The starting index of the target vector within the quadword, with size treated as floating point. (16 or 32)
diff --git a/ARMeilleure/Decoders/OpCode32SimdBinary.cs b/ARMeilleure/Decoders/OpCode32SimdBinary.cs
index 66f63dc5a4..72347b94c7 100644
--- a/ARMeilleure/Decoders/OpCode32SimdBinary.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdBinary.cs
@@ -5,6 +5,8 @@
     /// </summary>
     class OpCode32SimdBinary : OpCode32SimdReg
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode);
+
         public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = 3;
diff --git a/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs b/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
index 567147fbe5..c3c295a554 100644
--- a/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdCmpZ : OpCode32Simd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode);
+
         public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = (opCode >> 18) & 0x3;
diff --git a/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs b/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
index b654a1926f..30725eba79 100644
--- a/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdCvtFI : OpCode32SimdS
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode);
+
         public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Opc = (opCode >> 7) & 0x1;
diff --git a/ARMeilleure/Decoders/OpCode32SimdDupElem.cs b/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
index fd83aee5f8..9918d7a84b 100644
--- a/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdDupElem : OpCode32Simd
     {
-        public int Index { get; private set; }
+        public int Index { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode);
 
         public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdDupGP.cs b/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
index 58a8a7fe32..2aef836f6c 100644
--- a/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
@@ -2,10 +2,12 @@
 {
     class OpCode32SimdDupGP : OpCode32, IOpCode32Simd
     {
-        public int Size { get; private set; }
-        public int Vd { get; private set; }
-        public int Rt { get; private set; }
-        public bool Q { get; private set; }
+        public int Size { get; }
+        public int Vd { get; }
+        public int Rt { get; }
+        public bool Q { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode);
 
         public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdExt.cs b/ARMeilleure/Decoders/OpCode32SimdExt.cs
index 1ee0485ee3..cdb305df83 100644
--- a/ARMeilleure/Decoders/OpCode32SimdExt.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdExt.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdExt : OpCode32SimdReg
     {
-        public int Immediate { get; private set; }
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode);
 
         public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdImm.cs b/ARMeilleure/Decoders/OpCode32SimdImm.cs
index c6ae7ec59c..678f306463 100644
--- a/ARMeilleure/Decoders/OpCode32SimdImm.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdImm.cs
@@ -2,15 +2,17 @@
 {
     class OpCode32SimdImm : OpCode32SimdBase, IOpCode32SimdImm
     {
-        public bool Q { get; private set; }
-        public long Immediate { get; private set; }
+        public bool Q { get; }
+        public long Immediate { get; }
         public int Elems => GetBytesCount() >> Size;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode);
+
         public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Vd = (opCode >> 12) & 0xf;
             Vd |= (opCode >> 18) & 0x10;
-            
+
             Q = ((opCode >> 6) & 0x1) > 0;
 
             int cMode = (opCode >> 8) & 0xf;
diff --git a/ARMeilleure/Decoders/OpCode32SimdImm44.cs b/ARMeilleure/Decoders/OpCode32SimdImm44.cs
index f8f73bbba1..a2be6e6486 100644
--- a/ARMeilleure/Decoders/OpCode32SimdImm44.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdImm44.cs
@@ -2,17 +2,19 @@
 {
     class OpCode32SimdImm44 : OpCode32, IOpCode32SimdImm
     {
-        public int Vd { get; private set; }
-        public long Immediate { get; private set; }
-        public int Size { get; private set; }
-        public int Elems { get; private set; }
+        public int Vd { get; }
+        public long Immediate { get; }
+        public int Size { get; }
+        public int Elems { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
 
         public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = (opCode >> 8) & 0x3;
 
             bool single = Size != 3;
-            
+
             if (single)
             {
                 Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e);
diff --git a/ARMeilleure/Decoders/OpCode32SimdLong.cs b/ARMeilleure/Decoders/OpCode32SimdLong.cs
index c4b186832b..9cde8fffd5 100644
--- a/ARMeilleure/Decoders/OpCode32SimdLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdLong.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdLong : OpCode32SimdBase
     {
-        public bool U { get; private set; }
+        public bool U { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode);
 
         public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdMemImm.cs b/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
index 630566cc3f..8a163f090c 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
@@ -2,11 +2,13 @@
 {
     class OpCode32SimdMemImm : OpCode32, IOpCode32Simd
     {
-        public int Vd { get; private set; }
-        public int Rn { get; private set; }
-        public int Size { get; private set; }
-        public bool Add { get; private set; }
-        public int Immediate { get; private set; }
+        public int Vd { get; }
+        public int Rn { get; }
+        public int Size { get; }
+        public bool Add { get; }
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode);
 
         public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdMemMult.cs b/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
index 9d43a71eb2..33caf09264 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
@@ -2,15 +2,17 @@
 {
     class OpCode32SimdMemMult : OpCode32
     {
-        public int Rn { get; private set; }
-        public int Vd { get; private set; }
+        public int Rn { get; }
+        public int Vd { get; }
 
-        public int RegisterRange { get; private set; }
-        public int Offset { get; private set; }
-        public int PostOffset { get; private set; }
-        public bool IsLoad { get; private set; }
-        public bool DoubleWidth { get; private set; }
-        public bool Add { get; private set; }
+        public int RegisterRange { get; }
+        public int Offset { get; }
+        public int PostOffset { get; }
+        public bool IsLoad { get; }
+        public bool DoubleWidth { get; }
+        public bool Add { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
 
         public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdMemPair.cs b/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
index 93320e7f95..4cee05e826 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
@@ -10,19 +10,21 @@ namespace ARMeilleure.Decoders
             1, 1, 4, 2,
             1, 1, 3, 1,
             1, 1, 2, 1,
-            1, 1, 1, 1 
+            1, 1, 1, 1
         };
 
-        public int Vd { get; private set; }
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
-        public int Align { get; private set; }
-        public bool WBack { get; private set; }
-        public bool RegisterIndex { get; private set; }
-        public int Size { get; private set; }
+        public int Vd { get; }
+        public int Rn { get; }
+        public int Rm { get; }
+        public int Align { get; }
+        public bool WBack { get; }
+        public bool RegisterIndex { get; }
+        public int Size { get; }
         public int Elems => 8 >> Size;
-        public int Regs { get; private set; }
-        public int Increment { get; private set; }
+        public int Regs { get; }
+        public int Increment { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode);
 
         public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs b/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
index 8cdd374366..e90c222719 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
@@ -4,16 +4,18 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32SimdMemSingle : OpCode32, IOpCode32Simd
     {
-        public int Vd { get; private set; }
-        public int Rn { get; private set; }
-        public int Rm { get; private set; }
-        public int IndexAlign { get; private set; }
-        public int Index { get; private set; }
-        public bool WBack { get; private set; }
-        public bool RegisterIndex { get; private set; }
-        public int Size { get; private set; }
-        public bool Replicate { get; private set; }
-        public int Increment { get; private set; }
+        public int Vd { get; }
+        public int Rn { get; }
+        public int Rm { get; }
+        public int IndexAlign { get; }
+        public int Index { get; }
+        public bool WBack { get; }
+        public bool RegisterIndex { get; }
+        public int Size { get; }
+        public bool Replicate { get; }
+        public int Increment { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode);
 
         public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
@@ -29,8 +31,8 @@ namespace ARMeilleure.Decoders
                 Size = (opCode >> 6) & 0x3;
                 Increment = ((opCode >> 5) & 1) + 1;
                 Index = 0;
-            } 
-            else 
+            }
+            else
             {
                 Increment = (((IndexAlign >> Size) & 1) == 0) ? 1 : 2;
                 Index = IndexAlign >> (1 + Size);
diff --git a/ARMeilleure/Decoders/OpCode32SimdMovGp.cs b/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
index 918291a174..8e2c84fb63 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
@@ -4,12 +4,14 @@
     {
         public int Size => 2;
 
-        public int Vn { get; private set; }
-        public int Rt { get; private set; }
-        public int Op { get; private set; }
+        public int Vn { get; }
+        public int Rt { get; }
+        public int Op { get; }
 
-        public int Opc1 { get; private set; }
-        public int Opc2 { get; private set; }
+        public int Opc1 { get; }
+        public int Opc2 { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode);
 
         public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs b/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
index 5f2725e15e..dc89b719bc 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
@@ -4,16 +4,18 @@
     {
         public int Size => 3;
 
-        public int Vm { get; private set; }
-        public int Rt { get; private set; }
-        public int Rt2 { get; private set; }
-        public int Op { get; private set; }
+        public int Vm { get; }
+        public int Rt { get; }
+        public int Rt2 { get; }
+        public int Op { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode);
 
         public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             // Which one is used is instruction dependant.
             Op = (opCode >> 20) & 0x1;
-            
+
             Rt = (opCode >> 12) & 0xf;
             Rt2 = (opCode >> 16) & 0xf;
 
@@ -21,7 +23,7 @@
             if (single)
             {
                 Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
-            } 
+            }
             else
             {
                 Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);
diff --git a/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs b/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
index 350d5c8467..56e46413e0 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
@@ -2,14 +2,16 @@
 {
     class OpCode32SimdMovGpElem : OpCode32, IOpCode32Simd
     {
-        public int Size { get; private set; }
+        public int Size { get; }
 
-        public int Vd { get; private set; }
-        public int Rt { get; private set; }
-        public int Op { get; private set; }
-        public bool U { get; private set; }
+        public int Vd { get; }
+        public int Rt { get; }
+        public int Op { get; }
+        public bool U { get; }
 
-        public int Index { get; private set; }
+        public int Index { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode);
 
         public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
@@ -22,7 +24,7 @@
             {
                 Size = 0;
                 Index = opc & 0x7;
-            } 
+            }
             else if ((opc & 0b01001) == 0b00001)
             {
                 Size = 1;
@@ -32,7 +34,7 @@
             {
                 Size = 2;
                 Index = (opc >> 2) & 0x1;
-            } 
+            }
             else
             {
                 Instruction = InstDescriptor.Undefined;
diff --git a/ARMeilleure/Decoders/OpCode32SimdReg.cs b/ARMeilleure/Decoders/OpCode32SimdReg.cs
index da1d2e363f..50d1d24d58 100644
--- a/ARMeilleure/Decoders/OpCode32SimdReg.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdReg.cs
@@ -2,12 +2,14 @@
 {
     class OpCode32SimdReg : OpCode32Simd
     {
-        public int Vn { get; private set; }
+        public int Vn { get; }
 
         public int Qn => GetQuadwordIndex(Vn);
         public int In => GetQuadwordSubindex(Vn) << (3 - Size);
         public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode);
+
         public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
index c3b912b124..0802a17b77 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRegElem : OpCode32SimdReg
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode);
+
         public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Q = ((opCode >> 24) & 0x1) != 0;
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
index 26f86f34d7..e3ffed7d1e 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRegElemLong : OpCode32SimdRegElem
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode);
+
         public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Q = false;
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
index 144824b312..c8ca9b498d 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdRegLong : OpCode32SimdReg
     {
-        public bool Polynomial { get; private set; }
+        public bool Polynomial { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode);
 
         public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegS.cs b/ARMeilleure/Decoders/OpCode32SimdRegS.cs
index b4ffad80a2..07dffb4fc1 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegS.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegS.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdRegS : OpCode32SimdS
     {
-        public int Vn { get; private set; }
+        public int Vn { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode);
 
         public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
@@ -10,7 +12,7 @@
             if (single)
             {
                 Vn = ((opCode >> 7) & 0x1) | ((opCode >> 15) & 0x1e);
-            } 
+            }
             else
             {
                 Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
index 93ef69496f..9a3993faee 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRegWide : OpCode32SimdReg
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode);
+
         public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Q = false;
diff --git a/ARMeilleure/Decoders/OpCode32SimdRev.cs b/ARMeilleure/Decoders/OpCode32SimdRev.cs
index 547766a83c..88b45c7d7a 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRev.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRev.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdRev : OpCode32SimdCmpZ
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode);
+
         public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             if (Opc + Size >= 3)
diff --git a/ARMeilleure/Decoders/OpCode32SimdS.cs b/ARMeilleure/Decoders/OpCode32SimdS.cs
index 766cf4bae1..7bf6af474f 100644
--- a/ARMeilleure/Decoders/OpCode32SimdS.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdS.cs
@@ -5,9 +5,11 @@
         public int Vd { get; protected set; }
         public int Vm { get; protected set; }
         public int Opc { get; protected set; } // "with_zero" (Opc<1>) [Vcmp, Vcmpe].
-        public int Opc2 { get; private set; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
+        public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
         public int Size { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode);
+
         public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Opc = (opCode >> 15) & 0x3;
diff --git a/ARMeilleure/Decoders/OpCode32SimdSel.cs b/ARMeilleure/Decoders/OpCode32SimdSel.cs
index aefe138fa7..0832b3a398 100644
--- a/ARMeilleure/Decoders/OpCode32SimdSel.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdSel.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdSel : OpCode32SimdRegS
     {
-        public OpCode32SimdSelMode Cc { get; private set; }
+        public OpCode32SimdSelMode Cc { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode);
 
         public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdShImm.cs b/ARMeilleure/Decoders/OpCode32SimdShImm.cs
index e40107a27c..5e234ba2e7 100644
--- a/ARMeilleure/Decoders/OpCode32SimdShImm.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdShImm.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdShImm : OpCode32Simd
     {
-        public int Shift { get; private set; }
+        public int Shift { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode);
 
         public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs b/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
index 1e77b950ab..3ca55ed6fe 100644
--- a/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdShImmLong : OpCode32Simd
     {
-        public int Shift { get; private set; }
+        public int Shift { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode);
 
         public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs b/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
index 80f441425c..93b05cbab1 100644
--- a/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdShImmNarrow : OpCode32SimdShImm
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);
+
         public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }
diff --git a/ARMeilleure/Decoders/OpCode32SimdSpecial.cs b/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
index 986afcf94e..1f1411f08f 100644
--- a/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
@@ -2,8 +2,10 @@
 {
     class OpCode32SimdSpecial : OpCode32
     {
-        public int Rt { get; private set; }
-        public int Sreg { get; private set; }
+        public int Rt { get; }
+        public int Sreg { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
 
         public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32SimdSqrte.cs b/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
index 9eb7f775d9..74cb4cb68c 100644
--- a/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
@@ -2,6 +2,8 @@
 {
     class OpCode32SimdSqrte : OpCode32Simd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode);
+
         public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = (opCode >> 18) & 0x1;
diff --git a/ARMeilleure/Decoders/OpCode32SimdTbl.cs b/ARMeilleure/Decoders/OpCode32SimdTbl.cs
index e59627c300..4308aae14e 100644
--- a/ARMeilleure/Decoders/OpCode32SimdTbl.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdTbl.cs
@@ -2,7 +2,9 @@
 {
     class OpCode32SimdTbl : OpCode32SimdReg
     {
-        public int Length { get; private set; }
+        public int Length { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode);
 
         public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCode32System.cs b/ARMeilleure/Decoders/OpCode32System.cs
index bf4383017a..89e93349b2 100644
--- a/ARMeilleure/Decoders/OpCode32System.cs
+++ b/ARMeilleure/Decoders/OpCode32System.cs
@@ -2,14 +2,16 @@
 {
     class OpCode32System : OpCode32
     {
-        public int Opc1 { get; private set; }
-        public int CRn { get; private set; }
-        public int Rt { get; private set; }
-        public int Opc2 { get; private set; }
-        public int CRm { get; private set; }
-        public int MrrcOp { get; private set; }
+        public int Opc1 { get; }
+        public int CRn { get; }
+        public int Rt { get; }
+        public int Opc2 { get; }
+        public int CRm { get; }
+        public int MrrcOp { get; }
 
-        public int Coproc { get; private set; }
+        public int Coproc { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32System(inst, address, opCode);
 
         public OpCode32System(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeAdr.cs b/ARMeilleure/Decoders/OpCodeAdr.cs
index fc8219f6c6..9655c766c2 100644
--- a/ARMeilleure/Decoders/OpCodeAdr.cs
+++ b/ARMeilleure/Decoders/OpCodeAdr.cs
@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAdr : OpCode
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
 
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
 
-         public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+         public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
+
+        public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rd = opCode & 0x1f;
 
diff --git a/ARMeilleure/Decoders/OpCodeAlu.cs b/ARMeilleure/Decoders/OpCodeAlu.cs
index 171662a066..4d7f03a716 100644
--- a/ARMeilleure/Decoders/OpCodeAlu.cs
+++ b/ARMeilleure/Decoders/OpCodeAlu.cs
@@ -3,9 +3,11 @@ namespace ARMeilleure.Decoders
     class OpCodeAlu : OpCode, IOpCodeAlu
     {
         public int Rd { get; protected set; }
-        public int Rn { get; private   set; }
+        public int Rn { get; }
 
-        public DataOp DataOp { get; private set; }
+        public DataOp DataOp { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAlu(inst, address, opCode);
 
         public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeAluBinary.cs b/ARMeilleure/Decoders/OpCodeAluBinary.cs
index 2bdf1d7986..e8b10656a0 100644
--- a/ARMeilleure/Decoders/OpCodeAluBinary.cs
+++ b/ARMeilleure/Decoders/OpCodeAluBinary.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluBinary : OpCodeAlu
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluBinary(inst, address, opCode);
 
         public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeAluImm.cs b/ARMeilleure/Decoders/OpCodeAluImm.cs
index 35c83fcc37..91aa955313 100644
--- a/ARMeilleure/Decoders/OpCodeAluImm.cs
+++ b/ARMeilleure/Decoders/OpCodeAluImm.cs
@@ -4,7 +4,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm
     {
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluImm(inst, address, opCode);
 
         public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeAluRs.cs b/ARMeilleure/Decoders/OpCodeAluRs.cs
index 84fb6ac6d1..9498333630 100644
--- a/ARMeilleure/Decoders/OpCodeAluRs.cs
+++ b/ARMeilleure/Decoders/OpCodeAluRs.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
     {
-        public int Shift { get; private set; }
-        public int Rm    { get; private set; }
+        public int Shift { get; }
+        public int Rm    { get; }
 
-        public ShiftType ShiftType { get; private set; }
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRs(inst, address, opCode);
 
         public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeAluRx.cs b/ARMeilleure/Decoders/OpCodeAluRx.cs
index 5c8d427e84..d39da9e74c 100644
--- a/ARMeilleure/Decoders/OpCodeAluRx.cs
+++ b/ARMeilleure/Decoders/OpCodeAluRx.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
     {
-        public int Shift { get; private set; }
-        public int Rm    { get; private set; }
+        public int Shift { get; }
+        public int Rm    { get; }
 
-        public IntType IntType { get; private set; }
+        public IntType IntType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRx(inst, address, opCode);
 
         public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeBImm.cs b/ARMeilleure/Decoders/OpCodeBImm.cs
index 2821a62461..e302516e2d 100644
--- a/ARMeilleure/Decoders/OpCodeBImm.cs
+++ b/ARMeilleure/Decoders/OpCodeBImm.cs
@@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
     {
         public long Immediate { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImm(inst, address, opCode);
+
         public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }
\ No newline at end of file
diff --git a/ARMeilleure/Decoders/OpCodeBImmAl.cs b/ARMeilleure/Decoders/OpCodeBImmAl.cs
index 94bcea8848..47ae5f5627 100644
--- a/ARMeilleure/Decoders/OpCodeBImmAl.cs
+++ b/ARMeilleure/Decoders/OpCodeBImmAl.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmAl : OpCodeBImm
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmAl(inst, address, opCode);
+
         public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
diff --git a/ARMeilleure/Decoders/OpCodeBImmCmp.cs b/ARMeilleure/Decoders/OpCodeBImmCmp.cs
index 2b7c283414..a524656992 100644
--- a/ARMeilleure/Decoders/OpCodeBImmCmp.cs
+++ b/ARMeilleure/Decoders/OpCodeBImmCmp.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmCmp : OpCodeBImm
     {
-        public int Rt { get; private set; }
+        public int Rt { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCmp(inst, address, opCode);
 
         public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeBImmCond.cs b/ARMeilleure/Decoders/OpCodeBImmCond.cs
index f898821ac8..b57a7ea855 100644
--- a/ARMeilleure/Decoders/OpCodeBImmCond.cs
+++ b/ARMeilleure/Decoders/OpCodeBImmCond.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmCond : OpCodeBImm, IOpCodeCond
     {
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCond(inst, address, opCode);
 
         public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeBImmTest.cs b/ARMeilleure/Decoders/OpCodeBImmTest.cs
index 6687c2e7a9..bad984055a 100644
--- a/ARMeilleure/Decoders/OpCodeBImmTest.cs
+++ b/ARMeilleure/Decoders/OpCodeBImmTest.cs
@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBImmTest : OpCodeBImm
     {
-        public int Rt  { get; private set; }
-        public int Bit { get; private set; }
+        public int Rt  { get; }
+        public int Bit { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode);
 
         public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeBReg.cs b/ARMeilleure/Decoders/OpCodeBReg.cs
index 00c51ec71e..b5dcbfd8e7 100644
--- a/ARMeilleure/Decoders/OpCodeBReg.cs
+++ b/ARMeilleure/Decoders/OpCodeBReg.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBReg : OpCode
     {
-        public int Rn { get; private set; }
+        public int Rn { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBReg(inst, address, opCode);
 
         public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeBfm.cs b/ARMeilleure/Decoders/OpCodeBfm.cs
index 2ae8edf56e..8e1c78361b 100644
--- a/ARMeilleure/Decoders/OpCodeBfm.cs
+++ b/ARMeilleure/Decoders/OpCodeBfm.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeBfm : OpCodeAlu
     {
-        public long WMask { get; private set; }
-        public long TMask { get; private set; }
-        public int  Pos   { get; private set; }
-        public int  Shift { get; private set; }
+        public long WMask { get; }
+        public long TMask { get; }
+        public int  Pos   { get; }
+        public int  Shift { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode);
 
         public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeCcmp.cs b/ARMeilleure/Decoders/OpCodeCcmp.cs
index c302f6a32a..aa47146f8e 100644
--- a/ARMeilleure/Decoders/OpCodeCcmp.cs
+++ b/ARMeilleure/Decoders/OpCodeCcmp.cs
@@ -4,10 +4,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeCcmp : OpCodeAlu, IOpCodeCond
     {
-        public    int Nzcv { get; private set; }
+        public    int Nzcv { get; }
         protected int RmImm;
 
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmp(inst, address, opCode);
 
         public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeCcmpImm.cs b/ARMeilleure/Decoders/OpCodeCcmpImm.cs
index 4a2d01f46e..3548f2da8e 100644
--- a/ARMeilleure/Decoders/OpCodeCcmpImm.cs
+++ b/ARMeilleure/Decoders/OpCodeCcmpImm.cs
@@ -4,6 +4,8 @@ namespace ARMeilleure.Decoders
     {
         public long Immediate => RmImm;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpImm(inst, address, opCode);
+
         public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }
\ No newline at end of file
diff --git a/ARMeilleure/Decoders/OpCodeCcmpReg.cs b/ARMeilleure/Decoders/OpCodeCcmpReg.cs
index 0e2b922cf2..d5df3b102e 100644
--- a/ARMeilleure/Decoders/OpCodeCcmpReg.cs
+++ b/ARMeilleure/Decoders/OpCodeCcmpReg.cs
@@ -8,6 +8,8 @@ namespace ARMeilleure.Decoders
 
         public ShiftType ShiftType => ShiftType.Lsl;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpReg(inst, address, opCode);
+
         public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
     }
 }
\ No newline at end of file
diff --git a/ARMeilleure/Decoders/OpCodeCsel.cs b/ARMeilleure/Decoders/OpCodeCsel.cs
index fd07e6fd49..4b8dc7fdd9 100644
--- a/ARMeilleure/Decoders/OpCodeCsel.cs
+++ b/ARMeilleure/Decoders/OpCodeCsel.cs
@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeCsel : OpCodeAlu, IOpCodeCond
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
 
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCsel(inst, address, opCode);
 
         public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeException.cs b/ARMeilleure/Decoders/OpCodeException.cs
index 9781c543bd..6b72138ee6 100644
--- a/ARMeilleure/Decoders/OpCodeException.cs
+++ b/ARMeilleure/Decoders/OpCodeException.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeException : OpCode
     {
-        public int Id { get; private set; }
+        public int Id { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeException(inst, address, opCode);
 
         public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeMem.cs b/ARMeilleure/Decoders/OpCodeMem.cs
index 5a7ab482a3..0ba2bcd18f 100644
--- a/ARMeilleure/Decoders/OpCodeMem.cs
+++ b/ARMeilleure/Decoders/OpCodeMem.cs
@@ -7,6 +7,8 @@ namespace ARMeilleure.Decoders
         public int  Size     { get; protected set; }
         public bool Extend64 { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode);
+
         public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rt   = (opCode >>  0) & 0x1f;
diff --git a/ARMeilleure/Decoders/OpCodeMemEx.cs b/ARMeilleure/Decoders/OpCodeMemEx.cs
index 5956f36722..8990248533 100644
--- a/ARMeilleure/Decoders/OpCodeMemEx.cs
+++ b/ARMeilleure/Decoders/OpCodeMemEx.cs
@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemEx : OpCodeMem
     {
-        public int Rt2 { get; private set; }
-        public int Rs  { get; private set; }
+        public int Rt2 { get; }
+        public int Rs  { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode);
 
         public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeMemImm.cs b/ARMeilleure/Decoders/OpCodeMemImm.cs
index 517434f290..d6ed2282fd 100644
--- a/ARMeilleure/Decoders/OpCodeMemImm.cs
+++ b/ARMeilleure/Decoders/OpCodeMemImm.cs
@@ -5,7 +5,7 @@ namespace ARMeilleure.Decoders
         public    long Immediate { get; protected set; }
         public    bool WBack     { get; protected set; }
         public    bool PostIdx   { get; protected set; }
-        protected bool Unscaled  { get; private   set; }
+        protected bool Unscaled  { get; }
 
         private enum MemOp
         {
@@ -16,6 +16,8 @@ namespace ARMeilleure.Decoders
             Unsigned
         }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode);
+
         public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Extend64 = ((opCode >> 22) & 3) == 2;
diff --git a/ARMeilleure/Decoders/OpCodeMemLit.cs b/ARMeilleure/Decoders/OpCodeMemLit.cs
index b80585cb49..986d663409 100644
--- a/ARMeilleure/Decoders/OpCodeMemLit.cs
+++ b/ARMeilleure/Decoders/OpCodeMemLit.cs
@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemLit : OpCode, IOpCodeLit
     {
-        public int  Rt        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
-        public bool Signed    { get; private set; }
-        public bool Prefetch  { get; private set; }
+        public int  Rt        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
+        public bool Signed    { get; }
+        public bool Prefetch  { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode);
 
         public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeMemPair.cs b/ARMeilleure/Decoders/OpCodeMemPair.cs
index ea329a1db7..21018033dc 100644
--- a/ARMeilleure/Decoders/OpCodeMemPair.cs
+++ b/ARMeilleure/Decoders/OpCodeMemPair.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemPair : OpCodeMemImm
     {
-        public int Rt2 { get; private set; }
+        public int Rt2 { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemPair(inst, address, opCode);
 
         public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeMemReg.cs b/ARMeilleure/Decoders/OpCodeMemReg.cs
index f5c2f9911e..73d6c5d2c0 100644
--- a/ARMeilleure/Decoders/OpCodeMemReg.cs
+++ b/ARMeilleure/Decoders/OpCodeMemReg.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMemReg : OpCodeMem
     {
-        public bool Shift { get; private set; }
-        public int  Rm    { get; private set; }
+        public bool Shift { get; }
+        public int  Rm    { get; }
 
-        public IntType IntType { get; private set; }
+        public IntType IntType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemReg(inst, address, opCode);
 
         public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeMov.cs b/ARMeilleure/Decoders/OpCodeMov.cs
index b65178cff3..50af88cb91 100644
--- a/ARMeilleure/Decoders/OpCodeMov.cs
+++ b/ARMeilleure/Decoders/OpCodeMov.cs
@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMov : OpCode
     {
-        public int Rd { get; private set; }
+        public int Rd { get; }
 
-        public long Immediate { get; private set; }
+        public long Immediate { get; }
 
-        public int Bit { get; private set; }
+        public int Bit { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMov(inst, address, opCode);
 
         public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeMul.cs b/ARMeilleure/Decoders/OpCodeMul.cs
index 3eb4dc97c5..31d140a654 100644
--- a/ARMeilleure/Decoders/OpCodeMul.cs
+++ b/ARMeilleure/Decoders/OpCodeMul.cs
@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeMul : OpCodeAlu
     {
-        public int Rm { get; private set; }
-        public int Ra { get; private set; }
+        public int Rm { get; }
+        public int Ra { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMul(inst, address, opCode);
 
         public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimd.cs b/ARMeilleure/Decoders/OpCodeSimd.cs
index a258446c19..85713690a7 100644
--- a/ARMeilleure/Decoders/OpCodeSimd.cs
+++ b/ARMeilleure/Decoders/OpCodeSimd.cs
@@ -2,11 +2,13 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimd : OpCode, IOpCodeSimd
     {
-        public int Rd   { get; private   set; }
-        public int Rn   { get; private   set; }
-        public int Opc  { get; private   set; }
+        public int Rd   { get; }
+        public int Rn   { get; }
+        public int Opc  { get; }
         public int Size { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode);
+
         public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rd   = (opCode >>  0) & 0x1f;
diff --git a/ARMeilleure/Decoders/OpCodeSimdCvt.cs b/ARMeilleure/Decoders/OpCodeSimdCvt.cs
index 15658bb89d..05b32941a2 100644
--- a/ARMeilleure/Decoders/OpCodeSimdCvt.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdCvt.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdCvt : OpCodeSimd
     {
-        public int FBits { get; private set; }
+        public int FBits { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdCvt(inst, address, opCode);
 
         public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdExt.cs b/ARMeilleure/Decoders/OpCodeSimdExt.cs
index d585449c12..a0e264d9da 100644
--- a/ARMeilleure/Decoders/OpCodeSimdExt.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdExt.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdExt : OpCodeSimdReg
     {
-        public int Imm4 { get; private set; }
+        public int Imm4 { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdExt(inst, address, opCode);
 
         public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdFcond.cs b/ARMeilleure/Decoders/OpCodeSimdFcond.cs
index 9e7a5f3bf6..aa16e0c190 100644
--- a/ARMeilleure/Decoders/OpCodeSimdFcond.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdFcond.cs
@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond
     {
-        public int Nzcv { get; private set; }
+        public int Nzcv { get; }
 
-        public Condition Cond { get; private set; }
+        public Condition Cond { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFcond(inst, address, opCode);
 
         public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdFmov.cs b/ARMeilleure/Decoders/OpCodeSimdFmov.cs
index f0da03968d..9f9062b8d6 100644
--- a/ARMeilleure/Decoders/OpCodeSimdFmov.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdFmov.cs
@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdFmov : OpCode, IOpCodeSimd
     {
-        public int  Rd        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
+        public int  Rd        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode);
 
         public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdImm.cs b/ARMeilleure/Decoders/OpCodeSimdImm.cs
index a88e360ee4..eeca770960 100644
--- a/ARMeilleure/Decoders/OpCodeSimdImm.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdImm.cs
@@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdImm : OpCode, IOpCodeSimd
     {
-        public int  Rd        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
+        public int  Rd        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode);
 
         public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdIns.cs b/ARMeilleure/Decoders/OpCodeSimdIns.cs
index 78328adb56..f6f9249d17 100644
--- a/ARMeilleure/Decoders/OpCodeSimdIns.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdIns.cs
@@ -2,8 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdIns : OpCodeSimd
     {
-        public int SrcIndex { get; private set; }
-        public int DstIndex { get; private set; }
+        public int SrcIndex { get; }
+        public int DstIndex { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdIns(inst, address, opCode);
 
         public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdMemImm.cs b/ARMeilleure/Decoders/OpCodeSimdMemImm.cs
index 6a495cafe0..c11594cb0e 100644
--- a/ARMeilleure/Decoders/OpCodeSimdMemImm.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdMemImm.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemImm(inst, address, opCode);
+
         public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size |= (opCode >> 21) & 4;
diff --git a/ARMeilleure/Decoders/OpCodeSimdMemLit.cs b/ARMeilleure/Decoders/OpCodeSimdMemLit.cs
index 607df1392c..8e21296614 100644
--- a/ARMeilleure/Decoders/OpCodeSimdMemLit.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdMemLit.cs
@@ -2,12 +2,14 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit
     {
-        public int  Rt        { get; private set; }
-        public long Immediate { get; private set; }
-        public int  Size      { get; private set; }
+        public int  Rt        { get; }
+        public long Immediate { get; }
+        public int  Size      { get; }
         public bool Signed   => false;
         public bool Prefetch => false;
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode);
+
         public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             int opc = (opCode >> 30) & 3;
diff --git a/ARMeilleure/Decoders/OpCodeSimdMemMs.cs b/ARMeilleure/Decoders/OpCodeSimdMemMs.cs
index 9fa5ff42c4..8922c18f6f 100644
--- a/ARMeilleure/Decoders/OpCodeSimdMemMs.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdMemMs.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd
     {
-        public int  Reps   { get; private set; }
-        public int  SElems { get; private set; }
-        public int  Elems  { get; private set; }
-        public bool WBack  { get; private set; }
+        public int  Reps   { get; }
+        public int  SElems { get; }
+        public int  Elems  { get; }
+        public bool WBack  { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode);
 
         public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdMemPair.cs b/ARMeilleure/Decoders/OpCodeSimdMemPair.cs
index a4af49d022..1ab9536794 100644
--- a/ARMeilleure/Decoders/OpCodeSimdMemPair.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdMemPair.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemPair(inst, address, opCode);
+
         public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = ((opCode >> 30) & 3) + 2;
diff --git a/ARMeilleure/Decoders/OpCodeSimdMemReg.cs b/ARMeilleure/Decoders/OpCodeSimdMemReg.cs
index cad8ca634c..9ea6dda37c 100644
--- a/ARMeilleure/Decoders/OpCodeSimdMemReg.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdMemReg.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemReg(inst, address, opCode);
+
         public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size |= (opCode >> 21) & 4;
diff --git a/ARMeilleure/Decoders/OpCodeSimdMemSs.cs b/ARMeilleure/Decoders/OpCodeSimdMemSs.cs
index 302decbcc5..44abdd389a 100644
--- a/ARMeilleure/Decoders/OpCodeSimdMemSs.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdMemSs.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
     {
-        public int  SElems    { get; private set; }
-        public int  Index     { get; private set; }
-        public bool Replicate { get; private set; }
-        public bool WBack     { get; private set; }
+        public int  SElems    { get; }
+        public int  Index     { get; }
+        public bool Replicate { get; }
+        public bool WBack     { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode);
 
         public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdReg.cs b/ARMeilleure/Decoders/OpCodeSimdReg.cs
index d076806a61..ac4f71dae2 100644
--- a/ARMeilleure/Decoders/OpCodeSimdReg.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdReg.cs
@@ -2,10 +2,12 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdReg : OpCodeSimd
     {
-        public bool Bit3 { get; private   set; }
-        public int  Ra   { get; private   set; }
+        public bool Bit3 { get; }
+        public int  Ra   { get; }
         public int  Rm   { get; protected set; }
 
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode);
+
         public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Bit3 = ((opCode >>  3) & 0x1) != 0;
diff --git a/ARMeilleure/Decoders/OpCodeSimdRegElem.cs b/ARMeilleure/Decoders/OpCodeSimdRegElem.cs
index d2f1583d22..92368deeae 100644
--- a/ARMeilleure/Decoders/OpCodeSimdRegElem.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdRegElem.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdRegElem : OpCodeSimdReg
     {
-        public int Index { get; private set; }
+        public int Index { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdRegElem(inst, address, opCode);
 
         public OpCodeSimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs b/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs
index 365b77172a..d46dd57ede 100644
--- a/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdRegElemF : OpCodeSimdReg
     {
-        public int Index { get; private set; }
+        public int Index { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdRegElemF(inst, address, opCode);
 
         public OpCodeSimdRegElemF(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdShImm.cs b/ARMeilleure/Decoders/OpCodeSimdShImm.cs
index d260c4b3e8..7064f1d2d3 100644
--- a/ARMeilleure/Decoders/OpCodeSimdShImm.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdShImm.cs
@@ -4,7 +4,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdShImm : OpCodeSimd
     {
-        public int Imm { get; private set; }
+        public int Imm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdShImm(inst, address, opCode);
 
         public OpCodeSimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeSimdTbl.cs b/ARMeilleure/Decoders/OpCodeSimdTbl.cs
index 14fdd6489e..9c631e485c 100644
--- a/ARMeilleure/Decoders/OpCodeSimdTbl.cs
+++ b/ARMeilleure/Decoders/OpCodeSimdTbl.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSimdTbl : OpCodeSimdReg
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdTbl(inst, address, opCode);
+
         public OpCodeSimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Size = ((opCode >> 13) & 3) + 1;
diff --git a/ARMeilleure/Decoders/OpCodeSystem.cs b/ARMeilleure/Decoders/OpCodeSystem.cs
index cf7c5cc159..4d79421a85 100644
--- a/ARMeilleure/Decoders/OpCodeSystem.cs
+++ b/ARMeilleure/Decoders/OpCodeSystem.cs
@@ -2,12 +2,14 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeSystem : OpCode
     {
-        public int Rt  { get; private set; }
-        public int Op2 { get; private set; }
-        public int CRm { get; private set; }
-        public int CRn { get; private set; }
-        public int Op1 { get; private set; }
-        public int Op0 { get; private set; }
+        public int Rt  { get; }
+        public int Op2 { get; }
+        public int CRm { get; }
+        public int CRn { get; }
+        public int Op1 { get; }
+        public int Op0 { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSystem(inst, address, opCode);
 
         public OpCodeSystem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeT16.cs b/ARMeilleure/Decoders/OpCodeT16.cs
index e7b7aff533..c7c30186b4 100644
--- a/ARMeilleure/Decoders/OpCodeT16.cs
+++ b/ARMeilleure/Decoders/OpCodeT16.cs
@@ -2,6 +2,8 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeT16 : OpCode32
     {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16(inst, address, opCode);
+
         public OpCodeT16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Cond = Condition.Al;
diff --git a/ARMeilleure/Decoders/OpCodeT16AluImm8.cs b/ARMeilleure/Decoders/OpCodeT16AluImm8.cs
index 197d3b091f..d31f37a27d 100644
--- a/ARMeilleure/Decoders/OpCodeT16AluImm8.cs
+++ b/ARMeilleure/Decoders/OpCodeT16AluImm8.cs
@@ -9,7 +9,9 @@ namespace ARMeilleure.Decoders
 
         public bool SetFlags => false;
 
-        public int Immediate { get; private set; }
+        public int Immediate { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluImm8(inst, address, opCode);
 
         public OpCodeT16AluImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeT16BReg.cs b/ARMeilleure/Decoders/OpCodeT16BReg.cs
index 1fb3975916..38c074800d 100644
--- a/ARMeilleure/Decoders/OpCodeT16BReg.cs
+++ b/ARMeilleure/Decoders/OpCodeT16BReg.cs
@@ -2,7 +2,9 @@ namespace ARMeilleure.Decoders
 {
     class OpCodeT16BReg : OpCodeT16, IOpCode32BReg
     {
-        public int Rm { get; private set; }
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BReg(inst, address, opCode);
 
         public OpCodeT16BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs
index 903eaebdba..3d08fb6caa 100644
--- a/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/ARMeilleure/Decoders/OpCodeTable.cs
@@ -2,13 +2,12 @@ using ARMeilleure.Instructions;
 using ARMeilleure.State;
 using System;
 using System.Collections.Generic;
-using System.Reflection.Emit;
 
 namespace ARMeilleure.Decoders
 {
     static class OpCodeTable
     {
-        public delegate object MakeOp(InstDescriptor inst, ulong address, int opCode);
+        public delegate OpCode MakeOp(InstDescriptor inst, ulong address, int opCode);
 
         private const int FastLookupSize = 0x1000;
 
@@ -19,961 +18,941 @@ namespace ARMeilleure.Decoders
 
             public InstDescriptor Inst { get; }
 
-            public Type Type { get; }
-
             public MakeOp MakeOp { get; }
 
-            public InstInfo(int mask, int value, InstDescriptor inst, Type type)
+            public InstInfo(int mask, int value, InstDescriptor inst, MakeOp makeOp)
             {
-                Mask  = mask;
-                Value = value;
-                Inst  = inst;
-                Type  = type;
-                MakeOp = CacheOpActivator(type);
-            }
-
-            private static MakeOp CacheOpActivator(Type type)
-            {
-                Type[] argTypes = new Type[] { typeof(InstDescriptor), typeof(ulong), typeof(int) };
-
-                DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
-
-                ILGenerator generator = mthd.GetILGenerator();
-
-                generator.Emit(OpCodes.Ldarg_0);
-                generator.Emit(OpCodes.Ldarg_1);
-                generator.Emit(OpCodes.Ldarg_2);
-                generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
-                generator.Emit(OpCodes.Ret);
-
-                return (MakeOp)mthd.CreateDelegate(typeof(MakeOp));
+                Mask   = mask;
+                Value  = value;
+                Inst   = inst;
+                MakeOp = makeOp;
             }
         }
 
-        private static List<InstInfo> _allInstA32 = new List<InstInfo>();
-        private static List<InstInfo> _allInstT32 = new List<InstInfo>();
-        private static List<InstInfo> _allInstA64 = new List<InstInfo>();
+        private static List<InstInfo> AllInstA32 = new List<InstInfo>();
+        private static List<InstInfo> AllInstT32 = new List<InstInfo>();
+        private static List<InstInfo> AllInstA64 = new List<InstInfo>();
 
-        private static InstInfo[][] _instA32FastLookup = new InstInfo[FastLookupSize][];
-        private static InstInfo[][] _instT32FastLookup = new InstInfo[FastLookupSize][];
-        private static InstInfo[][] _instA64FastLookup = new InstInfo[FastLookupSize][];
+        private static InstInfo[][] InstA32FastLookup = new InstInfo[FastLookupSize][];
+        private static InstInfo[][] InstT32FastLookup = new InstInfo[FastLookupSize][];
+        private static InstInfo[][] InstA64FastLookup = new InstInfo[FastLookupSize][];
 
         static OpCodeTable()
         {
 #region "OpCode Table (AArch64)"
             // Base
-            SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstName.Adc,             InstEmit.Adc,             typeof(OpCodeAluRs));
-            SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstName.Adcs,            InstEmit.Adcs,            typeof(OpCodeAluRs));
-            SetA64("x00100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             typeof(OpCodeAluImm));
-            SetA64("00001011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             typeof(OpCodeAluRs));
-            SetA64("10001011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             typeof(OpCodeAluRs));
-            SetA64("x0001011001xxxxxxxx0xxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             typeof(OpCodeAluRx));
-            SetA64("x0001011001xxxxxxxx100xxxxxxxxxx", InstName.Add,             InstEmit.Add,             typeof(OpCodeAluRx));
-            SetA64("x01100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            typeof(OpCodeAluImm));
-            SetA64("00101011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            typeof(OpCodeAluRs));
-            SetA64("10101011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            typeof(OpCodeAluRs));
-            SetA64("x0101011001xxxxxxxx0xxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            typeof(OpCodeAluRx));
-            SetA64("x0101011001xxxxxxxx100xxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            typeof(OpCodeAluRx));
-            SetA64("0xx10000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Adr,             InstEmit.Adr,             typeof(OpCodeAdr));
-            SetA64("1xx10000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Adrp,            InstEmit.Adrp,            typeof(OpCodeAdr));
-            SetA64("0001001000xxxxxxxxxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             typeof(OpCodeAluImm));
-            SetA64("100100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             typeof(OpCodeAluImm));
-            SetA64("00001010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             typeof(OpCodeAluRs));
-            SetA64("10001010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             typeof(OpCodeAluRs));
-            SetA64("0111001000xxxxxxxxxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            typeof(OpCodeAluImm));
-            SetA64("111100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            typeof(OpCodeAluImm));
-            SetA64("01101010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            typeof(OpCodeAluRs));
-            SetA64("11101010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            typeof(OpCodeAluRs));
-            SetA64("x0011010110xxxxx001010xxxxxxxxxx", InstName.Asrv,            InstEmit.Asrv,            typeof(OpCodeAluRs));
-            SetA64("000101xxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.B,               InstEmit.B,               typeof(OpCodeBImmAl));
-            SetA64("01010100xxxxxxxxxxxxxxxxxxx0xxxx", InstName.B_Cond,          InstEmit.B_Cond,          typeof(OpCodeBImmCond));
-            SetA64("00110011000xxxxx0xxxxxxxxxxxxxxx", InstName.Bfm,             InstEmit.Bfm,             typeof(OpCodeBfm));
-            SetA64("1011001101xxxxxxxxxxxxxxxxxxxxxx", InstName.Bfm,             InstEmit.Bfm,             typeof(OpCodeBfm));
-            SetA64("00001010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Bic,             InstEmit.Bic,             typeof(OpCodeAluRs));
-            SetA64("10001010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Bic,             InstEmit.Bic,             typeof(OpCodeAluRs));
-            SetA64("01101010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Bics,            InstEmit.Bics,            typeof(OpCodeAluRs));
-            SetA64("11101010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Bics,            InstEmit.Bics,            typeof(OpCodeAluRs));
-            SetA64("100101xxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Bl,              InstEmit.Bl,              typeof(OpCodeBImmAl));
-            SetA64("1101011000111111000000xxxxx00000", InstName.Blr,             InstEmit.Blr,             typeof(OpCodeBReg));
-            SetA64("1101011000011111000000xxxxx00000", InstName.Br,              InstEmit.Br,              typeof(OpCodeBReg));
-            SetA64("11010100001xxxxxxxxxxxxxxxx00000", InstName.Brk,             InstEmit.Brk,             typeof(OpCodeException));
-            SetA64("x0110101xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cbnz,            InstEmit.Cbnz,            typeof(OpCodeBImmCmp));
-            SetA64("x0110100xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cbz,             InstEmit.Cbz,             typeof(OpCodeBImmCmp));
-            SetA64("x0111010010xxxxxxxxx10xxxxx0xxxx", InstName.Ccmn,            InstEmit.Ccmn,            typeof(OpCodeCcmpImm));
-            SetA64("x0111010010xxxxxxxxx00xxxxx0xxxx", InstName.Ccmn,            InstEmit.Ccmn,            typeof(OpCodeCcmpReg));
-            SetA64("x1111010010xxxxxxxxx10xxxxx0xxxx", InstName.Ccmp,            InstEmit.Ccmp,            typeof(OpCodeCcmpImm));
-            SetA64("x1111010010xxxxxxxxx00xxxxx0xxxx", InstName.Ccmp,            InstEmit.Ccmp,            typeof(OpCodeCcmpReg));
-            SetA64("11010101000000110011xxxx01011111", InstName.Clrex,           InstEmit.Clrex,           typeof(OpCodeSystem));
-            SetA64("x101101011000000000101xxxxxxxxxx", InstName.Cls,             InstEmit.Cls,             typeof(OpCodeAlu));
-            SetA64("x101101011000000000100xxxxxxxxxx", InstName.Clz,             InstEmit.Clz,             typeof(OpCodeAlu));
-            SetA64("00011010110xxxxx010000xxxxxxxxxx", InstName.Crc32b,          InstEmit.Crc32b,          typeof(OpCodeAluBinary));
-            SetA64("00011010110xxxxx010001xxxxxxxxxx", InstName.Crc32h,          InstEmit.Crc32h,          typeof(OpCodeAluBinary));
-            SetA64("00011010110xxxxx010010xxxxxxxxxx", InstName.Crc32w,          InstEmit.Crc32w,          typeof(OpCodeAluBinary));
-            SetA64("10011010110xxxxx010011xxxxxxxxxx", InstName.Crc32x,          InstEmit.Crc32x,          typeof(OpCodeAluBinary));
-            SetA64("00011010110xxxxx010100xxxxxxxxxx", InstName.Crc32cb,         InstEmit.Crc32cb,         typeof(OpCodeAluBinary));
-            SetA64("00011010110xxxxx010101xxxxxxxxxx", InstName.Crc32ch,         InstEmit.Crc32ch,         typeof(OpCodeAluBinary));
-            SetA64("00011010110xxxxx010110xxxxxxxxxx", InstName.Crc32cw,         InstEmit.Crc32cw,         typeof(OpCodeAluBinary));
-            SetA64("10011010110xxxxx010111xxxxxxxxxx", InstName.Crc32cx,         InstEmit.Crc32cx,         typeof(OpCodeAluBinary));
-            SetA64("x0011010100xxxxxxxxx00xxxxxxxxxx", InstName.Csel,            InstEmit.Csel,            typeof(OpCodeCsel));
-            SetA64("x0011010100xxxxxxxxx01xxxxxxxxxx", InstName.Csinc,           InstEmit.Csinc,           typeof(OpCodeCsel));
-            SetA64("x1011010100xxxxxxxxx00xxxxxxxxxx", InstName.Csinv,           InstEmit.Csinv,           typeof(OpCodeCsel));
-            SetA64("x1011010100xxxxxxxxx01xxxxxxxxxx", InstName.Csneg,           InstEmit.Csneg,           typeof(OpCodeCsel));
-            SetA64("11010101000000110011xxxx10111111", InstName.Dmb,             InstEmit.Dmb,             typeof(OpCodeSystem));
-            SetA64("11010101000000110011xxxx10011111", InstName.Dsb,             InstEmit.Dsb,             typeof(OpCodeSystem));
-            SetA64("01001010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Eon,             InstEmit.Eon,             typeof(OpCodeAluRs));
-            SetA64("11001010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Eon,             InstEmit.Eon,             typeof(OpCodeAluRs));
-            SetA64("0101001000xxxxxxxxxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             typeof(OpCodeAluImm));
-            SetA64("110100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             typeof(OpCodeAluImm));
-            SetA64("01001010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             typeof(OpCodeAluRs));
-            SetA64("11001010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             typeof(OpCodeAluRs));
-            SetA64("00010011100xxxxx0xxxxxxxxxxxxxxx", InstName.Extr,            InstEmit.Extr,            typeof(OpCodeAluRs));
-            SetA64("10010011110xxxxxxxxxxxxxxxxxxxxx", InstName.Extr,            InstEmit.Extr,            typeof(OpCodeAluRs));
-            SetA64("11010101000000110010xxxxxxx11111", InstName.Hint,            InstEmit.Hint,            typeof(OpCodeSystem));
-            SetA64("11010101000000110011xxxx11011111", InstName.Isb,             InstEmit.Isb,             typeof(OpCodeSystem));
-            SetA64("xx001000110xxxxx1xxxxxxxxxxxxxxx", InstName.Ldar,            InstEmit.Ldar,            typeof(OpCodeMemEx));
-            SetA64("1x001000011xxxxx1xxxxxxxxxxxxxxx", InstName.Ldaxp,           InstEmit.Ldaxp,           typeof(OpCodeMemEx));
-            SetA64("xx001000010xxxxx1xxxxxxxxxxxxxxx", InstName.Ldaxr,           InstEmit.Ldaxr,           typeof(OpCodeMemEx));
-            SetA64("<<10100xx1xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldp,             InstEmit.Ldp,             typeof(OpCodeMemPair));
-            SetA64("xx111000010xxxxxxxxxxxxxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeMemImm));
-            SetA64("xx11100101xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeMemImm));
-            SetA64("xx111000011xxxxxxxxx10xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeMemReg));
-            SetA64("xx011000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr_Literal,     InstEmit.Ldr_Literal,     typeof(OpCodeMemLit));
-            SetA64("0x1110001x0xxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            typeof(OpCodeMemImm));
-            SetA64("0x1110011xxxxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            typeof(OpCodeMemImm));
-            SetA64("10111000100xxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            typeof(OpCodeMemImm));
-            SetA64("1011100110xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            typeof(OpCodeMemImm));
-            SetA64("0x1110001x1xxxxxxxxx10xxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            typeof(OpCodeMemReg));
-            SetA64("10111000101xxxxxxxxx10xxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            typeof(OpCodeMemReg));
-            SetA64("xx001000010xxxxx0xxxxxxxxxxxxxxx", InstName.Ldxr,            InstEmit.Ldxr,            typeof(OpCodeMemEx));
-            SetA64("1x001000011xxxxx0xxxxxxxxxxxxxxx", InstName.Ldxp,            InstEmit.Ldxp,            typeof(OpCodeMemEx));
-            SetA64("x0011010110xxxxx001000xxxxxxxxxx", InstName.Lslv,            InstEmit.Lslv,            typeof(OpCodeAluRs));
-            SetA64("x0011010110xxxxx001001xxxxxxxxxx", InstName.Lsrv,            InstEmit.Lsrv,            typeof(OpCodeAluRs));
-            SetA64("x0011011000xxxxx0xxxxxxxxxxxxxxx", InstName.Madd,            InstEmit.Madd,            typeof(OpCodeMul));
-            SetA64("0111001010xxxxxxxxxxxxxxxxxxxxxx", InstName.Movk,            InstEmit.Movk,            typeof(OpCodeMov));
-            SetA64("111100101xxxxxxxxxxxxxxxxxxxxxxx", InstName.Movk,            InstEmit.Movk,            typeof(OpCodeMov));
-            SetA64("0001001010xxxxxxxxxxxxxxxxxxxxxx", InstName.Movn,            InstEmit.Movn,            typeof(OpCodeMov));
-            SetA64("100100101xxxxxxxxxxxxxxxxxxxxxxx", InstName.Movn,            InstEmit.Movn,            typeof(OpCodeMov));
-            SetA64("0101001010xxxxxxxxxxxxxxxxxxxxxx", InstName.Movz,            InstEmit.Movz,            typeof(OpCodeMov));
-            SetA64("110100101xxxxxxxxxxxxxxxxxxxxxxx", InstName.Movz,            InstEmit.Movz,            typeof(OpCodeMov));
-            SetA64("110101010011xxxxxxxxxxxxxxxxxxxx", InstName.Mrs,             InstEmit.Mrs,             typeof(OpCodeSystem));
-            SetA64("110101010001xxxxxxxxxxxxxxxxxxxx", InstName.Msr,             InstEmit.Msr,             typeof(OpCodeSystem));
-            SetA64("x0011011000xxxxx1xxxxxxxxxxxxxxx", InstName.Msub,            InstEmit.Msub,            typeof(OpCodeMul));
-            SetA64("11010101000000110010000000011111", InstName.Nop,             InstEmit.Nop,             typeof(OpCodeSystem));
-            SetA64("00101010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Orn,             InstEmit.Orn,             typeof(OpCodeAluRs));
-            SetA64("10101010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Orn,             InstEmit.Orn,             typeof(OpCodeAluRs));
-            SetA64("0011001000xxxxxxxxxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             typeof(OpCodeAluImm));
-            SetA64("101100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             typeof(OpCodeAluImm));
-            SetA64("00101010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             typeof(OpCodeAluRs));
-            SetA64("10101010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             typeof(OpCodeAluRs));
-            SetA64("1111100110xxxxxxxxxxxxxxxxxxxxxx", InstName.Pfrm,            InstEmit.Pfrm,            typeof(OpCodeMemImm));
-            SetA64("11111000100xxxxxxxxx00xxxxxxxxxx", InstName.Pfrm,            InstEmit.Pfrm,            typeof(OpCodeMemImm));
-            SetA64("11011000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Pfrm,            InstEmit.Pfrm,            typeof(OpCodeMemLit));
-            SetA64("x101101011000000000000xxxxxxxxxx", InstName.Rbit,            InstEmit.Rbit,            typeof(OpCodeAlu));
-            SetA64("1101011001011111000000xxxxx00000", InstName.Ret,             InstEmit.Ret,             typeof(OpCodeBReg));
-            SetA64("x101101011000000000001xxxxxxxxxx", InstName.Rev16,           InstEmit.Rev16,           typeof(OpCodeAlu));
-            SetA64("x101101011000000000010xxxxxxxxxx", InstName.Rev32,           InstEmit.Rev32,           typeof(OpCodeAlu));
-            SetA64("1101101011000000000011xxxxxxxxxx", InstName.Rev64,           InstEmit.Rev64,           typeof(OpCodeAlu));
-            SetA64("x0011010110xxxxx001011xxxxxxxxxx", InstName.Rorv,            InstEmit.Rorv,            typeof(OpCodeAluRs));
-            SetA64("x1011010000xxxxx000000xxxxxxxxxx", InstName.Sbc,             InstEmit.Sbc,             typeof(OpCodeAluRs));
-            SetA64("x1111010000xxxxx000000xxxxxxxxxx", InstName.Sbcs,            InstEmit.Sbcs,            typeof(OpCodeAluRs));
-            SetA64("00010011000xxxxx0xxxxxxxxxxxxxxx", InstName.Sbfm,            InstEmit.Sbfm,            typeof(OpCodeBfm));
-            SetA64("1001001101xxxxxxxxxxxxxxxxxxxxxx", InstName.Sbfm,            InstEmit.Sbfm,            typeof(OpCodeBfm));
-            SetA64("x0011010110xxxxx000011xxxxxxxxxx", InstName.Sdiv,            InstEmit.Sdiv,            typeof(OpCodeAluBinary));
-            SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", InstName.Smaddl,          InstEmit.Smaddl,          typeof(OpCodeMul));
-            SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", InstName.Smsubl,          InstEmit.Smsubl,          typeof(OpCodeMul));
-            SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", InstName.Smulh,           InstEmit.Smulh,           typeof(OpCodeMul));
-            SetA64("xx001000100xxxxx1xxxxxxxxxxxxxxx", InstName.Stlr,            InstEmit.Stlr,            typeof(OpCodeMemEx));
-            SetA64("1x001000001xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxp,           InstEmit.Stlxp,           typeof(OpCodeMemEx));
-            SetA64("xx001000000xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxr,           InstEmit.Stlxr,           typeof(OpCodeMemEx));
-            SetA64("x010100xx0xxxxxxxxxxxxxxxxxxxxxx", InstName.Stp,             InstEmit.Stp,             typeof(OpCodeMemPair));
-            SetA64("xx111000000xxxxxxxxxxxxxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeMemImm));
-            SetA64("xx11100100xxxxxxxxxxxxxxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeMemImm));
-            SetA64("xx111000001xxxxxxxxx10xxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeMemReg));
-            SetA64("1x001000001xxxxx0xxxxxxxxxxxxxxx", InstName.Stxp,            InstEmit.Stxp,            typeof(OpCodeMemEx));
-            SetA64("xx001000000xxxxx0xxxxxxxxxxxxxxx", InstName.Stxr,            InstEmit.Stxr,            typeof(OpCodeMemEx));
-            SetA64("x10100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             typeof(OpCodeAluImm));
-            SetA64("01001011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             typeof(OpCodeAluRs));
-            SetA64("11001011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             typeof(OpCodeAluRs));
-            SetA64("x1001011001xxxxxxxx0xxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             typeof(OpCodeAluRx));
-            SetA64("x1001011001xxxxxxxx100xxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             typeof(OpCodeAluRx));
-            SetA64("x11100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            typeof(OpCodeAluImm));
-            SetA64("01101011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            typeof(OpCodeAluRs));
-            SetA64("11101011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            typeof(OpCodeAluRs));
-            SetA64("x1101011001xxxxxxxx0xxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            typeof(OpCodeAluRx));
-            SetA64("x1101011001xxxxxxxx100xxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            typeof(OpCodeAluRx));
-            SetA64("11010100000xxxxxxxxxxxxxxxx00001", InstName.Svc,             InstEmit.Svc,             typeof(OpCodeException));
-            SetA64("1101010100001xxxxxxxxxxxxxxxxxxx", InstName.Sys,             InstEmit.Sys,             typeof(OpCodeSystem));
-            SetA64("x0110111xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Tbnz,            InstEmit.Tbnz,            typeof(OpCodeBImmTest));
-            SetA64("x0110110xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Tbz,             InstEmit.Tbz,             typeof(OpCodeBImmTest));
-            SetA64("01010011000xxxxx0xxxxxxxxxxxxxxx", InstName.Ubfm,            InstEmit.Ubfm,            typeof(OpCodeBfm));
-            SetA64("1101001101xxxxxxxxxxxxxxxxxxxxxx", InstName.Ubfm,            InstEmit.Ubfm,            typeof(OpCodeBfm));
-            SetA64("x0011010110xxxxx000010xxxxxxxxxx", InstName.Udiv,            InstEmit.Udiv,            typeof(OpCodeAluBinary));
-            SetA64("10011011101xxxxx0xxxxxxxxxxxxxxx", InstName.Umaddl,          InstEmit.Umaddl,          typeof(OpCodeMul));
-            SetA64("10011011101xxxxx1xxxxxxxxxxxxxxx", InstName.Umsubl,          InstEmit.Umsubl,          typeof(OpCodeMul));
-            SetA64("10011011110xxxxx0xxxxxxxxxxxxxxx", InstName.Umulh,           InstEmit.Umulh,           typeof(OpCodeMul));
+            SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstName.Adc,             InstEmit.Adc,             OpCodeAluRs.Create);
+            SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstName.Adcs,            InstEmit.Adcs,            OpCodeAluRs.Create);
+            SetA64("x00100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             OpCodeAluImm.Create);
+            SetA64("00001011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             OpCodeAluRs.Create);
+            SetA64("10001011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             OpCodeAluRs.Create);
+            SetA64("x0001011001xxxxxxxx0xxxxxxxxxxxx", InstName.Add,             InstEmit.Add,             OpCodeAluRx.Create);
+            SetA64("x0001011001xxxxxxxx100xxxxxxxxxx", InstName.Add,             InstEmit.Add,             OpCodeAluRx.Create);
+            SetA64("x01100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            OpCodeAluImm.Create);
+            SetA64("00101011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            OpCodeAluRs.Create);
+            SetA64("10101011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            OpCodeAluRs.Create);
+            SetA64("x0101011001xxxxxxxx0xxxxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            OpCodeAluRx.Create);
+            SetA64("x0101011001xxxxxxxx100xxxxxxxxxx", InstName.Adds,            InstEmit.Adds,            OpCodeAluRx.Create);
+            SetA64("0xx10000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Adr,             InstEmit.Adr,             OpCodeAdr.Create);
+            SetA64("1xx10000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Adrp,            InstEmit.Adrp,            OpCodeAdr.Create);
+            SetA64("0001001000xxxxxxxxxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             OpCodeAluImm.Create);
+            SetA64("100100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             OpCodeAluImm.Create);
+            SetA64("00001010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             OpCodeAluRs.Create);
+            SetA64("10001010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.And,             InstEmit.And,             OpCodeAluRs.Create);
+            SetA64("0111001000xxxxxxxxxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            OpCodeAluImm.Create);
+            SetA64("111100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            OpCodeAluImm.Create);
+            SetA64("01101010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            OpCodeAluRs.Create);
+            SetA64("11101010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.Ands,            InstEmit.Ands,            OpCodeAluRs.Create);
+            SetA64("x0011010110xxxxx001010xxxxxxxxxx", InstName.Asrv,            InstEmit.Asrv,            OpCodeAluRs.Create);
+            SetA64("000101xxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.B,               InstEmit.B,               OpCodeBImmAl.Create);
+            SetA64("01010100xxxxxxxxxxxxxxxxxxx0xxxx", InstName.B_Cond,          InstEmit.B_Cond,          OpCodeBImmCond.Create);
+            SetA64("00110011000xxxxx0xxxxxxxxxxxxxxx", InstName.Bfm,             InstEmit.Bfm,             OpCodeBfm.Create);
+            SetA64("1011001101xxxxxxxxxxxxxxxxxxxxxx", InstName.Bfm,             InstEmit.Bfm,             OpCodeBfm.Create);
+            SetA64("00001010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Bic,             InstEmit.Bic,             OpCodeAluRs.Create);
+            SetA64("10001010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Bic,             InstEmit.Bic,             OpCodeAluRs.Create);
+            SetA64("01101010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Bics,            InstEmit.Bics,            OpCodeAluRs.Create);
+            SetA64("11101010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Bics,            InstEmit.Bics,            OpCodeAluRs.Create);
+            SetA64("100101xxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Bl,              InstEmit.Bl,              OpCodeBImmAl.Create);
+            SetA64("1101011000111111000000xxxxx00000", InstName.Blr,             InstEmit.Blr,             OpCodeBReg.Create);
+            SetA64("1101011000011111000000xxxxx00000", InstName.Br,              InstEmit.Br,              OpCodeBReg.Create);
+            SetA64("11010100001xxxxxxxxxxxxxxxx00000", InstName.Brk,             InstEmit.Brk,             OpCodeException.Create);
+            SetA64("x0110101xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cbnz,            InstEmit.Cbnz,            OpCodeBImmCmp.Create);
+            SetA64("x0110100xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Cbz,             InstEmit.Cbz,             OpCodeBImmCmp.Create);
+            SetA64("x0111010010xxxxxxxxx10xxxxx0xxxx", InstName.Ccmn,            InstEmit.Ccmn,            OpCodeCcmpImm.Create);
+            SetA64("x0111010010xxxxxxxxx00xxxxx0xxxx", InstName.Ccmn,            InstEmit.Ccmn,            OpCodeCcmpReg.Create);
+            SetA64("x1111010010xxxxxxxxx10xxxxx0xxxx", InstName.Ccmp,            InstEmit.Ccmp,            OpCodeCcmpImm.Create);
+            SetA64("x1111010010xxxxxxxxx00xxxxx0xxxx", InstName.Ccmp,            InstEmit.Ccmp,            OpCodeCcmpReg.Create);
+            SetA64("11010101000000110011xxxx01011111", InstName.Clrex,           InstEmit.Clrex,           OpCodeSystem.Create);
+            SetA64("x101101011000000000101xxxxxxxxxx", InstName.Cls,             InstEmit.Cls,             OpCodeAlu.Create);
+            SetA64("x101101011000000000100xxxxxxxxxx", InstName.Clz,             InstEmit.Clz,             OpCodeAlu.Create);
+            SetA64("00011010110xxxxx010000xxxxxxxxxx", InstName.Crc32b,          InstEmit.Crc32b,          OpCodeAluBinary.Create);
+            SetA64("00011010110xxxxx010001xxxxxxxxxx", InstName.Crc32h,          InstEmit.Crc32h,          OpCodeAluBinary.Create);
+            SetA64("00011010110xxxxx010010xxxxxxxxxx", InstName.Crc32w,          InstEmit.Crc32w,          OpCodeAluBinary.Create);
+            SetA64("10011010110xxxxx010011xxxxxxxxxx", InstName.Crc32x,          InstEmit.Crc32x,          OpCodeAluBinary.Create);
+            SetA64("00011010110xxxxx010100xxxxxxxxxx", InstName.Crc32cb,         InstEmit.Crc32cb,         OpCodeAluBinary.Create);
+            SetA64("00011010110xxxxx010101xxxxxxxxxx", InstName.Crc32ch,         InstEmit.Crc32ch,         OpCodeAluBinary.Create);
+            SetA64("00011010110xxxxx010110xxxxxxxxxx", InstName.Crc32cw,         InstEmit.Crc32cw,         OpCodeAluBinary.Create);
+            SetA64("10011010110xxxxx010111xxxxxxxxxx", InstName.Crc32cx,         InstEmit.Crc32cx,         OpCodeAluBinary.Create);
+            SetA64("x0011010100xxxxxxxxx00xxxxxxxxxx", InstName.Csel,            InstEmit.Csel,            OpCodeCsel.Create);
+            SetA64("x0011010100xxxxxxxxx01xxxxxxxxxx", InstName.Csinc,           InstEmit.Csinc,           OpCodeCsel.Create);
+            SetA64("x1011010100xxxxxxxxx00xxxxxxxxxx", InstName.Csinv,           InstEmit.Csinv,           OpCodeCsel.Create);
+            SetA64("x1011010100xxxxxxxxx01xxxxxxxxxx", InstName.Csneg,           InstEmit.Csneg,           OpCodeCsel.Create);
+            SetA64("11010101000000110011xxxx10111111", InstName.Dmb,             InstEmit.Dmb,             OpCodeSystem.Create);
+            SetA64("11010101000000110011xxxx10011111", InstName.Dsb,             InstEmit.Dsb,             OpCodeSystem.Create);
+            SetA64("01001010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Eon,             InstEmit.Eon,             OpCodeAluRs.Create);
+            SetA64("11001010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Eon,             InstEmit.Eon,             OpCodeAluRs.Create);
+            SetA64("0101001000xxxxxxxxxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             OpCodeAluImm.Create);
+            SetA64("110100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             OpCodeAluImm.Create);
+            SetA64("01001010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             OpCodeAluRs.Create);
+            SetA64("11001010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             OpCodeAluRs.Create);
+            SetA64("00010011100xxxxx0xxxxxxxxxxxxxxx", InstName.Extr,            InstEmit.Extr,            OpCodeAluRs.Create);
+            SetA64("10010011110xxxxxxxxxxxxxxxxxxxxx", InstName.Extr,            InstEmit.Extr,            OpCodeAluRs.Create);
+            SetA64("11010101000000110010xxxxxxx11111", InstName.Hint,            InstEmit.Hint,            OpCodeSystem.Create);
+            SetA64("11010101000000110011xxxx11011111", InstName.Isb,             InstEmit.Isb,             OpCodeSystem.Create);
+            SetA64("xx001000110xxxxx1xxxxxxxxxxxxxxx", InstName.Ldar,            InstEmit.Ldar,            OpCodeMemEx.Create);
+            SetA64("1x001000011xxxxx1xxxxxxxxxxxxxxx", InstName.Ldaxp,           InstEmit.Ldaxp,           OpCodeMemEx.Create);
+            SetA64("xx001000010xxxxx1xxxxxxxxxxxxxxx", InstName.Ldaxr,           InstEmit.Ldaxr,           OpCodeMemEx.Create);
+            SetA64("<<10100xx1xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldp,             InstEmit.Ldp,             OpCodeMemPair.Create);
+            SetA64("xx111000010xxxxxxxxxxxxxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeMemImm.Create);
+            SetA64("xx11100101xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeMemImm.Create);
+            SetA64("xx111000011xxxxxxxxx10xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeMemReg.Create);
+            SetA64("xx011000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr_Literal,     InstEmit.Ldr_Literal,     OpCodeMemLit.Create);
+            SetA64("0x1110001x0xxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            OpCodeMemImm.Create);
+            SetA64("0x1110011xxxxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            OpCodeMemImm.Create);
+            SetA64("10111000100xxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            OpCodeMemImm.Create);
+            SetA64("1011100110xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            OpCodeMemImm.Create);
+            SetA64("0x1110001x1xxxxxxxxx10xxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            OpCodeMemReg.Create);
+            SetA64("10111000101xxxxxxxxx10xxxxxxxxxx", InstName.Ldrs,            InstEmit.Ldrs,            OpCodeMemReg.Create);
+            SetA64("xx001000010xxxxx0xxxxxxxxxxxxxxx", InstName.Ldxr,            InstEmit.Ldxr,            OpCodeMemEx.Create);
+            SetA64("1x001000011xxxxx0xxxxxxxxxxxxxxx", InstName.Ldxp,            InstEmit.Ldxp,            OpCodeMemEx.Create);
+            SetA64("x0011010110xxxxx001000xxxxxxxxxx", InstName.Lslv,            InstEmit.Lslv,            OpCodeAluRs.Create);
+            SetA64("x0011010110xxxxx001001xxxxxxxxxx", InstName.Lsrv,            InstEmit.Lsrv,            OpCodeAluRs.Create);
+            SetA64("x0011011000xxxxx0xxxxxxxxxxxxxxx", InstName.Madd,            InstEmit.Madd,            OpCodeMul.Create);
+            SetA64("0111001010xxxxxxxxxxxxxxxxxxxxxx", InstName.Movk,            InstEmit.Movk,            OpCodeMov.Create);
+            SetA64("111100101xxxxxxxxxxxxxxxxxxxxxxx", InstName.Movk,            InstEmit.Movk,            OpCodeMov.Create);
+            SetA64("0001001010xxxxxxxxxxxxxxxxxxxxxx", InstName.Movn,            InstEmit.Movn,            OpCodeMov.Create);
+            SetA64("100100101xxxxxxxxxxxxxxxxxxxxxxx", InstName.Movn,            InstEmit.Movn,            OpCodeMov.Create);
+            SetA64("0101001010xxxxxxxxxxxxxxxxxxxxxx", InstName.Movz,            InstEmit.Movz,            OpCodeMov.Create);
+            SetA64("110100101xxxxxxxxxxxxxxxxxxxxxxx", InstName.Movz,            InstEmit.Movz,            OpCodeMov.Create);
+            SetA64("110101010011xxxxxxxxxxxxxxxxxxxx", InstName.Mrs,             InstEmit.Mrs,             OpCodeSystem.Create);
+            SetA64("110101010001xxxxxxxxxxxxxxxxxxxx", InstName.Msr,             InstEmit.Msr,             OpCodeSystem.Create);
+            SetA64("x0011011000xxxxx1xxxxxxxxxxxxxxx", InstName.Msub,            InstEmit.Msub,            OpCodeMul.Create);
+            SetA64("11010101000000110010000000011111", InstName.Nop,             InstEmit.Nop,             OpCodeSystem.Create);
+            SetA64("00101010xx1xxxxx0xxxxxxxxxxxxxxx", InstName.Orn,             InstEmit.Orn,             OpCodeAluRs.Create);
+            SetA64("10101010xx1xxxxxxxxxxxxxxxxxxxxx", InstName.Orn,             InstEmit.Orn,             OpCodeAluRs.Create);
+            SetA64("0011001000xxxxxxxxxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             OpCodeAluImm.Create);
+            SetA64("101100100xxxxxxxxxxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             OpCodeAluImm.Create);
+            SetA64("00101010xx0xxxxx0xxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             OpCodeAluRs.Create);
+            SetA64("10101010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.Orr,             InstEmit.Orr,             OpCodeAluRs.Create);
+            SetA64("1111100110xxxxxxxxxxxxxxxxxxxxxx", InstName.Pfrm,            InstEmit.Pfrm,            OpCodeMemImm.Create);
+            SetA64("11111000100xxxxxxxxx00xxxxxxxxxx", InstName.Pfrm,            InstEmit.Pfrm,            OpCodeMemImm.Create);
+            SetA64("11011000xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Pfrm,            InstEmit.Pfrm,            OpCodeMemLit.Create);
+            SetA64("x101101011000000000000xxxxxxxxxx", InstName.Rbit,            InstEmit.Rbit,            OpCodeAlu.Create);
+            SetA64("1101011001011111000000xxxxx00000", InstName.Ret,             InstEmit.Ret,             OpCodeBReg.Create);
+            SetA64("x101101011000000000001xxxxxxxxxx", InstName.Rev16,           InstEmit.Rev16,           OpCodeAlu.Create);
+            SetA64("x101101011000000000010xxxxxxxxxx", InstName.Rev32,           InstEmit.Rev32,           OpCodeAlu.Create);
+            SetA64("1101101011000000000011xxxxxxxxxx", InstName.Rev64,           InstEmit.Rev64,           OpCodeAlu.Create);
+            SetA64("x0011010110xxxxx001011xxxxxxxxxx", InstName.Rorv,            InstEmit.Rorv,            OpCodeAluRs.Create);
+            SetA64("x1011010000xxxxx000000xxxxxxxxxx", InstName.Sbc,             InstEmit.Sbc,             OpCodeAluRs.Create);
+            SetA64("x1111010000xxxxx000000xxxxxxxxxx", InstName.Sbcs,            InstEmit.Sbcs,            OpCodeAluRs.Create);
+            SetA64("00010011000xxxxx0xxxxxxxxxxxxxxx", InstName.Sbfm,            InstEmit.Sbfm,            OpCodeBfm.Create);
+            SetA64("1001001101xxxxxxxxxxxxxxxxxxxxxx", InstName.Sbfm,            InstEmit.Sbfm,            OpCodeBfm.Create);
+            SetA64("x0011010110xxxxx000011xxxxxxxxxx", InstName.Sdiv,            InstEmit.Sdiv,            OpCodeAluBinary.Create);
+            SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", InstName.Smaddl,          InstEmit.Smaddl,          OpCodeMul.Create);
+            SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", InstName.Smsubl,          InstEmit.Smsubl,          OpCodeMul.Create);
+            SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", InstName.Smulh,           InstEmit.Smulh,           OpCodeMul.Create);
+            SetA64("xx001000100xxxxx1xxxxxxxxxxxxxxx", InstName.Stlr,            InstEmit.Stlr,            OpCodeMemEx.Create);
+            SetA64("1x001000001xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxp,           InstEmit.Stlxp,           OpCodeMemEx.Create);
+            SetA64("xx001000000xxxxx1xxxxxxxxxxxxxxx", InstName.Stlxr,           InstEmit.Stlxr,           OpCodeMemEx.Create);
+            SetA64("x010100xx0xxxxxxxxxxxxxxxxxxxxxx", InstName.Stp,             InstEmit.Stp,             OpCodeMemPair.Create);
+            SetA64("xx111000000xxxxxxxxxxxxxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeMemImm.Create);
+            SetA64("xx11100100xxxxxxxxxxxxxxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeMemImm.Create);
+            SetA64("xx111000001xxxxxxxxx10xxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeMemReg.Create);
+            SetA64("1x001000001xxxxx0xxxxxxxxxxxxxxx", InstName.Stxp,            InstEmit.Stxp,            OpCodeMemEx.Create);
+            SetA64("xx001000000xxxxx0xxxxxxxxxxxxxxx", InstName.Stxr,            InstEmit.Stxr,            OpCodeMemEx.Create);
+            SetA64("x10100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             OpCodeAluImm.Create);
+            SetA64("01001011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             OpCodeAluRs.Create);
+            SetA64("11001011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             OpCodeAluRs.Create);
+            SetA64("x1001011001xxxxxxxx0xxxxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             OpCodeAluRx.Create);
+            SetA64("x1001011001xxxxxxxx100xxxxxxxxxx", InstName.Sub,             InstEmit.Sub,             OpCodeAluRx.Create);
+            SetA64("x11100010xxxxxxxxxxxxxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            OpCodeAluImm.Create);
+            SetA64("01101011<<0xxxxx0xxxxxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            OpCodeAluRs.Create);
+            SetA64("11101011<<0xxxxxxxxxxxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            OpCodeAluRs.Create);
+            SetA64("x1101011001xxxxxxxx0xxxxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            OpCodeAluRx.Create);
+            SetA64("x1101011001xxxxxxxx100xxxxxxxxxx", InstName.Subs,            InstEmit.Subs,            OpCodeAluRx.Create);
+            SetA64("11010100000xxxxxxxxxxxxxxxx00001", InstName.Svc,             InstEmit.Svc,             OpCodeException.Create);
+            SetA64("1101010100001xxxxxxxxxxxxxxxxxxx", InstName.Sys,             InstEmit.Sys,             OpCodeSystem.Create);
+            SetA64("x0110111xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Tbnz,            InstEmit.Tbnz,            OpCodeBImmTest.Create);
+            SetA64("x0110110xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Tbz,             InstEmit.Tbz,             OpCodeBImmTest.Create);
+            SetA64("01010011000xxxxx0xxxxxxxxxxxxxxx", InstName.Ubfm,            InstEmit.Ubfm,            OpCodeBfm.Create);
+            SetA64("1101001101xxxxxxxxxxxxxxxxxxxxxx", InstName.Ubfm,            InstEmit.Ubfm,            OpCodeBfm.Create);
+            SetA64("x0011010110xxxxx000010xxxxxxxxxx", InstName.Udiv,            InstEmit.Udiv,            OpCodeAluBinary.Create);
+            SetA64("10011011101xxxxx0xxxxxxxxxxxxxxx", InstName.Umaddl,          InstEmit.Umaddl,          OpCodeMul.Create);
+            SetA64("10011011101xxxxx1xxxxxxxxxxxxxxx", InstName.Umsubl,          InstEmit.Umsubl,          OpCodeMul.Create);
+            SetA64("10011011110xxxxx0xxxxxxxxxxxxxxx", InstName.Umulh,           InstEmit.Umulh,           OpCodeMul.Create);
 
             // FP & SIMD
-            SetA64("0101111011100000101110xxxxxxxxxx", InstName.Abs_S,           InstEmit.Abs_S,           typeof(OpCodeSimd));
-            SetA64("0>001110<<100000101110xxxxxxxxxx", InstName.Abs_V,           InstEmit.Abs_V,           typeof(OpCodeSimd));
-            SetA64("01011110111xxxxx100001xxxxxxxxxx", InstName.Add_S,           InstEmit.Add_S,           typeof(OpCodeSimdReg));
-            SetA64("0>001110<<1xxxxx100001xxxxxxxxxx", InstName.Add_V,           InstEmit.Add_V,           typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx010000xxxxxxxxxx", InstName.Addhn_V,         InstEmit.Addhn_V,         typeof(OpCodeSimdReg));
-            SetA64("0101111011110001101110xxxxxxxxxx", InstName.Addp_S,          InstEmit.Addp_S,          typeof(OpCodeSimd));
-            SetA64("0>001110<<1xxxxx101111xxxxxxxxxx", InstName.Addp_V,          InstEmit.Addp_V,          typeof(OpCodeSimdReg));
-            SetA64("000011100x110001101110xxxxxxxxxx", InstName.Addv_V,          InstEmit.Addv_V,          typeof(OpCodeSimd));
-            SetA64("01001110<<110001101110xxxxxxxxxx", InstName.Addv_V,          InstEmit.Addv_V,          typeof(OpCodeSimd));
-            SetA64("0100111000101000010110xxxxxxxxxx", InstName.Aesd_V,          InstEmit.Aesd_V,          typeof(OpCodeSimd));
-            SetA64("0100111000101000010010xxxxxxxxxx", InstName.Aese_V,          InstEmit.Aese_V,          typeof(OpCodeSimd));
-            SetA64("0100111000101000011110xxxxxxxxxx", InstName.Aesimc_V,        InstEmit.Aesimc_V,        typeof(OpCodeSimd));
-            SetA64("0100111000101000011010xxxxxxxxxx", InstName.Aesmc_V,         InstEmit.Aesmc_V,         typeof(OpCodeSimd));
-            SetA64("0x001110001xxxxx000111xxxxxxxxxx", InstName.And_V,           InstEmit.And_V,           typeof(OpCodeSimdReg));
-            SetA64("0x001110011xxxxx000111xxxxxxxxxx", InstName.Bic_V,           InstEmit.Bic_V,           typeof(OpCodeSimdReg));
-            SetA64("0x10111100000xxx0xx101xxxxxxxxxx", InstName.Bic_Vi,          InstEmit.Bic_Vi,          typeof(OpCodeSimdImm));
-            SetA64("0x10111100000xxx10x101xxxxxxxxxx", InstName.Bic_Vi,          InstEmit.Bic_Vi,          typeof(OpCodeSimdImm));
-            SetA64("0x101110111xxxxx000111xxxxxxxxxx", InstName.Bif_V,           InstEmit.Bif_V,           typeof(OpCodeSimdReg));
-            SetA64("0x101110101xxxxx000111xxxxxxxxxx", InstName.Bit_V,           InstEmit.Bit_V,           typeof(OpCodeSimdReg));
-            SetA64("0x101110011xxxxx000111xxxxxxxxxx", InstName.Bsl_V,           InstEmit.Bsl_V,           typeof(OpCodeSimdReg));
-            SetA64("0x001110<<100000010010xxxxxxxxxx", InstName.Cls_V,           InstEmit.Cls_V,           typeof(OpCodeSimd));
-            SetA64("0x101110<<100000010010xxxxxxxxxx", InstName.Clz_V,           InstEmit.Clz_V,           typeof(OpCodeSimd));
-            SetA64("01111110111xxxxx100011xxxxxxxxxx", InstName.Cmeq_S,          InstEmit.Cmeq_S,          typeof(OpCodeSimdReg));
-            SetA64("0101111011100000100110xxxxxxxxxx", InstName.Cmeq_S,          InstEmit.Cmeq_S,          typeof(OpCodeSimd));
-            SetA64("0>101110<<1xxxxx100011xxxxxxxxxx", InstName.Cmeq_V,          InstEmit.Cmeq_V,          typeof(OpCodeSimdReg));
-            SetA64("0>001110<<100000100110xxxxxxxxxx", InstName.Cmeq_V,          InstEmit.Cmeq_V,          typeof(OpCodeSimd));
-            SetA64("01011110111xxxxx001111xxxxxxxxxx", InstName.Cmge_S,          InstEmit.Cmge_S,          typeof(OpCodeSimdReg));
-            SetA64("0111111011100000100010xxxxxxxxxx", InstName.Cmge_S,          InstEmit.Cmge_S,          typeof(OpCodeSimd));
-            SetA64("0>001110<<1xxxxx001111xxxxxxxxxx", InstName.Cmge_V,          InstEmit.Cmge_V,          typeof(OpCodeSimdReg));
-            SetA64("0>101110<<100000100010xxxxxxxxxx", InstName.Cmge_V,          InstEmit.Cmge_V,          typeof(OpCodeSimd));
-            SetA64("01011110111xxxxx001101xxxxxxxxxx", InstName.Cmgt_S,          InstEmit.Cmgt_S,          typeof(OpCodeSimdReg));
-            SetA64("0101111011100000100010xxxxxxxxxx", InstName.Cmgt_S,          InstEmit.Cmgt_S,          typeof(OpCodeSimd));
-            SetA64("0>001110<<1xxxxx001101xxxxxxxxxx", InstName.Cmgt_V,          InstEmit.Cmgt_V,          typeof(OpCodeSimdReg));
-            SetA64("0>001110<<100000100010xxxxxxxxxx", InstName.Cmgt_V,          InstEmit.Cmgt_V,          typeof(OpCodeSimd));
-            SetA64("01111110111xxxxx001101xxxxxxxxxx", InstName.Cmhi_S,          InstEmit.Cmhi_S,          typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx001101xxxxxxxxxx", InstName.Cmhi_V,          InstEmit.Cmhi_V,          typeof(OpCodeSimdReg));
-            SetA64("01111110111xxxxx001111xxxxxxxxxx", InstName.Cmhs_S,          InstEmit.Cmhs_S,          typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx001111xxxxxxxxxx", InstName.Cmhs_V,          InstEmit.Cmhs_V,          typeof(OpCodeSimdReg));
-            SetA64("0111111011100000100110xxxxxxxxxx", InstName.Cmle_S,          InstEmit.Cmle_S,          typeof(OpCodeSimd));
-            SetA64("0>101110<<100000100110xxxxxxxxxx", InstName.Cmle_V,          InstEmit.Cmle_V,          typeof(OpCodeSimd));
-            SetA64("0101111011100000101010xxxxxxxxxx", InstName.Cmlt_S,          InstEmit.Cmlt_S,          typeof(OpCodeSimd));
-            SetA64("0>001110<<100000101010xxxxxxxxxx", InstName.Cmlt_V,          InstEmit.Cmlt_V,          typeof(OpCodeSimd));
-            SetA64("01011110111xxxxx100011xxxxxxxxxx", InstName.Cmtst_S,         InstEmit.Cmtst_S,         typeof(OpCodeSimdReg));
-            SetA64("0>001110<<1xxxxx100011xxxxxxxxxx", InstName.Cmtst_V,         InstEmit.Cmtst_V,         typeof(OpCodeSimdReg));
-            SetA64("0x00111000100000010110xxxxxxxxxx", InstName.Cnt_V,           InstEmit.Cnt_V,           typeof(OpCodeSimd));
-            SetA64("0>001110000x<>>>000011xxxxxxxxxx", InstName.Dup_Gp,          InstEmit.Dup_Gp,          typeof(OpCodeSimdIns));
-            SetA64("01011110000xxxxx000001xxxxxxxxxx", InstName.Dup_S,           InstEmit.Dup_S,           typeof(OpCodeSimdIns));
-            SetA64("0>001110000x<>>>000001xxxxxxxxxx", InstName.Dup_V,           InstEmit.Dup_V,           typeof(OpCodeSimdIns));
-            SetA64("0x101110001xxxxx000111xxxxxxxxxx", InstName.Eor_V,           InstEmit.Eor_V,           typeof(OpCodeSimdReg));
-            SetA64("0>101110000xxxxx0<xxx0xxxxxxxxxx", InstName.Ext_V,           InstEmit.Ext_V,           typeof(OpCodeSimdExt));
-            SetA64("011111101x1xxxxx110101xxxxxxxxxx", InstName.Fabd_S,          InstEmit.Fabd_S,          typeof(OpCodeSimdReg));
-            SetA64("0>1011101<1xxxxx110101xxxxxxxxxx", InstName.Fabd_V,          InstEmit.Fabd_V,          typeof(OpCodeSimdReg));
-            SetA64("000111100x100000110000xxxxxxxxxx", InstName.Fabs_S,          InstEmit.Fabs_S,          typeof(OpCodeSimd));
-            SetA64("0>0011101<100000111110xxxxxxxxxx", InstName.Fabs_V,          InstEmit.Fabs_V,          typeof(OpCodeSimd));
-            SetA64("011111100x1xxxxx111011xxxxxxxxxx", InstName.Facge_S,         InstEmit.Facge_S,         typeof(OpCodeSimdReg));
-            SetA64("0>1011100<1xxxxx111011xxxxxxxxxx", InstName.Facge_V,         InstEmit.Facge_V,         typeof(OpCodeSimdReg));
-            SetA64("011111101x1xxxxx111011xxxxxxxxxx", InstName.Facgt_S,         InstEmit.Facgt_S,         typeof(OpCodeSimdReg));
-            SetA64("0>1011101<1xxxxx111011xxxxxxxxxx", InstName.Facgt_V,         InstEmit.Facgt_V,         typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxx001010xxxxxxxxxx", InstName.Fadd_S,          InstEmit.Fadd_S,          typeof(OpCodeSimdReg));
-            SetA64("0>0011100<1xxxxx110101xxxxxxxxxx", InstName.Fadd_V,          InstEmit.Fadd_V,          typeof(OpCodeSimdReg));
-            SetA64("011111100x110000110110xxxxxxxxxx", InstName.Faddp_S,         InstEmit.Faddp_S,         typeof(OpCodeSimd));
-            SetA64("0>1011100<1xxxxx110101xxxxxxxxxx", InstName.Faddp_V,         InstEmit.Faddp_V,         typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxxxxxx01xxxxx0xxxx", InstName.Fccmp_S,         InstEmit.Fccmp_S,         typeof(OpCodeSimdFcond));
-            SetA64("000111100x1xxxxxxxxx01xxxxx1xxxx", InstName.Fccmpe_S,        InstEmit.Fccmpe_S,        typeof(OpCodeSimdFcond));
-            SetA64("010111100x1xxxxx111001xxxxxxxxxx", InstName.Fcmeq_S,         InstEmit.Fcmeq_S,         typeof(OpCodeSimdReg));
-            SetA64("010111101x100000110110xxxxxxxxxx", InstName.Fcmeq_S,         InstEmit.Fcmeq_S,         typeof(OpCodeSimd));
-            SetA64("0>0011100<1xxxxx111001xxxxxxxxxx", InstName.Fcmeq_V,         InstEmit.Fcmeq_V,         typeof(OpCodeSimdReg));
-            SetA64("0>0011101<100000110110xxxxxxxxxx", InstName.Fcmeq_V,         InstEmit.Fcmeq_V,         typeof(OpCodeSimd));
-            SetA64("011111100x1xxxxx111001xxxxxxxxxx", InstName.Fcmge_S,         InstEmit.Fcmge_S,         typeof(OpCodeSimdReg));
-            SetA64("011111101x100000110010xxxxxxxxxx", InstName.Fcmge_S,         InstEmit.Fcmge_S,         typeof(OpCodeSimd));
-            SetA64("0>1011100<1xxxxx111001xxxxxxxxxx", InstName.Fcmge_V,         InstEmit.Fcmge_V,         typeof(OpCodeSimdReg));
-            SetA64("0>1011101<100000110010xxxxxxxxxx", InstName.Fcmge_V,         InstEmit.Fcmge_V,         typeof(OpCodeSimd));
-            SetA64("011111101x1xxxxx111001xxxxxxxxxx", InstName.Fcmgt_S,         InstEmit.Fcmgt_S,         typeof(OpCodeSimdReg));
-            SetA64("010111101x100000110010xxxxxxxxxx", InstName.Fcmgt_S,         InstEmit.Fcmgt_S,         typeof(OpCodeSimd));
-            SetA64("0>1011101<1xxxxx111001xxxxxxxxxx", InstName.Fcmgt_V,         InstEmit.Fcmgt_V,         typeof(OpCodeSimdReg));
-            SetA64("0>0011101<100000110010xxxxxxxxxx", InstName.Fcmgt_V,         InstEmit.Fcmgt_V,         typeof(OpCodeSimd));
-            SetA64("011111101x100000110110xxxxxxxxxx", InstName.Fcmle_S,         InstEmit.Fcmle_S,         typeof(OpCodeSimd));
-            SetA64("0>1011101<100000110110xxxxxxxxxx", InstName.Fcmle_V,         InstEmit.Fcmle_V,         typeof(OpCodeSimd));
-            SetA64("010111101x100000111010xxxxxxxxxx", InstName.Fcmlt_S,         InstEmit.Fcmlt_S,         typeof(OpCodeSimd));
-            SetA64("0>0011101<100000111010xxxxxxxxxx", InstName.Fcmlt_V,         InstEmit.Fcmlt_V,         typeof(OpCodeSimd));
-            SetA64("000111100x1xxxxx001000xxxxx0x000", InstName.Fcmp_S,          InstEmit.Fcmp_S,          typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxx001000xxxxx1x000", InstName.Fcmpe_S,         InstEmit.Fcmpe_S,         typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxxxxxx11xxxxxxxxxx", InstName.Fcsel_S,         InstEmit.Fcsel_S,         typeof(OpCodeSimdFcond));
-            SetA64("00011110xx10001xx10000xxxxxxxxxx", InstName.Fcvt_S,          InstEmit.Fcvt_S,          typeof(OpCodeSimd));
-            SetA64("x00111100x100100000000xxxxxxxxxx", InstName.Fcvtas_Gp,       InstEmit.Fcvtas_Gp,       typeof(OpCodeSimdCvt));
-            SetA64("010111100x100001110010xxxxxxxxxx", InstName.Fcvtas_S,        InstEmit.Fcvtas_S,        typeof(OpCodeSimd));
-            SetA64("0>0011100<100001110010xxxxxxxxxx", InstName.Fcvtas_V,        InstEmit.Fcvtas_V,        typeof(OpCodeSimd));
-            SetA64("x00111100x100101000000xxxxxxxxxx", InstName.Fcvtau_Gp,       InstEmit.Fcvtau_Gp,       typeof(OpCodeSimdCvt));
-            SetA64("011111100x100001110010xxxxxxxxxx", InstName.Fcvtau_S,        InstEmit.Fcvtau_S,        typeof(OpCodeSimd));
-            SetA64("0>1011100<100001110010xxxxxxxxxx", InstName.Fcvtau_V,        InstEmit.Fcvtau_V,        typeof(OpCodeSimd));
-            SetA64("0x0011100x100001011110xxxxxxxxxx", InstName.Fcvtl_V,         InstEmit.Fcvtl_V,         typeof(OpCodeSimd));
-            SetA64("x00111100x110000000000xxxxxxxxxx", InstName.Fcvtms_Gp,       InstEmit.Fcvtms_Gp,       typeof(OpCodeSimdCvt));
-            SetA64("x00111100x110001000000xxxxxxxxxx", InstName.Fcvtmu_Gp,       InstEmit.Fcvtmu_Gp,       typeof(OpCodeSimdCvt));
-            SetA64("0x0011100x100001011010xxxxxxxxxx", InstName.Fcvtn_V,         InstEmit.Fcvtn_V,         typeof(OpCodeSimd));
-            SetA64("010111100x100001101010xxxxxxxxxx", InstName.Fcvtns_S,        InstEmit.Fcvtns_S,        typeof(OpCodeSimd));
-            SetA64("0>0011100<100001101010xxxxxxxxxx", InstName.Fcvtns_V,        InstEmit.Fcvtns_V,        typeof(OpCodeSimd));
-            SetA64("011111100x100001101010xxxxxxxxxx", InstName.Fcvtnu_S,        InstEmit.Fcvtnu_S,        typeof(OpCodeSimd));
-            SetA64("0>1011100<100001101010xxxxxxxxxx", InstName.Fcvtnu_V,        InstEmit.Fcvtnu_V,        typeof(OpCodeSimd));
-            SetA64("x00111100x101000000000xxxxxxxxxx", InstName.Fcvtps_Gp,       InstEmit.Fcvtps_Gp,       typeof(OpCodeSimdCvt));
-            SetA64("x00111100x101001000000xxxxxxxxxx", InstName.Fcvtpu_Gp,       InstEmit.Fcvtpu_Gp,       typeof(OpCodeSimdCvt));
-            SetA64("x00111100x111000000000xxxxxxxxxx", InstName.Fcvtzs_Gp,       InstEmit.Fcvtzs_Gp,       typeof(OpCodeSimdCvt));
-            SetA64(">00111100x011000>xxxxxxxxxxxxxxx", InstName.Fcvtzs_Gp_Fixed, InstEmit.Fcvtzs_Gp_Fixed, typeof(OpCodeSimdCvt));
-            SetA64("010111101x100001101110xxxxxxxxxx", InstName.Fcvtzs_S,        InstEmit.Fcvtzs_S,        typeof(OpCodeSimd));
-            SetA64("0>0011101<100001101110xxxxxxxxxx", InstName.Fcvtzs_V,        InstEmit.Fcvtzs_V,        typeof(OpCodeSimd));
-            SetA64("0x001111001xxxxx111111xxxxxxxxxx", InstName.Fcvtzs_V_Fixed,  InstEmit.Fcvtzs_V_Fixed,  typeof(OpCodeSimdShImm));
-            SetA64("0100111101xxxxxx111111xxxxxxxxxx", InstName.Fcvtzs_V_Fixed,  InstEmit.Fcvtzs_V_Fixed,  typeof(OpCodeSimdShImm));
-            SetA64("x00111100x111001000000xxxxxxxxxx", InstName.Fcvtzu_Gp,       InstEmit.Fcvtzu_Gp,       typeof(OpCodeSimdCvt));
-            SetA64(">00111100x011001>xxxxxxxxxxxxxxx", InstName.Fcvtzu_Gp_Fixed, InstEmit.Fcvtzu_Gp_Fixed, typeof(OpCodeSimdCvt));
-            SetA64("011111101x100001101110xxxxxxxxxx", InstName.Fcvtzu_S,        InstEmit.Fcvtzu_S,        typeof(OpCodeSimd));
-            SetA64("0>1011101<100001101110xxxxxxxxxx", InstName.Fcvtzu_V,        InstEmit.Fcvtzu_V,        typeof(OpCodeSimd));
-            SetA64("0x101111001xxxxx111111xxxxxxxxxx", InstName.Fcvtzu_V_Fixed,  InstEmit.Fcvtzu_V_Fixed,  typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx111111xxxxxxxxxx", InstName.Fcvtzu_V_Fixed,  InstEmit.Fcvtzu_V_Fixed,  typeof(OpCodeSimdShImm));
-            SetA64("000111100x1xxxxx000110xxxxxxxxxx", InstName.Fdiv_S,          InstEmit.Fdiv_S,          typeof(OpCodeSimdReg));
-            SetA64("0>1011100<1xxxxx111111xxxxxxxxxx", InstName.Fdiv_V,          InstEmit.Fdiv_V,          typeof(OpCodeSimdReg));
-            SetA64("000111110x0xxxxx0xxxxxxxxxxxxxxx", InstName.Fmadd_S,         InstEmit.Fmadd_S,         typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxx010010xxxxxxxxxx", InstName.Fmax_S,          InstEmit.Fmax_S,          typeof(OpCodeSimdReg));
-            SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", InstName.Fmax_V,          InstEmit.Fmax_V,          typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxx011010xxxxxxxxxx", InstName.Fmaxnm_S,        InstEmit.Fmaxnm_S,        typeof(OpCodeSimdReg));
-            SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", InstName.Fmaxnm_V,        InstEmit.Fmaxnm_V,        typeof(OpCodeSimdReg));
-            SetA64("0>1011100<1xxxxx110001xxxxxxxxxx", InstName.Fmaxnmp_V,       InstEmit.Fmaxnmp_V,       typeof(OpCodeSimdReg));
-            SetA64("0110111000110000110010xxxxxxxxxx", InstName.Fmaxnmv_V,       InstEmit.Fmaxnmv_V,       typeof(OpCodeSimd));
-            SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", InstName.Fmaxp_V,         InstEmit.Fmaxp_V,         typeof(OpCodeSimdReg));
-            SetA64("0110111000110000111110xxxxxxxxxx", InstName.Fmaxv_V,         InstEmit.Fmaxv_V,         typeof(OpCodeSimd));
-            SetA64("000111100x1xxxxx010110xxxxxxxxxx", InstName.Fmin_S,          InstEmit.Fmin_S,          typeof(OpCodeSimdReg));
-            SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", InstName.Fmin_V,          InstEmit.Fmin_V,          typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxx011110xxxxxxxxxx", InstName.Fminnm_S,        InstEmit.Fminnm_S,        typeof(OpCodeSimdReg));
-            SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", InstName.Fminnm_V,        InstEmit.Fminnm_V,        typeof(OpCodeSimdReg));
-            SetA64("0>1011101<1xxxxx110001xxxxxxxxxx", InstName.Fminnmp_V,       InstEmit.Fminnmp_V,       typeof(OpCodeSimdReg));
-            SetA64("0110111010110000110010xxxxxxxxxx", InstName.Fminnmv_V,       InstEmit.Fminnmv_V,       typeof(OpCodeSimd));
-            SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", InstName.Fminp_V,         InstEmit.Fminp_V,         typeof(OpCodeSimdReg));
-            SetA64("0110111010110000111110xxxxxxxxxx", InstName.Fminv_V,         InstEmit.Fminv_V,         typeof(OpCodeSimd));
-            SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", InstName.Fmla_Se,         InstEmit.Fmla_Se,         typeof(OpCodeSimdRegElemF));
-            SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", InstName.Fmla_V,          InstEmit.Fmla_V,          typeof(OpCodeSimdReg));
-            SetA64("0>0011111<xxxxxx0001x0xxxxxxxxxx", InstName.Fmla_Ve,         InstEmit.Fmla_Ve,         typeof(OpCodeSimdRegElemF));
-            SetA64("010111111xxxxxxx0101x0xxxxxxxxxx", InstName.Fmls_Se,         InstEmit.Fmls_Se,         typeof(OpCodeSimdRegElemF));
-            SetA64("0>0011101<1xxxxx110011xxxxxxxxxx", InstName.Fmls_V,          InstEmit.Fmls_V,          typeof(OpCodeSimdReg));
-            SetA64("0>0011111<xxxxxx0101x0xxxxxxxxxx", InstName.Fmls_Ve,         InstEmit.Fmls_Ve,         typeof(OpCodeSimdRegElemF));
-            SetA64("000111100x100000010000xxxxxxxxxx", InstName.Fmov_S,          InstEmit.Fmov_S,          typeof(OpCodeSimd));
-            SetA64("000111100x1xxxxxxxx10000000xxxxx", InstName.Fmov_Si,         InstEmit.Fmov_Si,         typeof(OpCodeSimdFmov));
-            SetA64("0x00111100000xxx111101xxxxxxxxxx", InstName.Fmov_Vi,         InstEmit.Fmov_Vi,         typeof(OpCodeSimdImm));
-            SetA64("0110111100000xxx111101xxxxxxxxxx", InstName.Fmov_Vi,         InstEmit.Fmov_Vi,         typeof(OpCodeSimdImm));
-            SetA64("0001111000100110000000xxxxxxxxxx", InstName.Fmov_Ftoi,       InstEmit.Fmov_Ftoi,       typeof(OpCodeSimd));
-            SetA64("1001111001100110000000xxxxxxxxxx", InstName.Fmov_Ftoi,       InstEmit.Fmov_Ftoi,       typeof(OpCodeSimd));
-            SetA64("0001111000100111000000xxxxxxxxxx", InstName.Fmov_Itof,       InstEmit.Fmov_Itof,       typeof(OpCodeSimd));
-            SetA64("1001111001100111000000xxxxxxxxxx", InstName.Fmov_Itof,       InstEmit.Fmov_Itof,       typeof(OpCodeSimd));
-            SetA64("1001111010101110000000xxxxxxxxxx", InstName.Fmov_Ftoi1,      InstEmit.Fmov_Ftoi1,      typeof(OpCodeSimd));
-            SetA64("1001111010101111000000xxxxxxxxxx", InstName.Fmov_Itof1,      InstEmit.Fmov_Itof1,      typeof(OpCodeSimd));
-            SetA64("000111110x0xxxxx1xxxxxxxxxxxxxxx", InstName.Fmsub_S,         InstEmit.Fmsub_S,         typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxx000010xxxxxxxxxx", InstName.Fmul_S,          InstEmit.Fmul_S,          typeof(OpCodeSimdReg));
-            SetA64("010111111xxxxxxx1001x0xxxxxxxxxx", InstName.Fmul_Se,         InstEmit.Fmul_Se,         typeof(OpCodeSimdRegElemF));
-            SetA64("0>1011100<1xxxxx110111xxxxxxxxxx", InstName.Fmul_V,          InstEmit.Fmul_V,          typeof(OpCodeSimdReg));
-            SetA64("0>0011111<xxxxxx1001x0xxxxxxxxxx", InstName.Fmul_Ve,         InstEmit.Fmul_Ve,         typeof(OpCodeSimdRegElemF));
-            SetA64("010111100x1xxxxx110111xxxxxxxxxx", InstName.Fmulx_S,         InstEmit.Fmulx_S,         typeof(OpCodeSimdReg));
-            SetA64("011111111xxxxxxx1001x0xxxxxxxxxx", InstName.Fmulx_Se,        InstEmit.Fmulx_Se,        typeof(OpCodeSimdRegElemF));
-            SetA64("0>0011100<1xxxxx110111xxxxxxxxxx", InstName.Fmulx_V,         InstEmit.Fmulx_V,         typeof(OpCodeSimdReg));
-            SetA64("0>1011111<xxxxxx1001x0xxxxxxxxxx", InstName.Fmulx_Ve,        InstEmit.Fmulx_Ve,        typeof(OpCodeSimdRegElemF));
-            SetA64("000111100x100001010000xxxxxxxxxx", InstName.Fneg_S,          InstEmit.Fneg_S,          typeof(OpCodeSimd));
-            SetA64("0>1011101<100000111110xxxxxxxxxx", InstName.Fneg_V,          InstEmit.Fneg_V,          typeof(OpCodeSimd));
-            SetA64("000111110x1xxxxx0xxxxxxxxxxxxxxx", InstName.Fnmadd_S,        InstEmit.Fnmadd_S,        typeof(OpCodeSimdReg));
-            SetA64("000111110x1xxxxx1xxxxxxxxxxxxxxx", InstName.Fnmsub_S,        InstEmit.Fnmsub_S,        typeof(OpCodeSimdReg));
-            SetA64("000111100x1xxxxx100010xxxxxxxxxx", InstName.Fnmul_S,         InstEmit.Fnmul_S,         typeof(OpCodeSimdReg));
-            SetA64("010111101x100001110110xxxxxxxxxx", InstName.Frecpe_S,        InstEmit.Frecpe_S,        typeof(OpCodeSimd));
-            SetA64("0>0011101<100001110110xxxxxxxxxx", InstName.Frecpe_V,        InstEmit.Frecpe_V,        typeof(OpCodeSimd));
-            SetA64("010111100x1xxxxx111111xxxxxxxxxx", InstName.Frecps_S,        InstEmit.Frecps_S,        typeof(OpCodeSimdReg));
-            SetA64("0>0011100<1xxxxx111111xxxxxxxxxx", InstName.Frecps_V,        InstEmit.Frecps_V,        typeof(OpCodeSimdReg));
-            SetA64("010111101x100001111110xxxxxxxxxx", InstName.Frecpx_S,        InstEmit.Frecpx_S,        typeof(OpCodeSimd));
-            SetA64("000111100x100110010000xxxxxxxxxx", InstName.Frinta_S,        InstEmit.Frinta_S,        typeof(OpCodeSimd));
-            SetA64("0>1011100<100001100010xxxxxxxxxx", InstName.Frinta_V,        InstEmit.Frinta_V,        typeof(OpCodeSimd));
-            SetA64("000111100x100111110000xxxxxxxxxx", InstName.Frinti_S,        InstEmit.Frinti_S,        typeof(OpCodeSimd));
-            SetA64("0>1011101<100001100110xxxxxxxxxx", InstName.Frinti_V,        InstEmit.Frinti_V,        typeof(OpCodeSimd));
-            SetA64("000111100x100101010000xxxxxxxxxx", InstName.Frintm_S,        InstEmit.Frintm_S,        typeof(OpCodeSimd));
-            SetA64("0>0011100<100001100110xxxxxxxxxx", InstName.Frintm_V,        InstEmit.Frintm_V,        typeof(OpCodeSimd));
-            SetA64("000111100x100100010000xxxxxxxxxx", InstName.Frintn_S,        InstEmit.Frintn_S,        typeof(OpCodeSimd));
-            SetA64("0>0011100<100001100010xxxxxxxxxx", InstName.Frintn_V,        InstEmit.Frintn_V,        typeof(OpCodeSimd));
-            SetA64("000111100x100100110000xxxxxxxxxx", InstName.Frintp_S,        InstEmit.Frintp_S,        typeof(OpCodeSimd));
-            SetA64("0>0011101<100001100010xxxxxxxxxx", InstName.Frintp_V,        InstEmit.Frintp_V,        typeof(OpCodeSimd));
-            SetA64("000111100x100111010000xxxxxxxxxx", InstName.Frintx_S,        InstEmit.Frintx_S,        typeof(OpCodeSimd));
-            SetA64("0>1011100<100001100110xxxxxxxxxx", InstName.Frintx_V,        InstEmit.Frintx_V,        typeof(OpCodeSimd));
-            SetA64("000111100x100101110000xxxxxxxxxx", InstName.Frintz_S,        InstEmit.Frintz_S,        typeof(OpCodeSimd));
-            SetA64("0>0011101<100001100110xxxxxxxxxx", InstName.Frintz_V,        InstEmit.Frintz_V,        typeof(OpCodeSimd));
-            SetA64("011111101x100001110110xxxxxxxxxx", InstName.Frsqrte_S,       InstEmit.Frsqrte_S,       typeof(OpCodeSimd));
-            SetA64("0>1011101<100001110110xxxxxxxxxx", InstName.Frsqrte_V,       InstEmit.Frsqrte_V,       typeof(OpCodeSimd));
-            SetA64("010111101x1xxxxx111111xxxxxxxxxx", InstName.Frsqrts_S,       InstEmit.Frsqrts_S,       typeof(OpCodeSimdReg));
-            SetA64("0>0011101<1xxxxx111111xxxxxxxxxx", InstName.Frsqrts_V,       InstEmit.Frsqrts_V,       typeof(OpCodeSimdReg));
-            SetA64("000111100x100001110000xxxxxxxxxx", InstName.Fsqrt_S,         InstEmit.Fsqrt_S,         typeof(OpCodeSimd));
-            SetA64("0>1011101<100001111110xxxxxxxxxx", InstName.Fsqrt_V,         InstEmit.Fsqrt_V,         typeof(OpCodeSimd));
-            SetA64("000111100x1xxxxx001110xxxxxxxxxx", InstName.Fsub_S,          InstEmit.Fsub_S,          typeof(OpCodeSimdReg));
-            SetA64("0>0011101<1xxxxx110101xxxxxxxxxx", InstName.Fsub_V,          InstEmit.Fsub_V,          typeof(OpCodeSimdReg));
-            SetA64("01001110000xxxxx000111xxxxxxxxxx", InstName.Ins_Gp,          InstEmit.Ins_Gp,          typeof(OpCodeSimdIns));
-            SetA64("01101110000xxxxx0xxxx1xxxxxxxxxx", InstName.Ins_V,           InstEmit.Ins_V,           typeof(OpCodeSimdIns));
-            SetA64("0x00110001000000xxxxxxxxxxxxxxxx", InstName.Ld__Vms,         InstEmit.Ld__Vms,         typeof(OpCodeSimdMemMs));
-            SetA64("0x001100110xxxxxxxxxxxxxxxxxxxxx", InstName.Ld__Vms,         InstEmit.Ld__Vms,         typeof(OpCodeSimdMemMs));
-            SetA64("0x00110101x00000xxxxxxxxxxxxxxxx", InstName.Ld__Vss,         InstEmit.Ld__Vss,         typeof(OpCodeSimdMemSs));
-            SetA64("0x00110111xxxxxxxxxxxxxxxxxxxxxx", InstName.Ld__Vss,         InstEmit.Ld__Vss,         typeof(OpCodeSimdMemSs));
-            SetA64("<<10110xx1xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldp,             InstEmit.Ldp,             typeof(OpCodeSimdMemPair));
-            SetA64("xx111100x10xxxxxxxxx00xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111100x10xxxxxxxxx01xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111100x10xxxxxxxxx11xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111101x1xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111100x11xxxxxx1xx10xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             typeof(OpCodeSimdMemReg));
-            SetA64("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr_Literal,     InstEmit.Ldr_Literal,     typeof(OpCodeSimdMemLit));
-            SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", InstName.Mla_V,           InstEmit.Mla_V,           typeof(OpCodeSimdReg));
-            SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", InstName.Mla_Ve,          InstEmit.Mla_Ve,          typeof(OpCodeSimdRegElem));
-            SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", InstName.Mls_V,           InstEmit.Mls_V,           typeof(OpCodeSimdReg));
-            SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", InstName.Mls_Ve,          InstEmit.Mls_Ve,          typeof(OpCodeSimdRegElem));
-            SetA64("0x00111100000xxx0xx001xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          typeof(OpCodeSimdImm));
-            SetA64("0x00111100000xxx10x001xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          typeof(OpCodeSimdImm));
-            SetA64("0x00111100000xxx110x01xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          typeof(OpCodeSimdImm));
-            SetA64("0xx0111100000xxx111001xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          typeof(OpCodeSimdImm));
-            SetA64("0x001110<<1xxxxx100111xxxxxxxxxx", InstName.Mul_V,           InstEmit.Mul_V,           typeof(OpCodeSimdReg));
-            SetA64("0x001111xxxxxxxx1000x0xxxxxxxxxx", InstName.Mul_Ve,          InstEmit.Mul_Ve,          typeof(OpCodeSimdRegElem));
-            SetA64("0x10111100000xxx0xx001xxxxxxxxxx", InstName.Mvni_V,          InstEmit.Mvni_V,          typeof(OpCodeSimdImm));
-            SetA64("0x10111100000xxx10x001xxxxxxxxxx", InstName.Mvni_V,          InstEmit.Mvni_V,          typeof(OpCodeSimdImm));
-            SetA64("0x10111100000xxx110x01xxxxxxxxxx", InstName.Mvni_V,          InstEmit.Mvni_V,          typeof(OpCodeSimdImm));
-            SetA64("0111111011100000101110xxxxxxxxxx", InstName.Neg_S,           InstEmit.Neg_S,           typeof(OpCodeSimd));
-            SetA64("0>101110<<100000101110xxxxxxxxxx", InstName.Neg_V,           InstEmit.Neg_V,           typeof(OpCodeSimd));
-            SetA64("0x10111000100000010110xxxxxxxxxx", InstName.Not_V,           InstEmit.Not_V,           typeof(OpCodeSimd));
-            SetA64("0x001110111xxxxx000111xxxxxxxxxx", InstName.Orn_V,           InstEmit.Orn_V,           typeof(OpCodeSimdReg));
-            SetA64("0x001110101xxxxx000111xxxxxxxxxx", InstName.Orr_V,           InstEmit.Orr_V,           typeof(OpCodeSimdReg));
-            SetA64("0x00111100000xxx0xx101xxxxxxxxxx", InstName.Orr_Vi,          InstEmit.Orr_Vi,          typeof(OpCodeSimdImm));
-            SetA64("0x00111100000xxx10x101xxxxxxxxxx", InstName.Orr_Vi,          InstEmit.Orr_Vi,          typeof(OpCodeSimdImm));
-            SetA64("0x101110<<1xxxxx010000xxxxxxxxxx", InstName.Raddhn_V,        InstEmit.Raddhn_V,        typeof(OpCodeSimdReg));
-            SetA64("0x10111001100000010110xxxxxxxxxx", InstName.Rbit_V,          InstEmit.Rbit_V,          typeof(OpCodeSimd));
-            SetA64("0x00111000100000000110xxxxxxxxxx", InstName.Rev16_V,         InstEmit.Rev16_V,         typeof(OpCodeSimd));
-            SetA64("0x1011100x100000000010xxxxxxxxxx", InstName.Rev32_V,         InstEmit.Rev32_V,         typeof(OpCodeSimd));
-            SetA64("0x001110<<100000000010xxxxxxxxxx", InstName.Rev64_V,         InstEmit.Rev64_V,         typeof(OpCodeSimd));
-            SetA64("0x00111100>>>xxx100011xxxxxxxxxx", InstName.Rshrn_V,         InstEmit.Rshrn_V,         typeof(OpCodeSimdShImm));
-            SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", InstName.Rsubhn_V,        InstEmit.Rsubhn_V,        typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", InstName.Saba_V,          InstEmit.Saba_V,          typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", InstName.Sabal_V,         InstEmit.Sabal_V,         typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", InstName.Sabd_V,          InstEmit.Sabd_V,          typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", InstName.Sabdl_V,         InstEmit.Sabdl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x001110<<100000011010xxxxxxxxxx", InstName.Sadalp_V,        InstEmit.Sadalp_V,        typeof(OpCodeSimd));
-            SetA64("0x001110<<1xxxxx000000xxxxxxxxxx", InstName.Saddl_V,         InstEmit.Saddl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x001110<<100000001010xxxxxxxxxx", InstName.Saddlp_V,        InstEmit.Saddlp_V,        typeof(OpCodeSimd));
-            SetA64("000011100x110000001110xxxxxxxxxx", InstName.Saddlv_V,        InstEmit.Saddlv_V,        typeof(OpCodeSimd));
-            SetA64("01001110<<110000001110xxxxxxxxxx", InstName.Saddlv_V,        InstEmit.Saddlv_V,        typeof(OpCodeSimd));
-            SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", InstName.Saddw_V,         InstEmit.Saddw_V,         typeof(OpCodeSimdReg));
-            SetA64("x00111100x100010000000xxxxxxxxxx", InstName.Scvtf_Gp,        InstEmit.Scvtf_Gp,        typeof(OpCodeSimdCvt));
-            SetA64(">00111100x000010>xxxxxxxxxxxxxxx", InstName.Scvtf_Gp_Fixed,  InstEmit.Scvtf_Gp_Fixed,  typeof(OpCodeSimdCvt));
-            SetA64("010111100x100001110110xxxxxxxxxx", InstName.Scvtf_S,         InstEmit.Scvtf_S,         typeof(OpCodeSimd));
-            SetA64("010111110>>xxxxx111001xxxxxxxxxx", InstName.Scvtf_S_Fixed,   InstEmit.Scvtf_S_Fixed,   typeof(OpCodeSimdShImm));
-            SetA64("0>0011100<100001110110xxxxxxxxxx", InstName.Scvtf_V,         InstEmit.Scvtf_V,         typeof(OpCodeSimd));
-            SetA64("0x001111001xxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed,   InstEmit.Scvtf_V_Fixed,   typeof(OpCodeSimdShImm));
-            SetA64("0100111101xxxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed,   InstEmit.Scvtf_V_Fixed,   typeof(OpCodeSimdShImm));
-            SetA64("01011110000xxxxx000000xxxxxxxxxx", InstName.Sha1c_V,         InstEmit.Sha1c_V,         typeof(OpCodeSimdReg));
-            SetA64("0101111000101000000010xxxxxxxxxx", InstName.Sha1h_V,         InstEmit.Sha1h_V,         typeof(OpCodeSimd));
-            SetA64("01011110000xxxxx001000xxxxxxxxxx", InstName.Sha1m_V,         InstEmit.Sha1m_V,         typeof(OpCodeSimdReg));
-            SetA64("01011110000xxxxx000100xxxxxxxxxx", InstName.Sha1p_V,         InstEmit.Sha1p_V,         typeof(OpCodeSimdReg));
-            SetA64("01011110000xxxxx001100xxxxxxxxxx", InstName.Sha1su0_V,       InstEmit.Sha1su0_V,       typeof(OpCodeSimdReg));
-            SetA64("0101111000101000000110xxxxxxxxxx", InstName.Sha1su1_V,       InstEmit.Sha1su1_V,       typeof(OpCodeSimd));
-            SetA64("01011110000xxxxx010000xxxxxxxxxx", InstName.Sha256h_V,       InstEmit.Sha256h_V,       typeof(OpCodeSimdReg));
-            SetA64("01011110000xxxxx010100xxxxxxxxxx", InstName.Sha256h2_V,      InstEmit.Sha256h2_V,      typeof(OpCodeSimdReg));
-            SetA64("0101111000101000001010xxxxxxxxxx", InstName.Sha256su0_V,     InstEmit.Sha256su0_V,     typeof(OpCodeSimd));
-            SetA64("01011110000xxxxx011000xxxxxxxxxx", InstName.Sha256su1_V,     InstEmit.Sha256su1_V,     typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", InstName.Shadd_V,         InstEmit.Shadd_V,         typeof(OpCodeSimdReg));
-            SetA64("0101111101xxxxxx010101xxxxxxxxxx", InstName.Shl_S,           InstEmit.Shl_S,           typeof(OpCodeSimdShImm));
-            SetA64("0x00111100>>>xxx010101xxxxxxxxxx", InstName.Shl_V,           InstEmit.Shl_V,           typeof(OpCodeSimdShImm));
-            SetA64("0100111101xxxxxx010101xxxxxxxxxx", InstName.Shl_V,           InstEmit.Shl_V,           typeof(OpCodeSimdShImm));
-            SetA64("0x101110<<100001001110xxxxxxxxxx", InstName.Shll_V,          InstEmit.Shll_V,          typeof(OpCodeSimd));
-            SetA64("0x00111100>>>xxx100001xxxxxxxxxx", InstName.Shrn_V,          InstEmit.Shrn_V,          typeof(OpCodeSimdShImm));
-            SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", InstName.Shsub_V,         InstEmit.Shsub_V,         typeof(OpCodeSimdReg));
-            SetA64("0111111101xxxxxx010101xxxxxxxxxx", InstName.Sli_S,           InstEmit.Sli_S,           typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx010101xxxxxxxxxx", InstName.Sli_V,           InstEmit.Sli_V,           typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx010101xxxxxxxxxx", InstName.Sli_V,           InstEmit.Sli_V,           typeof(OpCodeSimdShImm));
-            SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", InstName.Smax_V,          InstEmit.Smax_V,          typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", InstName.Smaxp_V,         InstEmit.Smaxp_V,         typeof(OpCodeSimdReg));
-            SetA64("000011100x110000101010xxxxxxxxxx", InstName.Smaxv_V,         InstEmit.Smaxv_V,         typeof(OpCodeSimd));
-            SetA64("01001110<<110000101010xxxxxxxxxx", InstName.Smaxv_V,         InstEmit.Smaxv_V,         typeof(OpCodeSimd));
-            SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", InstName.Smin_V,          InstEmit.Smin_V,          typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", InstName.Sminp_V,         InstEmit.Sminp_V,         typeof(OpCodeSimdReg));
-            SetA64("000011100x110001101010xxxxxxxxxx", InstName.Sminv_V,         InstEmit.Sminv_V,         typeof(OpCodeSimd));
-            SetA64("01001110<<110001101010xxxxxxxxxx", InstName.Sminv_V,         InstEmit.Sminv_V,         typeof(OpCodeSimd));
-            SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", InstName.Smlal_V,         InstEmit.Smlal_V,         typeof(OpCodeSimdReg));
-            SetA64("0x001111xxxxxxxx0010x0xxxxxxxxxx", InstName.Smlal_Ve,        InstEmit.Smlal_Ve,        typeof(OpCodeSimdRegElem));
-            SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", InstName.Smlsl_V,         InstEmit.Smlsl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x001111xxxxxxxx0110x0xxxxxxxxxx", InstName.Smlsl_Ve,        InstEmit.Smlsl_Ve,        typeof(OpCodeSimdRegElem));
-            SetA64("0x001110000xxxxx001011xxxxxxxxxx", InstName.Smov_S,          InstEmit.Smov_S,          typeof(OpCodeSimdIns));
-            SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", InstName.Smull_V,         InstEmit.Smull_V,         typeof(OpCodeSimdReg));
-            SetA64("0x001111xxxxxxxx1010x0xxxxxxxxxx", InstName.Smull_Ve,        InstEmit.Smull_Ve,        typeof(OpCodeSimdRegElem));
-            SetA64("01011110xx100000011110xxxxxxxxxx", InstName.Sqabs_S,         InstEmit.Sqabs_S,         typeof(OpCodeSimd));
-            SetA64("0>001110<<100000011110xxxxxxxxxx", InstName.Sqabs_V,         InstEmit.Sqabs_V,         typeof(OpCodeSimd));
-            SetA64("01011110xx1xxxxx000011xxxxxxxxxx", InstName.Sqadd_S,         InstEmit.Sqadd_S,         typeof(OpCodeSimdReg));
-            SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", InstName.Sqadd_V,         InstEmit.Sqadd_V,         typeof(OpCodeSimdReg));
-            SetA64("01011110011xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_S,       InstEmit.Sqdmulh_S,       typeof(OpCodeSimdReg));
-            SetA64("01011110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_S,       InstEmit.Sqdmulh_S,       typeof(OpCodeSimdReg));
-            SetA64("0x001110011xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V,       InstEmit.Sqdmulh_V,       typeof(OpCodeSimdReg));
-            SetA64("0x001110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V,       InstEmit.Sqdmulh_V,       typeof(OpCodeSimdReg));
-            SetA64("01111110xx100000011110xxxxxxxxxx", InstName.Sqneg_S,         InstEmit.Sqneg_S,         typeof(OpCodeSimd));
-            SetA64("0>101110<<100000011110xxxxxxxxxx", InstName.Sqneg_V,         InstEmit.Sqneg_V,         typeof(OpCodeSimd));
-            SetA64("01111110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S,      InstEmit.Sqrdmulh_S,      typeof(OpCodeSimdReg));
-            SetA64("01111110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S,      InstEmit.Sqrdmulh_S,      typeof(OpCodeSimdReg));
-            SetA64("0x101110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V,      InstEmit.Sqrdmulh_V,      typeof(OpCodeSimdReg));
-            SetA64("0x101110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V,      InstEmit.Sqrdmulh_V,      typeof(OpCodeSimdReg));
-            SetA64("0>001110<<1xxxxx010111xxxxxxxxxx", InstName.Sqrshl_V,        InstEmit.Sqrshl_V,        typeof(OpCodeSimdReg));
-            SetA64("0101111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_S,       InstEmit.Sqrshrn_S,       typeof(OpCodeSimdShImm));
-            SetA64("0x00111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_V,       InstEmit.Sqrshrn_V,       typeof(OpCodeSimdShImm));
-            SetA64("0111111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_S,      InstEmit.Sqrshrun_S,      typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_V,      InstEmit.Sqrshrun_V,      typeof(OpCodeSimdShImm));
-            SetA64("0>001110<<1xxxxx010011xxxxxxxxxx", InstName.Sqshl_V,         InstEmit.Sqshl_V,         typeof(OpCodeSimdReg));
-            SetA64("0101111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_S,        InstEmit.Sqshrn_S,        typeof(OpCodeSimdShImm));
-            SetA64("0x00111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_V,        InstEmit.Sqshrn_V,        typeof(OpCodeSimdShImm));
-            SetA64("0111111100>>>xxx100001xxxxxxxxxx", InstName.Sqshrun_S,       InstEmit.Sqshrun_S,       typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx100001xxxxxxxxxx", InstName.Sqshrun_V,       InstEmit.Sqshrun_V,       typeof(OpCodeSimdShImm));
-            SetA64("01011110xx1xxxxx001011xxxxxxxxxx", InstName.Sqsub_S,         InstEmit.Sqsub_S,         typeof(OpCodeSimdReg));
-            SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", InstName.Sqsub_V,         InstEmit.Sqsub_V,         typeof(OpCodeSimdReg));
-            SetA64("01011110<<100001010010xxxxxxxxxx", InstName.Sqxtn_S,         InstEmit.Sqxtn_S,         typeof(OpCodeSimd));
-            SetA64("0x001110<<100001010010xxxxxxxxxx", InstName.Sqxtn_V,         InstEmit.Sqxtn_V,         typeof(OpCodeSimd));
-            SetA64("01111110<<100001001010xxxxxxxxxx", InstName.Sqxtun_S,        InstEmit.Sqxtun_S,        typeof(OpCodeSimd));
-            SetA64("0x101110<<100001001010xxxxxxxxxx", InstName.Sqxtun_V,        InstEmit.Sqxtun_V,        typeof(OpCodeSimd));
-            SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", InstName.Srhadd_V,        InstEmit.Srhadd_V,        typeof(OpCodeSimdReg));
-            SetA64("0111111101xxxxxx010001xxxxxxxxxx", InstName.Sri_S,           InstEmit.Sri_S,           typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx010001xxxxxxxxxx", InstName.Sri_V,           InstEmit.Sri_V,           typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx010001xxxxxxxxxx", InstName.Sri_V,           InstEmit.Sri_V,           typeof(OpCodeSimdShImm));
-            SetA64("0>001110<<1xxxxx010101xxxxxxxxxx", InstName.Srshl_V,         InstEmit.Srshl_V,         typeof(OpCodeSimdReg));
-            SetA64("0101111101xxxxxx001001xxxxxxxxxx", InstName.Srshr_S,         InstEmit.Srshr_S,         typeof(OpCodeSimdShImm));
-            SetA64("0x00111100>>>xxx001001xxxxxxxxxx", InstName.Srshr_V,         InstEmit.Srshr_V,         typeof(OpCodeSimdShImm));
-            SetA64("0100111101xxxxxx001001xxxxxxxxxx", InstName.Srshr_V,         InstEmit.Srshr_V,         typeof(OpCodeSimdShImm));
-            SetA64("0101111101xxxxxx001101xxxxxxxxxx", InstName.Srsra_S,         InstEmit.Srsra_S,         typeof(OpCodeSimdShImm));
-            SetA64("0x00111100>>>xxx001101xxxxxxxxxx", InstName.Srsra_V,         InstEmit.Srsra_V,         typeof(OpCodeSimdShImm));
-            SetA64("0100111101xxxxxx001101xxxxxxxxxx", InstName.Srsra_V,         InstEmit.Srsra_V,         typeof(OpCodeSimdShImm));
-            SetA64("01011110111xxxxx010001xxxxxxxxxx", InstName.Sshl_S,          InstEmit.Sshl_S,          typeof(OpCodeSimdReg));
-            SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", InstName.Sshl_V,          InstEmit.Sshl_V,          typeof(OpCodeSimdReg));
-            SetA64("0x00111100>>>xxx101001xxxxxxxxxx", InstName.Sshll_V,         InstEmit.Sshll_V,         typeof(OpCodeSimdShImm));
-            SetA64("0101111101xxxxxx000001xxxxxxxxxx", InstName.Sshr_S,          InstEmit.Sshr_S,          typeof(OpCodeSimdShImm));
-            SetA64("0x00111100>>>xxx000001xxxxxxxxxx", InstName.Sshr_V,          InstEmit.Sshr_V,          typeof(OpCodeSimdShImm));
-            SetA64("0100111101xxxxxx000001xxxxxxxxxx", InstName.Sshr_V,          InstEmit.Sshr_V,          typeof(OpCodeSimdShImm));
-            SetA64("0101111101xxxxxx000101xxxxxxxxxx", InstName.Ssra_S,          InstEmit.Ssra_S,          typeof(OpCodeSimdShImm));
-            SetA64("0x00111100>>>xxx000101xxxxxxxxxx", InstName.Ssra_V,          InstEmit.Ssra_V,          typeof(OpCodeSimdShImm));
-            SetA64("0100111101xxxxxx000101xxxxxxxxxx", InstName.Ssra_V,          InstEmit.Ssra_V,          typeof(OpCodeSimdShImm));
-            SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", InstName.Ssubl_V,         InstEmit.Ssubl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx001100xxxxxxxxxx", InstName.Ssubw_V,         InstEmit.Ssubw_V,         typeof(OpCodeSimdReg));
-            SetA64("0x00110000000000xxxxxxxxxxxxxxxx", InstName.St__Vms,         InstEmit.St__Vms,         typeof(OpCodeSimdMemMs));
-            SetA64("0x001100100xxxxxxxxxxxxxxxxxxxxx", InstName.St__Vms,         InstEmit.St__Vms,         typeof(OpCodeSimdMemMs));
-            SetA64("0x00110100x00000xxxxxxxxxxxxxxxx", InstName.St__Vss,         InstEmit.St__Vss,         typeof(OpCodeSimdMemSs));
-            SetA64("0x00110110xxxxxxxxxxxxxxxxxxxxxx", InstName.St__Vss,         InstEmit.St__Vss,         typeof(OpCodeSimdMemSs));
-            SetA64("<<10110xx0xxxxxxxxxxxxxxxxxxxxxx", InstName.Stp,             InstEmit.Stp,             typeof(OpCodeSimdMemPair));
-            SetA64("xx111100x00xxxxxxxxx00xxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111100x00xxxxxxxxx01xxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111100x00xxxxxxxxx11xxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111101x0xxxxxxxxxxxxxxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeSimdMemImm));
-            SetA64("xx111100x01xxxxxx1xx10xxxxxxxxxx", InstName.Str,             InstEmit.Str,             typeof(OpCodeSimdMemReg));
-            SetA64("01111110111xxxxx100001xxxxxxxxxx", InstName.Sub_S,           InstEmit.Sub_S,           typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx100001xxxxxxxxxx", InstName.Sub_V,           InstEmit.Sub_V,           typeof(OpCodeSimdReg));
-            SetA64("0x001110<<1xxxxx011000xxxxxxxxxx", InstName.Subhn_V,         InstEmit.Subhn_V,         typeof(OpCodeSimdReg));
-            SetA64("01011110xx100000001110xxxxxxxxxx", InstName.Suqadd_S,        InstEmit.Suqadd_S,        typeof(OpCodeSimd));
-            SetA64("0>001110<<100000001110xxxxxxxxxx", InstName.Suqadd_V,        InstEmit.Suqadd_V,        typeof(OpCodeSimd));
-            SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", InstName.Tbl_V,           InstEmit.Tbl_V,           typeof(OpCodeSimdTbl));
-            SetA64("0x001110000xxxxx0xx100xxxxxxxxxx", InstName.Tbx_V,           InstEmit.Tbx_V,           typeof(OpCodeSimdTbl));
-            SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", InstName.Trn1_V,          InstEmit.Trn1_V,          typeof(OpCodeSimdReg));
-            SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", InstName.Trn2_V,          InstEmit.Trn2_V,          typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx011111xxxxxxxxxx", InstName.Uaba_V,          InstEmit.Uaba_V,          typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", InstName.Uabal_V,         InstEmit.Uabal_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", InstName.Uabd_V,          InstEmit.Uabd_V,          typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", InstName.Uabdl_V,         InstEmit.Uabdl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101110<<100000011010xxxxxxxxxx", InstName.Uadalp_V,        InstEmit.Uadalp_V,        typeof(OpCodeSimd));
-            SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", InstName.Uaddl_V,         InstEmit.Uaddl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101110<<100000001010xxxxxxxxxx", InstName.Uaddlp_V,        InstEmit.Uaddlp_V,        typeof(OpCodeSimd));
-            SetA64("001011100x110000001110xxxxxxxxxx", InstName.Uaddlv_V,        InstEmit.Uaddlv_V,        typeof(OpCodeSimd));
-            SetA64("01101110<<110000001110xxxxxxxxxx", InstName.Uaddlv_V,        InstEmit.Uaddlv_V,        typeof(OpCodeSimd));
-            SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", InstName.Uaddw_V,         InstEmit.Uaddw_V,         typeof(OpCodeSimdReg));
-            SetA64("x00111100x100011000000xxxxxxxxxx", InstName.Ucvtf_Gp,        InstEmit.Ucvtf_Gp,        typeof(OpCodeSimdCvt));
-            SetA64(">00111100x000011>xxxxxxxxxxxxxxx", InstName.Ucvtf_Gp_Fixed,  InstEmit.Ucvtf_Gp_Fixed,  typeof(OpCodeSimdCvt));
-            SetA64("011111100x100001110110xxxxxxxxxx", InstName.Ucvtf_S,         InstEmit.Ucvtf_S,         typeof(OpCodeSimd));
-            SetA64("011111110>>xxxxx111001xxxxxxxxxx", InstName.Ucvtf_S_Fixed,   InstEmit.Ucvtf_S_Fixed,   typeof(OpCodeSimdShImm));
-            SetA64("0>1011100<100001110110xxxxxxxxxx", InstName.Ucvtf_V,         InstEmit.Ucvtf_V,         typeof(OpCodeSimd));
-            SetA64("0x101111001xxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed,   InstEmit.Ucvtf_V_Fixed,   typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed,   InstEmit.Ucvtf_V_Fixed,   typeof(OpCodeSimdShImm));
-            SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", InstName.Uhadd_V,         InstEmit.Uhadd_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", InstName.Uhsub_V,         InstEmit.Uhsub_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", InstName.Umax_V,          InstEmit.Umax_V,          typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", InstName.Umaxp_V,         InstEmit.Umaxp_V,         typeof(OpCodeSimdReg));
-            SetA64("001011100x110000101010xxxxxxxxxx", InstName.Umaxv_V,         InstEmit.Umaxv_V,         typeof(OpCodeSimd));
-            SetA64("01101110<<110000101010xxxxxxxxxx", InstName.Umaxv_V,         InstEmit.Umaxv_V,         typeof(OpCodeSimd));
-            SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", InstName.Umin_V,          InstEmit.Umin_V,          typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", InstName.Uminp_V,         InstEmit.Uminp_V,         typeof(OpCodeSimdReg));
-            SetA64("001011100x110001101010xxxxxxxxxx", InstName.Uminv_V,         InstEmit.Uminv_V,         typeof(OpCodeSimd));
-            SetA64("01101110<<110001101010xxxxxxxxxx", InstName.Uminv_V,         InstEmit.Uminv_V,         typeof(OpCodeSimd));
-            SetA64("0x101110<<1xxxxx100000xxxxxxxxxx", InstName.Umlal_V,         InstEmit.Umlal_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101111xxxxxxxx0010x0xxxxxxxxxx", InstName.Umlal_Ve,        InstEmit.Umlal_Ve,        typeof(OpCodeSimdRegElem));
-            SetA64("0x101110<<1xxxxx101000xxxxxxxxxx", InstName.Umlsl_V,         InstEmit.Umlsl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101111xxxxxxxx0110x0xxxxxxxxxx", InstName.Umlsl_Ve,        InstEmit.Umlsl_Ve,        typeof(OpCodeSimdRegElem));
-            SetA64("0x001110000xxxxx001111xxxxxxxxxx", InstName.Umov_S,          InstEmit.Umov_S,          typeof(OpCodeSimdIns));
-            SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", InstName.Umull_V,         InstEmit.Umull_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101111xxxxxxxx1010x0xxxxxxxxxx", InstName.Umull_Ve,        InstEmit.Umull_Ve,        typeof(OpCodeSimdRegElem));
-            SetA64("01111110xx1xxxxx000011xxxxxxxxxx", InstName.Uqadd_S,         InstEmit.Uqadd_S,         typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx000011xxxxxxxxxx", InstName.Uqadd_V,         InstEmit.Uqadd_V,         typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx010111xxxxxxxxxx", InstName.Uqrshl_V,        InstEmit.Uqrshl_V,        typeof(OpCodeSimdReg));
-            SetA64("0111111100>>>xxx100111xxxxxxxxxx", InstName.Uqrshrn_S,       InstEmit.Uqrshrn_S,       typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx100111xxxxxxxxxx", InstName.Uqrshrn_V,       InstEmit.Uqrshrn_V,       typeof(OpCodeSimdShImm));
-            SetA64("0>101110<<1xxxxx010011xxxxxxxxxx", InstName.Uqshl_V,         InstEmit.Uqshl_V,         typeof(OpCodeSimdReg));
-            SetA64("0111111100>>>xxx100101xxxxxxxxxx", InstName.Uqshrn_S,        InstEmit.Uqshrn_S,        typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx100101xxxxxxxxxx", InstName.Uqshrn_V,        InstEmit.Uqshrn_V,        typeof(OpCodeSimdShImm));
-            SetA64("01111110xx1xxxxx001011xxxxxxxxxx", InstName.Uqsub_S,         InstEmit.Uqsub_S,         typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", InstName.Uqsub_V,         InstEmit.Uqsub_V,         typeof(OpCodeSimdReg));
-            SetA64("01111110<<100001010010xxxxxxxxxx", InstName.Uqxtn_S,         InstEmit.Uqxtn_S,         typeof(OpCodeSimd));
-            SetA64("0x101110<<100001010010xxxxxxxxxx", InstName.Uqxtn_V,         InstEmit.Uqxtn_V,         typeof(OpCodeSimd));
-            SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", InstName.Urhadd_V,        InstEmit.Urhadd_V,        typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx010101xxxxxxxxxx", InstName.Urshl_V,         InstEmit.Urshl_V,         typeof(OpCodeSimdReg));
-            SetA64("0111111101xxxxxx001001xxxxxxxxxx", InstName.Urshr_S,         InstEmit.Urshr_S,         typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx001001xxxxxxxxxx", InstName.Urshr_V,         InstEmit.Urshr_V,         typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx001001xxxxxxxxxx", InstName.Urshr_V,         InstEmit.Urshr_V,         typeof(OpCodeSimdShImm));
-            SetA64("0111111101xxxxxx001101xxxxxxxxxx", InstName.Ursra_S,         InstEmit.Ursra_S,         typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx001101xxxxxxxxxx", InstName.Ursra_V,         InstEmit.Ursra_V,         typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx001101xxxxxxxxxx", InstName.Ursra_V,         InstEmit.Ursra_V,         typeof(OpCodeSimdShImm));
-            SetA64("01111110111xxxxx010001xxxxxxxxxx", InstName.Ushl_S,          InstEmit.Ushl_S,          typeof(OpCodeSimdReg));
-            SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", InstName.Ushl_V,          InstEmit.Ushl_V,          typeof(OpCodeSimdReg));
-            SetA64("0x10111100>>>xxx101001xxxxxxxxxx", InstName.Ushll_V,         InstEmit.Ushll_V,         typeof(OpCodeSimdShImm));
-            SetA64("0111111101xxxxxx000001xxxxxxxxxx", InstName.Ushr_S,          InstEmit.Ushr_S,          typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx000001xxxxxxxxxx", InstName.Ushr_V,          InstEmit.Ushr_V,          typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx000001xxxxxxxxxx", InstName.Ushr_V,          InstEmit.Ushr_V,          typeof(OpCodeSimdShImm));
-            SetA64("01111110xx100000001110xxxxxxxxxx", InstName.Usqadd_S,        InstEmit.Usqadd_S,        typeof(OpCodeSimd));
-            SetA64("0>101110<<100000001110xxxxxxxxxx", InstName.Usqadd_V,        InstEmit.Usqadd_V,        typeof(OpCodeSimd));
-            SetA64("0111111101xxxxxx000101xxxxxxxxxx", InstName.Usra_S,          InstEmit.Usra_S,          typeof(OpCodeSimdShImm));
-            SetA64("0x10111100>>>xxx000101xxxxxxxxxx", InstName.Usra_V,          InstEmit.Usra_V,          typeof(OpCodeSimdShImm));
-            SetA64("0110111101xxxxxx000101xxxxxxxxxx", InstName.Usra_V,          InstEmit.Usra_V,          typeof(OpCodeSimdShImm));
-            SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", InstName.Usubl_V,         InstEmit.Usubl_V,         typeof(OpCodeSimdReg));
-            SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", InstName.Usubw_V,         InstEmit.Usubw_V,         typeof(OpCodeSimdReg));
-            SetA64("0>001110<<0xxxxx000110xxxxxxxxxx", InstName.Uzp1_V,          InstEmit.Uzp1_V,          typeof(OpCodeSimdReg));
-            SetA64("0>001110<<0xxxxx010110xxxxxxxxxx", InstName.Uzp2_V,          InstEmit.Uzp2_V,          typeof(OpCodeSimdReg));
-            SetA64("0x001110<<100001001010xxxxxxxxxx", InstName.Xtn_V,           InstEmit.Xtn_V,           typeof(OpCodeSimd));
-            SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", InstName.Zip1_V,          InstEmit.Zip1_V,          typeof(OpCodeSimdReg));
-            SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V,          InstEmit.Zip2_V,          typeof(OpCodeSimdReg));
+            SetA64("0101111011100000101110xxxxxxxxxx", InstName.Abs_S,           InstEmit.Abs_S,           OpCodeSimd.Create);
+            SetA64("0>001110<<100000101110xxxxxxxxxx", InstName.Abs_V,           InstEmit.Abs_V,           OpCodeSimd.Create);
+            SetA64("01011110111xxxxx100001xxxxxxxxxx", InstName.Add_S,           InstEmit.Add_S,           OpCodeSimdReg.Create);
+            SetA64("0>001110<<1xxxxx100001xxxxxxxxxx", InstName.Add_V,           InstEmit.Add_V,           OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx010000xxxxxxxxxx", InstName.Addhn_V,         InstEmit.Addhn_V,         OpCodeSimdReg.Create);
+            SetA64("0101111011110001101110xxxxxxxxxx", InstName.Addp_S,          InstEmit.Addp_S,          OpCodeSimd.Create);
+            SetA64("0>001110<<1xxxxx101111xxxxxxxxxx", InstName.Addp_V,          InstEmit.Addp_V,          OpCodeSimdReg.Create);
+            SetA64("000011100x110001101110xxxxxxxxxx", InstName.Addv_V,          InstEmit.Addv_V,          OpCodeSimd.Create);
+            SetA64("01001110<<110001101110xxxxxxxxxx", InstName.Addv_V,          InstEmit.Addv_V,          OpCodeSimd.Create);
+            SetA64("0100111000101000010110xxxxxxxxxx", InstName.Aesd_V,          InstEmit.Aesd_V,          OpCodeSimd.Create);
+            SetA64("0100111000101000010010xxxxxxxxxx", InstName.Aese_V,          InstEmit.Aese_V,          OpCodeSimd.Create);
+            SetA64("0100111000101000011110xxxxxxxxxx", InstName.Aesimc_V,        InstEmit.Aesimc_V,        OpCodeSimd.Create);
+            SetA64("0100111000101000011010xxxxxxxxxx", InstName.Aesmc_V,         InstEmit.Aesmc_V,         OpCodeSimd.Create);
+            SetA64("0x001110001xxxxx000111xxxxxxxxxx", InstName.And_V,           InstEmit.And_V,           OpCodeSimdReg.Create);
+            SetA64("0x001110011xxxxx000111xxxxxxxxxx", InstName.Bic_V,           InstEmit.Bic_V,           OpCodeSimdReg.Create);
+            SetA64("0x10111100000xxx0xx101xxxxxxxxxx", InstName.Bic_Vi,          InstEmit.Bic_Vi,          OpCodeSimdImm.Create);
+            SetA64("0x10111100000xxx10x101xxxxxxxxxx", InstName.Bic_Vi,          InstEmit.Bic_Vi,          OpCodeSimdImm.Create);
+            SetA64("0x101110111xxxxx000111xxxxxxxxxx", InstName.Bif_V,           InstEmit.Bif_V,           OpCodeSimdReg.Create);
+            SetA64("0x101110101xxxxx000111xxxxxxxxxx", InstName.Bit_V,           InstEmit.Bit_V,           OpCodeSimdReg.Create);
+            SetA64("0x101110011xxxxx000111xxxxxxxxxx", InstName.Bsl_V,           InstEmit.Bsl_V,           OpCodeSimdReg.Create);
+            SetA64("0x001110<<100000010010xxxxxxxxxx", InstName.Cls_V,           InstEmit.Cls_V,           OpCodeSimd.Create);
+            SetA64("0x101110<<100000010010xxxxxxxxxx", InstName.Clz_V,           InstEmit.Clz_V,           OpCodeSimd.Create);
+            SetA64("01111110111xxxxx100011xxxxxxxxxx", InstName.Cmeq_S,          InstEmit.Cmeq_S,          OpCodeSimdReg.Create);
+            SetA64("0101111011100000100110xxxxxxxxxx", InstName.Cmeq_S,          InstEmit.Cmeq_S,          OpCodeSimd.Create);
+            SetA64("0>101110<<1xxxxx100011xxxxxxxxxx", InstName.Cmeq_V,          InstEmit.Cmeq_V,          OpCodeSimdReg.Create);
+            SetA64("0>001110<<100000100110xxxxxxxxxx", InstName.Cmeq_V,          InstEmit.Cmeq_V,          OpCodeSimd.Create);
+            SetA64("01011110111xxxxx001111xxxxxxxxxx", InstName.Cmge_S,          InstEmit.Cmge_S,          OpCodeSimdReg.Create);
+            SetA64("0111111011100000100010xxxxxxxxxx", InstName.Cmge_S,          InstEmit.Cmge_S,          OpCodeSimd.Create);
+            SetA64("0>001110<<1xxxxx001111xxxxxxxxxx", InstName.Cmge_V,          InstEmit.Cmge_V,          OpCodeSimdReg.Create);
+            SetA64("0>101110<<100000100010xxxxxxxxxx", InstName.Cmge_V,          InstEmit.Cmge_V,          OpCodeSimd.Create);
+            SetA64("01011110111xxxxx001101xxxxxxxxxx", InstName.Cmgt_S,          InstEmit.Cmgt_S,          OpCodeSimdReg.Create);
+            SetA64("0101111011100000100010xxxxxxxxxx", InstName.Cmgt_S,          InstEmit.Cmgt_S,          OpCodeSimd.Create);
+            SetA64("0>001110<<1xxxxx001101xxxxxxxxxx", InstName.Cmgt_V,          InstEmit.Cmgt_V,          OpCodeSimdReg.Create);
+            SetA64("0>001110<<100000100010xxxxxxxxxx", InstName.Cmgt_V,          InstEmit.Cmgt_V,          OpCodeSimd.Create);
+            SetA64("01111110111xxxxx001101xxxxxxxxxx", InstName.Cmhi_S,          InstEmit.Cmhi_S,          OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx001101xxxxxxxxxx", InstName.Cmhi_V,          InstEmit.Cmhi_V,          OpCodeSimdReg.Create);
+            SetA64("01111110111xxxxx001111xxxxxxxxxx", InstName.Cmhs_S,          InstEmit.Cmhs_S,          OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx001111xxxxxxxxxx", InstName.Cmhs_V,          InstEmit.Cmhs_V,          OpCodeSimdReg.Create);
+            SetA64("0111111011100000100110xxxxxxxxxx", InstName.Cmle_S,          InstEmit.Cmle_S,          OpCodeSimd.Create);
+            SetA64("0>101110<<100000100110xxxxxxxxxx", InstName.Cmle_V,          InstEmit.Cmle_V,          OpCodeSimd.Create);
+            SetA64("0101111011100000101010xxxxxxxxxx", InstName.Cmlt_S,          InstEmit.Cmlt_S,          OpCodeSimd.Create);
+            SetA64("0>001110<<100000101010xxxxxxxxxx", InstName.Cmlt_V,          InstEmit.Cmlt_V,          OpCodeSimd.Create);
+            SetA64("01011110111xxxxx100011xxxxxxxxxx", InstName.Cmtst_S,         InstEmit.Cmtst_S,         OpCodeSimdReg.Create);
+            SetA64("0>001110<<1xxxxx100011xxxxxxxxxx", InstName.Cmtst_V,         InstEmit.Cmtst_V,         OpCodeSimdReg.Create);
+            SetA64("0x00111000100000010110xxxxxxxxxx", InstName.Cnt_V,           InstEmit.Cnt_V,           OpCodeSimd.Create);
+            SetA64("0>001110000x<>>>000011xxxxxxxxxx", InstName.Dup_Gp,          InstEmit.Dup_Gp,          OpCodeSimdIns.Create);
+            SetA64("01011110000xxxxx000001xxxxxxxxxx", InstName.Dup_S,           InstEmit.Dup_S,           OpCodeSimdIns.Create);
+            SetA64("0>001110000x<>>>000001xxxxxxxxxx", InstName.Dup_V,           InstEmit.Dup_V,           OpCodeSimdIns.Create);
+            SetA64("0x101110001xxxxx000111xxxxxxxxxx", InstName.Eor_V,           InstEmit.Eor_V,           OpCodeSimdReg.Create);
+            SetA64("0>101110000xxxxx0<xxx0xxxxxxxxxx", InstName.Ext_V,           InstEmit.Ext_V,           OpCodeSimdExt.Create);
+            SetA64("011111101x1xxxxx110101xxxxxxxxxx", InstName.Fabd_S,          InstEmit.Fabd_S,          OpCodeSimdReg.Create);
+            SetA64("0>1011101<1xxxxx110101xxxxxxxxxx", InstName.Fabd_V,          InstEmit.Fabd_V,          OpCodeSimdReg.Create);
+            SetA64("000111100x100000110000xxxxxxxxxx", InstName.Fabs_S,          InstEmit.Fabs_S,          OpCodeSimd.Create);
+            SetA64("0>0011101<100000111110xxxxxxxxxx", InstName.Fabs_V,          InstEmit.Fabs_V,          OpCodeSimd.Create);
+            SetA64("011111100x1xxxxx111011xxxxxxxxxx", InstName.Facge_S,         InstEmit.Facge_S,         OpCodeSimdReg.Create);
+            SetA64("0>1011100<1xxxxx111011xxxxxxxxxx", InstName.Facge_V,         InstEmit.Facge_V,         OpCodeSimdReg.Create);
+            SetA64("011111101x1xxxxx111011xxxxxxxxxx", InstName.Facgt_S,         InstEmit.Facgt_S,         OpCodeSimdReg.Create);
+            SetA64("0>1011101<1xxxxx111011xxxxxxxxxx", InstName.Facgt_V,         InstEmit.Facgt_V,         OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxx001010xxxxxxxxxx", InstName.Fadd_S,          InstEmit.Fadd_S,          OpCodeSimdReg.Create);
+            SetA64("0>0011100<1xxxxx110101xxxxxxxxxx", InstName.Fadd_V,          InstEmit.Fadd_V,          OpCodeSimdReg.Create);
+            SetA64("011111100x110000110110xxxxxxxxxx", InstName.Faddp_S,         InstEmit.Faddp_S,         OpCodeSimd.Create);
+            SetA64("0>1011100<1xxxxx110101xxxxxxxxxx", InstName.Faddp_V,         InstEmit.Faddp_V,         OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxxxxxx01xxxxx0xxxx", InstName.Fccmp_S,         InstEmit.Fccmp_S,         OpCodeSimdFcond.Create);
+            SetA64("000111100x1xxxxxxxxx01xxxxx1xxxx", InstName.Fccmpe_S,        InstEmit.Fccmpe_S,        OpCodeSimdFcond.Create);
+            SetA64("010111100x1xxxxx111001xxxxxxxxxx", InstName.Fcmeq_S,         InstEmit.Fcmeq_S,         OpCodeSimdReg.Create);
+            SetA64("010111101x100000110110xxxxxxxxxx", InstName.Fcmeq_S,         InstEmit.Fcmeq_S,         OpCodeSimd.Create);
+            SetA64("0>0011100<1xxxxx111001xxxxxxxxxx", InstName.Fcmeq_V,         InstEmit.Fcmeq_V,         OpCodeSimdReg.Create);
+            SetA64("0>0011101<100000110110xxxxxxxxxx", InstName.Fcmeq_V,         InstEmit.Fcmeq_V,         OpCodeSimd.Create);
+            SetA64("011111100x1xxxxx111001xxxxxxxxxx", InstName.Fcmge_S,         InstEmit.Fcmge_S,         OpCodeSimdReg.Create);
+            SetA64("011111101x100000110010xxxxxxxxxx", InstName.Fcmge_S,         InstEmit.Fcmge_S,         OpCodeSimd.Create);
+            SetA64("0>1011100<1xxxxx111001xxxxxxxxxx", InstName.Fcmge_V,         InstEmit.Fcmge_V,         OpCodeSimdReg.Create);
+            SetA64("0>1011101<100000110010xxxxxxxxxx", InstName.Fcmge_V,         InstEmit.Fcmge_V,         OpCodeSimd.Create);
+            SetA64("011111101x1xxxxx111001xxxxxxxxxx", InstName.Fcmgt_S,         InstEmit.Fcmgt_S,         OpCodeSimdReg.Create);
+            SetA64("010111101x100000110010xxxxxxxxxx", InstName.Fcmgt_S,         InstEmit.Fcmgt_S,         OpCodeSimd.Create);
+            SetA64("0>1011101<1xxxxx111001xxxxxxxxxx", InstName.Fcmgt_V,         InstEmit.Fcmgt_V,         OpCodeSimdReg.Create);
+            SetA64("0>0011101<100000110010xxxxxxxxxx", InstName.Fcmgt_V,         InstEmit.Fcmgt_V,         OpCodeSimd.Create);
+            SetA64("011111101x100000110110xxxxxxxxxx", InstName.Fcmle_S,         InstEmit.Fcmle_S,         OpCodeSimd.Create);
+            SetA64("0>1011101<100000110110xxxxxxxxxx", InstName.Fcmle_V,         InstEmit.Fcmle_V,         OpCodeSimd.Create);
+            SetA64("010111101x100000111010xxxxxxxxxx", InstName.Fcmlt_S,         InstEmit.Fcmlt_S,         OpCodeSimd.Create);
+            SetA64("0>0011101<100000111010xxxxxxxxxx", InstName.Fcmlt_V,         InstEmit.Fcmlt_V,         OpCodeSimd.Create);
+            SetA64("000111100x1xxxxx001000xxxxx0x000", InstName.Fcmp_S,          InstEmit.Fcmp_S,          OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxx001000xxxxx1x000", InstName.Fcmpe_S,         InstEmit.Fcmpe_S,         OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxxxxxx11xxxxxxxxxx", InstName.Fcsel_S,         InstEmit.Fcsel_S,         OpCodeSimdFcond.Create);
+            SetA64("00011110xx10001xx10000xxxxxxxxxx", InstName.Fcvt_S,          InstEmit.Fcvt_S,          OpCodeSimd.Create);
+            SetA64("x00111100x100100000000xxxxxxxxxx", InstName.Fcvtas_Gp,       InstEmit.Fcvtas_Gp,       OpCodeSimdCvt.Create);
+            SetA64("010111100x100001110010xxxxxxxxxx", InstName.Fcvtas_S,        InstEmit.Fcvtas_S,        OpCodeSimd.Create);
+            SetA64("0>0011100<100001110010xxxxxxxxxx", InstName.Fcvtas_V,        InstEmit.Fcvtas_V,        OpCodeSimd.Create);
+            SetA64("x00111100x100101000000xxxxxxxxxx", InstName.Fcvtau_Gp,       InstEmit.Fcvtau_Gp,       OpCodeSimdCvt.Create);
+            SetA64("011111100x100001110010xxxxxxxxxx", InstName.Fcvtau_S,        InstEmit.Fcvtau_S,        OpCodeSimd.Create);
+            SetA64("0>1011100<100001110010xxxxxxxxxx", InstName.Fcvtau_V,        InstEmit.Fcvtau_V,        OpCodeSimd.Create);
+            SetA64("0x0011100x100001011110xxxxxxxxxx", InstName.Fcvtl_V,         InstEmit.Fcvtl_V,         OpCodeSimd.Create);
+            SetA64("x00111100x110000000000xxxxxxxxxx", InstName.Fcvtms_Gp,       InstEmit.Fcvtms_Gp,       OpCodeSimdCvt.Create);
+            SetA64("x00111100x110001000000xxxxxxxxxx", InstName.Fcvtmu_Gp,       InstEmit.Fcvtmu_Gp,       OpCodeSimdCvt.Create);
+            SetA64("0x0011100x100001011010xxxxxxxxxx", InstName.Fcvtn_V,         InstEmit.Fcvtn_V,         OpCodeSimd.Create);
+            SetA64("010111100x100001101010xxxxxxxxxx", InstName.Fcvtns_S,        InstEmit.Fcvtns_S,        OpCodeSimd.Create);
+            SetA64("0>0011100<100001101010xxxxxxxxxx", InstName.Fcvtns_V,        InstEmit.Fcvtns_V,        OpCodeSimd.Create);
+            SetA64("011111100x100001101010xxxxxxxxxx", InstName.Fcvtnu_S,        InstEmit.Fcvtnu_S,        OpCodeSimd.Create);
+            SetA64("0>1011100<100001101010xxxxxxxxxx", InstName.Fcvtnu_V,        InstEmit.Fcvtnu_V,        OpCodeSimd.Create);
+            SetA64("x00111100x101000000000xxxxxxxxxx", InstName.Fcvtps_Gp,       InstEmit.Fcvtps_Gp,       OpCodeSimdCvt.Create);
+            SetA64("x00111100x101001000000xxxxxxxxxx", InstName.Fcvtpu_Gp,       InstEmit.Fcvtpu_Gp,       OpCodeSimdCvt.Create);
+            SetA64("x00111100x111000000000xxxxxxxxxx", InstName.Fcvtzs_Gp,       InstEmit.Fcvtzs_Gp,       OpCodeSimdCvt.Create);
+            SetA64(">00111100x011000>xxxxxxxxxxxxxxx", InstName.Fcvtzs_Gp_Fixed, InstEmit.Fcvtzs_Gp_Fixed, OpCodeSimdCvt.Create);
+            SetA64("010111101x100001101110xxxxxxxxxx", InstName.Fcvtzs_S,        InstEmit.Fcvtzs_S,        OpCodeSimd.Create);
+            SetA64("0>0011101<100001101110xxxxxxxxxx", InstName.Fcvtzs_V,        InstEmit.Fcvtzs_V,        OpCodeSimd.Create);
+            SetA64("0x001111001xxxxx111111xxxxxxxxxx", InstName.Fcvtzs_V_Fixed,  InstEmit.Fcvtzs_V_Fixed,  OpCodeSimdShImm.Create);
+            SetA64("0100111101xxxxxx111111xxxxxxxxxx", InstName.Fcvtzs_V_Fixed,  InstEmit.Fcvtzs_V_Fixed,  OpCodeSimdShImm.Create);
+            SetA64("x00111100x111001000000xxxxxxxxxx", InstName.Fcvtzu_Gp,       InstEmit.Fcvtzu_Gp,       OpCodeSimdCvt.Create);
+            SetA64(">00111100x011001>xxxxxxxxxxxxxxx", InstName.Fcvtzu_Gp_Fixed, InstEmit.Fcvtzu_Gp_Fixed, OpCodeSimdCvt.Create);
+            SetA64("011111101x100001101110xxxxxxxxxx", InstName.Fcvtzu_S,        InstEmit.Fcvtzu_S,        OpCodeSimd.Create);
+            SetA64("0>1011101<100001101110xxxxxxxxxx", InstName.Fcvtzu_V,        InstEmit.Fcvtzu_V,        OpCodeSimd.Create);
+            SetA64("0x101111001xxxxx111111xxxxxxxxxx", InstName.Fcvtzu_V_Fixed,  InstEmit.Fcvtzu_V_Fixed,  OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx111111xxxxxxxxxx", InstName.Fcvtzu_V_Fixed,  InstEmit.Fcvtzu_V_Fixed,  OpCodeSimdShImm.Create);
+            SetA64("000111100x1xxxxx000110xxxxxxxxxx", InstName.Fdiv_S,          InstEmit.Fdiv_S,          OpCodeSimdReg.Create);
+            SetA64("0>1011100<1xxxxx111111xxxxxxxxxx", InstName.Fdiv_V,          InstEmit.Fdiv_V,          OpCodeSimdReg.Create);
+            SetA64("000111110x0xxxxx0xxxxxxxxxxxxxxx", InstName.Fmadd_S,         InstEmit.Fmadd_S,         OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxx010010xxxxxxxxxx", InstName.Fmax_S,          InstEmit.Fmax_S,          OpCodeSimdReg.Create);
+            SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", InstName.Fmax_V,          InstEmit.Fmax_V,          OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxx011010xxxxxxxxxx", InstName.Fmaxnm_S,        InstEmit.Fmaxnm_S,        OpCodeSimdReg.Create);
+            SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", InstName.Fmaxnm_V,        InstEmit.Fmaxnm_V,        OpCodeSimdReg.Create);
+            SetA64("0>1011100<1xxxxx110001xxxxxxxxxx", InstName.Fmaxnmp_V,       InstEmit.Fmaxnmp_V,       OpCodeSimdReg.Create);
+            SetA64("0110111000110000110010xxxxxxxxxx", InstName.Fmaxnmv_V,       InstEmit.Fmaxnmv_V,       OpCodeSimd.Create);
+            SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", InstName.Fmaxp_V,         InstEmit.Fmaxp_V,         OpCodeSimdReg.Create);
+            SetA64("0110111000110000111110xxxxxxxxxx", InstName.Fmaxv_V,         InstEmit.Fmaxv_V,         OpCodeSimd.Create);
+            SetA64("000111100x1xxxxx010110xxxxxxxxxx", InstName.Fmin_S,          InstEmit.Fmin_S,          OpCodeSimdReg.Create);
+            SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", InstName.Fmin_V,          InstEmit.Fmin_V,          OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxx011110xxxxxxxxxx", InstName.Fminnm_S,        InstEmit.Fminnm_S,        OpCodeSimdReg.Create);
+            SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", InstName.Fminnm_V,        InstEmit.Fminnm_V,        OpCodeSimdReg.Create);
+            SetA64("0>1011101<1xxxxx110001xxxxxxxxxx", InstName.Fminnmp_V,       InstEmit.Fminnmp_V,       OpCodeSimdReg.Create);
+            SetA64("0110111010110000110010xxxxxxxxxx", InstName.Fminnmv_V,       InstEmit.Fminnmv_V,       OpCodeSimd.Create);
+            SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", InstName.Fminp_V,         InstEmit.Fminp_V,         OpCodeSimdReg.Create);
+            SetA64("0110111010110000111110xxxxxxxxxx", InstName.Fminv_V,         InstEmit.Fminv_V,         OpCodeSimd.Create);
+            SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", InstName.Fmla_Se,         InstEmit.Fmla_Se,         OpCodeSimdRegElemF.Create);
+            SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", InstName.Fmla_V,          InstEmit.Fmla_V,          OpCodeSimdReg.Create);
+            SetA64("0>0011111<xxxxxx0001x0xxxxxxxxxx", InstName.Fmla_Ve,         InstEmit.Fmla_Ve,         OpCodeSimdRegElemF.Create);
+            SetA64("010111111xxxxxxx0101x0xxxxxxxxxx", InstName.Fmls_Se,         InstEmit.Fmls_Se,         OpCodeSimdRegElemF.Create);
+            SetA64("0>0011101<1xxxxx110011xxxxxxxxxx", InstName.Fmls_V,          InstEmit.Fmls_V,          OpCodeSimdReg.Create);
+            SetA64("0>0011111<xxxxxx0101x0xxxxxxxxxx", InstName.Fmls_Ve,         InstEmit.Fmls_Ve,         OpCodeSimdRegElemF.Create);
+            SetA64("000111100x100000010000xxxxxxxxxx", InstName.Fmov_S,          InstEmit.Fmov_S,          OpCodeSimd.Create);
+            SetA64("000111100x1xxxxxxxx10000000xxxxx", InstName.Fmov_Si,         InstEmit.Fmov_Si,         OpCodeSimdFmov.Create);
+            SetA64("0x00111100000xxx111101xxxxxxxxxx", InstName.Fmov_Vi,         InstEmit.Fmov_Vi,         OpCodeSimdImm.Create);
+            SetA64("0110111100000xxx111101xxxxxxxxxx", InstName.Fmov_Vi,         InstEmit.Fmov_Vi,         OpCodeSimdImm.Create);
+            SetA64("0001111000100110000000xxxxxxxxxx", InstName.Fmov_Ftoi,       InstEmit.Fmov_Ftoi,       OpCodeSimd.Create);
+            SetA64("1001111001100110000000xxxxxxxxxx", InstName.Fmov_Ftoi,       InstEmit.Fmov_Ftoi,       OpCodeSimd.Create);
+            SetA64("0001111000100111000000xxxxxxxxxx", InstName.Fmov_Itof,       InstEmit.Fmov_Itof,       OpCodeSimd.Create);
+            SetA64("1001111001100111000000xxxxxxxxxx", InstName.Fmov_Itof,       InstEmit.Fmov_Itof,       OpCodeSimd.Create);
+            SetA64("1001111010101110000000xxxxxxxxxx", InstName.Fmov_Ftoi1,      InstEmit.Fmov_Ftoi1,      OpCodeSimd.Create);
+            SetA64("1001111010101111000000xxxxxxxxxx", InstName.Fmov_Itof1,      InstEmit.Fmov_Itof1,      OpCodeSimd.Create);
+            SetA64("000111110x0xxxxx1xxxxxxxxxxxxxxx", InstName.Fmsub_S,         InstEmit.Fmsub_S,         OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxx000010xxxxxxxxxx", InstName.Fmul_S,          InstEmit.Fmul_S,          OpCodeSimdReg.Create);
+            SetA64("010111111xxxxxxx1001x0xxxxxxxxxx", InstName.Fmul_Se,         InstEmit.Fmul_Se,         OpCodeSimdRegElemF.Create);
+            SetA64("0>1011100<1xxxxx110111xxxxxxxxxx", InstName.Fmul_V,          InstEmit.Fmul_V,          OpCodeSimdReg.Create);
+            SetA64("0>0011111<xxxxxx1001x0xxxxxxxxxx", InstName.Fmul_Ve,         InstEmit.Fmul_Ve,         OpCodeSimdRegElemF.Create);
+            SetA64("010111100x1xxxxx110111xxxxxxxxxx", InstName.Fmulx_S,         InstEmit.Fmulx_S,         OpCodeSimdReg.Create);
+            SetA64("011111111xxxxxxx1001x0xxxxxxxxxx", InstName.Fmulx_Se,        InstEmit.Fmulx_Se,        OpCodeSimdRegElemF.Create);
+            SetA64("0>0011100<1xxxxx110111xxxxxxxxxx", InstName.Fmulx_V,         InstEmit.Fmulx_V,         OpCodeSimdReg.Create);
+            SetA64("0>1011111<xxxxxx1001x0xxxxxxxxxx", InstName.Fmulx_Ve,        InstEmit.Fmulx_Ve,        OpCodeSimdRegElemF.Create);
+            SetA64("000111100x100001010000xxxxxxxxxx", InstName.Fneg_S,          InstEmit.Fneg_S,          OpCodeSimd.Create);
+            SetA64("0>1011101<100000111110xxxxxxxxxx", InstName.Fneg_V,          InstEmit.Fneg_V,          OpCodeSimd.Create);
+            SetA64("000111110x1xxxxx0xxxxxxxxxxxxxxx", InstName.Fnmadd_S,        InstEmit.Fnmadd_S,        OpCodeSimdReg.Create);
+            SetA64("000111110x1xxxxx1xxxxxxxxxxxxxxx", InstName.Fnmsub_S,        InstEmit.Fnmsub_S,        OpCodeSimdReg.Create);
+            SetA64("000111100x1xxxxx100010xxxxxxxxxx", InstName.Fnmul_S,         InstEmit.Fnmul_S,         OpCodeSimdReg.Create);
+            SetA64("010111101x100001110110xxxxxxxxxx", InstName.Frecpe_S,        InstEmit.Frecpe_S,        OpCodeSimd.Create);
+            SetA64("0>0011101<100001110110xxxxxxxxxx", InstName.Frecpe_V,        InstEmit.Frecpe_V,        OpCodeSimd.Create);
+            SetA64("010111100x1xxxxx111111xxxxxxxxxx", InstName.Frecps_S,        InstEmit.Frecps_S,        OpCodeSimdReg.Create);
+            SetA64("0>0011100<1xxxxx111111xxxxxxxxxx", InstName.Frecps_V,        InstEmit.Frecps_V,        OpCodeSimdReg.Create);
+            SetA64("010111101x100001111110xxxxxxxxxx", InstName.Frecpx_S,        InstEmit.Frecpx_S,        OpCodeSimd.Create);
+            SetA64("000111100x100110010000xxxxxxxxxx", InstName.Frinta_S,        InstEmit.Frinta_S,        OpCodeSimd.Create);
+            SetA64("0>1011100<100001100010xxxxxxxxxx", InstName.Frinta_V,        InstEmit.Frinta_V,        OpCodeSimd.Create);
+            SetA64("000111100x100111110000xxxxxxxxxx", InstName.Frinti_S,        InstEmit.Frinti_S,        OpCodeSimd.Create);
+            SetA64("0>1011101<100001100110xxxxxxxxxx", InstName.Frinti_V,        InstEmit.Frinti_V,        OpCodeSimd.Create);
+            SetA64("000111100x100101010000xxxxxxxxxx", InstName.Frintm_S,        InstEmit.Frintm_S,        OpCodeSimd.Create);
+            SetA64("0>0011100<100001100110xxxxxxxxxx", InstName.Frintm_V,        InstEmit.Frintm_V,        OpCodeSimd.Create);
+            SetA64("000111100x100100010000xxxxxxxxxx", InstName.Frintn_S,        InstEmit.Frintn_S,        OpCodeSimd.Create);
+            SetA64("0>0011100<100001100010xxxxxxxxxx", InstName.Frintn_V,        InstEmit.Frintn_V,        OpCodeSimd.Create);
+            SetA64("000111100x100100110000xxxxxxxxxx", InstName.Frintp_S,        InstEmit.Frintp_S,        OpCodeSimd.Create);
+            SetA64("0>0011101<100001100010xxxxxxxxxx", InstName.Frintp_V,        InstEmit.Frintp_V,        OpCodeSimd.Create);
+            SetA64("000111100x100111010000xxxxxxxxxx", InstName.Frintx_S,        InstEmit.Frintx_S,        OpCodeSimd.Create);
+            SetA64("0>1011100<100001100110xxxxxxxxxx", InstName.Frintx_V,        InstEmit.Frintx_V,        OpCodeSimd.Create);
+            SetA64("000111100x100101110000xxxxxxxxxx", InstName.Frintz_S,        InstEmit.Frintz_S,        OpCodeSimd.Create);
+            SetA64("0>0011101<100001100110xxxxxxxxxx", InstName.Frintz_V,        InstEmit.Frintz_V,        OpCodeSimd.Create);
+            SetA64("011111101x100001110110xxxxxxxxxx", InstName.Frsqrte_S,       InstEmit.Frsqrte_S,       OpCodeSimd.Create);
+            SetA64("0>1011101<100001110110xxxxxxxxxx", InstName.Frsqrte_V,       InstEmit.Frsqrte_V,       OpCodeSimd.Create);
+            SetA64("010111101x1xxxxx111111xxxxxxxxxx", InstName.Frsqrts_S,       InstEmit.Frsqrts_S,       OpCodeSimdReg.Create);
+            SetA64("0>0011101<1xxxxx111111xxxxxxxxxx", InstName.Frsqrts_V,       InstEmit.Frsqrts_V,       OpCodeSimdReg.Create);
+            SetA64("000111100x100001110000xxxxxxxxxx", InstName.Fsqrt_S,         InstEmit.Fsqrt_S,         OpCodeSimd.Create);
+            SetA64("0>1011101<100001111110xxxxxxxxxx", InstName.Fsqrt_V,         InstEmit.Fsqrt_V,         OpCodeSimd.Create);
+            SetA64("000111100x1xxxxx001110xxxxxxxxxx", InstName.Fsub_S,          InstEmit.Fsub_S,          OpCodeSimdReg.Create);
+            SetA64("0>0011101<1xxxxx110101xxxxxxxxxx", InstName.Fsub_V,          InstEmit.Fsub_V,          OpCodeSimdReg.Create);
+            SetA64("01001110000xxxxx000111xxxxxxxxxx", InstName.Ins_Gp,          InstEmit.Ins_Gp,          OpCodeSimdIns.Create);
+            SetA64("01101110000xxxxx0xxxx1xxxxxxxxxx", InstName.Ins_V,           InstEmit.Ins_V,           OpCodeSimdIns.Create);
+            SetA64("0x00110001000000xxxxxxxxxxxxxxxx", InstName.Ld__Vms,         InstEmit.Ld__Vms,         OpCodeSimdMemMs.Create);
+            SetA64("0x001100110xxxxxxxxxxxxxxxxxxxxx", InstName.Ld__Vms,         InstEmit.Ld__Vms,         OpCodeSimdMemMs.Create);
+            SetA64("0x00110101x00000xxxxxxxxxxxxxxxx", InstName.Ld__Vss,         InstEmit.Ld__Vss,         OpCodeSimdMemSs.Create);
+            SetA64("0x00110111xxxxxxxxxxxxxxxxxxxxxx", InstName.Ld__Vss,         InstEmit.Ld__Vss,         OpCodeSimdMemSs.Create);
+            SetA64("<<10110xx1xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldp,             InstEmit.Ldp,             OpCodeSimdMemPair.Create);
+            SetA64("xx111100x10xxxxxxxxx00xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeSimdMemImm.Create);
+            SetA64("xx111100x10xxxxxxxxx01xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeSimdMemImm.Create);
+            SetA64("xx111100x10xxxxxxxxx11xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeSimdMemImm.Create);
+            SetA64("xx111101x1xxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeSimdMemImm.Create);
+            SetA64("xx111100x11xxxxxx1xx10xxxxxxxxxx", InstName.Ldr,             InstEmit.Ldr,             OpCodeSimdMemReg.Create);
+            SetA64("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ldr_Literal,     InstEmit.Ldr_Literal,     OpCodeSimdMemLit.Create);
+            SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", InstName.Mla_V,           InstEmit.Mla_V,           OpCodeSimdReg.Create);
+            SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", InstName.Mla_Ve,          InstEmit.Mla_Ve,          OpCodeSimdRegElem.Create);
+            SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", InstName.Mls_V,           InstEmit.Mls_V,           OpCodeSimdReg.Create);
+            SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", InstName.Mls_Ve,          InstEmit.Mls_Ve,          OpCodeSimdRegElem.Create);
+            SetA64("0x00111100000xxx0xx001xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          OpCodeSimdImm.Create);
+            SetA64("0x00111100000xxx10x001xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          OpCodeSimdImm.Create);
+            SetA64("0x00111100000xxx110x01xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          OpCodeSimdImm.Create);
+            SetA64("0xx0111100000xxx111001xxxxxxxxxx", InstName.Movi_V,          InstEmit.Movi_V,          OpCodeSimdImm.Create);
+            SetA64("0x001110<<1xxxxx100111xxxxxxxxxx", InstName.Mul_V,           InstEmit.Mul_V,           OpCodeSimdReg.Create);
+            SetA64("0x001111xxxxxxxx1000x0xxxxxxxxxx", InstName.Mul_Ve,          InstEmit.Mul_Ve,          OpCodeSimdRegElem.Create);
+            SetA64("0x10111100000xxx0xx001xxxxxxxxxx", InstName.Mvni_V,          InstEmit.Mvni_V,          OpCodeSimdImm.Create);
+            SetA64("0x10111100000xxx10x001xxxxxxxxxx", InstName.Mvni_V,          InstEmit.Mvni_V,          OpCodeSimdImm.Create);
+            SetA64("0x10111100000xxx110x01xxxxxxxxxx", InstName.Mvni_V,          InstEmit.Mvni_V,          OpCodeSimdImm.Create);
+            SetA64("0111111011100000101110xxxxxxxxxx", InstName.Neg_S,           InstEmit.Neg_S,           OpCodeSimd.Create);
+            SetA64("0>101110<<100000101110xxxxxxxxxx", InstName.Neg_V,           InstEmit.Neg_V,           OpCodeSimd.Create);
+            SetA64("0x10111000100000010110xxxxxxxxxx", InstName.Not_V,           InstEmit.Not_V,           OpCodeSimd.Create);
+            SetA64("0x001110111xxxxx000111xxxxxxxxxx", InstName.Orn_V,           InstEmit.Orn_V,           OpCodeSimdReg.Create);
+            SetA64("0x001110101xxxxx000111xxxxxxxxxx", InstName.Orr_V,           InstEmit.Orr_V,           OpCodeSimdReg.Create);
+            SetA64("0x00111100000xxx0xx101xxxxxxxxxx", InstName.Orr_Vi,          InstEmit.Orr_Vi,          OpCodeSimdImm.Create);
+            SetA64("0x00111100000xxx10x101xxxxxxxxxx", InstName.Orr_Vi,          InstEmit.Orr_Vi,          OpCodeSimdImm.Create);
+            SetA64("0x101110<<1xxxxx010000xxxxxxxxxx", InstName.Raddhn_V,        InstEmit.Raddhn_V,        OpCodeSimdReg.Create);
+            SetA64("0x10111001100000010110xxxxxxxxxx", InstName.Rbit_V,          InstEmit.Rbit_V,          OpCodeSimd.Create);
+            SetA64("0x00111000100000000110xxxxxxxxxx", InstName.Rev16_V,         InstEmit.Rev16_V,         OpCodeSimd.Create);
+            SetA64("0x1011100x100000000010xxxxxxxxxx", InstName.Rev32_V,         InstEmit.Rev32_V,         OpCodeSimd.Create);
+            SetA64("0x001110<<100000000010xxxxxxxxxx", InstName.Rev64_V,         InstEmit.Rev64_V,         OpCodeSimd.Create);
+            SetA64("0x00111100>>>xxx100011xxxxxxxxxx", InstName.Rshrn_V,         InstEmit.Rshrn_V,         OpCodeSimdShImm.Create);
+            SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", InstName.Rsubhn_V,        InstEmit.Rsubhn_V,        OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", InstName.Saba_V,          InstEmit.Saba_V,          OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", InstName.Sabal_V,         InstEmit.Sabal_V,         OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", InstName.Sabd_V,          InstEmit.Sabd_V,          OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", InstName.Sabdl_V,         InstEmit.Sabdl_V,         OpCodeSimdReg.Create);
+            SetA64("0x001110<<100000011010xxxxxxxxxx", InstName.Sadalp_V,        InstEmit.Sadalp_V,        OpCodeSimd.Create);
+            SetA64("0x001110<<1xxxxx000000xxxxxxxxxx", InstName.Saddl_V,         InstEmit.Saddl_V,         OpCodeSimdReg.Create);
+            SetA64("0x001110<<100000001010xxxxxxxxxx", InstName.Saddlp_V,        InstEmit.Saddlp_V,        OpCodeSimd.Create);
+            SetA64("000011100x110000001110xxxxxxxxxx", InstName.Saddlv_V,        InstEmit.Saddlv_V,        OpCodeSimd.Create);
+            SetA64("01001110<<110000001110xxxxxxxxxx", InstName.Saddlv_V,        InstEmit.Saddlv_V,        OpCodeSimd.Create);
+            SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", InstName.Saddw_V,         InstEmit.Saddw_V,         OpCodeSimdReg.Create);
+            SetA64("x00111100x100010000000xxxxxxxxxx", InstName.Scvtf_Gp,        InstEmit.Scvtf_Gp,        OpCodeSimdCvt.Create);
+            SetA64(">00111100x000010>xxxxxxxxxxxxxxx", InstName.Scvtf_Gp_Fixed,  InstEmit.Scvtf_Gp_Fixed,  OpCodeSimdCvt.Create);
+            SetA64("010111100x100001110110xxxxxxxxxx", InstName.Scvtf_S,         InstEmit.Scvtf_S,         OpCodeSimd.Create);
+            SetA64("010111110>>xxxxx111001xxxxxxxxxx", InstName.Scvtf_S_Fixed,   InstEmit.Scvtf_S_Fixed,   OpCodeSimdShImm.Create);
+            SetA64("0>0011100<100001110110xxxxxxxxxx", InstName.Scvtf_V,         InstEmit.Scvtf_V,         OpCodeSimd.Create);
+            SetA64("0x001111001xxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed,   InstEmit.Scvtf_V_Fixed,   OpCodeSimdShImm.Create);
+            SetA64("0100111101xxxxxx111001xxxxxxxxxx", InstName.Scvtf_V_Fixed,   InstEmit.Scvtf_V_Fixed,   OpCodeSimdShImm.Create);
+            SetA64("01011110000xxxxx000000xxxxxxxxxx", InstName.Sha1c_V,         InstEmit.Sha1c_V,         OpCodeSimdReg.Create);
+            SetA64("0101111000101000000010xxxxxxxxxx", InstName.Sha1h_V,         InstEmit.Sha1h_V,         OpCodeSimd.Create);
+            SetA64("01011110000xxxxx001000xxxxxxxxxx", InstName.Sha1m_V,         InstEmit.Sha1m_V,         OpCodeSimdReg.Create);
+            SetA64("01011110000xxxxx000100xxxxxxxxxx", InstName.Sha1p_V,         InstEmit.Sha1p_V,         OpCodeSimdReg.Create);
+            SetA64("01011110000xxxxx001100xxxxxxxxxx", InstName.Sha1su0_V,       InstEmit.Sha1su0_V,       OpCodeSimdReg.Create);
+            SetA64("0101111000101000000110xxxxxxxxxx", InstName.Sha1su1_V,       InstEmit.Sha1su1_V,       OpCodeSimd.Create);
+            SetA64("01011110000xxxxx010000xxxxxxxxxx", InstName.Sha256h_V,       InstEmit.Sha256h_V,       OpCodeSimdReg.Create);
+            SetA64("01011110000xxxxx010100xxxxxxxxxx", InstName.Sha256h2_V,      InstEmit.Sha256h2_V,      OpCodeSimdReg.Create);
+            SetA64("0101111000101000001010xxxxxxxxxx", InstName.Sha256su0_V,     InstEmit.Sha256su0_V,     OpCodeSimd.Create);
+            SetA64("01011110000xxxxx011000xxxxxxxxxx", InstName.Sha256su1_V,     InstEmit.Sha256su1_V,     OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", InstName.Shadd_V,         InstEmit.Shadd_V,         OpCodeSimdReg.Create);
+            SetA64("0101111101xxxxxx010101xxxxxxxxxx", InstName.Shl_S,           InstEmit.Shl_S,           OpCodeSimdShImm.Create);
+            SetA64("0x00111100>>>xxx010101xxxxxxxxxx", InstName.Shl_V,           InstEmit.Shl_V,           OpCodeSimdShImm.Create);
+            SetA64("0100111101xxxxxx010101xxxxxxxxxx", InstName.Shl_V,           InstEmit.Shl_V,           OpCodeSimdShImm.Create);
+            SetA64("0x101110<<100001001110xxxxxxxxxx", InstName.Shll_V,          InstEmit.Shll_V,          OpCodeSimd.Create);
+            SetA64("0x00111100>>>xxx100001xxxxxxxxxx", InstName.Shrn_V,          InstEmit.Shrn_V,          OpCodeSimdShImm.Create);
+            SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", InstName.Shsub_V,         InstEmit.Shsub_V,         OpCodeSimdReg.Create);
+            SetA64("0111111101xxxxxx010101xxxxxxxxxx", InstName.Sli_S,           InstEmit.Sli_S,           OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx010101xxxxxxxxxx", InstName.Sli_V,           InstEmit.Sli_V,           OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx010101xxxxxxxxxx", InstName.Sli_V,           InstEmit.Sli_V,           OpCodeSimdShImm.Create);
+            SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", InstName.Smax_V,          InstEmit.Smax_V,          OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", InstName.Smaxp_V,         InstEmit.Smaxp_V,         OpCodeSimdReg.Create);
+            SetA64("000011100x110000101010xxxxxxxxxx", InstName.Smaxv_V,         InstEmit.Smaxv_V,         OpCodeSimd.Create);
+            SetA64("01001110<<110000101010xxxxxxxxxx", InstName.Smaxv_V,         InstEmit.Smaxv_V,         OpCodeSimd.Create);
+            SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", InstName.Smin_V,          InstEmit.Smin_V,          OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", InstName.Sminp_V,         InstEmit.Sminp_V,         OpCodeSimdReg.Create);
+            SetA64("000011100x110001101010xxxxxxxxxx", InstName.Sminv_V,         InstEmit.Sminv_V,         OpCodeSimd.Create);
+            SetA64("01001110<<110001101010xxxxxxxxxx", InstName.Sminv_V,         InstEmit.Sminv_V,         OpCodeSimd.Create);
+            SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", InstName.Smlal_V,         InstEmit.Smlal_V,         OpCodeSimdReg.Create);
+            SetA64("0x001111xxxxxxxx0010x0xxxxxxxxxx", InstName.Smlal_Ve,        InstEmit.Smlal_Ve,        OpCodeSimdRegElem.Create);
+            SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", InstName.Smlsl_V,         InstEmit.Smlsl_V,         OpCodeSimdReg.Create);
+            SetA64("0x001111xxxxxxxx0110x0xxxxxxxxxx", InstName.Smlsl_Ve,        InstEmit.Smlsl_Ve,        OpCodeSimdRegElem.Create);
+            SetA64("0x001110000xxxxx001011xxxxxxxxxx", InstName.Smov_S,          InstEmit.Smov_S,          OpCodeSimdIns.Create);
+            SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", InstName.Smull_V,         InstEmit.Smull_V,         OpCodeSimdReg.Create);
+            SetA64("0x001111xxxxxxxx1010x0xxxxxxxxxx", InstName.Smull_Ve,        InstEmit.Smull_Ve,        OpCodeSimdRegElem.Create);
+            SetA64("01011110xx100000011110xxxxxxxxxx", InstName.Sqabs_S,         InstEmit.Sqabs_S,         OpCodeSimd.Create);
+            SetA64("0>001110<<100000011110xxxxxxxxxx", InstName.Sqabs_V,         InstEmit.Sqabs_V,         OpCodeSimd.Create);
+            SetA64("01011110xx1xxxxx000011xxxxxxxxxx", InstName.Sqadd_S,         InstEmit.Sqadd_S,         OpCodeSimdReg.Create);
+            SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", InstName.Sqadd_V,         InstEmit.Sqadd_V,         OpCodeSimdReg.Create);
+            SetA64("01011110011xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_S,       InstEmit.Sqdmulh_S,       OpCodeSimdReg.Create);
+            SetA64("01011110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_S,       InstEmit.Sqdmulh_S,       OpCodeSimdReg.Create);
+            SetA64("0x001110011xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V,       InstEmit.Sqdmulh_V,       OpCodeSimdReg.Create);
+            SetA64("0x001110101xxxxx101101xxxxxxxxxx", InstName.Sqdmulh_V,       InstEmit.Sqdmulh_V,       OpCodeSimdReg.Create);
+            SetA64("01111110xx100000011110xxxxxxxxxx", InstName.Sqneg_S,         InstEmit.Sqneg_S,         OpCodeSimd.Create);
+            SetA64("0>101110<<100000011110xxxxxxxxxx", InstName.Sqneg_V,         InstEmit.Sqneg_V,         OpCodeSimd.Create);
+            SetA64("01111110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S,      InstEmit.Sqrdmulh_S,      OpCodeSimdReg.Create);
+            SetA64("01111110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_S,      InstEmit.Sqrdmulh_S,      OpCodeSimdReg.Create);
+            SetA64("0x101110011xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V,      InstEmit.Sqrdmulh_V,      OpCodeSimdReg.Create);
+            SetA64("0x101110101xxxxx101101xxxxxxxxxx", InstName.Sqrdmulh_V,      InstEmit.Sqrdmulh_V,      OpCodeSimdReg.Create);
+            SetA64("0>001110<<1xxxxx010111xxxxxxxxxx", InstName.Sqrshl_V,        InstEmit.Sqrshl_V,        OpCodeSimdReg.Create);
+            SetA64("0101111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_S,       InstEmit.Sqrshrn_S,       OpCodeSimdShImm.Create);
+            SetA64("0x00111100>>>xxx100111xxxxxxxxxx", InstName.Sqrshrn_V,       InstEmit.Sqrshrn_V,       OpCodeSimdShImm.Create);
+            SetA64("0111111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_S,      InstEmit.Sqrshrun_S,      OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx100011xxxxxxxxxx", InstName.Sqrshrun_V,      InstEmit.Sqrshrun_V,      OpCodeSimdShImm.Create);
+            SetA64("0>001110<<1xxxxx010011xxxxxxxxxx", InstName.Sqshl_V,         InstEmit.Sqshl_V,         OpCodeSimdReg.Create);
+            SetA64("0101111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_S,        InstEmit.Sqshrn_S,        OpCodeSimdShImm.Create);
+            SetA64("0x00111100>>>xxx100101xxxxxxxxxx", InstName.Sqshrn_V,        InstEmit.Sqshrn_V,        OpCodeSimdShImm.Create);
+            SetA64("0111111100>>>xxx100001xxxxxxxxxx", InstName.Sqshrun_S,       InstEmit.Sqshrun_S,       OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx100001xxxxxxxxxx", InstName.Sqshrun_V,       InstEmit.Sqshrun_V,       OpCodeSimdShImm.Create);
+            SetA64("01011110xx1xxxxx001011xxxxxxxxxx", InstName.Sqsub_S,         InstEmit.Sqsub_S,         OpCodeSimdReg.Create);
+            SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", InstName.Sqsub_V,         InstEmit.Sqsub_V,         OpCodeSimdReg.Create);
+            SetA64("01011110<<100001010010xxxxxxxxxx", InstName.Sqxtn_S,         InstEmit.Sqxtn_S,         OpCodeSimd.Create);
+            SetA64("0x001110<<100001010010xxxxxxxxxx", InstName.Sqxtn_V,         InstEmit.Sqxtn_V,         OpCodeSimd.Create);
+            SetA64("01111110<<100001001010xxxxxxxxxx", InstName.Sqxtun_S,        InstEmit.Sqxtun_S,        OpCodeSimd.Create);
+            SetA64("0x101110<<100001001010xxxxxxxxxx", InstName.Sqxtun_V,        InstEmit.Sqxtun_V,        OpCodeSimd.Create);
+            SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", InstName.Srhadd_V,        InstEmit.Srhadd_V,        OpCodeSimdReg.Create);
+            SetA64("0111111101xxxxxx010001xxxxxxxxxx", InstName.Sri_S,           InstEmit.Sri_S,           OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx010001xxxxxxxxxx", InstName.Sri_V,           InstEmit.Sri_V,           OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx010001xxxxxxxxxx", InstName.Sri_V,           InstEmit.Sri_V,           OpCodeSimdShImm.Create);
+            SetA64("0>001110<<1xxxxx010101xxxxxxxxxx", InstName.Srshl_V,         InstEmit.Srshl_V,         OpCodeSimdReg.Create);
+            SetA64("0101111101xxxxxx001001xxxxxxxxxx", InstName.Srshr_S,         InstEmit.Srshr_S,         OpCodeSimdShImm.Create);
+            SetA64("0x00111100>>>xxx001001xxxxxxxxxx", InstName.Srshr_V,         InstEmit.Srshr_V,         OpCodeSimdShImm.Create);
+            SetA64("0100111101xxxxxx001001xxxxxxxxxx", InstName.Srshr_V,         InstEmit.Srshr_V,         OpCodeSimdShImm.Create);
+            SetA64("0101111101xxxxxx001101xxxxxxxxxx", InstName.Srsra_S,         InstEmit.Srsra_S,         OpCodeSimdShImm.Create);
+            SetA64("0x00111100>>>xxx001101xxxxxxxxxx", InstName.Srsra_V,         InstEmit.Srsra_V,         OpCodeSimdShImm.Create);
+            SetA64("0100111101xxxxxx001101xxxxxxxxxx", InstName.Srsra_V,         InstEmit.Srsra_V,         OpCodeSimdShImm.Create);
+            SetA64("01011110111xxxxx010001xxxxxxxxxx", InstName.Sshl_S,          InstEmit.Sshl_S,          OpCodeSimdReg.Create);
+            SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", InstName.Sshl_V,          InstEmit.Sshl_V,          OpCodeSimdReg.Create);
+            SetA64("0x00111100>>>xxx101001xxxxxxxxxx", InstName.Sshll_V,         InstEmit.Sshll_V,         OpCodeSimdShImm.Create);
+            SetA64("0101111101xxxxxx000001xxxxxxxxxx", InstName.Sshr_S,          InstEmit.Sshr_S,          OpCodeSimdShImm.Create);
+            SetA64("0x00111100>>>xxx000001xxxxxxxxxx", InstName.Sshr_V,          InstEmit.Sshr_V,          OpCodeSimdShImm.Create);
+            SetA64("0100111101xxxxxx000001xxxxxxxxxx", InstName.Sshr_V,          InstEmit.Sshr_V,          OpCodeSimdShImm.Create);
+            SetA64("0101111101xxxxxx000101xxxxxxxxxx", InstName.Ssra_S,          InstEmit.Ssra_S,          OpCodeSimdShImm.Create);
+            SetA64("0x00111100>>>xxx000101xxxxxxxxxx", InstName.Ssra_V,          InstEmit.Ssra_V,          OpCodeSimdShImm.Create);
+            SetA64("0100111101xxxxxx000101xxxxxxxxxx", InstName.Ssra_V,          InstEmit.Ssra_V,          OpCodeSimdShImm.Create);
+            SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", InstName.Ssubl_V,         InstEmit.Ssubl_V,         OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx001100xxxxxxxxxx", InstName.Ssubw_V,         InstEmit.Ssubw_V,         OpCodeSimdReg.Create);
+            SetA64("0x00110000000000xxxxxxxxxxxxxxxx", InstName.St__Vms,         InstEmit.St__Vms,         OpCodeSimdMemMs.Create);
+            SetA64("0x001100100xxxxxxxxxxxxxxxxxxxxx", InstName.St__Vms,         InstEmit.St__Vms,         OpCodeSimdMemMs.Create);
+            SetA64("0x00110100x00000xxxxxxxxxxxxxxxx", InstName.St__Vss,         InstEmit.St__Vss,         OpCodeSimdMemSs.Create);
+            SetA64("0x00110110xxxxxxxxxxxxxxxxxxxxxx", InstName.St__Vss,         InstEmit.St__Vss,         OpCodeSimdMemSs.Create);
+            SetA64("<<10110xx0xxxxxxxxxxxxxxxxxxxxxx", InstName.Stp,             InstEmit.Stp,             OpCodeSimdMemPair.Create);
+            SetA64("xx111100x00xxxxxxxxx00xxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeSimdMemImm.Create);
+            SetA64("xx111100x00xxxxxxxxx01xxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeSimdMemImm.Create);
+            SetA64("xx111100x00xxxxxxxxx11xxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeSimdMemImm.Create);
+            SetA64("xx111101x0xxxxxxxxxxxxxxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeSimdMemImm.Create);
+            SetA64("xx111100x01xxxxxx1xx10xxxxxxxxxx", InstName.Str,             InstEmit.Str,             OpCodeSimdMemReg.Create);
+            SetA64("01111110111xxxxx100001xxxxxxxxxx", InstName.Sub_S,           InstEmit.Sub_S,           OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx100001xxxxxxxxxx", InstName.Sub_V,           InstEmit.Sub_V,           OpCodeSimdReg.Create);
+            SetA64("0x001110<<1xxxxx011000xxxxxxxxxx", InstName.Subhn_V,         InstEmit.Subhn_V,         OpCodeSimdReg.Create);
+            SetA64("01011110xx100000001110xxxxxxxxxx", InstName.Suqadd_S,        InstEmit.Suqadd_S,        OpCodeSimd.Create);
+            SetA64("0>001110<<100000001110xxxxxxxxxx", InstName.Suqadd_V,        InstEmit.Suqadd_V,        OpCodeSimd.Create);
+            SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", InstName.Tbl_V,           InstEmit.Tbl_V,           OpCodeSimdTbl.Create);
+            SetA64("0x001110000xxxxx0xx100xxxxxxxxxx", InstName.Tbx_V,           InstEmit.Tbx_V,           OpCodeSimdTbl.Create);
+            SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", InstName.Trn1_V,          InstEmit.Trn1_V,          OpCodeSimdReg.Create);
+            SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", InstName.Trn2_V,          InstEmit.Trn2_V,          OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx011111xxxxxxxxxx", InstName.Uaba_V,          InstEmit.Uaba_V,          OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", InstName.Uabal_V,         InstEmit.Uabal_V,         OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", InstName.Uabd_V,          InstEmit.Uabd_V,          OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", InstName.Uabdl_V,         InstEmit.Uabdl_V,         OpCodeSimdReg.Create);
+            SetA64("0x101110<<100000011010xxxxxxxxxx", InstName.Uadalp_V,        InstEmit.Uadalp_V,        OpCodeSimd.Create);
+            SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", InstName.Uaddl_V,         InstEmit.Uaddl_V,         OpCodeSimdReg.Create);
+            SetA64("0x101110<<100000001010xxxxxxxxxx", InstName.Uaddlp_V,        InstEmit.Uaddlp_V,        OpCodeSimd.Create);
+            SetA64("001011100x110000001110xxxxxxxxxx", InstName.Uaddlv_V,        InstEmit.Uaddlv_V,        OpCodeSimd.Create);
+            SetA64("01101110<<110000001110xxxxxxxxxx", InstName.Uaddlv_V,        InstEmit.Uaddlv_V,        OpCodeSimd.Create);
+            SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", InstName.Uaddw_V,         InstEmit.Uaddw_V,         OpCodeSimdReg.Create);
+            SetA64("x00111100x100011000000xxxxxxxxxx", InstName.Ucvtf_Gp,        InstEmit.Ucvtf_Gp,        OpCodeSimdCvt.Create);
+            SetA64(">00111100x000011>xxxxxxxxxxxxxxx", InstName.Ucvtf_Gp_Fixed,  InstEmit.Ucvtf_Gp_Fixed,  OpCodeSimdCvt.Create);
+            SetA64("011111100x100001110110xxxxxxxxxx", InstName.Ucvtf_S,         InstEmit.Ucvtf_S,         OpCodeSimd.Create);
+            SetA64("011111110>>xxxxx111001xxxxxxxxxx", InstName.Ucvtf_S_Fixed,   InstEmit.Ucvtf_S_Fixed,   OpCodeSimdShImm.Create);
+            SetA64("0>1011100<100001110110xxxxxxxxxx", InstName.Ucvtf_V,         InstEmit.Ucvtf_V,         OpCodeSimd.Create);
+            SetA64("0x101111001xxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed,   InstEmit.Ucvtf_V_Fixed,   OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx111001xxxxxxxxxx", InstName.Ucvtf_V_Fixed,   InstEmit.Ucvtf_V_Fixed,   OpCodeSimdShImm.Create);
+            SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", InstName.Uhadd_V,         InstEmit.Uhadd_V,         OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", InstName.Uhsub_V,         InstEmit.Uhsub_V,         OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", InstName.Umax_V,          InstEmit.Umax_V,          OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", InstName.Umaxp_V,         InstEmit.Umaxp_V,         OpCodeSimdReg.Create);
+            SetA64("001011100x110000101010xxxxxxxxxx", InstName.Umaxv_V,         InstEmit.Umaxv_V,         OpCodeSimd.Create);
+            SetA64("01101110<<110000101010xxxxxxxxxx", InstName.Umaxv_V,         InstEmit.Umaxv_V,         OpCodeSimd.Create);
+            SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", InstName.Umin_V,          InstEmit.Umin_V,          OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", InstName.Uminp_V,         InstEmit.Uminp_V,         OpCodeSimdReg.Create);
+            SetA64("001011100x110001101010xxxxxxxxxx", InstName.Uminv_V,         InstEmit.Uminv_V,         OpCodeSimd.Create);
+            SetA64("01101110<<110001101010xxxxxxxxxx", InstName.Uminv_V,         InstEmit.Uminv_V,         OpCodeSimd.Create);
+            SetA64("0x101110<<1xxxxx100000xxxxxxxxxx", InstName.Umlal_V,         InstEmit.Umlal_V,         OpCodeSimdReg.Create);
+            SetA64("0x101111xxxxxxxx0010x0xxxxxxxxxx", InstName.Umlal_Ve,        InstEmit.Umlal_Ve,        OpCodeSimdRegElem.Create);
+            SetA64("0x101110<<1xxxxx101000xxxxxxxxxx", InstName.Umlsl_V,         InstEmit.Umlsl_V,         OpCodeSimdReg.Create);
+            SetA64("0x101111xxxxxxxx0110x0xxxxxxxxxx", InstName.Umlsl_Ve,        InstEmit.Umlsl_Ve,        OpCodeSimdRegElem.Create);
+            SetA64("0x001110000xxxxx001111xxxxxxxxxx", InstName.Umov_S,          InstEmit.Umov_S,          OpCodeSimdIns.Create);
+            SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", InstName.Umull_V,         InstEmit.Umull_V,         OpCodeSimdReg.Create);
+            SetA64("0x101111xxxxxxxx1010x0xxxxxxxxxx", InstName.Umull_Ve,        InstEmit.Umull_Ve,        OpCodeSimdRegElem.Create);
+            SetA64("01111110xx1xxxxx000011xxxxxxxxxx", InstName.Uqadd_S,         InstEmit.Uqadd_S,         OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx000011xxxxxxxxxx", InstName.Uqadd_V,         InstEmit.Uqadd_V,         OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx010111xxxxxxxxxx", InstName.Uqrshl_V,        InstEmit.Uqrshl_V,        OpCodeSimdReg.Create);
+            SetA64("0111111100>>>xxx100111xxxxxxxxxx", InstName.Uqrshrn_S,       InstEmit.Uqrshrn_S,       OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx100111xxxxxxxxxx", InstName.Uqrshrn_V,       InstEmit.Uqrshrn_V,       OpCodeSimdShImm.Create);
+            SetA64("0>101110<<1xxxxx010011xxxxxxxxxx", InstName.Uqshl_V,         InstEmit.Uqshl_V,         OpCodeSimdReg.Create);
+            SetA64("0111111100>>>xxx100101xxxxxxxxxx", InstName.Uqshrn_S,        InstEmit.Uqshrn_S,        OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx100101xxxxxxxxxx", InstName.Uqshrn_V,        InstEmit.Uqshrn_V,        OpCodeSimdShImm.Create);
+            SetA64("01111110xx1xxxxx001011xxxxxxxxxx", InstName.Uqsub_S,         InstEmit.Uqsub_S,         OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", InstName.Uqsub_V,         InstEmit.Uqsub_V,         OpCodeSimdReg.Create);
+            SetA64("01111110<<100001010010xxxxxxxxxx", InstName.Uqxtn_S,         InstEmit.Uqxtn_S,         OpCodeSimd.Create);
+            SetA64("0x101110<<100001010010xxxxxxxxxx", InstName.Uqxtn_V,         InstEmit.Uqxtn_V,         OpCodeSimd.Create);
+            SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", InstName.Urhadd_V,        InstEmit.Urhadd_V,        OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx010101xxxxxxxxxx", InstName.Urshl_V,         InstEmit.Urshl_V,         OpCodeSimdReg.Create);
+            SetA64("0111111101xxxxxx001001xxxxxxxxxx", InstName.Urshr_S,         InstEmit.Urshr_S,         OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx001001xxxxxxxxxx", InstName.Urshr_V,         InstEmit.Urshr_V,         OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx001001xxxxxxxxxx", InstName.Urshr_V,         InstEmit.Urshr_V,         OpCodeSimdShImm.Create);
+            SetA64("0111111101xxxxxx001101xxxxxxxxxx", InstName.Ursra_S,         InstEmit.Ursra_S,         OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx001101xxxxxxxxxx", InstName.Ursra_V,         InstEmit.Ursra_V,         OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx001101xxxxxxxxxx", InstName.Ursra_V,         InstEmit.Ursra_V,         OpCodeSimdShImm.Create);
+            SetA64("01111110111xxxxx010001xxxxxxxxxx", InstName.Ushl_S,          InstEmit.Ushl_S,          OpCodeSimdReg.Create);
+            SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", InstName.Ushl_V,          InstEmit.Ushl_V,          OpCodeSimdReg.Create);
+            SetA64("0x10111100>>>xxx101001xxxxxxxxxx", InstName.Ushll_V,         InstEmit.Ushll_V,         OpCodeSimdShImm.Create);
+            SetA64("0111111101xxxxxx000001xxxxxxxxxx", InstName.Ushr_S,          InstEmit.Ushr_S,          OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx000001xxxxxxxxxx", InstName.Ushr_V,          InstEmit.Ushr_V,          OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx000001xxxxxxxxxx", InstName.Ushr_V,          InstEmit.Ushr_V,          OpCodeSimdShImm.Create);
+            SetA64("01111110xx100000001110xxxxxxxxxx", InstName.Usqadd_S,        InstEmit.Usqadd_S,        OpCodeSimd.Create);
+            SetA64("0>101110<<100000001110xxxxxxxxxx", InstName.Usqadd_V,        InstEmit.Usqadd_V,        OpCodeSimd.Create);
+            SetA64("0111111101xxxxxx000101xxxxxxxxxx", InstName.Usra_S,          InstEmit.Usra_S,          OpCodeSimdShImm.Create);
+            SetA64("0x10111100>>>xxx000101xxxxxxxxxx", InstName.Usra_V,          InstEmit.Usra_V,          OpCodeSimdShImm.Create);
+            SetA64("0110111101xxxxxx000101xxxxxxxxxx", InstName.Usra_V,          InstEmit.Usra_V,          OpCodeSimdShImm.Create);
+            SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", InstName.Usubl_V,         InstEmit.Usubl_V,         OpCodeSimdReg.Create);
+            SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", InstName.Usubw_V,         InstEmit.Usubw_V,         OpCodeSimdReg.Create);
+            SetA64("0>001110<<0xxxxx000110xxxxxxxxxx", InstName.Uzp1_V,          InstEmit.Uzp1_V,          OpCodeSimdReg.Create);
+            SetA64("0>001110<<0xxxxx010110xxxxxxxxxx", InstName.Uzp2_V,          InstEmit.Uzp2_V,          OpCodeSimdReg.Create);
+            SetA64("0x001110<<100001001010xxxxxxxxxx", InstName.Xtn_V,           InstEmit.Xtn_V,           OpCodeSimd.Create);
+            SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", InstName.Zip1_V,          InstEmit.Zip1_V,          OpCodeSimdReg.Create);
+            SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V,          InstEmit.Zip2_V,          OpCodeSimdReg.Create);
 #endregion
 
 #region "OpCode Table (AArch32)"
             // Base
-            SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc,     InstEmit32.Adc,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc,     InstEmit32.Adc,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000101xxxxxxxxxxxxx0xx1xxxx", InstName.Adc,     InstEmit32.Adc,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0010100xxxxxxxxxxxxxxxxxxxxx", InstName.Add,     InstEmit32.Add,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000100xxxxxxxxxxxxxxxx0xxxx", InstName.Add,     InstEmit32.Add,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000100xxxxxxxxxxxxx0xx1xxxx", InstName.Add,     InstEmit32.Add,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0010000xxxxxxxxxxxxxxxxxxxxx", InstName.And,     InstEmit32.And,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000000xxxxxxxxxxxxxxxx0xxxx", InstName.And,     InstEmit32.And,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000000xxxxxxxxxxxxx0xx1xxxx", InstName.And,     InstEmit32.And,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<1010xxxxxxxxxxxxxxxxxxxxxxxx", InstName.B,       InstEmit32.B,       typeof(OpCode32BImm));
-            SetA32("<<<<0111110xxxxxxxxxxxxxx0011111", InstName.Bfc,     InstEmit32.Bfc,     typeof(OpCode32AluBf));
-            SetA32("<<<<0111110xxxxxxxxxxxxxx001xxxx", InstName.Bfi,     InstEmit32.Bfi,     typeof(OpCode32AluBf));
-            SetA32("<<<<0011110xxxxxxxxxxxxxxxxxxxxx", InstName.Bic,     InstEmit32.Bic,     typeof(OpCode32AluImm));
-            SetA32("<<<<0001110xxxxxxxxxxxxxxxx0xxxx", InstName.Bic,     InstEmit32.Bic,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0001110xxxxxxxxxxxxx0xx1xxxx", InstName.Bic,     InstEmit32.Bic,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<1011xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Bl,      InstEmit32.Bl,      typeof(OpCode32BImm));
-            SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Blx,     InstEmit32.Blx,     typeof(OpCode32BImm));
-            SetA32("<<<<000100101111111111110011xxxx", InstName.Blx,     InstEmit32.Blxr,    typeof(OpCode32BReg));
-            SetA32("<<<<000100101111111111110001xxxx", InstName.Bx,      InstEmit32.Bx,      typeof(OpCode32BReg));
-            SetT32("xxxxxxxxxxxxxxxx010001110xxxx000", InstName.Bx,      InstEmit32.Bx,      typeof(OpCodeT16BReg));
-            SetA32("11110101011111111111000000011111", InstName.Clrex,   InstEmit32.Clrex,   typeof(OpCode32));
-            SetA32("<<<<000101101111xxxx11110001xxxx", InstName.Clz,     InstEmit32.Clz,     typeof(OpCode32AluReg));
-            SetA32("<<<<00110111xxxx0000xxxxxxxxxxxx", InstName.Cmn,     InstEmit32.Cmn,     typeof(OpCode32AluImm));
-            SetA32("<<<<00010111xxxx0000xxxxxxx0xxxx", InstName.Cmn,     InstEmit32.Cmn,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<00110101xxxx0000xxxxxxxxxxxx", InstName.Cmp,     InstEmit32.Cmp,     typeof(OpCode32AluImm));
-            SetA32("<<<<00010101xxxx0000xxxxxxx0xxxx", InstName.Cmp,     InstEmit32.Cmp,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<00010101xxxx0000xxxx0xx1xxxx", InstName.Cmp,     InstEmit32.Cmp,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<00010000xxxxxxxx00000100xxxx", InstName.Crc32b,  InstEmit32.Crc32b,  typeof(OpCode32AluReg));
-            SetA32("<<<<00010000xxxxxxxx00100100xxxx", InstName.Crc32cb, InstEmit32.Crc32cb, typeof(OpCode32AluReg));
-            SetA32("<<<<00010010xxxxxxxx00100100xxxx", InstName.Crc32ch, InstEmit32.Crc32ch, typeof(OpCode32AluReg));
-            SetA32("<<<<00010100xxxxxxxx00100100xxxx", InstName.Crc32cw, InstEmit32.Crc32cw, typeof(OpCode32AluReg));
-            SetA32("<<<<00010010xxxxxxxx00000100xxxx", InstName.Crc32h,  InstEmit32.Crc32h,  typeof(OpCode32AluReg));
-            SetA32("<<<<00010100xxxxxxxx00000100xxxx", InstName.Crc32w,  InstEmit32.Crc32w,  typeof(OpCode32AluReg));
-            SetA32("1111010101111111111100000101xxxx", InstName.Dmb,     InstEmit32.Dmb,     typeof(OpCode32));
-            SetA32("1111010101111111111100000100xxxx", InstName.Dsb,     InstEmit32.Dsb,     typeof(OpCode32));
-            SetA32("<<<<0010001xxxxxxxxxxxxxxxxxxxxx", InstName.Eor,     InstEmit32.Eor,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000001xxxxxxxxxxxxxxxx0xxxx", InstName.Eor,     InstEmit32.Eor,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000001xxxxxxxxxxxxx0xx1xxxx", InstName.Eor,     InstEmit32.Eor,     typeof(OpCode32AluRsReg));
-            SetA32("1111010101111111111100000110xxxx", InstName.Isb,     InstEmit32.Nop,     typeof(OpCode32));
-            SetA32("<<<<00011001xxxxxxxx110010011111", InstName.Lda,     InstEmit32.Lda,     typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011101xxxxxxxx110010011111", InstName.Ldab,    InstEmit32.Ldab,    typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011001xxxxxxxx111010011111", InstName.Ldaex,   InstEmit32.Ldaex,   typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011101xxxxxxxx111010011111", InstName.Ldaexb,  InstEmit32.Ldaexb,  typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011011xxxxxxxx111010011111", InstName.Ldaexd,  InstEmit32.Ldaexd,  typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011111xxxxxxxx111010011111", InstName.Ldaexh,  InstEmit32.Ldaexh,  typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011111xxxxxxxx110010011111", InstName.Ldah,    InstEmit32.Ldah,    typeof(OpCode32MemLdEx));
-            SetA32("<<<<100xx0x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm,     InstEmit32.Ldm,     typeof(OpCode32MemMult));
-            SetA32("<<<<010xx0x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldr,     InstEmit32.Ldr,     typeof(OpCode32MemImm));
-            SetA32("<<<<011xx0x1xxxxxxxxxxxxxxx0xxxx", InstName.Ldr,     InstEmit32.Ldr,     typeof(OpCode32MemRsImm));
-            SetA32("<<<<010xx1x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldrb,    InstEmit32.Ldrb,    typeof(OpCode32MemImm));
-            SetA32("<<<<011xx1x1xxxxxxxxxxxxxxx0xxxx", InstName.Ldrb,    InstEmit32.Ldrb,    typeof(OpCode32MemRsImm));
-            SetA32("<<<<000xx1x0xxxxxxxxxxxx1101xxxx", InstName.Ldrd,    InstEmit32.Ldrd,    typeof(OpCode32MemImm8));
-            SetA32("<<<<000xx0x0xxxxxxxx00001101xxxx", InstName.Ldrd,    InstEmit32.Ldrd,    typeof(OpCode32MemReg));
-            SetA32("<<<<00011001xxxxxxxx111110011111", InstName.Ldrex,   InstEmit32.Ldrex,   typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011101xxxxxxxx111110011111", InstName.Ldrexb,  InstEmit32.Ldrexb,  typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011011xxxxxxxx111110011111", InstName.Ldrexd,  InstEmit32.Ldrexd,  typeof(OpCode32MemLdEx));
-            SetA32("<<<<00011111xxxxxxxx111110011111", InstName.Ldrexh,  InstEmit32.Ldrexh,  typeof(OpCode32MemLdEx));
-            SetA32("<<<<000xx1x1xxxxxxxxxxxx1011xxxx", InstName.Ldrh,    InstEmit32.Ldrh,    typeof(OpCode32MemImm8));
-            SetA32("<<<<000xx0x1xxxxxxxx00001011xxxx", InstName.Ldrh,    InstEmit32.Ldrh,    typeof(OpCode32MemReg));
-            SetA32("<<<<000xx1x1xxxxxxxxxxxx1101xxxx", InstName.Ldrsb,   InstEmit32.Ldrsb,   typeof(OpCode32MemImm8));
-            SetA32("<<<<000xx0x1xxxxxxxx00001101xxxx", InstName.Ldrsb,   InstEmit32.Ldrsb,   typeof(OpCode32MemReg));
-            SetA32("<<<<000xx1x1xxxxxxxxxxxx1111xxxx", InstName.Ldrsh,   InstEmit32.Ldrsh,   typeof(OpCode32MemImm8));
-            SetA32("<<<<000xx0x1xxxxxxxx00001111xxxx", InstName.Ldrsh,   InstEmit32.Ldrsh,   typeof(OpCode32MemReg));
-            SetA32("<<<<1110xxx0xxxxxxxx111xxxx1xxxx", InstName.Mcr,     InstEmit32.Mcr,     typeof(OpCode32System));
-            SetA32("<<<<0000001xxxxxxxxxxxxx1001xxxx", InstName.Mla,     InstEmit32.Mla,     typeof(OpCode32AluMla));
-            SetA32("<<<<00000110xxxxxxxxxxxx1001xxxx", InstName.Mls,     InstEmit32.Mls,     typeof(OpCode32AluMla));
-            SetA32("<<<<0011101x0000xxxxxxxxxxxxxxxx", InstName.Mov,     InstEmit32.Mov,     typeof(OpCode32AluImm));
-            SetA32("<<<<0001101x0000xxxxxxxxxxx0xxxx", InstName.Mov,     InstEmit32.Mov,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0001101x0000xxxxxxxx0xx1xxxx", InstName.Mov,     InstEmit32.Mov,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<00110000xxxxxxxxxxxxxxxxxxxx", InstName.Mov,     InstEmit32.Mov,     typeof(OpCode32AluImm16));
-            SetT32("xxxxxxxxxxxxxxxx00100xxxxxxxxxxx", InstName.Mov,     InstEmit32.Mov,     typeof(OpCodeT16AluImm8));
-            SetA32("<<<<00110100xxxxxxxxxxxxxxxxxxxx", InstName.Movt,    InstEmit32.Movt,    typeof(OpCode32AluImm16));
-            SetA32("<<<<1110xxx1xxxxxxxx111xxxx1xxxx", InstName.Mrc,     InstEmit32.Mrc,     typeof(OpCode32System));
-            SetA32("<<<<11000101xxxxxxxx111xxxxxxxxx", InstName.Mrrc,    InstEmit32.Mrrc,    typeof(OpCode32System));
-            SetA32("<<<<0000000xxxxx0000xxxx1001xxxx", InstName.Mul,     InstEmit32.Mul,     typeof(OpCode32AluMla));
-            SetA32("<<<<0011111x0000xxxxxxxxxxxxxxxx", InstName.Mvn,     InstEmit32.Mvn,     typeof(OpCode32AluImm));
-            SetA32("<<<<0001111x0000xxxxxxxxxxx0xxxx", InstName.Mvn,     InstEmit32.Mvn,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0001111x0000xxxxxxxx0xx1xxxx", InstName.Mvn,     InstEmit32.Mvn,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0011001000001111000000000000", InstName.Nop,     InstEmit32.Nop,     typeof(OpCode32));
-            SetA32("<<<<0011100xxxxxxxxxxxxxxxxxxxxx", InstName.Orr,     InstEmit32.Orr,     typeof(OpCode32AluImm));
-            SetA32("<<<<0001100xxxxxxxxxxxxxxxx0xxxx", InstName.Orr,     InstEmit32.Orr,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0001100xxxxxxxxxxxxx0xx1xxxx", InstName.Orr,     InstEmit32.Orr,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<01101000xxxxxxxxxxxxxx01xxxx", InstName.Pkh,     InstEmit32.Pkh,     typeof(OpCode32AluRsImm));
-            SetA32("11110101xx01xxxx1111xxxxxxxxxxxx", InstName.Pld,     InstEmit32.Nop,     typeof(OpCode32));
-            SetA32("11110111xx01xxxx1111xxxxxxx0xxxx", InstName.Pld,     InstEmit32.Nop,     typeof(OpCode32));
-            SetA32("<<<<011011111111xxxx11110011xxxx", InstName.Rbit,    InstEmit32.Rbit,    typeof(OpCode32AluReg));
-            SetA32("<<<<011010111111xxxx11110011xxxx", InstName.Rev,     InstEmit32.Rev,     typeof(OpCode32AluReg));
-            SetA32("<<<<011010111111xxxx11111011xxxx", InstName.Rev16,   InstEmit32.Rev16,   typeof(OpCode32AluReg));
-            SetA32("<<<<011011111111xxxx11111011xxxx", InstName.Revsh,   InstEmit32.Revsh,   typeof(OpCode32AluReg));
-            SetA32("<<<<0010011xxxxxxxxxxxxxxxxxxxxx", InstName.Rsb,     InstEmit32.Rsb,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000011xxxxxxxxxxxxxxxx0xxxx", InstName.Rsb,     InstEmit32.Rsb,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000011xxxxxxxxxxxxx0xx1xxxx", InstName.Rsb,     InstEmit32.Rsb,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0010111xxxxxxxxxxxxxxxxxxxxx", InstName.Rsc,     InstEmit32.Rsc,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000111xxxxxxxxxxxxxxxx0xxxx", InstName.Rsc,     InstEmit32.Rsc,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000111xxxxxxxxxxxxx0xx1xxxx", InstName.Rsc,     InstEmit32.Rsc,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0010110xxxxxxxxxxxxxxxxxxxxx", InstName.Sbc,     InstEmit32.Sbc,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000110xxxxxxxxxxxxxxxx0xxxx", InstName.Sbc,     InstEmit32.Sbc,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000110xxxxxxxxxxxxx0xx1xxxx", InstName.Sbc,     InstEmit32.Sbc,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0111101xxxxxxxxxxxxxx101xxxx", InstName.Sbfx,    InstEmit32.Sbfx,    typeof(OpCode32AluBf));
-            SetA32("<<<<01110001xxxx1111xxxx0001xxxx", InstName.Sdiv,    InstEmit32.Sdiv,    typeof(OpCode32AluMla));
-            SetA32("<<<<00010000xxxxxxxxxxxx1xx0xxxx", InstName.Smla__,  InstEmit32.Smla__,  typeof(OpCode32AluMla));
-            SetA32("<<<<0000111xxxxxxxxxxxxx1001xxxx", InstName.Smlal,   InstEmit32.Smlal,   typeof(OpCode32AluUmull));
-            SetA32("<<<<00010100xxxxxxxxxxxx1xx0xxxx", InstName.Smlal__, InstEmit32.Smlal__, typeof(OpCode32AluUmull));
-            SetA32("<<<<00010010xxxxxxxxxxxx1x00xxxx", InstName.Smlaw_,  InstEmit32.Smlaw_,  typeof(OpCode32AluMla));
-            SetA32("<<<<01110101xxxxxxxxxxxx00x1xxxx", InstName.Smmla,   InstEmit32.Smmla,   typeof(OpCode32AluMla));
-            SetA32("<<<<01110101xxxxxxxxxxxx11x1xxxx", InstName.Smmls,   InstEmit32.Smmls,   typeof(OpCode32AluMla));
-            SetA32("<<<<00010110xxxxxxxxxxxx1xx0xxxx", InstName.Smul__,  InstEmit32.Smul__,  typeof(OpCode32AluMla));
-            SetA32("<<<<0000110xxxxxxxxxxxxx1001xxxx", InstName.Smull,   InstEmit32.Smull,   typeof(OpCode32AluUmull));
-            SetA32("<<<<00010010xxxx0000xxxx1x10xxxx", InstName.Smulw_,  InstEmit32.Smulw_,  typeof(OpCode32AluMla));
-            SetA32("<<<<0110101xxxxxxxxxxxxxxx01xxxx", InstName.Ssat,    InstEmit32.Ssat,    typeof(OpCode32Sat));
-            SetA32("<<<<01101010xxxxxxxx11110011xxxx", InstName.Ssat16,  InstEmit32.Ssat16,  typeof(OpCode32Sat16));
-            SetA32("<<<<00011000xxxx111111001001xxxx", InstName.Stl,     InstEmit32.Stl,     typeof(OpCode32MemStEx));
-            SetA32("<<<<00011100xxxx111111001001xxxx", InstName.Stlb,    InstEmit32.Stlb,    typeof(OpCode32MemStEx));
-            SetA32("<<<<00011000xxxxxxxx11101001xxxx", InstName.Stlex,   InstEmit32.Stlex,   typeof(OpCode32MemStEx));
-            SetA32("<<<<00011100xxxxxxxx11101001xxxx", InstName.Stlexb,  InstEmit32.Stlexb,  typeof(OpCode32MemStEx));
-            SetA32("<<<<00011010xxxxxxxx11101001xxxx", InstName.Stlexd,  InstEmit32.Stlexd,  typeof(OpCode32MemStEx));
-            SetA32("<<<<00011110xxxxxxxx11101001xxxx", InstName.Stlexh,  InstEmit32.Stlexh,  typeof(OpCode32MemStEx));
-            SetA32("<<<<00011110xxxx111111001001xxxx", InstName.Stlh,    InstEmit32.Stlh,    typeof(OpCode32MemStEx));
-            SetA32("<<<<100xx0x0xxxxxxxxxxxxxxxxxxxx", InstName.Stm,     InstEmit32.Stm,     typeof(OpCode32MemMult));
-            SetA32("<<<<010xx0x0xxxxxxxxxxxxxxxxxxxx", InstName.Str,     InstEmit32.Str,     typeof(OpCode32MemImm));
-            SetA32("<<<<011xx0x0xxxxxxxxxxxxxxx0xxxx", InstName.Str,     InstEmit32.Str,     typeof(OpCode32MemRsImm));
-            SetA32("<<<<010xx1x0xxxxxxxxxxxxxxxxxxxx", InstName.Strb,    InstEmit32.Strb,    typeof(OpCode32MemImm));
-            SetA32("<<<<011xx1x0xxxxxxxxxxxxxxx0xxxx", InstName.Strb,    InstEmit32.Strb,    typeof(OpCode32MemRsImm));
-            SetA32("<<<<000xx1x0xxxxxxxxxxxx1111xxxx", InstName.Strd,    InstEmit32.Strd,    typeof(OpCode32MemImm8));
-            SetA32("<<<<000xx0x0xxxxxxxx00001111xxxx", InstName.Strd,    InstEmit32.Strd,    typeof(OpCode32MemReg));
-            SetA32("<<<<00011000xxxxxxxx11111001xxxx", InstName.Strex,   InstEmit32.Strex,   typeof(OpCode32MemStEx));
-            SetA32("<<<<00011100xxxxxxxx11111001xxxx", InstName.Strexb,  InstEmit32.Strexb,  typeof(OpCode32MemStEx));
-            SetA32("<<<<00011010xxxxxxxx11111001xxxx", InstName.Strexd,  InstEmit32.Strexd,  typeof(OpCode32MemStEx));
-            SetA32("<<<<00011110xxxxxxxx11111001xxxx", InstName.Strexh,  InstEmit32.Strexh,  typeof(OpCode32MemStEx));
-            SetA32("<<<<000xx1x0xxxxxxxxxxxx1011xxxx", InstName.Strh,    InstEmit32.Strh,    typeof(OpCode32MemImm8));
-            SetA32("<<<<000xx0x0xxxxxxxx00001011xxxx", InstName.Strh,    InstEmit32.Strh,    typeof(OpCode32MemReg));
-            SetA32("<<<<0010010xxxxxxxxxxxxxxxxxxxxx", InstName.Sub,     InstEmit32.Sub,     typeof(OpCode32AluImm));
-            SetA32("<<<<0000010xxxxxxxxxxxxxxxx0xxxx", InstName.Sub,     InstEmit32.Sub,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<0000010xxxxxxxxxxxxx0xx1xxxx", InstName.Sub,     InstEmit32.Sub,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<1111xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Svc,     InstEmit32.Svc,     typeof(OpCode32Exception));
-            SetA32("<<<<01101010xxxxxxxxxx000111xxxx", InstName.Sxtb,    InstEmit32.Sxtb,    typeof(OpCode32AluUx));
-            SetA32("<<<<01101000xxxxxxxxxx000111xxxx", InstName.Sxtb16,  InstEmit32.Sxtb16,  typeof(OpCode32AluUx));
-            SetA32("<<<<01101011xxxxxxxxxx000111xxxx", InstName.Sxth,    InstEmit32.Sxth,    typeof(OpCode32AluUx));
-            SetA32("<<<<00110011xxxx0000xxxxxxxxxxxx", InstName.Teq,     InstEmit32.Teq,     typeof(OpCode32AluImm));
-            SetA32("<<<<00010011xxxx0000xxxxxxx0xxxx", InstName.Teq,     InstEmit32.Teq,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<00010011xxxx0000xxxx0xx1xxxx", InstName.Teq,     InstEmit32.Teq,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0111111111111101111011111110", InstName.Trap,    InstEmit32.Trap,    typeof(OpCode32Exception));
-            SetA32("<<<<00110001xxxx0000xxxxxxxxxxxx", InstName.Tst,     InstEmit32.Tst,     typeof(OpCode32AluImm));
-            SetA32("<<<<00010001xxxx0000xxxxxxx0xxxx", InstName.Tst,     InstEmit32.Tst,     typeof(OpCode32AluRsImm));
-            SetA32("<<<<00010001xxxx0000xxxx0xx1xxxx", InstName.Tst,     InstEmit32.Tst,     typeof(OpCode32AluRsReg));
-            SetA32("<<<<0111111xxxxxxxxxxxxxx101xxxx", InstName.Ubfx,    InstEmit32.Ubfx,    typeof(OpCode32AluBf));
-            SetA32("<<<<01110011xxxx1111xxxx0001xxxx", InstName.Udiv,    InstEmit32.Udiv,    typeof(OpCode32AluMla));
-            SetA32("<<<<00000100xxxxxxxxxxxx1001xxxx", InstName.Umaal,   InstEmit32.Umaal,   typeof(OpCode32AluUmull));
-            SetA32("<<<<0000101xxxxxxxxxxxxx1001xxxx", InstName.Umlal,   InstEmit32.Umlal,   typeof(OpCode32AluUmull));
-            SetA32("<<<<0000100xxxxxxxxxxxxx1001xxxx", InstName.Umull,   InstEmit32.Umull,   typeof(OpCode32AluUmull));
-            SetA32("<<<<0110111xxxxxxxxxxxxxxx01xxxx", InstName.Usat,    InstEmit32.Usat,    typeof(OpCode32Sat));
-            SetA32("<<<<01101110xxxxxxxx11110011xxxx", InstName.Usat16,  InstEmit32.Usat16,  typeof(OpCode32Sat16));
-            SetA32("<<<<01101110xxxxxxxxxx000111xxxx", InstName.Uxtb,    InstEmit32.Uxtb,    typeof(OpCode32AluUx));
-            SetA32("<<<<01101100xxxxxxxxxx000111xxxx", InstName.Uxtb16,  InstEmit32.Uxtb16,  typeof(OpCode32AluUx));
-            SetA32("<<<<01101111xxxxxxxxxx000111xxxx", InstName.Uxth,    InstEmit32.Uxth,    typeof(OpCode32AluUx));
+            SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc,     InstEmit32.Adc,     OpCode32AluImm.Create);
+            SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc,     InstEmit32.Adc,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000101xxxxxxxxxxxxx0xx1xxxx", InstName.Adc,     InstEmit32.Adc,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0010100xxxxxxxxxxxxxxxxxxxxx", InstName.Add,     InstEmit32.Add,     OpCode32AluImm.Create);
+            SetA32("<<<<0000100xxxxxxxxxxxxxxxx0xxxx", InstName.Add,     InstEmit32.Add,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000100xxxxxxxxxxxxx0xx1xxxx", InstName.Add,     InstEmit32.Add,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0010000xxxxxxxxxxxxxxxxxxxxx", InstName.And,     InstEmit32.And,     OpCode32AluImm.Create);
+            SetA32("<<<<0000000xxxxxxxxxxxxxxxx0xxxx", InstName.And,     InstEmit32.And,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000000xxxxxxxxxxxxx0xx1xxxx", InstName.And,     InstEmit32.And,     OpCode32AluRsReg.Create);
+            SetA32("<<<<1010xxxxxxxxxxxxxxxxxxxxxxxx", InstName.B,       InstEmit32.B,       OpCode32BImm.Create);
+            SetA32("<<<<0111110xxxxxxxxxxxxxx0011111", InstName.Bfc,     InstEmit32.Bfc,     OpCode32AluBf.Create);
+            SetA32("<<<<0111110xxxxxxxxxxxxxx001xxxx", InstName.Bfi,     InstEmit32.Bfi,     OpCode32AluBf.Create);
+            SetA32("<<<<0011110xxxxxxxxxxxxxxxxxxxxx", InstName.Bic,     InstEmit32.Bic,     OpCode32AluImm.Create);
+            SetA32("<<<<0001110xxxxxxxxxxxxxxxx0xxxx", InstName.Bic,     InstEmit32.Bic,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0001110xxxxxxxxxxxxx0xx1xxxx", InstName.Bic,     InstEmit32.Bic,     OpCode32AluRsReg.Create);
+            SetA32("<<<<1011xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Bl,      InstEmit32.Bl,      OpCode32BImm.Create);
+            SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Blx,     InstEmit32.Blx,     OpCode32BImm.Create);
+            SetA32("<<<<000100101111111111110011xxxx", InstName.Blx,     InstEmit32.Blxr,    OpCode32BReg.Create);
+            SetA32("<<<<000100101111111111110001xxxx", InstName.Bx,      InstEmit32.Bx,      OpCode32BReg.Create);
+            SetT32("xxxxxxxxxxxxxxxx010001110xxxx000", InstName.Bx,      InstEmit32.Bx,      OpCodeT16BReg.Create);
+            SetA32("11110101011111111111000000011111", InstName.Clrex,   InstEmit32.Clrex,   OpCode32.Create);
+            SetA32("<<<<000101101111xxxx11110001xxxx", InstName.Clz,     InstEmit32.Clz,     OpCode32AluReg.Create);
+            SetA32("<<<<00110111xxxx0000xxxxxxxxxxxx", InstName.Cmn,     InstEmit32.Cmn,     OpCode32AluImm.Create);
+            SetA32("<<<<00010111xxxx0000xxxxxxx0xxxx", InstName.Cmn,     InstEmit32.Cmn,     OpCode32AluRsImm.Create);
+            SetA32("<<<<00110101xxxx0000xxxxxxxxxxxx", InstName.Cmp,     InstEmit32.Cmp,     OpCode32AluImm.Create);
+            SetA32("<<<<00010101xxxx0000xxxxxxx0xxxx", InstName.Cmp,     InstEmit32.Cmp,     OpCode32AluRsImm.Create);
+            SetA32("<<<<00010101xxxx0000xxxx0xx1xxxx", InstName.Cmp,     InstEmit32.Cmp,     OpCode32AluRsReg.Create);
+            SetA32("<<<<00010000xxxxxxxx00000100xxxx", InstName.Crc32b,  InstEmit32.Crc32b,  OpCode32AluReg.Create);
+            SetA32("<<<<00010000xxxxxxxx00100100xxxx", InstName.Crc32cb, InstEmit32.Crc32cb, OpCode32AluReg.Create);
+            SetA32("<<<<00010010xxxxxxxx00100100xxxx", InstName.Crc32ch, InstEmit32.Crc32ch, OpCode32AluReg.Create);
+            SetA32("<<<<00010100xxxxxxxx00100100xxxx", InstName.Crc32cw, InstEmit32.Crc32cw, OpCode32AluReg.Create);
+            SetA32("<<<<00010010xxxxxxxx00000100xxxx", InstName.Crc32h,  InstEmit32.Crc32h,  OpCode32AluReg.Create);
+            SetA32("<<<<00010100xxxxxxxx00000100xxxx", InstName.Crc32w,  InstEmit32.Crc32w,  OpCode32AluReg.Create);
+            SetA32("1111010101111111111100000101xxxx", InstName.Dmb,     InstEmit32.Dmb,     OpCode32.Create);
+            SetA32("1111010101111111111100000100xxxx", InstName.Dsb,     InstEmit32.Dsb,     OpCode32.Create);
+            SetA32("<<<<0010001xxxxxxxxxxxxxxxxxxxxx", InstName.Eor,     InstEmit32.Eor,     OpCode32AluImm.Create);
+            SetA32("<<<<0000001xxxxxxxxxxxxxxxx0xxxx", InstName.Eor,     InstEmit32.Eor,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000001xxxxxxxxxxxxx0xx1xxxx", InstName.Eor,     InstEmit32.Eor,     OpCode32AluRsReg.Create);
+            SetA32("1111010101111111111100000110xxxx", InstName.Isb,     InstEmit32.Nop,     OpCode32.Create);
+            SetA32("<<<<00011001xxxxxxxx110010011111", InstName.Lda,     InstEmit32.Lda,     OpCode32MemLdEx.Create);
+            SetA32("<<<<00011101xxxxxxxx110010011111", InstName.Ldab,    InstEmit32.Ldab,    OpCode32MemLdEx.Create);
+            SetA32("<<<<00011001xxxxxxxx111010011111", InstName.Ldaex,   InstEmit32.Ldaex,   OpCode32MemLdEx.Create);
+            SetA32("<<<<00011101xxxxxxxx111010011111", InstName.Ldaexb,  InstEmit32.Ldaexb,  OpCode32MemLdEx.Create);
+            SetA32("<<<<00011011xxxxxxxx111010011111", InstName.Ldaexd,  InstEmit32.Ldaexd,  OpCode32MemLdEx.Create);
+            SetA32("<<<<00011111xxxxxxxx111010011111", InstName.Ldaexh,  InstEmit32.Ldaexh,  OpCode32MemLdEx.Create);
+            SetA32("<<<<00011111xxxxxxxx110010011111", InstName.Ldah,    InstEmit32.Ldah,    OpCode32MemLdEx.Create);
+            SetA32("<<<<100xx0x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm,     InstEmit32.Ldm,     OpCode32MemMult.Create);
+            SetA32("<<<<010xx0x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldr,     InstEmit32.Ldr,     OpCode32MemImm.Create);
+            SetA32("<<<<011xx0x1xxxxxxxxxxxxxxx0xxxx", InstName.Ldr,     InstEmit32.Ldr,     OpCode32MemRsImm.Create);
+            SetA32("<<<<010xx1x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldrb,    InstEmit32.Ldrb,    OpCode32MemImm.Create);
+            SetA32("<<<<011xx1x1xxxxxxxxxxxxxxx0xxxx", InstName.Ldrb,    InstEmit32.Ldrb,    OpCode32MemRsImm.Create);
+            SetA32("<<<<000xx1x0xxxxxxxxxxxx1101xxxx", InstName.Ldrd,    InstEmit32.Ldrd,    OpCode32MemImm8.Create);
+            SetA32("<<<<000xx0x0xxxxxxxx00001101xxxx", InstName.Ldrd,    InstEmit32.Ldrd,    OpCode32MemReg.Create);
+            SetA32("<<<<00011001xxxxxxxx111110011111", InstName.Ldrex,   InstEmit32.Ldrex,   OpCode32MemLdEx.Create);
+            SetA32("<<<<00011101xxxxxxxx111110011111", InstName.Ldrexb,  InstEmit32.Ldrexb,  OpCode32MemLdEx.Create);
+            SetA32("<<<<00011011xxxxxxxx111110011111", InstName.Ldrexd,  InstEmit32.Ldrexd,  OpCode32MemLdEx.Create);
+            SetA32("<<<<00011111xxxxxxxx111110011111", InstName.Ldrexh,  InstEmit32.Ldrexh,  OpCode32MemLdEx.Create);
+            SetA32("<<<<000xx1x1xxxxxxxxxxxx1011xxxx", InstName.Ldrh,    InstEmit32.Ldrh,    OpCode32MemImm8.Create);
+            SetA32("<<<<000xx0x1xxxxxxxx00001011xxxx", InstName.Ldrh,    InstEmit32.Ldrh,    OpCode32MemReg.Create);
+            SetA32("<<<<000xx1x1xxxxxxxxxxxx1101xxxx", InstName.Ldrsb,   InstEmit32.Ldrsb,   OpCode32MemImm8.Create);
+            SetA32("<<<<000xx0x1xxxxxxxx00001101xxxx", InstName.Ldrsb,   InstEmit32.Ldrsb,   OpCode32MemReg.Create);
+            SetA32("<<<<000xx1x1xxxxxxxxxxxx1111xxxx", InstName.Ldrsh,   InstEmit32.Ldrsh,   OpCode32MemImm8.Create);
+            SetA32("<<<<000xx0x1xxxxxxxx00001111xxxx", InstName.Ldrsh,   InstEmit32.Ldrsh,   OpCode32MemReg.Create);
+            SetA32("<<<<1110xxx0xxxxxxxx111xxxx1xxxx", InstName.Mcr,     InstEmit32.Mcr,     OpCode32System.Create);
+            SetA32("<<<<0000001xxxxxxxxxxxxx1001xxxx", InstName.Mla,     InstEmit32.Mla,     OpCode32AluMla.Create);
+            SetA32("<<<<00000110xxxxxxxxxxxx1001xxxx", InstName.Mls,     InstEmit32.Mls,     OpCode32AluMla.Create);
+            SetA32("<<<<0011101x0000xxxxxxxxxxxxxxxx", InstName.Mov,     InstEmit32.Mov,     OpCode32AluImm.Create);
+            SetA32("<<<<0001101x0000xxxxxxxxxxx0xxxx", InstName.Mov,     InstEmit32.Mov,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0001101x0000xxxxxxxx0xx1xxxx", InstName.Mov,     InstEmit32.Mov,     OpCode32AluRsReg.Create);
+            SetA32("<<<<00110000xxxxxxxxxxxxxxxxxxxx", InstName.Mov,     InstEmit32.Mov,     OpCode32AluImm16.Create);
+            SetT32("xxxxxxxxxxxxxxxx00100xxxxxxxxxxx", InstName.Mov,     InstEmit32.Mov,     OpCodeT16AluImm8.Create);
+            SetA32("<<<<00110100xxxxxxxxxxxxxxxxxxxx", InstName.Movt,    InstEmit32.Movt,    OpCode32AluImm16.Create);
+            SetA32("<<<<1110xxx1xxxxxxxx111xxxx1xxxx", InstName.Mrc,     InstEmit32.Mrc,     OpCode32System.Create);
+            SetA32("<<<<11000101xxxxxxxx111xxxxxxxxx", InstName.Mrrc,    InstEmit32.Mrrc,    OpCode32System.Create);
+            SetA32("<<<<0000000xxxxx0000xxxx1001xxxx", InstName.Mul,     InstEmit32.Mul,     OpCode32AluMla.Create);
+            SetA32("<<<<0011111x0000xxxxxxxxxxxxxxxx", InstName.Mvn,     InstEmit32.Mvn,     OpCode32AluImm.Create);
+            SetA32("<<<<0001111x0000xxxxxxxxxxx0xxxx", InstName.Mvn,     InstEmit32.Mvn,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0001111x0000xxxxxxxx0xx1xxxx", InstName.Mvn,     InstEmit32.Mvn,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0011001000001111000000000000", InstName.Nop,     InstEmit32.Nop,     OpCode32.Create);
+            SetA32("<<<<0011100xxxxxxxxxxxxxxxxxxxxx", InstName.Orr,     InstEmit32.Orr,     OpCode32AluImm.Create);
+            SetA32("<<<<0001100xxxxxxxxxxxxxxxx0xxxx", InstName.Orr,     InstEmit32.Orr,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0001100xxxxxxxxxxxxx0xx1xxxx", InstName.Orr,     InstEmit32.Orr,     OpCode32AluRsReg.Create);
+            SetA32("<<<<01101000xxxxxxxxxxxxxx01xxxx", InstName.Pkh,     InstEmit32.Pkh,     OpCode32AluRsImm.Create);
+            SetA32("11110101xx01xxxx1111xxxxxxxxxxxx", InstName.Pld,     InstEmit32.Nop,     OpCode32.Create);
+            SetA32("11110111xx01xxxx1111xxxxxxx0xxxx", InstName.Pld,     InstEmit32.Nop,     OpCode32.Create);
+            SetA32("<<<<011011111111xxxx11110011xxxx", InstName.Rbit,    InstEmit32.Rbit,    OpCode32AluReg.Create);
+            SetA32("<<<<011010111111xxxx11110011xxxx", InstName.Rev,     InstEmit32.Rev,     OpCode32AluReg.Create);
+            SetA32("<<<<011010111111xxxx11111011xxxx", InstName.Rev16,   InstEmit32.Rev16,   OpCode32AluReg.Create);
+            SetA32("<<<<011011111111xxxx11111011xxxx", InstName.Revsh,   InstEmit32.Revsh,   OpCode32AluReg.Create);
+            SetA32("<<<<0010011xxxxxxxxxxxxxxxxxxxxx", InstName.Rsb,     InstEmit32.Rsb,     OpCode32AluImm.Create);
+            SetA32("<<<<0000011xxxxxxxxxxxxxxxx0xxxx", InstName.Rsb,     InstEmit32.Rsb,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000011xxxxxxxxxxxxx0xx1xxxx", InstName.Rsb,     InstEmit32.Rsb,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0010111xxxxxxxxxxxxxxxxxxxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluImm.Create);
+            SetA32("<<<<0000111xxxxxxxxxxxxxxxx0xxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000111xxxxxxxxxxxxx0xx1xxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0010110xxxxxxxxxxxxxxxxxxxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluImm.Create);
+            SetA32("<<<<0000110xxxxxxxxxxxxxxxx0xxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000110xxxxxxxxxxxxx0xx1xxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0111101xxxxxxxxxxxxxx101xxxx", InstName.Sbfx,    InstEmit32.Sbfx,    OpCode32AluBf.Create);
+            SetA32("<<<<01110001xxxx1111xxxx0001xxxx", InstName.Sdiv,    InstEmit32.Sdiv,    OpCode32AluMla.Create);
+            SetA32("<<<<00010000xxxxxxxxxxxx1xx0xxxx", InstName.Smla__,  InstEmit32.Smla__,  OpCode32AluMla.Create);
+            SetA32("<<<<0000111xxxxxxxxxxxxx1001xxxx", InstName.Smlal,   InstEmit32.Smlal,   OpCode32AluUmull.Create);
+            SetA32("<<<<00010100xxxxxxxxxxxx1xx0xxxx", InstName.Smlal__, InstEmit32.Smlal__, OpCode32AluUmull.Create);
+            SetA32("<<<<00010010xxxxxxxxxxxx1x00xxxx", InstName.Smlaw_,  InstEmit32.Smlaw_,  OpCode32AluMla.Create);
+            SetA32("<<<<01110101xxxxxxxxxxxx00x1xxxx", InstName.Smmla,   InstEmit32.Smmla,   OpCode32AluMla.Create);
+            SetA32("<<<<01110101xxxxxxxxxxxx11x1xxxx", InstName.Smmls,   InstEmit32.Smmls,   OpCode32AluMla.Create);
+            SetA32("<<<<00010110xxxxxxxxxxxx1xx0xxxx", InstName.Smul__,  InstEmit32.Smul__,  OpCode32AluMla.Create);
+            SetA32("<<<<0000110xxxxxxxxxxxxx1001xxxx", InstName.Smull,   InstEmit32.Smull,   OpCode32AluUmull.Create);
+            SetA32("<<<<00010010xxxx0000xxxx1x10xxxx", InstName.Smulw_,  InstEmit32.Smulw_,  OpCode32AluMla.Create);
+            SetA32("<<<<0110101xxxxxxxxxxxxxxx01xxxx", InstName.Ssat,    InstEmit32.Ssat,    OpCode32Sat.Create);
+            SetA32("<<<<01101010xxxxxxxx11110011xxxx", InstName.Ssat16,  InstEmit32.Ssat16,  OpCode32Sat16.Create);
+            SetA32("<<<<00011000xxxx111111001001xxxx", InstName.Stl,     InstEmit32.Stl,     OpCode32MemStEx.Create);
+            SetA32("<<<<00011100xxxx111111001001xxxx", InstName.Stlb,    InstEmit32.Stlb,    OpCode32MemStEx.Create);
+            SetA32("<<<<00011000xxxxxxxx11101001xxxx", InstName.Stlex,   InstEmit32.Stlex,   OpCode32MemStEx.Create);
+            SetA32("<<<<00011100xxxxxxxx11101001xxxx", InstName.Stlexb,  InstEmit32.Stlexb,  OpCode32MemStEx.Create);
+            SetA32("<<<<00011010xxxxxxxx11101001xxxx", InstName.Stlexd,  InstEmit32.Stlexd,  OpCode32MemStEx.Create);
+            SetA32("<<<<00011110xxxxxxxx11101001xxxx", InstName.Stlexh,  InstEmit32.Stlexh,  OpCode32MemStEx.Create);
+            SetA32("<<<<00011110xxxx111111001001xxxx", InstName.Stlh,    InstEmit32.Stlh,    OpCode32MemStEx.Create);
+            SetA32("<<<<100xx0x0xxxxxxxxxxxxxxxxxxxx", InstName.Stm,     InstEmit32.Stm,     OpCode32MemMult.Create);
+            SetA32("<<<<010xx0x0xxxxxxxxxxxxxxxxxxxx", InstName.Str,     InstEmit32.Str,     OpCode32MemImm.Create);
+            SetA32("<<<<011xx0x0xxxxxxxxxxxxxxx0xxxx", InstName.Str,     InstEmit32.Str,     OpCode32MemRsImm.Create);
+            SetA32("<<<<010xx1x0xxxxxxxxxxxxxxxxxxxx", InstName.Strb,    InstEmit32.Strb,    OpCode32MemImm.Create);
+            SetA32("<<<<011xx1x0xxxxxxxxxxxxxxx0xxxx", InstName.Strb,    InstEmit32.Strb,    OpCode32MemRsImm.Create);
+            SetA32("<<<<000xx1x0xxxxxxxxxxxx1111xxxx", InstName.Strd,    InstEmit32.Strd,    OpCode32MemImm8.Create);
+            SetA32("<<<<000xx0x0xxxxxxxx00001111xxxx", InstName.Strd,    InstEmit32.Strd,    OpCode32MemReg.Create);
+            SetA32("<<<<00011000xxxxxxxx11111001xxxx", InstName.Strex,   InstEmit32.Strex,   OpCode32MemStEx.Create);
+            SetA32("<<<<00011100xxxxxxxx11111001xxxx", InstName.Strexb,  InstEmit32.Strexb,  OpCode32MemStEx.Create);
+            SetA32("<<<<00011010xxxxxxxx11111001xxxx", InstName.Strexd,  InstEmit32.Strexd,  OpCode32MemStEx.Create);
+            SetA32("<<<<00011110xxxxxxxx11111001xxxx", InstName.Strexh,  InstEmit32.Strexh,  OpCode32MemStEx.Create);
+            SetA32("<<<<000xx1x0xxxxxxxxxxxx1011xxxx", InstName.Strh,    InstEmit32.Strh,    OpCode32MemImm8.Create);
+            SetA32("<<<<000xx0x0xxxxxxxx00001011xxxx", InstName.Strh,    InstEmit32.Strh,    OpCode32MemReg.Create);
+            SetA32("<<<<0010010xxxxxxxxxxxxxxxxxxxxx", InstName.Sub,     InstEmit32.Sub,     OpCode32AluImm.Create);
+            SetA32("<<<<0000010xxxxxxxxxxxxxxxx0xxxx", InstName.Sub,     InstEmit32.Sub,     OpCode32AluRsImm.Create);
+            SetA32("<<<<0000010xxxxxxxxxxxxx0xx1xxxx", InstName.Sub,     InstEmit32.Sub,     OpCode32AluRsReg.Create);
+            SetA32("<<<<1111xxxxxxxxxxxxxxxxxxxxxxxx", InstName.Svc,     InstEmit32.Svc,     OpCode32Exception.Create);
+            SetA32("<<<<01101010xxxxxxxxxx000111xxxx", InstName.Sxtb,    InstEmit32.Sxtb,    OpCode32AluUx.Create);
+            SetA32("<<<<01101000xxxxxxxxxx000111xxxx", InstName.Sxtb16,  InstEmit32.Sxtb16,  OpCode32AluUx.Create);
+            SetA32("<<<<01101011xxxxxxxxxx000111xxxx", InstName.Sxth,    InstEmit32.Sxth,    OpCode32AluUx.Create);
+            SetA32("<<<<00110011xxxx0000xxxxxxxxxxxx", InstName.Teq,     InstEmit32.Teq,     OpCode32AluImm.Create);
+            SetA32("<<<<00010011xxxx0000xxxxxxx0xxxx", InstName.Teq,     InstEmit32.Teq,     OpCode32AluRsImm.Create);
+            SetA32("<<<<00010011xxxx0000xxxx0xx1xxxx", InstName.Teq,     InstEmit32.Teq,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0111111111111101111011111110", InstName.Trap,    InstEmit32.Trap,    OpCode32Exception.Create);
+            SetA32("<<<<00110001xxxx0000xxxxxxxxxxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluImm.Create);
+            SetA32("<<<<00010001xxxx0000xxxxxxx0xxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluRsImm.Create);
+            SetA32("<<<<00010001xxxx0000xxxx0xx1xxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0111111xxxxxxxxxxxxxx101xxxx", InstName.Ubfx,    InstEmit32.Ubfx,    OpCode32AluBf.Create);
+            SetA32("<<<<01110011xxxx1111xxxx0001xxxx", InstName.Udiv,    InstEmit32.Udiv,    OpCode32AluMla.Create);
+            SetA32("<<<<00000100xxxxxxxxxxxx1001xxxx", InstName.Umaal,   InstEmit32.Umaal,   OpCode32AluUmull.Create);
+            SetA32("<<<<0000101xxxxxxxxxxxxx1001xxxx", InstName.Umlal,   InstEmit32.Umlal,   OpCode32AluUmull.Create);
+            SetA32("<<<<0000100xxxxxxxxxxxxx1001xxxx", InstName.Umull,   InstEmit32.Umull,   OpCode32AluUmull.Create);
+            SetA32("<<<<0110111xxxxxxxxxxxxxxx01xxxx", InstName.Usat,    InstEmit32.Usat,    OpCode32Sat.Create);
+            SetA32("<<<<01101110xxxxxxxx11110011xxxx", InstName.Usat16,  InstEmit32.Usat16,  OpCode32Sat16.Create);
+            SetA32("<<<<01101110xxxxxxxxxx000111xxxx", InstName.Uxtb,    InstEmit32.Uxtb,    OpCode32AluUx.Create);
+            SetA32("<<<<01101100xxxxxxxxxx000111xxxx", InstName.Uxtb16,  InstEmit32.Uxtb16,  OpCode32AluUx.Create);
+            SetA32("<<<<01101111xxxxxxxxxx000111xxxx", InstName.Uxth,    InstEmit32.Uxth,    OpCode32AluUx.Create);
 
             // FP & SIMD
-            SetA32("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V,   InstEmit32.Aesd_V,   typeof(OpCode32Simd));
-            SetA32("111100111x110000xxx0001100x0xxx0", InstName.Aese_V,   InstEmit32.Aese_V,   typeof(OpCode32Simd));
-            SetA32("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V, InstEmit32.Aesimc_V, typeof(OpCode32Simd));
-            SetA32("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V,  InstEmit32.Aesmc_V,  typeof(OpCode32Simd));
-            SetA32("1111001x0x<<xxxxxxxx0111xxx0xxxx", InstName.Vabd,     InstEmit32.Vabd_I,   typeof(OpCode32SimdReg));
-            SetA32("1111001x1x<<xxxxxxxx0111x0x0xxxx", InstName.Vabdl,    InstEmit32.Vabdl_I,  typeof(OpCode32SimdRegLong));
-            SetA32("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs,     InstEmit32.Vabs_S,   typeof(OpCode32SimdS));
-            SetA32("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs,     InstEmit32.Vabs_V,   typeof(OpCode32SimdCmpZ));
-            SetA32("111100111x111001xxxx01110xx0xxxx", InstName.Vabs,     InstEmit32.Vabs_V,   typeof(OpCode32SimdCmpZ));
-            SetA32("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd,     InstEmit32.Vadd_I,   typeof(OpCode32SimdReg));
-            SetA32("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd,     InstEmit32.Vadd_S,   typeof(OpCode32SimdRegS));
-            SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd,     InstEmit32.Vadd_V,   typeof(OpCode32SimdReg));
-            SetA32("1111001x1x<<xxxxxxxx0000x0x0xxxx", InstName.Vaddl,    InstEmit32.Vaddl_I,  typeof(OpCode32SimdRegLong));
-            SetA32("1111001x1x<<xxxxxxxx0001x0x0xxxx", InstName.Vaddw,    InstEmit32.Vaddw_I,  typeof(OpCode32SimdRegWide));
-            SetA32("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand,     InstEmit32.Vand_I,   typeof(OpCode32SimdBinary));
-            SetA32("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic,     InstEmit32.Vbic_I,   typeof(OpCode32SimdBinary));
-            SetA32("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic,     InstEmit32.Vbic_II,  typeof(OpCode32SimdImm));
-            SetA32("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif,     InstEmit32.Vbif,     typeof(OpCode32SimdBinary));
-            SetA32("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit,     InstEmit32.Vbit,     typeof(OpCode32SimdBinary));
-            SetA32("111100110x01xxxxxxxx0001xxx1xxxx", InstName.Vbsl,     InstEmit32.Vbsl,     typeof(OpCode32SimdBinary));
-            SetA32("111100110x<<xxxxxxxx1000xxx1xxxx", InstName.Vceq,     InstEmit32.Vceq_I,   typeof(OpCode32SimdReg));
-            SetA32("111100100x00xxxxxxxx1110xxx0xxxx", InstName.Vceq,     InstEmit32.Vceq_V,   typeof(OpCode32SimdReg));
-            SetA32("111100111x11xx01xxxx0x010xx0xxxx", InstName.Vceq,     InstEmit32.Vceq_Z,   typeof(OpCode32SimdCmpZ));
-            SetA32("1111001x0x<<xxxxxxxx0011xxx1xxxx", InstName.Vcge,     InstEmit32.Vcge_I,   typeof(OpCode32SimdReg));
-            SetA32("111100110x00xxxxxxxx1110xxx0xxxx", InstName.Vcge,     InstEmit32.Vcge_V,   typeof(OpCode32SimdReg));
-            SetA32("111100111x11xx01xxxx0x001xx0xxxx", InstName.Vcge,     InstEmit32.Vcge_Z,   typeof(OpCode32SimdCmpZ));
-            SetA32("1111001x0x<<xxxxxxxx0011xxx0xxxx", InstName.Vcgt,     InstEmit32.Vcgt_I,   typeof(OpCode32SimdReg));
-            SetA32("111100110x10xxxxxxxx1110xxx0xxxx", InstName.Vcgt,     InstEmit32.Vcgt_V,   typeof(OpCode32SimdReg));
-            SetA32("111100111x11xx01xxxx0x000xx0xxxx", InstName.Vcgt,     InstEmit32.Vcgt_Z,   typeof(OpCode32SimdCmpZ));
-            SetA32("111100111x11xx01xxxx0x011xx0xxxx", InstName.Vcle,     InstEmit32.Vcle_Z,   typeof(OpCode32SimdCmpZ));
-            SetA32("111100111x11xx01xxxx0x100xx0xxxx", InstName.Vclt,     InstEmit32.Vclt_Z,   typeof(OpCode32SimdCmpZ));
-            SetA32("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp,     InstEmit32.Vcmp,     typeof(OpCode32SimdS));
-            SetA32("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe,    InstEmit32.Vcmpe,    typeof(OpCode32SimdS));
-            SetA32("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_FD,  typeof(OpCode32SimdS)); // FP 32 and 64, scalar.
-            SetA32("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_FI,  typeof(OpCode32SimdCvtFI)); // FP32 to int.
-            SetA32("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_FI,  typeof(OpCode32SimdCvtFI)); // Int to FP32.
-            SetA32("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_RM,  typeof(OpCode32SimdCvtFI)); // The many FP32 to int encodings (fp).
-            SetA32("111100111x111011xxxx011xxxx0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_V,   typeof(OpCode32SimdCmpZ)); // FP and integer, vector.
-            SetA32("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv,     InstEmit32.Vdiv_S,   typeof(OpCode32SimdRegS));
-            SetA32("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup,     InstEmit32.Vdup,     typeof(OpCode32SimdDupGP));
-            SetA32("111100111x11xxxxxxxx11000xx0xxxx", InstName.Vdup,     InstEmit32.Vdup_1,   typeof(OpCode32SimdDupElem));
-            SetA32("111100110x00xxxxxxxx0001xxx1xxxx", InstName.Veor,     InstEmit32.Veor_I,   typeof(OpCode32SimdBinary));
-            SetA32("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext,     InstEmit32.Vext,     typeof(OpCode32SimdExt));
-            SetA32("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma,     InstEmit32.Vfma_S,   typeof(OpCode32SimdRegS));
-            SetA32("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms,     InstEmit32.Vfms_S,   typeof(OpCode32SimdRegS));
-            SetA32("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd,    InstEmit32.Vhadd,    typeof(OpCode32SimdReg));
-            SetA32("111101001x10xxxxxxxxxx00xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x10xxxxxxxx0111xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     typeof(OpCode32SimdMemPair)); // Regs = 1.
-            SetA32("111101000x10xxxxxxxx1010xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     typeof(OpCode32SimdMemPair)); // Regs = 2.
-            SetA32("111101000x10xxxxxxxx0110xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     typeof(OpCode32SimdMemPair)); // Regs = 3.
-            SetA32("111101000x10xxxxxxxx0010xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     typeof(OpCode32SimdMemPair)); // Regs = 4.
-            SetA32("111101001x10xxxxxxxxxx01xxxxxxxx", InstName.Vld2,     InstEmit32.Vld2,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x10xxxxxxxx100xxxxxxxxx", InstName.Vld2,     InstEmit32.Vld2,     typeof(OpCode32SimdMemPair)); // Regs = 1, inc = 1/2 (itype).
-            SetA32("111101000x10xxxxxxxx0011xxxxxxxx", InstName.Vld2,     InstEmit32.Vld2,     typeof(OpCode32SimdMemPair)); // Regs = 2, inc = 2.
-            SetA32("111101001x10xxxxxxxxxx10xxxxxxxx", InstName.Vld3,     InstEmit32.Vld3,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x10xxxxxxxx010xxxxxxxxx", InstName.Vld3,     InstEmit32.Vld3,     typeof(OpCode32SimdMemPair)); // Inc = 1/2 (itype).
-            SetA32("111101001x10xxxxxxxxxx11xxxxxxxx", InstName.Vld4,     InstEmit32.Vld4,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x10xxxxxxxx000xxxxxxxxx", InstName.Vld4,     InstEmit32.Vld4,     typeof(OpCode32SimdMemPair)); // Inc = 1/2 (itype).
-            SetA32("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm,     InstEmit32.Vldm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,     InstEmit32.Vldm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,     InstEmit32.Vldm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm,     InstEmit32.Vldm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,     InstEmit32.Vldm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,     InstEmit32.Vldm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr,     InstEmit32.Vldr,     typeof(OpCode32SimdMemImm));
-            SetA32("1111001x0x<<xxxxxxxx0110xxx0xxxx", InstName.Vmax,     InstEmit32.Vmax_I,   typeof(OpCode32SimdReg));
-            SetA32("111100100x00xxxxxxxx1111xxx0xxxx", InstName.Vmax,     InstEmit32.Vmax_V,   typeof(OpCode32SimdReg));
-            SetA32("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin,     InstEmit32.Vmin_I,   typeof(OpCode32SimdReg));
-            SetA32("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin,     InstEmit32.Vmin_V,   typeof(OpCode32SimdReg));
-            SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm,   InstEmit32.Vmaxnm_S, typeof(OpCode32SimdRegS));
-            SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm,   InstEmit32.Vmaxnm_V, typeof(OpCode32SimdReg));
-            SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm,   InstEmit32.Vminnm_S, typeof(OpCode32SimdRegS));
-            SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm,   InstEmit32.Vminnm_V, typeof(OpCode32SimdReg));
-            SetA32("1111001x1x<<xxxxxxxx000xx1x0xxxx", InstName.Vmla,     InstEmit32.Vmla_1,   typeof(OpCode32SimdRegElem));
-            SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla,     InstEmit32.Vmla_I,   typeof(OpCode32SimdReg));
-            SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla,     InstEmit32.Vmla_S,   typeof(OpCode32SimdRegS));
-            SetA32("111100100x00xxxxxxxx1101xxx1xxxx", InstName.Vmla,     InstEmit32.Vmla_V,   typeof(OpCode32SimdReg));
-            SetA32("1111001x1x<<xxxxxxxx010xx1x0xxxx", InstName.Vmls,     InstEmit32.Vmls_1,   typeof(OpCode32SimdRegElem));
-            SetA32("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls,     InstEmit32.Vmls_S,   typeof(OpCode32SimdRegS));
-            SetA32("111100100x10xxxxxxxx1101xxx1xxxx", InstName.Vmls,     InstEmit32.Vmls_V,   typeof(OpCode32SimdReg));
-            SetA32("111100110xxxxxxxxxxx1001xxx0xxxx", InstName.Vmls,     InstEmit32.Vmls_I,   typeof(OpCode32SimdReg));
-            SetA32("1111001x1x<<xxxxxxx01010x0x0xxxx", InstName.Vmlsl,    InstEmit32.Vmlsl_I,  typeof(OpCode32SimdRegLong));
-            SetA32("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov,     InstEmit32.Vmov_G1,  typeof(OpCode32SimdMovGpElem)); // From gen purpose.
-            SetA32("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov,     InstEmit32.Vmov_G1,  typeof(OpCode32SimdMovGpElem)); // To gen purpose.
-            SetA32("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov,     InstEmit32.Vmov_G2,  typeof(OpCode32SimdMovGpDouble)); // To/from gen purpose x2 and single precision x2.
-            SetA32("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov,     InstEmit32.Vmov_GD,  typeof(OpCode32SimdMovGpDouble)); // To/from gen purpose x2 and double precision.
-            SetA32("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov,     InstEmit32.Vmov_GS,  typeof(OpCode32SimdMovGp)); // To/from gen purpose and single precision.
-            SetA32("1111001x1x000xxxxxxx0xx00x01xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   typeof(OpCode32SimdImm)); // D/Q vector I32.
-            SetA32("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   typeof(OpCode32SimdImm44)); // Scalar f16/32/64 based on size 01 10 11.
-            SetA32("1111001x1x000xxxxxxx10x00x01xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   typeof(OpCode32SimdImm)); // D/Q I16.
-            SetA32("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   typeof(OpCode32SimdImm)); // D/Q (dt - from cmode).
-            SetA32("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   typeof(OpCode32SimdImm)); // D/Q I64.
-            SetA32("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov,     InstEmit32.Vmov_S,   typeof(OpCode32SimdS));
-            SetA32("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl,    InstEmit32.Vmovl,    typeof(OpCode32SimdLong));
-            SetA32("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl,    InstEmit32.Vmovl,    typeof(OpCode32SimdLong));
-            SetA32("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl,    InstEmit32.Vmovl,    typeof(OpCode32SimdLong));
-            SetA32("111100111x11xx10xxxx001000x0xxx0", InstName.Vmovn,    InstEmit32.Vmovn,    typeof(OpCode32SimdCmpZ));
-            SetA32("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs,     InstEmit32.Vmrs,     typeof(OpCode32SimdSpecial));
-            SetA32("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr,     InstEmit32.Vmsr,     typeof(OpCode32SimdSpecial));
-            SetA32("1111001x1x<<xxxxxxxx100xx1x0xxxx", InstName.Vmul,     InstEmit32.Vmul_1,   typeof(OpCode32SimdRegElem));
-            SetA32("111100100x<<xxxxxxxx1001xxx1xxxx", InstName.Vmul,     InstEmit32.Vmul_I,   typeof(OpCode32SimdReg));
-            SetA32("111100110x00xxxxxxxx1001xxx1xxxx", InstName.Vmul,     InstEmit32.Vmul_I,   typeof(OpCode32SimdReg));
-            SetA32("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul,     InstEmit32.Vmul_S,   typeof(OpCode32SimdRegS));
-            SetA32("111100110x00xxxxxxxx1101xxx1xxxx", InstName.Vmul,     InstEmit32.Vmul_V,   typeof(OpCode32SimdReg));
-            SetA32("1111001x1x<<xxxxxxx01010x1x0xxxx", InstName.Vmull,    InstEmit32.Vmull_1,  typeof(OpCode32SimdRegElemLong));
-            SetA32("1111001x1x<<xxxxxxx01100x0x0xxxx", InstName.Vmull,    InstEmit32.Vmull_I,  typeof(OpCode32SimdRegLong));
-            SetA32("111100101x00xxxxxxx01110x0x0xxxx", InstName.Vmull,    InstEmit32.Vmull_I,  typeof(OpCode32SimdRegLong)); // Polynomial
-            SetA32("111100111x110000xxxx01011xx0xxxx", InstName.Vmvn,     InstEmit32.Vmvn_I,   typeof(OpCode32SimdBinary));
-            SetA32("1111001x1x000xxxxxxx0xx00x11xxxx", InstName.Vmvn,     InstEmit32.Vmvn_II,  typeof(OpCode32SimdImm)); // D/Q vector I32.
-            SetA32("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn,     InstEmit32.Vmvn_II,  typeof(OpCode32SimdImm));
-            SetA32("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn,     InstEmit32.Vmvn_II,  typeof(OpCode32SimdImm));
-            SetA32("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg,     InstEmit32.Vneg_S,   typeof(OpCode32SimdS));
-            SetA32("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg,     InstEmit32.Vneg_V,   typeof(OpCode32SimdCmpZ));
-            SetA32("111100111x111001xxxx01111xx0xxxx", InstName.Vneg,     InstEmit32.Vneg_V,   typeof(OpCode32SimdCmpZ));
-            SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,    InstEmit32.Vnmla_S,  typeof(OpCode32SimdRegS));
-            SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,    InstEmit32.Vnmls_S,  typeof(OpCode32SimdRegS));
-            SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,    InstEmit32.Vnmul_S,  typeof(OpCode32SimdRegS));
-            SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,     InstEmit32.Vorr_I,   typeof(OpCode32SimdBinary));
-            SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,     InstEmit32.Vorr_II,  typeof(OpCode32SimdImm));
-            SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,    InstEmit32.Vpadd_I,  typeof(OpCode32SimdReg));
-            SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd,    InstEmit32.Vpadd_V,  typeof(OpCode32SimdReg));
-            SetA32("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax,    InstEmit32.Vpmax_I,  typeof(OpCode32SimdReg));
-            SetA32("111100110x00xxxxxxxx1111x0x0xxxx", InstName.Vpmax,    InstEmit32.Vpmax_V,  typeof(OpCode32SimdReg));
-            SetA32("1111001x0x<<xxxxxxxx1010x0x1xxxx", InstName.Vpmin,    InstEmit32.Vpmin_I,  typeof(OpCode32SimdReg));
-            SetA32("111100110x10xxxxxxxx1111x0x0xxxx", InstName.Vpmin,    InstEmit32.Vpmin_V,  typeof(OpCode32SimdReg));
-            SetA32("1111001x1x>>>xxxxxxx100101x1xxx0", InstName.Vqrshrn,  InstEmit32.Vqrshrn,  typeof(OpCode32SimdShImmNarrow));
-            SetA32("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun, InstEmit32.Vqrshrun, typeof(OpCode32SimdShImmNarrow));
-            SetA32("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn,   InstEmit32.Vqshrn,   typeof(OpCode32SimdShImmNarrow));
-            SetA32("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe,   InstEmit32.Vrecpe,   typeof(OpCode32SimdSqrte));
-            SetA32("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps,   InstEmit32.Vrecps,   typeof(OpCode32SimdReg));
-            SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev,     InstEmit32.Vrev,     typeof(OpCode32SimdRev));
-            SetA32("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint,    InstEmit32.Vrint_RM, typeof(OpCode32SimdS));
-            SetA32("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint,    InstEmit32.Vrint_Z,  typeof(OpCode32SimdS));
-            SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr,    InstEmit32.Vrshr,    typeof(OpCode32SimdShImm));
-            SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte,  InstEmit32.Vrsqrte,  typeof(OpCode32SimdSqrte));
-            SetA32("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts,  InstEmit32.Vrsqrts,  typeof(OpCode32SimdReg));
-            SetA32("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel,     InstEmit32.Vsel,     typeof(OpCode32SimdSel));
-            SetA32("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl,     InstEmit32.Vshl,     typeof(OpCode32SimdShImm));
-            SetA32("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl,     InstEmit32.Vshl_I,   typeof(OpCode32SimdReg));
-            SetA32("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll,    InstEmit32.Vshll,    typeof(OpCode32SimdShImmLong)); // A1 encoding.
-            SetA32("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr,     InstEmit32.Vshr,     typeof(OpCode32SimdShImm));
-            SetA32("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn,    InstEmit32.Vshrn,    typeof(OpCode32SimdShImmNarrow));
-            SetA32("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt,    InstEmit32.Vsqrt_S,  typeof(OpCode32SimdS));
-            SetA32("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra,     InstEmit32.Vsra,     typeof(OpCode32SimdShImm));
-            SetA32("111101001x00xxxxxxxx<<00xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x00xxxxxxxx0111xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     typeof(OpCode32SimdMemPair)); // Regs = 1.
-            SetA32("111101000x00xxxxxxxx1010xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     typeof(OpCode32SimdMemPair)); // Regs = 2.
-            SetA32("111101000x00xxxxxxxx0110xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     typeof(OpCode32SimdMemPair)); // Regs = 3.
-            SetA32("111101000x00xxxxxxxx0010xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     typeof(OpCode32SimdMemPair)); // Regs = 4.
-            SetA32("111101001x00xxxxxxxx<<01xxxxxxxx", InstName.Vst2,     InstEmit32.Vst2,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x00xxxxxxxx100xxxxxxxxx", InstName.Vst2,     InstEmit32.Vst2,     typeof(OpCode32SimdMemPair)); // Regs = 1, inc = 1/2 (itype).
-            SetA32("111101000x00xxxxxxxx0011xxxxxxxx", InstName.Vst2,     InstEmit32.Vst2,     typeof(OpCode32SimdMemPair)); // Regs = 2, inc = 2.
-            SetA32("111101001x00xxxxxxxx<<10xxxxxxxx", InstName.Vst3,     InstEmit32.Vst3,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x00xxxxxxxx010xxxxxxxxx", InstName.Vst3,     InstEmit32.Vst3,     typeof(OpCode32SimdMemPair)); // Inc = 1/2 (itype).
-            SetA32("111101001x00xxxxxxxx<<11xxxxxxxx", InstName.Vst4,     InstEmit32.Vst4,     typeof(OpCode32SimdMemSingle));
-            SetA32("111101000x00xxxxxxxx000xxxxxxxxx", InstName.Vst4,     InstEmit32.Vst4,     typeof(OpCode32SimdMemPair)); // Inc = 1/2 (itype).
-            SetA32("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm,     InstEmit32.Vstm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,     InstEmit32.Vstm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,     InstEmit32.Vstm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm,     InstEmit32.Vstm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,     InstEmit32.Vstm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,     InstEmit32.Vstm,     typeof(OpCode32SimdMemMult));
-            SetA32("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr,     InstEmit32.Vstr,     typeof(OpCode32SimdMemImm));
-            SetA32("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub,     InstEmit32.Vsub_I,   typeof(OpCode32SimdReg));
-            SetA32("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub,     InstEmit32.Vsub_S,   typeof(OpCode32SimdRegS));
-            SetA32("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub,     InstEmit32.Vsub_V,   typeof(OpCode32SimdReg));
-            SetA32("1111001x1x<<xxxxxxxx0011x0x0xxxx", InstName.Vsubw,    InstEmit32.Vsubw_I,  typeof(OpCode32SimdRegWide));
-            SetA32("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl,     InstEmit32.Vtbl,     typeof(OpCode32SimdTbl));
-            SetA32("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn,     InstEmit32.Vtrn,     typeof(OpCode32SimdCmpZ));
-            SetA32("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst,     InstEmit32.Vtst,     typeof(OpCode32SimdReg));
-            SetA32("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp,     InstEmit32.Vuzp,     typeof(OpCode32SimdCmpZ));
-            SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip,     InstEmit32.Vzip,     typeof(OpCode32SimdCmpZ));
+            SetA32("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V,   InstEmit32.Aesd_V,   OpCode32Simd.Create);
+            SetA32("111100111x110000xxx0001100x0xxx0", InstName.Aese_V,   InstEmit32.Aese_V,   OpCode32Simd.Create);
+            SetA32("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V, InstEmit32.Aesimc_V, OpCode32Simd.Create);
+            SetA32("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V,  InstEmit32.Aesmc_V,  OpCode32Simd.Create);
+            SetA32("1111001x0x<<xxxxxxxx0111xxx0xxxx", InstName.Vabd,     InstEmit32.Vabd_I,   OpCode32SimdReg.Create);
+            SetA32("1111001x1x<<xxxxxxxx0111x0x0xxxx", InstName.Vabdl,    InstEmit32.Vabdl_I,  OpCode32SimdRegLong.Create);
+            SetA32("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs,     InstEmit32.Vabs_S,   OpCode32SimdS.Create);
+            SetA32("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs,     InstEmit32.Vabs_V,   OpCode32SimdCmpZ.Create);
+            SetA32("111100111x111001xxxx01110xx0xxxx", InstName.Vabs,     InstEmit32.Vabs_V,   OpCode32SimdCmpZ.Create);
+            SetA32("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd,     InstEmit32.Vadd_I,   OpCode32SimdReg.Create);
+            SetA32("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd,     InstEmit32.Vadd_S,   OpCode32SimdRegS.Create);
+            SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd,     InstEmit32.Vadd_V,   OpCode32SimdReg.Create);
+            SetA32("1111001x1x<<xxxxxxxx0000x0x0xxxx", InstName.Vaddl,    InstEmit32.Vaddl_I,  OpCode32SimdRegLong.Create);
+            SetA32("1111001x1x<<xxxxxxxx0001x0x0xxxx", InstName.Vaddw,    InstEmit32.Vaddw_I,  OpCode32SimdRegWide.Create);
+            SetA32("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand,     InstEmit32.Vand_I,   OpCode32SimdBinary.Create);
+            SetA32("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic,     InstEmit32.Vbic_I,   OpCode32SimdBinary.Create);
+            SetA32("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic,     InstEmit32.Vbic_II,  OpCode32SimdImm.Create);
+            SetA32("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif,     InstEmit32.Vbif,     OpCode32SimdBinary.Create);
+            SetA32("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit,     InstEmit32.Vbit,     OpCode32SimdBinary.Create);
+            SetA32("111100110x01xxxxxxxx0001xxx1xxxx", InstName.Vbsl,     InstEmit32.Vbsl,     OpCode32SimdBinary.Create);
+            SetA32("111100110x<<xxxxxxxx1000xxx1xxxx", InstName.Vceq,     InstEmit32.Vceq_I,   OpCode32SimdReg.Create);
+            SetA32("111100100x00xxxxxxxx1110xxx0xxxx", InstName.Vceq,     InstEmit32.Vceq_V,   OpCode32SimdReg.Create);
+            SetA32("111100111x11xx01xxxx0x010xx0xxxx", InstName.Vceq,     InstEmit32.Vceq_Z,   OpCode32SimdCmpZ.Create);
+            SetA32("1111001x0x<<xxxxxxxx0011xxx1xxxx", InstName.Vcge,     InstEmit32.Vcge_I,   OpCode32SimdReg.Create);
+            SetA32("111100110x00xxxxxxxx1110xxx0xxxx", InstName.Vcge,     InstEmit32.Vcge_V,   OpCode32SimdReg.Create);
+            SetA32("111100111x11xx01xxxx0x001xx0xxxx", InstName.Vcge,     InstEmit32.Vcge_Z,   OpCode32SimdCmpZ.Create);
+            SetA32("1111001x0x<<xxxxxxxx0011xxx0xxxx", InstName.Vcgt,     InstEmit32.Vcgt_I,   OpCode32SimdReg.Create);
+            SetA32("111100110x10xxxxxxxx1110xxx0xxxx", InstName.Vcgt,     InstEmit32.Vcgt_V,   OpCode32SimdReg.Create);
+            SetA32("111100111x11xx01xxxx0x000xx0xxxx", InstName.Vcgt,     InstEmit32.Vcgt_Z,   OpCode32SimdCmpZ.Create);
+            SetA32("111100111x11xx01xxxx0x011xx0xxxx", InstName.Vcle,     InstEmit32.Vcle_Z,   OpCode32SimdCmpZ.Create);
+            SetA32("111100111x11xx01xxxx0x100xx0xxxx", InstName.Vclt,     InstEmit32.Vclt_Z,   OpCode32SimdCmpZ.Create);
+            SetA32("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp,     InstEmit32.Vcmp,     OpCode32SimdS.Create);
+            SetA32("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe,    InstEmit32.Vcmpe,    OpCode32SimdS.Create);
+            SetA32("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_FD,  OpCode32SimdS.Create); // FP 32 and 64, scalar.
+            SetA32("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_FI,  OpCode32SimdCvtFI.Create); // FP32 to int.
+            SetA32("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_FI,  OpCode32SimdCvtFI.Create); // Int to FP32.
+            SetA32("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_RM,  OpCode32SimdCvtFI.Create); // The many FP32 to int encodings (fp).
+            SetA32("111100111x111011xxxx011xxxx0xxxx", InstName.Vcvt,     InstEmit32.Vcvt_V,   OpCode32SimdCmpZ.Create); // FP and integer, vector.
+            SetA32("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv,     InstEmit32.Vdiv_S,   OpCode32SimdRegS.Create);
+            SetA32("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup,     InstEmit32.Vdup,     OpCode32SimdDupGP.Create);
+            SetA32("111100111x11xxxxxxxx11000xx0xxxx", InstName.Vdup,     InstEmit32.Vdup_1,   OpCode32SimdDupElem.Create);
+            SetA32("111100110x00xxxxxxxx0001xxx1xxxx", InstName.Veor,     InstEmit32.Veor_I,   OpCode32SimdBinary.Create);
+            SetA32("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext,     InstEmit32.Vext,     OpCode32SimdExt.Create);
+            SetA32("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma,     InstEmit32.Vfma_S,   OpCode32SimdRegS.Create);
+            SetA32("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms,     InstEmit32.Vfms_S,   OpCode32SimdRegS.Create);
+            SetA32("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd,    InstEmit32.Vhadd,    OpCode32SimdReg.Create);
+            SetA32("111101001x10xxxxxxxxxx00xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x10xxxxxxxx0111xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     OpCode32SimdMemPair.Create); // Regs = 1.
+            SetA32("111101000x10xxxxxxxx1010xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     OpCode32SimdMemPair.Create); // Regs = 2.
+            SetA32("111101000x10xxxxxxxx0110xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     OpCode32SimdMemPair.Create); // Regs = 3.
+            SetA32("111101000x10xxxxxxxx0010xxxxxxxx", InstName.Vld1,     InstEmit32.Vld1,     OpCode32SimdMemPair.Create); // Regs = 4.
+            SetA32("111101001x10xxxxxxxxxx01xxxxxxxx", InstName.Vld2,     InstEmit32.Vld2,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x10xxxxxxxx100xxxxxxxxx", InstName.Vld2,     InstEmit32.Vld2,     OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
+            SetA32("111101000x10xxxxxxxx0011xxxxxxxx", InstName.Vld2,     InstEmit32.Vld2,     OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
+            SetA32("111101001x10xxxxxxxxxx10xxxxxxxx", InstName.Vld3,     InstEmit32.Vld3,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x10xxxxxxxx010xxxxxxxxx", InstName.Vld3,     InstEmit32.Vld3,     OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
+            SetA32("111101001x10xxxxxxxxxx11xxxxxxxx", InstName.Vld4,     InstEmit32.Vld4,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x10xxxxxxxx000xxxxxxxxx", InstName.Vld4,     InstEmit32.Vld4,     OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
+            SetA32("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm,     InstEmit32.Vldm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,     InstEmit32.Vldm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,     InstEmit32.Vldm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm,     InstEmit32.Vldm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,     InstEmit32.Vldm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,     InstEmit32.Vldm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr,     InstEmit32.Vldr,     OpCode32SimdMemImm.Create);
+            SetA32("1111001x0x<<xxxxxxxx0110xxx0xxxx", InstName.Vmax,     InstEmit32.Vmax_I,   OpCode32SimdReg.Create);
+            SetA32("111100100x00xxxxxxxx1111xxx0xxxx", InstName.Vmax,     InstEmit32.Vmax_V,   OpCode32SimdReg.Create);
+            SetA32("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin,     InstEmit32.Vmin_I,   OpCode32SimdReg.Create);
+            SetA32("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin,     InstEmit32.Vmin_V,   OpCode32SimdReg.Create);
+            SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm,   InstEmit32.Vmaxnm_S, OpCode32SimdRegS.Create);
+            SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm,   InstEmit32.Vmaxnm_V, OpCode32SimdReg.Create);
+            SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm,   InstEmit32.Vminnm_S, OpCode32SimdRegS.Create);
+            SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm,   InstEmit32.Vminnm_V, OpCode32SimdReg.Create);
+            SetA32("1111001x1x<<xxxxxxxx000xx1x0xxxx", InstName.Vmla,     InstEmit32.Vmla_1,   OpCode32SimdRegElem.Create);
+            SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla,     InstEmit32.Vmla_I,   OpCode32SimdReg.Create);
+            SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla,     InstEmit32.Vmla_S,   OpCode32SimdRegS.Create);
+            SetA32("111100100x00xxxxxxxx1101xxx1xxxx", InstName.Vmla,     InstEmit32.Vmla_V,   OpCode32SimdReg.Create);
+            SetA32("1111001x1x<<xxxxxxxx010xx1x0xxxx", InstName.Vmls,     InstEmit32.Vmls_1,   OpCode32SimdRegElem.Create);
+            SetA32("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls,     InstEmit32.Vmls_S,   OpCode32SimdRegS.Create);
+            SetA32("111100100x10xxxxxxxx1101xxx1xxxx", InstName.Vmls,     InstEmit32.Vmls_V,   OpCode32SimdReg.Create);
+            SetA32("111100110xxxxxxxxxxx1001xxx0xxxx", InstName.Vmls,     InstEmit32.Vmls_I,   OpCode32SimdReg.Create);
+            SetA32("1111001x1x<<xxxxxxx01010x0x0xxxx", InstName.Vmlsl,    InstEmit32.Vmlsl_I,  OpCode32SimdRegLong.Create);
+            SetA32("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov,     InstEmit32.Vmov_G1,  OpCode32SimdMovGpElem.Create); // From gen purpose.
+            SetA32("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov,     InstEmit32.Vmov_G1,  OpCode32SimdMovGpElem.Create); // To gen purpose.
+            SetA32("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov,     InstEmit32.Vmov_G2,  OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and single precision x2.
+            SetA32("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov,     InstEmit32.Vmov_GD,  OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and double precision.
+            SetA32("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov,     InstEmit32.Vmov_GS,  OpCode32SimdMovGp.Create); // To/from gen purpose and single precision.
+            SetA32("1111001x1x000xxxxxxx0xx00x01xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   OpCode32SimdImm.Create); // D/Q vector I32.
+            SetA32("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   OpCode32SimdImm44.Create); // Scalar f16/32/64 based on size 01 10 11.
+            SetA32("1111001x1x000xxxxxxx10x00x01xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   OpCode32SimdImm.Create); // D/Q I16.
+            SetA32("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   OpCode32SimdImm.Create); // D/Q (dt - from cmode).
+            SetA32("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov,     InstEmit32.Vmov_I,   OpCode32SimdImm.Create); // D/Q I64.
+            SetA32("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov,     InstEmit32.Vmov_S,   OpCode32SimdS.Create);
+            SetA32("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl,    InstEmit32.Vmovl,    OpCode32SimdLong.Create);
+            SetA32("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl,    InstEmit32.Vmovl,    OpCode32SimdLong.Create);
+            SetA32("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl,    InstEmit32.Vmovl,    OpCode32SimdLong.Create);
+            SetA32("111100111x11xx10xxxx001000x0xxx0", InstName.Vmovn,    InstEmit32.Vmovn,    OpCode32SimdCmpZ.Create);
+            SetA32("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs,     InstEmit32.Vmrs,     OpCode32SimdSpecial.Create);
+            SetA32("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr,     InstEmit32.Vmsr,     OpCode32SimdSpecial.Create);
+            SetA32("1111001x1x<<xxxxxxxx100xx1x0xxxx", InstName.Vmul,     InstEmit32.Vmul_1,   OpCode32SimdRegElem.Create);
+            SetA32("111100100x<<xxxxxxxx1001xxx1xxxx", InstName.Vmul,     InstEmit32.Vmul_I,   OpCode32SimdReg.Create);
+            SetA32("111100110x00xxxxxxxx1001xxx1xxxx", InstName.Vmul,     InstEmit32.Vmul_I,   OpCode32SimdReg.Create);
+            SetA32("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul,     InstEmit32.Vmul_S,   OpCode32SimdRegS.Create);
+            SetA32("111100110x00xxxxxxxx1101xxx1xxxx", InstName.Vmul,     InstEmit32.Vmul_V,   OpCode32SimdReg.Create);
+            SetA32("1111001x1x<<xxxxxxx01010x1x0xxxx", InstName.Vmull,    InstEmit32.Vmull_1,  OpCode32SimdRegElemLong.Create);
+            SetA32("1111001x1x<<xxxxxxx01100x0x0xxxx", InstName.Vmull,    InstEmit32.Vmull_I,  OpCode32SimdRegLong.Create);
+            SetA32("111100101x00xxxxxxx01110x0x0xxxx", InstName.Vmull,    InstEmit32.Vmull_I,  OpCode32SimdRegLong.Create); // Polynomial
+            SetA32("111100111x110000xxxx01011xx0xxxx", InstName.Vmvn,     InstEmit32.Vmvn_I,   OpCode32SimdBinary.Create);
+            SetA32("1111001x1x000xxxxxxx0xx00x11xxxx", InstName.Vmvn,     InstEmit32.Vmvn_II,  OpCode32SimdImm.Create); // D/Q vector I32.
+            SetA32("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn,     InstEmit32.Vmvn_II,  OpCode32SimdImm.Create);
+            SetA32("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn,     InstEmit32.Vmvn_II,  OpCode32SimdImm.Create);
+            SetA32("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg,     InstEmit32.Vneg_S,   OpCode32SimdS.Create);
+            SetA32("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg,     InstEmit32.Vneg_V,   OpCode32SimdCmpZ.Create);
+            SetA32("111100111x111001xxxx01111xx0xxxx", InstName.Vneg,     InstEmit32.Vneg_V,   OpCode32SimdCmpZ.Create);
+            SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,    InstEmit32.Vnmla_S,  OpCode32SimdRegS.Create);
+            SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,    InstEmit32.Vnmls_S,  OpCode32SimdRegS.Create);
+            SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,    InstEmit32.Vnmul_S,  OpCode32SimdRegS.Create);
+            SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,     InstEmit32.Vorr_I,   OpCode32SimdBinary.Create);
+            SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,     InstEmit32.Vorr_II,  OpCode32SimdImm.Create);
+            SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,    InstEmit32.Vpadd_I,  OpCode32SimdReg.Create);
+            SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd,    InstEmit32.Vpadd_V,  OpCode32SimdReg.Create);
+            SetA32("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax,    InstEmit32.Vpmax_I,  OpCode32SimdReg.Create);
+            SetA32("111100110x00xxxxxxxx1111x0x0xxxx", InstName.Vpmax,    InstEmit32.Vpmax_V,  OpCode32SimdReg.Create);
+            SetA32("1111001x0x<<xxxxxxxx1010x0x1xxxx", InstName.Vpmin,    InstEmit32.Vpmin_I,  OpCode32SimdReg.Create);
+            SetA32("111100110x10xxxxxxxx1111x0x0xxxx", InstName.Vpmin,    InstEmit32.Vpmin_V,  OpCode32SimdReg.Create);
+            SetA32("1111001x1x>>>xxxxxxx100101x1xxx0", InstName.Vqrshrn,  InstEmit32.Vqrshrn,  OpCode32SimdShImmNarrow.Create);
+            SetA32("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun, InstEmit32.Vqrshrun, OpCode32SimdShImmNarrow.Create);
+            SetA32("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn,   InstEmit32.Vqshrn,   OpCode32SimdShImmNarrow.Create);
+            SetA32("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe,   InstEmit32.Vrecpe,   OpCode32SimdSqrte.Create);
+            SetA32("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps,   InstEmit32.Vrecps,   OpCode32SimdReg.Create);
+            SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev,     InstEmit32.Vrev,     OpCode32SimdRev.Create);
+            SetA32("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint,    InstEmit32.Vrint_RM, OpCode32SimdS.Create);
+            SetA32("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint,    InstEmit32.Vrint_Z,  OpCode32SimdS.Create);
+            SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr,    InstEmit32.Vrshr,    OpCode32SimdShImm.Create);
+            SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte,  InstEmit32.Vrsqrte,  OpCode32SimdSqrte.Create);
+            SetA32("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts,  InstEmit32.Vrsqrts,  OpCode32SimdReg.Create);
+            SetA32("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel,     InstEmit32.Vsel,     OpCode32SimdSel.Create);
+            SetA32("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl,     InstEmit32.Vshl,     OpCode32SimdShImm.Create);
+            SetA32("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl,     InstEmit32.Vshl_I,   OpCode32SimdReg.Create);
+            SetA32("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll,    InstEmit32.Vshll,    OpCode32SimdShImmLong.Create); // A1 encoding.
+            SetA32("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr,     InstEmit32.Vshr,     OpCode32SimdShImm.Create);
+            SetA32("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn,    InstEmit32.Vshrn,    OpCode32SimdShImmNarrow.Create);
+            SetA32("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt,    InstEmit32.Vsqrt_S,  OpCode32SimdS.Create);
+            SetA32("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra,     InstEmit32.Vsra,     OpCode32SimdShImm.Create);
+            SetA32("111101001x00xxxxxxxx<<00xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x00xxxxxxxx0111xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     OpCode32SimdMemPair.Create); // Regs = 1.
+            SetA32("111101000x00xxxxxxxx1010xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     OpCode32SimdMemPair.Create); // Regs = 2.
+            SetA32("111101000x00xxxxxxxx0110xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     OpCode32SimdMemPair.Create); // Regs = 3.
+            SetA32("111101000x00xxxxxxxx0010xxxxxxxx", InstName.Vst1,     InstEmit32.Vst1,     OpCode32SimdMemPair.Create); // Regs = 4.
+            SetA32("111101001x00xxxxxxxx<<01xxxxxxxx", InstName.Vst2,     InstEmit32.Vst2,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x00xxxxxxxx100xxxxxxxxx", InstName.Vst2,     InstEmit32.Vst2,     OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
+            SetA32("111101000x00xxxxxxxx0011xxxxxxxx", InstName.Vst2,     InstEmit32.Vst2,     OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
+            SetA32("111101001x00xxxxxxxx<<10xxxxxxxx", InstName.Vst3,     InstEmit32.Vst3,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x00xxxxxxxx010xxxxxxxxx", InstName.Vst3,     InstEmit32.Vst3,     OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
+            SetA32("111101001x00xxxxxxxx<<11xxxxxxxx", InstName.Vst4,     InstEmit32.Vst4,     OpCode32SimdMemSingle.Create);
+            SetA32("111101000x00xxxxxxxx000xxxxxxxxx", InstName.Vst4,     InstEmit32.Vst4,     OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
+            SetA32("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm,     InstEmit32.Vstm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,     InstEmit32.Vstm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,     InstEmit32.Vstm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm,     InstEmit32.Vstm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,     InstEmit32.Vstm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,     InstEmit32.Vstm,     OpCode32SimdMemMult.Create);
+            SetA32("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr,     InstEmit32.Vstr,     OpCode32SimdMemImm.Create);
+            SetA32("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub,     InstEmit32.Vsub_I,   OpCode32SimdReg.Create);
+            SetA32("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub,     InstEmit32.Vsub_S,   OpCode32SimdRegS.Create);
+            SetA32("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub,     InstEmit32.Vsub_V,   OpCode32SimdReg.Create);
+            SetA32("1111001x1x<<xxxxxxxx0011x0x0xxxx", InstName.Vsubw,    InstEmit32.Vsubw_I,  OpCode32SimdRegWide.Create);
+            SetA32("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl,     InstEmit32.Vtbl,     OpCode32SimdTbl.Create);
+            SetA32("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn,     InstEmit32.Vtrn,     OpCode32SimdCmpZ.Create);
+            SetA32("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst,     InstEmit32.Vtst,     OpCode32SimdReg.Create);
+            SetA32("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp,     InstEmit32.Vuzp,     OpCode32SimdCmpZ.Create);
+            SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip,     InstEmit32.Vzip,     OpCode32SimdCmpZ.Create);
 #endregion
 
-            FillFastLookupTable(_instA32FastLookup, _allInstA32);
-            FillFastLookupTable(_instT32FastLookup, _allInstT32);
-            FillFastLookupTable(_instA64FastLookup, _allInstA64);
+            FillFastLookupTable(InstA32FastLookup, AllInstA32);
+            FillFastLookupTable(InstT32FastLookup, AllInstT32);
+            FillFastLookupTable(InstA64FastLookup, AllInstA64);
         }
 
         private static void FillFastLookupTable(InstInfo[][] table, List<InstInfo> allInsts)
@@ -1005,22 +984,22 @@ namespace ARMeilleure.Decoders
             }
         }
 
-        private static void SetA32(string encoding, InstName name, InstEmitter emitter, Type type)
+        private static void SetA32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
         {
-            Set(encoding, ExecutionMode.Aarch32Arm, new InstDescriptor(name, emitter), type);
+            Set(encoding, ExecutionMode.Aarch32Arm, new InstDescriptor(name, emitter), makeOp);
         }
 
-        private static void SetT32(string encoding, InstName name, InstEmitter emitter, Type type)
+        private static void SetT32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
         {
-            Set(encoding, ExecutionMode.Aarch32Thumb, new InstDescriptor(name, emitter), type);
+            Set(encoding, ExecutionMode.Aarch32Thumb, new InstDescriptor(name, emitter), makeOp);
         }
 
-        private static void SetA64(string encoding, InstName name, InstEmitter emitter, Type type)
+        private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
         {
-            Set(encoding, ExecutionMode.Aarch64, new InstDescriptor(name, emitter), type);
+            Set(encoding, ExecutionMode.Aarch64, new InstDescriptor(name, emitter), makeOp);
         }
 
-        private static void Set(string encoding, ExecutionMode mode, InstDescriptor inst, Type type)
+        private static void Set(string encoding, ExecutionMode mode, InstDescriptor inst, MakeOp makeOp)
         {
             int bit   = encoding.Length - 1;
             int value = 0;
@@ -1069,7 +1048,7 @@ namespace ARMeilleure.Decoders
 
             if (xBits == 0)
             {
-                InsertInst(new InstInfo(xMask, value, inst, type), mode);
+                InsertInst(new InstInfo(xMask, value, inst, makeOp), mode);
 
                 return;
             }
@@ -1085,7 +1064,7 @@ namespace ARMeilleure.Decoders
 
                 if (mask != blacklisted)
                 {
-                    InsertInst(new InstInfo(xMask, value | mask, inst, type), mode);
+                    InsertInst(new InstInfo(xMask, value | mask, inst, makeOp), mode);
                 }
             }
         }
@@ -1094,25 +1073,25 @@ namespace ARMeilleure.Decoders
         {
             switch (mode)
             {
-                case ExecutionMode.Aarch32Arm:   _allInstA32.Add(info); break;
-                case ExecutionMode.Aarch32Thumb: _allInstT32.Add(info); break;
-                case ExecutionMode.Aarch64:      _allInstA64.Add(info); break;
+                case ExecutionMode.Aarch32Arm:   AllInstA32.Add(info); break;
+                case ExecutionMode.Aarch32Thumb: AllInstT32.Add(info); break;
+                case ExecutionMode.Aarch64:      AllInstA64.Add(info); break;
             }
         }
 
         public static (InstDescriptor inst, MakeOp makeOp) GetInstA32(int opCode)
         {
-            return GetInstFromList(_instA32FastLookup[ToFastLookupIndex(opCode)], opCode);
+            return GetInstFromList(InstA32FastLookup[ToFastLookupIndex(opCode)], opCode);
         }
 
         public static (InstDescriptor inst, MakeOp makeOp) GetInstT32(int opCode)
         {
-            return GetInstFromList(_instT32FastLookup[ToFastLookupIndex(opCode)], opCode);
+            return GetInstFromList(InstT32FastLookup[ToFastLookupIndex(opCode)], opCode);
         }
 
         public static (InstDescriptor inst, MakeOp makeOp) GetInstA64(int opCode)
         {
-            return GetInstFromList(_instA64FastLookup[ToFastLookupIndex(opCode)], opCode);
+            return GetInstFromList(InstA64FastLookup[ToFastLookupIndex(opCode)], opCode);
         }
 
         private static (InstDescriptor inst, MakeOp makeOp) GetInstFromList(InstInfo[] insts, int opCode)
diff --git a/Ryujinx.Graphics.Shader/Decoders/Decoder.cs b/Ryujinx.Graphics.Shader/Decoders/Decoder.cs
index a15d7f9ee3..3f08bdd919 100644
--- a/Ryujinx.Graphics.Shader/Decoders/Decoder.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/Decoder.cs
@@ -231,7 +231,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
                 long opCode = gpuAccessor.MemoryRead<long>(startAddress + opAddress);
 
-                (InstEmitter emitter, OpCodeTable.OpActivator opActivator) = OpCodeTable.GetEmitter(opCode);
+                (InstEmitter emitter, OpCodeTable.MakeOp makeOp) = OpCodeTable.GetEmitter(opCode);
 
                 if (emitter == null)
                 {
@@ -242,12 +242,12 @@ namespace Ryujinx.Graphics.Shader.Decoders
                     continue;
                 }
 
-                if (opActivator == null)
+                if (makeOp == null)
                 {
-                    throw new ArgumentNullException(nameof(opActivator));
+                    throw new ArgumentNullException(nameof(makeOp));
                 }
 
-                OpCode op = (OpCode)opActivator(emitter, opAddress, opCode);
+                OpCode op = makeOp(emitter, opAddress, opCode);
 
                 block.OpCodes.Add(op);
             }
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCode.cs b/Ryujinx.Graphics.Shader/Decoders/OpCode.cs
index 94af49e05c..27e10f89f3 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCode.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCode.cs
@@ -16,6 +16,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         // When inverted, the always true predicate == always false.
         public bool NeverExecute => Predicate.Index == RegisterConsts.PredicateTrueIndex && InvertPredicate;
 
+        public static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCode(emitter, address, opCode);
+
         public OpCode(InstEmitter emitter, ulong address, long opCode)
         {
             Emitter   = emitter;
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs
index 15fbb9af79..035aa7301e 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs
@@ -16,6 +16,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public bool SetCondCode { get; protected set; }
         public bool Saturate    { get; protected set; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAlu(emitter, address, opCode);
+
         public OpCodeAlu(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd          = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs
index 9c12798947..04ef64dff7 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public int Offset { get; }
         public int Slot   { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluCbuf(emitter, address, opCode);
+
         public OpCodeAluCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs
index a407fc6bf8..7faa0d8003 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public int Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluImm(emitter, address, opCode);
+
         public OpCodeAluImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.DecodeS20Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs
index 9aeb32bd4d..b475c8a93a 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public int Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluImm2x10(emitter, address, opCode);
+
         public OpCodeAluImm2x10(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.Decode2xF10Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs
index 5941e0b9a2..26b27a3d86 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public int Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluImm32(emitter, address, opCode);
+
         public OpCodeAluImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = opCode.Extract(20, 32);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs
index 13b96a3ae8..fe61a51f1a 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public Register Rb { get; protected set; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluReg(emitter, address, opCode);
+
         public OpCodeAluReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs
index 6cf6bd2e22..628fb472bc 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public int Offset { get; }
         public int Slot   { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluRegCbuf(emitter, address, opCode);
+
         public OpCodeAluRegCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs
index b572703ec8..1bf5d0cd10 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs
@@ -16,6 +16,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public AtomicOp AtomicOp { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAtom(emitter, address, opCode);
+
         public OpCodeAtom(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs
index fd8e63fcfb..1457b60208 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public int AttributeOffset { get; }
         public int Count           { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAttribute(emitter, address, opCode);
+
         public OpCodeAttribute(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             AttributeOffset = opCode.Extract(20, 10);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs
index 81e28aa143..7c82c68382 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public BarrierMode Mode { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBarrier(emitter, address, opCode);
+
         public OpCodeBarrier(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Mode = (BarrierMode)((opCode >> 32) & 0x9b);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs
index c4fa921265..71cb9bca9c 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs
@@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public bool PushTarget { get; protected set; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBranch(emitter, address, opCode);
+
         public OpCodeBranch(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Condition = (Condition)(opCode & 0x1f);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs
index 3e694e61c8..b3911d6a07 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs
@@ -11,6 +11,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public int Offset { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBranchIndir(emitter, address, opCode);
+
         public OpCodeBranchIndir(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             PossibleTargets = new HashSet<Block>();
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs
index 7ea66fe455..f6c3e4f46a 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public Dictionary<OpCodePush, int> Targets { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBranchPop(emitter, address, opCode);
+
         public OpCodeBranchPop(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Targets = new Dictionary<OpCodePush, int>();
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs
index 99d4cdfdd1..f13bfc4760 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public float Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeDArithImm(emitter, address, opCode);
+
         public OpCodeDArithImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.DecodeD20Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs
index d50903eb4f..caad26a3a5 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public Condition Condition { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeExit(emitter, address, opCode);
+
         public OpCodeExit(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Condition = (Condition)opCode.Extract(0, 5);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs
index cfbf65c3dd..d262f1578f 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs
@@ -11,6 +11,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public bool FlushToZero { get; }
         public bool AbsoluteA   { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArith(emitter, address, opCode);
+
         public OpCodeFArith(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             RoundingMode = (RoundingMode)opCode.Extract(39, 2);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs
index 5486bb0b07..1475f11b86 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public int Offset { get; }
         public int Slot   { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithCbuf(emitter, address, opCode);
+
         public OpCodeFArithCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs
index 1bb6f42552..91a6561be6 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public float Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithImm(emitter, address, opCode);
+
         public OpCodeFArithImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.DecodeF20Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs
index aecc5143ca..09d0a13d87 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs
@@ -14,6 +14,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public float Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithImm32(emitter, address, opCode);
+
         public OpCodeFArithImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             int imm = opCode.Extract(20, 32);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs
index 55cf448597..f4b64584d4 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public Register Rb { get; protected set; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithReg(emitter, address, opCode);
+
         public OpCodeFArithReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs
index 315c2c8b15..c1b5cca6aa 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public int Offset { get; }
         public int Slot   { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithRegCbuf(emitter, address, opCode);
+
         public OpCodeFArithRegCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs
index cb5f155e82..aa216db2e6 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public float Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFsetImm(emitter, address, opCode);
+
         public OpCodeFsetImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.DecodeF20Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs
index 32f3cd7ab8..9123cb9755 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs
@@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public FPHalfSwizzle SwizzleA { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfma(emitter, address, opCode);
+
         public OpCodeHfma(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs
index 33768c7d01..d73223ab98 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs
@@ -14,6 +14,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public FPHalfSwizzle SwizzleB => FPHalfSwizzle.FP32;
         public FPHalfSwizzle SwizzleC { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaCbuf(emitter, address, opCode);
+
         public OpCodeHfmaCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs
index 80a5a14089..c847be0f1b 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs
@@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public FPHalfSwizzle SwizzleB => FPHalfSwizzle.FP16;
         public FPHalfSwizzle SwizzleC { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaImm2x10(emitter, address, opCode);
+
         public OpCodeHfmaImm2x10(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.Decode2xF10Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs
index 05eb9ffe0a..6d1ab265cb 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs
@@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public FPHalfSwizzle SwizzleB => FPHalfSwizzle.FP16;
         public FPHalfSwizzle SwizzleC => FPHalfSwizzle.FP16;
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaImm32(emitter, address, opCode);
+
         public OpCodeHfmaImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = opCode.Extract(20, 32);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs
index 714c89dead..ebb1fec903 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs
@@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public FPHalfSwizzle SwizzleB { get; }
         public FPHalfSwizzle SwizzleC { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaReg(emitter, address, opCode);
+
         public OpCodeHfmaReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs
index c0001908ce..dc5d2fe94e 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs
@@ -14,6 +14,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public FPHalfSwizzle SwizzleB { get; }
         public FPHalfSwizzle SwizzleC => FPHalfSwizzle.FP32;
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaRegCbuf(emitter, address, opCode);
+
         public OpCodeHfmaRegCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs
index 03e1e44cec..d5af5049ea 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public int Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHsetImm2x10(emitter, address, opCode);
+
         public OpCodeHsetImm2x10(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.Decode2xF10Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs
index 265d45a93c..5b2f806369 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs
@@ -20,6 +20,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public bool UseComponents { get; }
         public bool IsBindless    { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeImage(emitter, address, opCode);
+
         public OpCodeImage(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Ra = new Register(opCode.Extract(8,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs
index b475b6a16a..51138a1de9 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs
@@ -8,6 +8,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public InterpolationMode Mode { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeIpa(emitter, address, opCode);
+
         public OpCodeIpa(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             AttributeOffset = opCode.Extract(28, 10);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs
index 05bac28cbd..28d34d5aa1 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs
@@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public CbIndexMode IndexMode { get; }
         public IntegerSize Size { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLdc(emitter, address, opCode);
+
         public OpCodeLdc(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs
index c5f903451b..45399de0d1 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs
@@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public Register Predicate48 { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLop(emitter, address, opCode);
+
         public OpCodeLop(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             InvertA = opCode.Extract(39);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs
index f174733c42..7a32382acc 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public int Offset { get; }
         public int Slot   { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopCbuf(emitter, address, opCode);
+
         public OpCodeLopCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs
index a2f091a2c4..b2443688c2 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public int Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopImm(emitter, address, opCode);
+
         public OpCodeLopImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.DecodeS20Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs
index cb48f3a615..a751c2cd7a 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs
@@ -9,6 +9,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public bool InvertA { get; }
         public bool InvertB { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopImm32(emitter, address, opCode);
+
         public OpCodeLopImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             LogicalOp = (LogicalOperation)opCode.Extract(53, 2);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs
index 5f43db72b5..d14e4920d4 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public Register Rb { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopReg(emitter, address, opCode);
+
         public OpCodeLopReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs
index a0a9c8cacc..65da3aedb3 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs
@@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public IntegerSize Size { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeMemory(emitter, address, opCode);
+
         public OpCodeMemory(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs
index c31fe87b97..c086b460d6 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public BarrierLevel Level { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeMemoryBarrier(emitter, address, opCode);
+
         public OpCodeMemoryBarrier(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Level = (BarrierLevel)opCode.Extract(8, 2);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs
index df508442d3..9d88b86398 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs
@@ -12,6 +12,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public LogicalOperation LogicalOpAB { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodePset(emitter, address, opCode);
+
         public OpCodePset(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Predicate12 = new Register(opCode.Extract(12, 3), RegisterType.Predicate);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs
index a7657bcf8e..4f00a0697e 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs
@@ -8,6 +8,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public Dictionary<OpCodeBranchPop, Operand> PopOps { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodePush(emitter, address, opCode);
+
         public OpCodePush(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             PopOps = new Dictionary<OpCodeBranchPop, Operand>();
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs
index 2629d2899f..98bf9939a7 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs
@@ -15,6 +15,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public bool Extended { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeRed(emitter, address, opCode);
+
         public OpCodeRed(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs
index b4ee10fb3d..94ed0beeb2 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs
@@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public bool FlushToZero { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSet(emitter, address, opCode);
+
         public OpCodeSet(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Predicate0 = new Register(opCode.Extract(0, 3), RegisterType.Predicate);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs
index 4f3dbd7412..4e0eccf977 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public int Offset { get; }
         public int Slot   { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSetCbuf(emitter, address, opCode);
+
         public OpCodeSetCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Offset = opCode.Extract(20, 14);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs
index bc63b9f476..7c82c07c01 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public int Immediate { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSetImm(emitter, address, opCode);
+
         public OpCodeSetImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Immediate = DecoderHelper.DecodeS20Immediate(opCode);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs
index bbdee19622..8ef0d7e498 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public Register Rb { get; protected set; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSetReg(emitter, address, opCode);
+
         public OpCodeSetReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs
index 43693cf490..f9f424332c 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs
@@ -19,6 +19,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public Register Predicate48 { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeShuffle(emitter, address, opCode);
+
         public OpCodeShuffle(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs
index 1b5f5c7c24..61168b590f 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs
@@ -1,12 +1,11 @@
 using Ryujinx.Graphics.Shader.Instructions;
 using System;
-using System.Reflection.Emit;
 
 namespace Ryujinx.Graphics.Shader.Decoders
 {
     static class OpCodeTable
     {
-        public delegate object OpActivator(InstEmitter emitter, ulong address, long opCode);
+        public delegate OpCode MakeOp(InstEmitter emitter, ulong address, long opCode);
 
         private const int EncodingBits = 14;
 
@@ -14,35 +13,15 @@ namespace Ryujinx.Graphics.Shader.Decoders
         {
             public InstEmitter Emitter { get; }
 
-            public Type OpCodeType { get; }
+            public MakeOp MakeOp { get; }
 
             public int XBits { get; }
 
-            public OpActivator OpActivator { get; }
-
-            public TableEntry(InstEmitter emitter, Type opCodeType, int xBits)
+            public TableEntry(InstEmitter emitter, MakeOp makeOp, int xBits)
             {
-                Emitter     = emitter;
-                OpCodeType  = opCodeType;
-                XBits       = xBits;
-                OpActivator = CacheOpActivator(opCodeType);
-            }
-
-            private static OpActivator CacheOpActivator(Type type)
-            {
-                Type[] argTypes = new Type[] { typeof(InstEmitter), typeof(ulong), typeof(long) };
-
-                DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
-
-                ILGenerator generator = mthd.GetILGenerator();
-
-                generator.Emit(OpCodes.Ldarg_0);
-                generator.Emit(OpCodes.Ldarg_1);
-                generator.Emit(OpCodes.Ldarg_2);
-                generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
-                generator.Emit(OpCodes.Ret);
-
-                return (OpActivator)mthd.CreateDelegate(typeof(OpActivator));
+                Emitter = emitter;
+                MakeOp  = makeOp;
+                XBits   = xBits;
             }
         }
 
@@ -53,205 +32,205 @@ namespace Ryujinx.Graphics.Shader.Decoders
             _opCodes = new TableEntry[1 << EncodingBits];
 
 #region Instructions
-            Set("1110111111011x", InstEmit.Ald,     typeof(OpCodeAttribute));
-            Set("1110111111110x", InstEmit.Ast,     typeof(OpCodeAttribute));
-            Set("11101100xxxxxx", InstEmit.Atoms,   typeof(OpCodeAtom));
-            Set("1111000010101x", InstEmit.Bar,     typeof(OpCodeBarrier));
-            Set("0100110000000x", InstEmit.Bfe,     typeof(OpCodeAluCbuf));
-            Set("0011100x00000x", InstEmit.Bfe,     typeof(OpCodeAluImm));
-            Set("0101110000000x", InstEmit.Bfe,     typeof(OpCodeAluReg));
-            Set("0100101111110x", InstEmit.Bfi,     typeof(OpCodeAluCbuf));
-            Set("0011011x11110x", InstEmit.Bfi,     typeof(OpCodeAluImm));
-            Set("0101001111110x", InstEmit.Bfi,     typeof(OpCodeAluRegCbuf));
-            Set("0101101111110x", InstEmit.Bfi,     typeof(OpCodeAluReg));
-            Set("111000100100xx", InstEmit.Bra,     typeof(OpCodeBranch));
-            Set("111000110100xx", InstEmit.Brk,     typeof(OpCodeBranchPop));
-            Set("111000100101xx", InstEmit.Brx,     typeof(OpCodeBranchIndir));
-            Set("0101000010100x", InstEmit.Csetp,   typeof(OpCodePset));
-            Set("0100110001110x", InstEmit.Dadd,    typeof(OpCodeFArithCbuf));
-            Set("0011100x01110x", InstEmit.Dadd,    typeof(OpCodeDArithImm));
-            Set("0101110001110x", InstEmit.Dadd,    typeof(OpCodeFArithReg));
-            Set("1111000011110x", InstEmit.Depbar,  typeof(OpCode));
-            Set("010010110111xx", InstEmit.Dfma,    typeof(OpCodeFArithCbuf));
-            Set("0011011x0111xx", InstEmit.Dfma,    typeof(OpCodeDArithImm));
-            Set("010100110111xx", InstEmit.Dfma,    typeof(OpCodeFArithRegCbuf));
-            Set("010110110111xx", InstEmit.Dfma,    typeof(OpCodeFArithReg));
-            Set("0100110010000x", InstEmit.Dmul,    typeof(OpCodeFArithCbuf));
-            Set("0011100x10000x", InstEmit.Dmul,    typeof(OpCodeDArithImm));
-            Set("0101110010000x", InstEmit.Dmul,    typeof(OpCodeFArithReg));
-            Set("111000110000xx", InstEmit.Exit,    typeof(OpCodeExit));
-            Set("0100110010101x", InstEmit.F2F,     typeof(OpCodeFArithCbuf));
-            Set("0011100x10101x", InstEmit.F2F,     typeof(OpCodeFArithImm));
-            Set("0101110010101x", InstEmit.F2F,     typeof(OpCodeFArithReg));
-            Set("0100110010110x", InstEmit.F2I,     typeof(OpCodeFArithCbuf));
-            Set("0011100x10110x", InstEmit.F2I,     typeof(OpCodeFArithImm));
-            Set("0101110010110x", InstEmit.F2I,     typeof(OpCodeFArithReg));
-            Set("0100110001011x", InstEmit.Fadd,    typeof(OpCodeFArithCbuf));
-            Set("0011100x01011x", InstEmit.Fadd,    typeof(OpCodeFArithImm));
-            Set("000010xxxxxxxx", InstEmit.Fadd,    typeof(OpCodeFArithImm32));
-            Set("0101110001011x", InstEmit.Fadd,    typeof(OpCodeFArithReg));
-            Set("010010111010xx", InstEmit.Fcmp,    typeof(OpCodeFArithCbuf));
-            Set("0011011x1010xx", InstEmit.Fcmp,    typeof(OpCodeFArithImm));
-            Set("010110111010xx", InstEmit.Fcmp,    typeof(OpCodeFArithReg));
-            Set("010100111010xx", InstEmit.Fcmp,    typeof(OpCodeFArithRegCbuf));
-            Set("010010011xxxxx", InstEmit.Ffma,    typeof(OpCodeFArithCbuf));
-            Set("0011001x1xxxxx", InstEmit.Ffma,    typeof(OpCodeFArithImm));
-            Set("000011xxxxxxxx", InstEmit.Ffma32i, typeof(OpCodeFArithImm32));
-            Set("010100011xxxxx", InstEmit.Ffma,    typeof(OpCodeFArithRegCbuf));
-            Set("010110011xxxxx", InstEmit.Ffma,    typeof(OpCodeFArithReg));
-            Set("0100110000110x", InstEmit.Flo,     typeof(OpCodeAluCbuf));
-            Set("0011100x00110x", InstEmit.Flo,     typeof(OpCodeAluImm));
-            Set("0101110000110x", InstEmit.Flo,     typeof(OpCodeAluReg));
-            Set("0100110001100x", InstEmit.Fmnmx,   typeof(OpCodeFArithCbuf));
-            Set("0011100x01100x", InstEmit.Fmnmx,   typeof(OpCodeFArithImm));
-            Set("0101110001100x", InstEmit.Fmnmx,   typeof(OpCodeFArithReg));
-            Set("0100110001101x", InstEmit.Fmul,    typeof(OpCodeFArithCbuf));
-            Set("0011100x01101x", InstEmit.Fmul,    typeof(OpCodeFArithImm));
-            Set("00011110xxxxxx", InstEmit.Fmul,    typeof(OpCodeFArithImm32));
-            Set("0101110001101x", InstEmit.Fmul,    typeof(OpCodeFArithReg));
-            Set("0100100xxxxxxx", InstEmit.Fset,    typeof(OpCodeSetCbuf));
-            Set("0011000xxxxxxx", InstEmit.Fset,    typeof(OpCodeFsetImm));
-            Set("01011000xxxxxx", InstEmit.Fset,    typeof(OpCodeSetReg));
-            Set("010010111011xx", InstEmit.Fsetp,   typeof(OpCodeSetCbuf));
-            Set("0011011x1011xx", InstEmit.Fsetp,   typeof(OpCodeFsetImm));
-            Set("010110111011xx", InstEmit.Fsetp,   typeof(OpCodeSetReg));
-            Set("0101000011111x", InstEmit.Fswzadd, typeof(OpCodeAluReg));
-            Set("0111101x1xxxxx", InstEmit.Hadd2,   typeof(OpCodeAluCbuf));
-            Set("0111101x0xxxxx", InstEmit.Hadd2,   typeof(OpCodeAluImm2x10));
-            Set("0010110xxxxxxx", InstEmit.Hadd2,   typeof(OpCodeAluImm32));
-            Set("0101110100010x", InstEmit.Hadd2,   typeof(OpCodeAluReg));
-            Set("01110xxx1xxxxx", InstEmit.Hfma2,   typeof(OpCodeHfmaCbuf));
-            Set("01110xxx0xxxxx", InstEmit.Hfma2,   typeof(OpCodeHfmaImm2x10));
-            Set("0010100xxxxxxx", InstEmit.Hfma2,   typeof(OpCodeHfmaImm32));
-            Set("0101110100000x", InstEmit.Hfma2,   typeof(OpCodeHfmaReg));
-            Set("01100xxx1xxxxx", InstEmit.Hfma2,   typeof(OpCodeHfmaRegCbuf));
-            Set("0111100x1xxxxx", InstEmit.Hmul2,   typeof(OpCodeAluCbuf));
-            Set("0111100x0xxxxx", InstEmit.Hmul2,   typeof(OpCodeAluImm2x10));
-            Set("0010101xxxxxxx", InstEmit.Hmul2,   typeof(OpCodeAluImm32));
-            Set("0101110100001x", InstEmit.Hmul2,   typeof(OpCodeAluReg));
-            Set("0111110x1xxxxx", InstEmit.Hset2,   typeof(OpCodeSetCbuf));
-            Set("0111110x0xxxxx", InstEmit.Hset2,   typeof(OpCodeHsetImm2x10));
-            Set("0101110100011x", InstEmit.Hset2,   typeof(OpCodeSetReg));
-            Set("0111111x1xxxxx", InstEmit.Hsetp2,  typeof(OpCodeSetCbuf));
-            Set("0111111x0xxxxx", InstEmit.Hsetp2,  typeof(OpCodeHsetImm2x10));
-            Set("0101110100100x", InstEmit.Hsetp2,  typeof(OpCodeSetReg));
-            Set("0100110010111x", InstEmit.I2F,     typeof(OpCodeAluCbuf));
-            Set("0011100x10111x", InstEmit.I2F,     typeof(OpCodeAluImm));
-            Set("0101110010111x", InstEmit.I2F,     typeof(OpCodeAluReg));
-            Set("0100110011100x", InstEmit.I2I,     typeof(OpCodeAluCbuf));
-            Set("0011100x11100x", InstEmit.I2I,     typeof(OpCodeAluImm));
-            Set("0101110011100x", InstEmit.I2I,     typeof(OpCodeAluReg));
-            Set("0100110000010x", InstEmit.Iadd,    typeof(OpCodeAluCbuf));
-            Set("0011100x00010x", InstEmit.Iadd,    typeof(OpCodeAluImm));
-            Set("0001110x0xxxxx", InstEmit.Iadd,    typeof(OpCodeAluImm32));
-            Set("0101110000010x", InstEmit.Iadd,    typeof(OpCodeAluReg));
-            Set("010011001100xx", InstEmit.Iadd3,   typeof(OpCodeAluCbuf));
-            Set("0011100x1100xx", InstEmit.Iadd3,   typeof(OpCodeAluImm));
-            Set("010111001100xx", InstEmit.Iadd3,   typeof(OpCodeAluReg));
-            Set("010010110100xx", InstEmit.Icmp,    typeof(OpCodeAluCbuf));
-            Set("0011011x0100xx", InstEmit.Icmp,    typeof(OpCodeAluImm));
-            Set("010110110100xx", InstEmit.Icmp,    typeof(OpCodeAluReg));
-            Set("010100110100xx", InstEmit.Icmp,    typeof(OpCodeAluRegCbuf));
-            Set("010010100xxxxx", InstEmit.Imad,    typeof(OpCodeAluCbuf));
-            Set("0011010x0xxxxx", InstEmit.Imad,    typeof(OpCodeAluImm));
-            Set("010110100xxxxx", InstEmit.Imad,    typeof(OpCodeAluReg));
-            Set("010100100xxxxx", InstEmit.Imad,    typeof(OpCodeAluRegCbuf));
-            Set("0100110000100x", InstEmit.Imnmx,   typeof(OpCodeAluCbuf));
-            Set("0011100x00100x", InstEmit.Imnmx,   typeof(OpCodeAluImm));
-            Set("0101110000100x", InstEmit.Imnmx,   typeof(OpCodeAluReg));
-            Set("11100000xxxxxx", InstEmit.Ipa,     typeof(OpCodeIpa));
-            Set("1110111111010x", InstEmit.Isberd,  typeof(OpCodeAlu));
-            Set("0100110000011x", InstEmit.Iscadd,  typeof(OpCodeAluCbuf));
-            Set("0011100x00011x", InstEmit.Iscadd,  typeof(OpCodeAluImm));
-            Set("000101xxxxxxxx", InstEmit.Iscadd,  typeof(OpCodeAluImm32));
-            Set("0101110000011x", InstEmit.Iscadd,  typeof(OpCodeAluReg));
-            Set("010010110101xx", InstEmit.Iset,    typeof(OpCodeSetCbuf));
-            Set("0011011x0101xx", InstEmit.Iset,    typeof(OpCodeSetImm));
-            Set("010110110101xx", InstEmit.Iset,    typeof(OpCodeSetReg));
-            Set("010010110110xx", InstEmit.Isetp,   typeof(OpCodeSetCbuf));
-            Set("0011011x0110xx", InstEmit.Isetp,   typeof(OpCodeSetImm));
-            Set("010110110110xx", InstEmit.Isetp,   typeof(OpCodeSetReg));
-            Set("111000110011xx", InstEmit.Kil,     typeof(OpCodeExit));
-            Set("1110111101000x", InstEmit.Ld,      typeof(OpCodeMemory));
-            Set("1110111110010x", InstEmit.Ldc,     typeof(OpCodeLdc));
-            Set("1110111011010x", InstEmit.Ldg,     typeof(OpCodeMemory));
-            Set("1110111101001x", InstEmit.Lds,     typeof(OpCodeMemory));
-            Set("010010111101xx", InstEmit.Lea,     typeof(OpCodeAluCbuf));
-            Set("0011011x11010x", InstEmit.Lea,     typeof(OpCodeAluImm));
-            Set("0101101111010x", InstEmit.Lea,     typeof(OpCodeAluReg));
-            Set("000110xxxxxxxx", InstEmit.Lea_Hi,  typeof(OpCodeAluCbuf));
-            Set("0101101111011x", InstEmit.Lea_Hi,  typeof(OpCodeAluReg));
-            Set("0100110001000x", InstEmit.Lop,     typeof(OpCodeLopCbuf));
-            Set("0011100001000x", InstEmit.Lop,     typeof(OpCodeLopImm));
-            Set("000001xxxxxxxx", InstEmit.Lop,     typeof(OpCodeLopImm32));
-            Set("0101110001000x", InstEmit.Lop,     typeof(OpCodeLopReg));
-            Set("0000001xxxxxxx", InstEmit.Lop3,    typeof(OpCodeLopCbuf));
-            Set("001111xxxxxxxx", InstEmit.Lop3,    typeof(OpCodeLopImm));
-            Set("0101101111100x", InstEmit.Lop3,    typeof(OpCodeLopReg));
-            Set("1110111110011x", InstEmit.Membar,  typeof(OpCodeMemoryBarrier));
-            Set("0100110010011x", InstEmit.Mov,     typeof(OpCodeAluCbuf));
-            Set("0011100x10011x", InstEmit.Mov,     typeof(OpCodeAluImm));
-            Set("000000010000xx", InstEmit.Mov,     typeof(OpCodeAluImm32));
-            Set("0101110010011x", InstEmit.Mov,     typeof(OpCodeAluReg));
-            Set("0101000010000x", InstEmit.Mufu,    typeof(OpCodeFArith));
-            Set("0101000010110x", InstEmit.Nop,     typeof(OpCode));
-            Set("1111101111100x", InstEmit.Out,     typeof(OpCode));
-            Set("111000101010xx", InstEmit.Pbk,     typeof(OpCodePush));
-            Set("0100110000001x", InstEmit.Popc,    typeof(OpCodeAluCbuf));
-            Set("0011100x00001x", InstEmit.Popc,    typeof(OpCodeAluImm));
-            Set("0101110000001x", InstEmit.Popc,    typeof(OpCodeAluReg));
-            Set("0101000010001x", InstEmit.Pset,    typeof(OpCodePset));
-            Set("0101000010010x", InstEmit.Psetp,   typeof(OpCodePset));
-            Set("0100110011110x", InstEmit.R2p,     typeof(OpCodeAluCbuf));
-            Set("0011100x11110x", InstEmit.R2p,     typeof(OpCodeAluImm));
-            Set("0101110011110x", InstEmit.R2p,     typeof(OpCodeAluReg));
-            Set("1110101111111x", InstEmit.Red,     typeof(OpCodeRed));
-            Set("0100110010010x", InstEmit.Rro,     typeof(OpCodeFArithCbuf));
-            Set("0011100x10010x", InstEmit.Rro,     typeof(OpCodeFArithImm));
-            Set("0101110010010x", InstEmit.Rro,     typeof(OpCodeFArithReg));
-            Set("1111000011001x", InstEmit.S2r,     typeof(OpCodeAlu));
-            Set("0100110010100x", InstEmit.Sel,     typeof(OpCodeAluCbuf));
-            Set("0011100x10100x", InstEmit.Sel,     typeof(OpCodeAluImm));
-            Set("0101110010100x", InstEmit.Sel,     typeof(OpCodeAluReg));
-            Set("1110111100010x", InstEmit.Shfl,    typeof(OpCodeShuffle));
-            Set("0100110001001x", InstEmit.Shl,     typeof(OpCodeAluCbuf));
-            Set("0011100x01001x", InstEmit.Shl,     typeof(OpCodeAluImm));
-            Set("0101110001001x", InstEmit.Shl,     typeof(OpCodeAluReg));
-            Set("0100110000101x", InstEmit.Shr,     typeof(OpCodeAluCbuf));
-            Set("0011100x00101x", InstEmit.Shr,     typeof(OpCodeAluImm));
-            Set("0101110000101x", InstEmit.Shr,     typeof(OpCodeAluReg));
-            Set("111000101001xx", InstEmit.Ssy,     typeof(OpCodePush));
-            Set("1110111101010x", InstEmit.St,      typeof(OpCodeMemory));
-            Set("1110111011011x", InstEmit.Stg,     typeof(OpCodeMemory));
-            Set("1110111101011x", InstEmit.Sts,     typeof(OpCodeMemory));
-            Set("11101011000xxx", InstEmit.Suld,    typeof(OpCodeImage));
-            Set("11101011001xxx", InstEmit.Sust,    typeof(OpCodeImage));
-            Set("1111000011111x", InstEmit.Sync,    typeof(OpCodeBranchPop));
-            Set("110000xxxx111x", InstEmit.Tex,     typeof(OpCodeTex));
-            Set("1101111010111x", InstEmit.TexB,    typeof(OpCodeTexB));
-            Set("1101x00xxxxxxx", InstEmit.Texs,    typeof(OpCodeTexs));
-            Set("1101x01xxxxxxx", InstEmit.Texs,    typeof(OpCodeTlds));
-            Set("11011111x0xxxx", InstEmit.Texs,    typeof(OpCodeTld4s));
-            Set("11011100xx111x", InstEmit.Tld,     typeof(OpCodeTld));
-            Set("11011101xx111x", InstEmit.TldB,    typeof(OpCodeTld));
-            Set("110010xxxx111x", InstEmit.Tld4,    typeof(OpCodeTld4));
-            Set("1101111011111x", InstEmit.Tld4,    typeof(OpCodeTld4B));
-            Set("11011111011000", InstEmit.TmmlB,   typeof(OpCodeTexture));
-            Set("11011111010110", InstEmit.Tmml,    typeof(OpCodeTexture));
-            Set("110111100x1110", InstEmit.Txd,     typeof(OpCodeTxd));
-            Set("1101111101001x", InstEmit.Txq,     typeof(OpCodeTex));
-            Set("1101111101010x", InstEmit.TxqB,    typeof(OpCodeTex));
-            Set("01011111xxxxxx", InstEmit.Vmad,    typeof(OpCodeVideo));
-            Set("0011101xxxxxxx", InstEmit.Vmnmx,   typeof(OpCodeVideo));
-            Set("0101000011011x", InstEmit.Vote,    typeof(OpCodeVote));
-            Set("0100111xxxxxxx", InstEmit.Xmad,    typeof(OpCodeAluCbuf));
-            Set("0011011x00xxxx", InstEmit.Xmad,    typeof(OpCodeAluImm));
-            Set("010100010xxxxx", InstEmit.Xmad,    typeof(OpCodeAluRegCbuf));
-            Set("0101101100xxxx", InstEmit.Xmad,    typeof(OpCodeAluReg));
+            Set("1110111111011x", InstEmit.Ald,     OpCodeAttribute.Create);
+            Set("1110111111110x", InstEmit.Ast,     OpCodeAttribute.Create);
+            Set("11101100xxxxxx", InstEmit.Atoms,   OpCodeAtom.Create);
+            Set("1111000010101x", InstEmit.Bar,     OpCodeBarrier.Create);
+            Set("0100110000000x", InstEmit.Bfe,     OpCodeAluCbuf.Create);
+            Set("0011100x00000x", InstEmit.Bfe,     OpCodeAluImm.Create);
+            Set("0101110000000x", InstEmit.Bfe,     OpCodeAluReg.Create);
+            Set("0100101111110x", InstEmit.Bfi,     OpCodeAluCbuf.Create);
+            Set("0011011x11110x", InstEmit.Bfi,     OpCodeAluImm.Create);
+            Set("0101001111110x", InstEmit.Bfi,     OpCodeAluRegCbuf.Create);
+            Set("0101101111110x", InstEmit.Bfi,     OpCodeAluReg.Create);
+            Set("111000100100xx", InstEmit.Bra,     OpCodeBranch.Create);
+            Set("111000110100xx", InstEmit.Brk,     OpCodeBranchPop.Create);
+            Set("111000100101xx", InstEmit.Brx,     OpCodeBranchIndir.Create);
+            Set("0101000010100x", InstEmit.Csetp,   OpCodePset.Create);
+            Set("0100110001110x", InstEmit.Dadd,    OpCodeFArithCbuf.Create);
+            Set("0011100x01110x", InstEmit.Dadd,    OpCodeDArithImm.Create);
+            Set("0101110001110x", InstEmit.Dadd,    OpCodeFArithReg.Create);
+            Set("1111000011110x", InstEmit.Depbar,  OpCode.Create);
+            Set("010010110111xx", InstEmit.Dfma,    OpCodeFArithCbuf.Create);
+            Set("0011011x0111xx", InstEmit.Dfma,    OpCodeDArithImm.Create);
+            Set("010100110111xx", InstEmit.Dfma,    OpCodeFArithRegCbuf.Create);
+            Set("010110110111xx", InstEmit.Dfma,    OpCodeFArithReg.Create);
+            Set("0100110010000x", InstEmit.Dmul,    OpCodeFArithCbuf.Create);
+            Set("0011100x10000x", InstEmit.Dmul,    OpCodeDArithImm.Create);
+            Set("0101110010000x", InstEmit.Dmul,    OpCodeFArithReg.Create);
+            Set("111000110000xx", InstEmit.Exit,    OpCodeExit.Create);
+            Set("0100110010101x", InstEmit.F2F,     OpCodeFArithCbuf.Create);
+            Set("0011100x10101x", InstEmit.F2F,     OpCodeFArithImm.Create);
+            Set("0101110010101x", InstEmit.F2F,     OpCodeFArithReg.Create);
+            Set("0100110010110x", InstEmit.F2I,     OpCodeFArithCbuf.Create);
+            Set("0011100x10110x", InstEmit.F2I,     OpCodeFArithImm.Create);
+            Set("0101110010110x", InstEmit.F2I,     OpCodeFArithReg.Create);
+            Set("0100110001011x", InstEmit.Fadd,    OpCodeFArithCbuf.Create);
+            Set("0011100x01011x", InstEmit.Fadd,    OpCodeFArithImm.Create);
+            Set("000010xxxxxxxx", InstEmit.Fadd,    OpCodeFArithImm32.Create);
+            Set("0101110001011x", InstEmit.Fadd,    OpCodeFArithReg.Create);
+            Set("010010111010xx", InstEmit.Fcmp,    OpCodeFArithCbuf.Create);
+            Set("0011011x1010xx", InstEmit.Fcmp,    OpCodeFArithImm.Create);
+            Set("010110111010xx", InstEmit.Fcmp,    OpCodeFArithReg.Create);
+            Set("010100111010xx", InstEmit.Fcmp,    OpCodeFArithRegCbuf.Create);
+            Set("010010011xxxxx", InstEmit.Ffma,    OpCodeFArithCbuf.Create);
+            Set("0011001x1xxxxx", InstEmit.Ffma,    OpCodeFArithImm.Create);
+            Set("000011xxxxxxxx", InstEmit.Ffma32i, OpCodeFArithImm32.Create);
+            Set("010100011xxxxx", InstEmit.Ffma,    OpCodeFArithRegCbuf.Create);
+            Set("010110011xxxxx", InstEmit.Ffma,    OpCodeFArithReg.Create);
+            Set("0100110000110x", InstEmit.Flo,     OpCodeAluCbuf.Create);
+            Set("0011100x00110x", InstEmit.Flo,     OpCodeAluImm.Create);
+            Set("0101110000110x", InstEmit.Flo,     OpCodeAluReg.Create);
+            Set("0100110001100x", InstEmit.Fmnmx,   OpCodeFArithCbuf.Create);
+            Set("0011100x01100x", InstEmit.Fmnmx,   OpCodeFArithImm.Create);
+            Set("0101110001100x", InstEmit.Fmnmx,   OpCodeFArithReg.Create);
+            Set("0100110001101x", InstEmit.Fmul,    OpCodeFArithCbuf.Create);
+            Set("0011100x01101x", InstEmit.Fmul,    OpCodeFArithImm.Create);
+            Set("00011110xxxxxx", InstEmit.Fmul,    OpCodeFArithImm32.Create);
+            Set("0101110001101x", InstEmit.Fmul,    OpCodeFArithReg.Create);
+            Set("0100100xxxxxxx", InstEmit.Fset,    OpCodeSetCbuf.Create);
+            Set("0011000xxxxxxx", InstEmit.Fset,    OpCodeFsetImm.Create);
+            Set("01011000xxxxxx", InstEmit.Fset,    OpCodeSetReg.Create);
+            Set("010010111011xx", InstEmit.Fsetp,   OpCodeSetCbuf.Create);
+            Set("0011011x1011xx", InstEmit.Fsetp,   OpCodeFsetImm.Create);
+            Set("010110111011xx", InstEmit.Fsetp,   OpCodeSetReg.Create);
+            Set("0101000011111x", InstEmit.Fswzadd, OpCodeAluReg.Create);
+            Set("0111101x1xxxxx", InstEmit.Hadd2,   OpCodeAluCbuf.Create);
+            Set("0111101x0xxxxx", InstEmit.Hadd2,   OpCodeAluImm2x10.Create);
+            Set("0010110xxxxxxx", InstEmit.Hadd2,   OpCodeAluImm32.Create);
+            Set("0101110100010x", InstEmit.Hadd2,   OpCodeAluReg.Create);
+            Set("01110xxx1xxxxx", InstEmit.Hfma2,   OpCodeHfmaCbuf.Create);
+            Set("01110xxx0xxxxx", InstEmit.Hfma2,   OpCodeHfmaImm2x10.Create);
+            Set("0010100xxxxxxx", InstEmit.Hfma2,   OpCodeHfmaImm32.Create);
+            Set("0101110100000x", InstEmit.Hfma2,   OpCodeHfmaReg.Create);
+            Set("01100xxx1xxxxx", InstEmit.Hfma2,   OpCodeHfmaRegCbuf.Create);
+            Set("0111100x1xxxxx", InstEmit.Hmul2,   OpCodeAluCbuf.Create);
+            Set("0111100x0xxxxx", InstEmit.Hmul2,   OpCodeAluImm2x10.Create);
+            Set("0010101xxxxxxx", InstEmit.Hmul2,   OpCodeAluImm32.Create);
+            Set("0101110100001x", InstEmit.Hmul2,   OpCodeAluReg.Create);
+            Set("0111110x1xxxxx", InstEmit.Hset2,   OpCodeSetCbuf.Create);
+            Set("0111110x0xxxxx", InstEmit.Hset2,   OpCodeHsetImm2x10.Create);
+            Set("0101110100011x", InstEmit.Hset2,   OpCodeSetReg.Create);
+            Set("0111111x1xxxxx", InstEmit.Hsetp2,  OpCodeSetCbuf.Create);
+            Set("0111111x0xxxxx", InstEmit.Hsetp2,  OpCodeHsetImm2x10.Create);
+            Set("0101110100100x", InstEmit.Hsetp2,  OpCodeSetReg.Create);
+            Set("0100110010111x", InstEmit.I2F,     OpCodeAluCbuf.Create);
+            Set("0011100x10111x", InstEmit.I2F,     OpCodeAluImm.Create);
+            Set("0101110010111x", InstEmit.I2F,     OpCodeAluReg.Create);
+            Set("0100110011100x", InstEmit.I2I,     OpCodeAluCbuf.Create);
+            Set("0011100x11100x", InstEmit.I2I,     OpCodeAluImm.Create);
+            Set("0101110011100x", InstEmit.I2I,     OpCodeAluReg.Create);
+            Set("0100110000010x", InstEmit.Iadd,    OpCodeAluCbuf.Create);
+            Set("0011100x00010x", InstEmit.Iadd,    OpCodeAluImm.Create);
+            Set("0001110x0xxxxx", InstEmit.Iadd,    OpCodeAluImm32.Create);
+            Set("0101110000010x", InstEmit.Iadd,    OpCodeAluReg.Create);
+            Set("010011001100xx", InstEmit.Iadd3,   OpCodeAluCbuf.Create);
+            Set("0011100x1100xx", InstEmit.Iadd3,   OpCodeAluImm.Create);
+            Set("010111001100xx", InstEmit.Iadd3,   OpCodeAluReg.Create);
+            Set("010010110100xx", InstEmit.Icmp,    OpCodeAluCbuf.Create);
+            Set("0011011x0100xx", InstEmit.Icmp,    OpCodeAluImm.Create);
+            Set("010110110100xx", InstEmit.Icmp,    OpCodeAluReg.Create);
+            Set("010100110100xx", InstEmit.Icmp,    OpCodeAluRegCbuf.Create);
+            Set("010010100xxxxx", InstEmit.Imad,    OpCodeAluCbuf.Create);
+            Set("0011010x0xxxxx", InstEmit.Imad,    OpCodeAluImm.Create);
+            Set("010110100xxxxx", InstEmit.Imad,    OpCodeAluReg.Create);
+            Set("010100100xxxxx", InstEmit.Imad,    OpCodeAluRegCbuf.Create);
+            Set("0100110000100x", InstEmit.Imnmx,   OpCodeAluCbuf.Create);
+            Set("0011100x00100x", InstEmit.Imnmx,   OpCodeAluImm.Create);
+            Set("0101110000100x", InstEmit.Imnmx,   OpCodeAluReg.Create);
+            Set("11100000xxxxxx", InstEmit.Ipa,     OpCodeIpa.Create);
+            Set("1110111111010x", InstEmit.Isberd,  OpCodeAlu.Create);
+            Set("0100110000011x", InstEmit.Iscadd,  OpCodeAluCbuf.Create);
+            Set("0011100x00011x", InstEmit.Iscadd,  OpCodeAluImm.Create);
+            Set("000101xxxxxxxx", InstEmit.Iscadd,  OpCodeAluImm32.Create);
+            Set("0101110000011x", InstEmit.Iscadd,  OpCodeAluReg.Create);
+            Set("010010110101xx", InstEmit.Iset,    OpCodeSetCbuf.Create);
+            Set("0011011x0101xx", InstEmit.Iset,    OpCodeSetImm.Create);
+            Set("010110110101xx", InstEmit.Iset,    OpCodeSetReg.Create);
+            Set("010010110110xx", InstEmit.Isetp,   OpCodeSetCbuf.Create);
+            Set("0011011x0110xx", InstEmit.Isetp,   OpCodeSetImm.Create);
+            Set("010110110110xx", InstEmit.Isetp,   OpCodeSetReg.Create);
+            Set("111000110011xx", InstEmit.Kil,     OpCodeExit.Create);
+            Set("1110111101000x", InstEmit.Ld,      OpCodeMemory.Create);
+            Set("1110111110010x", InstEmit.Ldc,     OpCodeLdc.Create);
+            Set("1110111011010x", InstEmit.Ldg,     OpCodeMemory.Create);
+            Set("1110111101001x", InstEmit.Lds,     OpCodeMemory.Create);
+            Set("010010111101xx", InstEmit.Lea,     OpCodeAluCbuf.Create);
+            Set("0011011x11010x", InstEmit.Lea,     OpCodeAluImm.Create);
+            Set("0101101111010x", InstEmit.Lea,     OpCodeAluReg.Create);
+            Set("000110xxxxxxxx", InstEmit.Lea_Hi,  OpCodeAluCbuf.Create);
+            Set("0101101111011x", InstEmit.Lea_Hi,  OpCodeAluReg.Create);
+            Set("0100110001000x", InstEmit.Lop,     OpCodeLopCbuf.Create);
+            Set("0011100001000x", InstEmit.Lop,     OpCodeLopImm.Create);
+            Set("000001xxxxxxxx", InstEmit.Lop,     OpCodeLopImm32.Create);
+            Set("0101110001000x", InstEmit.Lop,     OpCodeLopReg.Create);
+            Set("0000001xxxxxxx", InstEmit.Lop3,    OpCodeLopCbuf.Create);
+            Set("001111xxxxxxxx", InstEmit.Lop3,    OpCodeLopImm.Create);
+            Set("0101101111100x", InstEmit.Lop3,    OpCodeLopReg.Create);
+            Set("1110111110011x", InstEmit.Membar,  OpCodeMemoryBarrier.Create);
+            Set("0100110010011x", InstEmit.Mov,     OpCodeAluCbuf.Create);
+            Set("0011100x10011x", InstEmit.Mov,     OpCodeAluImm.Create);
+            Set("000000010000xx", InstEmit.Mov,     OpCodeAluImm32.Create);
+            Set("0101110010011x", InstEmit.Mov,     OpCodeAluReg.Create);
+            Set("0101000010000x", InstEmit.Mufu,    OpCodeFArith.Create);
+            Set("0101000010110x", InstEmit.Nop,     OpCode.Create);
+            Set("1111101111100x", InstEmit.Out,     OpCode.Create);
+            Set("111000101010xx", InstEmit.Pbk,     OpCodePush.Create);
+            Set("0100110000001x", InstEmit.Popc,    OpCodeAluCbuf.Create);
+            Set("0011100x00001x", InstEmit.Popc,    OpCodeAluImm.Create);
+            Set("0101110000001x", InstEmit.Popc,    OpCodeAluReg.Create);
+            Set("0101000010001x", InstEmit.Pset,    OpCodePset.Create);
+            Set("0101000010010x", InstEmit.Psetp,   OpCodePset.Create);
+            Set("0100110011110x", InstEmit.R2p,     OpCodeAluCbuf.Create);
+            Set("0011100x11110x", InstEmit.R2p,     OpCodeAluImm.Create);
+            Set("0101110011110x", InstEmit.R2p,     OpCodeAluReg.Create);
+            Set("1110101111111x", InstEmit.Red,     OpCodeRed.Create);
+            Set("0100110010010x", InstEmit.Rro,     OpCodeFArithCbuf.Create);
+            Set("0011100x10010x", InstEmit.Rro,     OpCodeFArithImm.Create);
+            Set("0101110010010x", InstEmit.Rro,     OpCodeFArithReg.Create);
+            Set("1111000011001x", InstEmit.S2r,     OpCodeAlu.Create);
+            Set("0100110010100x", InstEmit.Sel,     OpCodeAluCbuf.Create);
+            Set("0011100x10100x", InstEmit.Sel,     OpCodeAluImm.Create);
+            Set("0101110010100x", InstEmit.Sel,     OpCodeAluReg.Create);
+            Set("1110111100010x", InstEmit.Shfl,    OpCodeShuffle.Create);
+            Set("0100110001001x", InstEmit.Shl,     OpCodeAluCbuf.Create);
+            Set("0011100x01001x", InstEmit.Shl,     OpCodeAluImm.Create);
+            Set("0101110001001x", InstEmit.Shl,     OpCodeAluReg.Create);
+            Set("0100110000101x", InstEmit.Shr,     OpCodeAluCbuf.Create);
+            Set("0011100x00101x", InstEmit.Shr,     OpCodeAluImm.Create);
+            Set("0101110000101x", InstEmit.Shr,     OpCodeAluReg.Create);
+            Set("111000101001xx", InstEmit.Ssy,     OpCodePush.Create);
+            Set("1110111101010x", InstEmit.St,      OpCodeMemory.Create);
+            Set("1110111011011x", InstEmit.Stg,     OpCodeMemory.Create);
+            Set("1110111101011x", InstEmit.Sts,     OpCodeMemory.Create);
+            Set("11101011000xxx", InstEmit.Suld,    OpCodeImage.Create);
+            Set("11101011001xxx", InstEmit.Sust,    OpCodeImage.Create);
+            Set("1111000011111x", InstEmit.Sync,    OpCodeBranchPop.Create);
+            Set("110000xxxx111x", InstEmit.Tex,     OpCodeTex.Create);
+            Set("1101111010111x", InstEmit.TexB,    OpCodeTexB.Create);
+            Set("1101x00xxxxxxx", InstEmit.Texs,    OpCodeTexs.Create);
+            Set("1101x01xxxxxxx", InstEmit.Texs,    OpCodeTlds.Create);
+            Set("11011111x0xxxx", InstEmit.Texs,    OpCodeTld4s.Create);
+            Set("11011100xx111x", InstEmit.Tld,     OpCodeTld.Create);
+            Set("11011101xx111x", InstEmit.TldB,    OpCodeTld.Create);
+            Set("110010xxxx111x", InstEmit.Tld4,    OpCodeTld4.Create);
+            Set("1101111011111x", InstEmit.Tld4,    OpCodeTld4B.Create);
+            Set("11011111011000", InstEmit.TmmlB,   OpCodeTexture.Create);
+            Set("11011111010110", InstEmit.Tmml,    OpCodeTexture.Create);
+            Set("110111100x1110", InstEmit.Txd,     OpCodeTxd.Create);
+            Set("1101111101001x", InstEmit.Txq,     OpCodeTex.Create);
+            Set("1101111101010x", InstEmit.TxqB,    OpCodeTex.Create);
+            Set("01011111xxxxxx", InstEmit.Vmad,    OpCodeVideo.Create);
+            Set("0011101xxxxxxx", InstEmit.Vmnmx,   OpCodeVideo.Create);
+            Set("0101000011011x", InstEmit.Vote,    OpCodeVote.Create);
+            Set("0100111xxxxxxx", InstEmit.Xmad,    OpCodeAluCbuf.Create);
+            Set("0011011x00xxxx", InstEmit.Xmad,    OpCodeAluImm.Create);
+            Set("010100010xxxxx", InstEmit.Xmad,    OpCodeAluRegCbuf.Create);
+            Set("0101101100xxxx", InstEmit.Xmad,    OpCodeAluReg.Create);
 #endregion
         }
 
-        private static void Set(string encoding, InstEmitter emitter, Type opCodeType)
+        private static void Set(string encoding, InstEmitter emitter, MakeOp makeOp)
         {
             if (encoding.Length != EncodingBits)
             {
@@ -283,7 +262,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
             xMask = ~xMask;
 
-            TableEntry entry = new TableEntry(emitter, opCodeType, xBits);
+            TableEntry entry = new TableEntry(emitter, makeOp, xBits);
 
             for (int index = 0; index < (1 << xBits); index++)
             {
@@ -301,13 +280,13 @@ namespace Ryujinx.Graphics.Shader.Decoders
             }
         }
 
-        public static (InstEmitter emitter, OpActivator opActivator) GetEmitter(long opCode)
+        public static (InstEmitter Emitter, MakeOp MakeOp) GetEmitter(long opCode)
         {
             TableEntry entry = _opCodes[(ulong)opCode >> (64 - EncodingBits)];
 
             if (entry != null)
             {
-                return (entry.Emitter, entry.OpActivator);
+                return (entry.Emitter, entry.MakeOp);
             }
 
             return (null, null);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs
index da8756b91c..c0e4da0245 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs
@@ -4,6 +4,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 {
     class OpCodeTex : OpCodeTexture
     {
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTex(emitter, address, opCode);
+
         public OpCodeTex(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             HasDepthCompare = opCode.Extract(50);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs
index b18bf3befa..33434ae197 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs
@@ -4,6 +4,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 {
     class OpCodeTexB : OpCodeTex
     {
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTexB(emitter, address, opCode);
+
         public OpCodeTexB(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             switch (opCode.Extract(37, 3))
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs
index fb90ccf60a..ea3057c883 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public TextureTarget Target => (TextureTarget)RawType;
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTexs(emitter, address, opCode);
+
         public OpCodeTexs(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { }
     }
 }
\ No newline at end of file
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs
index 76e95118f7..f19f7dadef 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs
@@ -22,6 +22,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public bool HasDepthCompare { get; protected set; }
         public bool IsMultisample   { get; protected set; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTexture(emitter, address, opCode);
+
         public OpCodeTexture(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs
index 543f8d1367..3ccd185cfb 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs
@@ -41,6 +41,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public bool IsFp16 { get; protected set; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTextureScalar(emitter, address, opCode);
+
         public OpCodeTextureScalar(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd0 = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs
index 61bd900b2d..199cf23441 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs
@@ -4,6 +4,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 {
     class OpCodeTld : OpCodeTexture
     {
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld(emitter, address, opCode);
+
         public OpCodeTld(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             HasOffset = opCode.Extract(35);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs
index 0ffafbe1a4..db6572addd 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs
@@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public bool Bindless => false;
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld4(emitter, address, opCode);
+
         public OpCodeTld4(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             HasDepthCompare = opCode.Extract(50);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs
index dc274d1415..a3988d00de 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs
@@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public bool Bindless => true;
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld4B(emitter, address, opCode);
+
         public OpCodeTld4B(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             HasDepthCompare = opCode.Extract(50);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs
index fd3240a0ee..442d36da7d 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs
@@ -9,6 +9,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public int GatherCompIndex { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld4s(emitter, address, opCode);
+
         public OpCodeTld4s(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             HasDepthCompare = opCode.Extract(50);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs
index 1e4e943ffa..97b328c49b 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public TexelLoadTarget Target => (TexelLoadTarget)RawType;
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTlds(emitter, address, opCode);
+
         public OpCodeTlds(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { }
     }
 }
\ No newline at end of file
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs
index 25df1f81f9..63185a1b0c 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs
@@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
     {
         public bool IsBindless { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTxd(emitter, address, opCode);
+
         public OpCodeTxd(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             HasOffset = opCode.Extract(35);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs
index c2bdc22f42..786b81dcfc 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs
@@ -26,6 +26,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         public bool DstSigned { get; }
         public bool Saturate  { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeVideo(emitter, address, opCode);
+
         public OpCodeVideo(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs
index 374767bd2d..4fc988bcb2 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs
@@ -12,6 +12,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
 
         public bool InvertP { get; }
 
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeVote(emitter, address, opCode);
+
         public OpCodeVote(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
         {
             Rd          = new Register(opCode.Extract(0,  8), RegisterType.Gpr);