From ca1e37a29553f97ecf574fb3678422dd93a2b91d Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 8 Sep 2018 19:23:07 +0200
Subject: [PATCH] Remove old Tester, update Tests (some reworks). (#400)
* Delete Bits.cs
* Delete Integer.cs
* Delete Instructions.cs
* Delete Pseudocode.cs
* Add files via upload
* Add mnemonic.
* Literals all uppercase.
* Nit.
* Allow FPSR control.
* Allow FPSR control.
* Allow FPSR control.
---
Ryujinx.Tests/Cpu/CpuTest.cs | 103 +-
Ryujinx.Tests/Cpu/CpuTestAlu.cs | 223 +-
Ryujinx.Tests/Cpu/CpuTestAluImm.cs | 556 +-
Ryujinx.Tests/Cpu/CpuTestAluRs.cs | 1337 +---
Ryujinx.Tests/Cpu/CpuTestAluRx.cs | 825 +--
Ryujinx.Tests/Cpu/CpuTestBfm.cs | 159 +-
Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs | 99 +-
Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs | 102 +-
Ryujinx.Tests/Cpu/CpuTestCsel.cs | 189 +-
Ryujinx.Tests/Cpu/CpuTestMisc.cs | 66 +-
Ryujinx.Tests/Cpu/CpuTestMov.cs | 127 +-
Ryujinx.Tests/Cpu/CpuTestMul.cs | 257 +-
Ryujinx.Tests/Cpu/CpuTestSimd.cs | 1058 +--
Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 391 +-
Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs | 52 +-
Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | 8 +
Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs | 4 +-
Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 1772 +----
Ryujinx.Tests/Cpu/Tester/Instructions.cs | 7346 --------------------
Ryujinx.Tests/Cpu/Tester/Pseudocode.cs | 1740 -----
Ryujinx.Tests/Cpu/Tester/Types/Bits.cs | 282 -
Ryujinx.Tests/Cpu/Tester/Types/Integer.cs | 42 -
22 files changed, 1354 insertions(+), 15384 deletions(-)
delete mode 100644 Ryujinx.Tests/Cpu/Tester/Instructions.cs
delete mode 100644 Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
delete mode 100644 Ryujinx.Tests/Cpu/Tester/Types/Bits.cs
delete mode 100644 Ryujinx.Tests/Cpu/Tester/Types/Integer.cs
diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs
index 6e013aa055..1f7151ffe7 100644
--- a/Ryujinx.Tests/Cpu/CpuTest.cs
+++ b/Ryujinx.Tests/Cpu/CpuTest.cs
@@ -33,9 +33,10 @@ namespace Ryujinx.Tests.Cpu
static CpuTest()
{
UnicornAvailable = UnicornAArch64.IsAvailable();
+
if (!UnicornAvailable)
{
- Console.WriteLine("WARNING: Could not find unicorn");
+ Console.WriteLine("WARNING: Could not find Unicorn.");
}
}
@@ -43,7 +44,7 @@ namespace Ryujinx.Tests.Cpu
public void Setup()
{
Position = 0x1000;
- Size = 0x1000;
+ Size = 0x1000;
EntryPoint = Position;
@@ -79,10 +80,12 @@ namespace Ryujinx.Tests.Cpu
protected void Opcode(uint Opcode)
{
Thread.Memory.WriteUInt32(Position, Opcode);
+
if (UnicornAvailable)
{
UnicornEmu.MemoryWrite32((ulong)Position, Opcode);
}
+
Position += 4;
}
@@ -97,14 +100,18 @@ namespace Ryujinx.Tests.Cpu
Thread.ThreadState.X1 = X1;
Thread.ThreadState.X2 = X2;
Thread.ThreadState.X3 = X3;
+
Thread.ThreadState.X31 = X31;
+
Thread.ThreadState.V0 = V0;
Thread.ThreadState.V1 = V1;
Thread.ThreadState.V2 = V2;
+
Thread.ThreadState.Overflow = Overflow;
- Thread.ThreadState.Carry = Carry;
- Thread.ThreadState.Zero = Zero;
+ Thread.ThreadState.Carry = Carry;
+ Thread.ThreadState.Zero = Zero;
Thread.ThreadState.Negative = Negative;
+
Thread.ThreadState.Fpcr = Fpcr;
Thread.ThreadState.Fpsr = Fpsr;
@@ -114,14 +121,18 @@ namespace Ryujinx.Tests.Cpu
UnicornEmu.X[1] = X1;
UnicornEmu.X[2] = X2;
UnicornEmu.X[3] = X3;
+
UnicornEmu.SP = X31;
+
UnicornEmu.Q[0] = V0;
UnicornEmu.Q[1] = V1;
UnicornEmu.Q[2] = V2;
+
UnicornEmu.OverflowFlag = Overflow;
- UnicornEmu.CarryFlag = Carry;
- UnicornEmu.ZeroFlag = Zero;
+ UnicornEmu.CarryFlag = Carry;
+ UnicornEmu.ZeroFlag = Zero;
UnicornEmu.NegativeFlag = Negative;
+
UnicornEmu.Fpcr = Fpcr;
UnicornEmu.Fpsr = Fpsr;
}
@@ -144,10 +155,7 @@ namespace Ryujinx.Tests.Cpu
}
}
- protected AThreadState GetThreadState()
- {
- return Thread.ThreadState;
- }
+ protected AThreadState GetThreadState() => Thread.ThreadState;
protected AThreadState SingleOpcode(uint Opcode,
ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0,
@@ -166,23 +174,44 @@ namespace Ryujinx.Tests.Cpu
return GetThreadState();
}
- protected void CompareAgainstUnicorn()
+ [Flags]
+ protected enum FPSR
+ {
+ None = 0,
+
+ /// Invalid Operation cumulative floating-point exception bit.
+ IOC = 1 << 0,
+ /// Divide by Zero cumulative floating-point exception bit.
+ DZC = 1 << 1,
+ /// Overflow cumulative floating-point exception bit.
+ OFC = 1 << 2,
+ /// Underflow cumulative floating-point exception bit.
+ UFC = 1 << 3,
+ /// Inexact cumulative floating-point exception bit.
+ IXC = 1 << 4,
+ /// Input Denormal cumulative floating-point exception bit.
+ IDC = 1 << 7,
+ /// Cumulative saturation bit.
+ QC = 1 << 27
+ }
+
+ protected void CompareAgainstUnicorn(FPSR FpsrMask = FPSR.None)
{
if (!UnicornAvailable)
{
return;
}
- Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0]));
- Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1]));
- Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2]));
- Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3]));
- Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4]));
- Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5]));
- Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6]));
- Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7]));
- Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8]));
- Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9]));
+ Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0]));
+ Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1]));
+ Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2]));
+ Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3]));
+ Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4]));
+ Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5]));
+ Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6]));
+ Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7]));
+ Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8]));
+ Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9]));
Assert.That(Thread.ThreadState.X10, Is.EqualTo(UnicornEmu.X[10]));
Assert.That(Thread.ThreadState.X11, Is.EqualTo(UnicornEmu.X[11]));
Assert.That(Thread.ThreadState.X12, Is.EqualTo(UnicornEmu.X[12]));
@@ -204,17 +233,19 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Thread.ThreadState.X28, Is.EqualTo(UnicornEmu.X[28]));
Assert.That(Thread.ThreadState.X29, Is.EqualTo(UnicornEmu.X[29]));
Assert.That(Thread.ThreadState.X30, Is.EqualTo(UnicornEmu.X[30]));
+
Assert.That(Thread.ThreadState.X31, Is.EqualTo(UnicornEmu.SP));
- Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0]));
- Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1]));
- Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2]));
- Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3]));
- Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4]));
- Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5]));
- Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6]));
- Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7]));
- Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8]));
- Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9]));
+
+ Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0]));
+ Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1]));
+ Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2]));
+ Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3]));
+ Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4]));
+ Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5]));
+ Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6]));
+ Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7]));
+ Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8]));
+ Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9]));
Assert.That(Thread.ThreadState.V10, Is.EqualTo(UnicornEmu.Q[10]));
Assert.That(Thread.ThreadState.V11, Is.EqualTo(UnicornEmu.Q[11]));
Assert.That(Thread.ThreadState.V12, Is.EqualTo(UnicornEmu.Q[12]));
@@ -238,11 +269,13 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Thread.ThreadState.V30, Is.EqualTo(UnicornEmu.Q[30]));
Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31]));
Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31]));
- Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr));
- Assert.That(Thread.ThreadState.Fpsr & 0x08000000, Is.EqualTo(UnicornEmu.Fpsr & 0x08000000));
+
+ Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr));
+ Assert.That(Thread.ThreadState.Fpsr & (int)FpsrMask, Is.EqualTo(UnicornEmu.Fpsr & (int)FpsrMask));
+
Assert.That(Thread.ThreadState.Overflow, Is.EqualTo(UnicornEmu.OverflowFlag));
- Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag));
- Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag));
+ Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag));
+ Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag));
Assert.That(Thread.ThreadState.Negative, Is.EqualTo(UnicornEmu.NegativeFlag));
}
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
index 3a47dbee69..43952d195b 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
@@ -1,4 +1,4 @@
-//#define Alu
+#define Alu
using ChocolArm64.State;
@@ -6,334 +6,185 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
- using Tester;
- using Tester.Types;
-
- [Category("Alu"), Ignore("Tested: second half of 2018.")]
+ [Category("Alu")] // Tested: second half of 2018.
public sealed class CpuTestAlu : CpuTest
{
#if Alu
- [SetUp]
- public void SetupTester()
- {
- AArch64.TakeReset(false);
- }
+ private const int RndCnt = 2;
- [Test, Description("CLS , ")]
+ [Test, Pairwise, Description("CLS , ")]
public void Cls_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC01400; // CLS X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("CLS , ")]
+ [Test, Pairwise, Description("CLS , ")]
public void Cls_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC01400; // CLS W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
+ CompareAgainstUnicorn();
}
- [Test, Description("CLZ , ")]
+ [Test, Pairwise, Description("CLZ , ")]
public void Clz_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC01000; // CLZ X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("CLZ , ")]
+ [Test, Pairwise, Description("CLZ , ")]
public void Clz_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC01000; // CLZ W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("RBIT , ")]
+ [Test, Pairwise, Description("RBIT , ")]
public void Rbit_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00000; // RBIT X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("RBIT , ")]
+ [Test, Pairwise, Description("RBIT , ")]
public void Rbit_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC00000; // RBIT W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("REV16 , ")]
+ [Test, Pairwise, Description("REV16 , ")]
public void Rev16_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00400; // REV16 X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("REV16 , ")]
+ [Test, Pairwise, Description("REV16 , ")]
public void Rev16_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC00400; // REV16 W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("REV32 , ")]
+ [Test, Pairwise, Description("REV32 , ")]
public void Rev32_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00800; // REV32 X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("REV , ")]
+ [Test, Pairwise, Description("REV , ")]
public void Rev32_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC00800; // REV W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("REV64 , ")]
+ [Test, Pairwise, Description("REV64 , ")]
public void Rev64_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00C00; // REV64 X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Rev64(Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
CompareAgainstUnicorn();
}
#endif
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
index b648a337e3..61eadefd35 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
@@ -1,4 +1,4 @@
-//#define AluImm
+#define AluImm
using ChocolArm64.State;
@@ -6,824 +6,448 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
- using Tester;
- using Tester.Types;
-
- [Category("AluImm"), Ignore("Tested: second half of 2018.")]
+ [Category("AluImm")] // Tested: second half of 2018.
public sealed class CpuTestAluImm : CpuTest
{
#if AluImm
- [SetUp]
- public void SetupTester()
- {
- AArch64.TakeReset(false);
- }
+ private const int RndCnt = 2;
+ private const int RndCntImm = 2;
+ private const int RndCntImms = 2;
+ private const int RndCntImmr = 2;
- [Test, Description("ADD , , #{, }")]
+ [Test, Pairwise, Description("ADD , , #{, }")]
public void Add_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
-
- AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
-
- AArch64.SP(new Bits(Xn_SP));
}
- Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ADD , , #{, }")]
+ [Test, Pairwise, Description("ADD , , #{, }")]
public void Add_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
-
- AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
-
- AArch64.SP(new Bits(Wn_WSP));
}
- Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- uint WSP = AArch64.SP(32).ToUInt32();
-
- Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ADDS , , #{, }")]
+ [Test, Pairwise, Description("ADDS , , #{, }")]
public void Adds_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
-
- AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
-
- AArch64.SP(new Bits(Xn_SP));
}
- Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong _X31 = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("ADDS , , #{, }")]
+ [Test, Pairwise, Description("ADDS , , #{, }")]
public void Adds_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
-
- AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
-
- AArch64.SP(new Bits(Wn_WSP));
}
- Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- uint _W31 = AArch64.SP(32).ToUInt32();
-
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("AND , , #")]
+ [Test, Pairwise, Description("AND , , #")]
public void And_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
{
uint Opcode = 0x92400000; // AND X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("AND , , #")]
+ [Test, Pairwise, Description("AND , , #")]
public void And_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0x92000000; // AND X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("AND , , #")]
+ [Test, Pairwise, Description("AND , , #")]
public void And_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0x12000000; // AND W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- AArch64.X((int)Rn, new Bits(Wn));
- Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- uint WSP = AArch64.SP(32).ToUInt32();
-
- Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ANDS , , #")]
+ [Test, Pairwise, Description("ANDS , , #")]
public void Ands_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
{
uint Opcode = 0xF2400000; // ANDS X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- if (Rd != 31)
- {
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("ANDS , , #")]
+ [Test, Pairwise, Description("ANDS , , #")]
public void Ands_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- if (Rd != 31)
- {
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("ANDS , , #")]
+ [Test, Pairwise, Description("ANDS , , #")]
public void Ands_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0x72000000; // ANDS W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- if (Rd != 31)
- {
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("EOR , , #")]
+ [Test, Pairwise, Description("EOR , , #")]
public void Eor_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
{
uint Opcode = 0xD2400000; // EOR X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("EOR , , #")]
+ [Test, Pairwise, Description("EOR , , #")]
public void Eor_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0xD2000000; // EOR X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("EOR , , #")]
+ [Test, Pairwise, Description("EOR , , #")]
public void Eor_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0x52000000; // EOR W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- uint WSP = AArch64.SP(32).ToUInt32();
-
- Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ORR , , #")]
+ [Test, Pairwise, Description("ORR , , #")]
public void Orr_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, //
- [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, //
+ [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) //
{
uint Opcode = 0xB2400000; // ORR X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ORR , , #")]
+ [Test, Pairwise, Description("ORR , , #")]
public void Orr_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0xB2000000; // ORR X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
- AArch64.X((int)Rn, new Bits(Xn));
- Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ORR , , #")]
+ [Test, Pairwise, Description("ORR , , #")]
public void Orr_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
- [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, //
- [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) //
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
+ [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, //
+ [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) //
{
uint Opcode = 0x32000000; // ORR W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
- AArch64.X((int)Rn, new Bits(Wn));
- Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- uint WSP = AArch64.SP(32).ToUInt32();
-
- Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("SUB , , #{, }")]
+ [Test, Pairwise, Description("SUB , , #{, }")]
public void Sub_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
-
- AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
-
- AArch64.SP(new Bits(Xn_SP));
}
- Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong SP = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("SUB , , #{, }")]
+ [Test, Pairwise, Description("SUB , , #{, }")]
public void Sub_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
-
- AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
-
- AArch64.SP(new Bits(Wn_WSP));
}
- Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- uint WSP = AArch64.SP(32).ToUInt32();
-
- Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
- }
CompareAgainstUnicorn();
}
- [Test, Description("SUBS , , #{, }")]
+ [Test, Pairwise, Description("SUBS , , #{, }")]
public void Subs_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
-
- AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
-
- AArch64.SP(new Bits(Xn_SP));
}
- Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- ulong _X31 = AArch64.SP(64).ToUInt64();
-
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("SUBS , , #{, }")]
+ [Test, Pairwise, Description("SUBS , , #{, }")]
public void Subs_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
- [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
+ [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) //
{
uint Opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
- Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
-
- AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
-
- AArch64.SP(new Bits(Wn_WSP));
}
- Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
-
- if (Rd != 31)
- {
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- uint _W31 = AArch64.SP(32).ToUInt32();
-
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
#endif
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
index 49c82b7425..58a99dfb18 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs
@@ -1,4 +1,4 @@
-//#define AluRs
+#define AluRs
using ChocolArm64.State;
@@ -6,1958 +6,1117 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
- using Tester;
- using Tester.Types;
-
- [Category("AluRs"), Ignore("Tested: second half of 2018.")]
+ [Category("AluRs")] // Tested: second half of 2018.
public sealed class CpuTestAluRs : CpuTest
{
#if AluRs
- [SetUp]
- public void SetupTester()
- {
- AArch64.TakeReset(false);
- }
+ private const int RndCnt = 2;
+ private const int RndCntAmount = 2;
+ private const int RndCntLsb = 2;
- [Test, Description("ADC , , ")]
+ [Test, Pairwise, Description("ADC , , ")]
public void Adc_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values] bool CarryIn)
{
uint Opcode = 0x9A000000; // ADC X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Xn));
- AArch64.X((int)Rm, new Bits(Xm));
- Shared.PSTATE.C = CarryIn;
- Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ADC , , ")]
+ [Test, Pairwise, Description("ADC , , ")]
public void Adc_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm,
+ 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values] bool CarryIn)
{
uint Opcode = 0x1A000000; // ADC W0, W0, W0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn);
- if (Rd != 31)
- {
- Bits Op = new Bits(Opcode);
-
- AArch64.X((int)Rn, new Bits(Wn));
- AArch64.X((int)Rm, new Bits(Wm));
- Shared.PSTATE.C = CarryIn;
- Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]);
- uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
-
- Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
- }
- else
- {
- Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
- }
CompareAgainstUnicorn();
}
- [Test, Description("ADCS , , ")]
+ [Test, Pairwise, Description("ADCS , , ")]
public void Adcs_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values] bool CarryIn)
{
uint Opcode = 0xBA000000; // ADCS X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
- Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
+
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn);
- AArch64.X((int)Rn, new Bits(Xn));
- AArch64.X((int)Rm, new Bits(Xm));
- Shared.PSTATE.C = CarryIn;
- Base.Adcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]);
- ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
-
- if (Rd != 31)
- {
- Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
- }
- else
- {
- Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
- }
- Assert.Multiple(() =>
- {
- Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
- Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
- Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
- Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
- });
CompareAgainstUnicorn();
}
- [Test, Description("ADCS