mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-11 12:19:50 +00:00
894459fcd7
* Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update ASoftFloat.cs * Update AOpCodeSimdRegElemF.cs * Update CpuTestSimdIns.cs * Update CpuTestSimdRegElem.cs * Create CpuTestSimdRegElemF.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Superseded Fmul_Se Test. Nit. * Address PR feedback. * Address PR feedback. * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update AInstEmitSimdShift.cs
33 lines
807 B
C#
33 lines
807 B
C#
using ChocolArm64.Instruction;
|
|
|
|
namespace ChocolArm64.Decoder
|
|
{
|
|
class AOpCodeSimdRegElemF : AOpCodeSimdReg
|
|
{
|
|
public int Index { get; private set; }
|
|
|
|
public AOpCodeSimdRegElemF(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
|
|
{
|
|
switch ((OpCode >> 21) & 3) // sz:L
|
|
{
|
|
case 0: // H:0
|
|
Index = (OpCode >> 10) & 2; // 0, 2
|
|
|
|
break;
|
|
|
|
case 1: // H:1
|
|
Index = (OpCode >> 10) & 2;
|
|
Index++; // 1, 3
|
|
|
|
break;
|
|
|
|
case 2: // H
|
|
Index = (OpCode >> 11) & 1; // 0, 1
|
|
|
|
break;
|
|
|
|
default: Emitter = AInstEmit.Und; return;
|
|
}
|
|
}
|
|
}
|
|
}
|