From 3a45eacb16d1d80dd378fc3ae7330fce351a21de Mon Sep 17 00:00:00 2001
From: Jannik Vogel <email@jannikvogel.de>
Date: Wed, 18 May 2016 13:59:05 +0200
Subject: [PATCH] Fix read-after-write in SMUAD, SMLAD, SMUSD, SMLSD

---
 src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 8d4b26815..cfc67287f 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -5527,28 +5527,32 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             // SMUAD and SMLAD
             if (BIT(op2, 1) == 0) {
-                RD = (product1 + product2);
+                u32 rd_val = (product1 + product2);
 
                 if (inst_cream->Ra != 15) {
-                    RD += cpu->Reg[inst_cream->Ra];
+                    rd_val += cpu->Reg[inst_cream->Ra];
 
                     if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra]))
                         cpu->Cpsr |= (1 << 27);
                 }
 
+                RD = rd_val;
+
                 if (ARMul_AddOverflowQ(product1, product2))
                     cpu->Cpsr |= (1 << 27);
             }
             // SMUSD and SMLSD
             else {
-                RD = (product1 - product2);
+                u32 rd_val = (product1 - product2);
 
                 if (inst_cream->Ra != 15) {
-                    RD += cpu->Reg[inst_cream->Ra];
+                    rd_val += cpu->Reg[inst_cream->Ra];
 
                     if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra]))
                         cpu->Cpsr |= (1 << 27);
                 }
+
+                RD = rd_val;
             }
         }