diff --git a/embassy-stm32/src/rcc/l0/mod.rs b/embassy-stm32/src/rcc/l0/mod.rs
index 0b11e708f..6107d5f55 100644
--- a/embassy-stm32/src/rcc/l0/mod.rs
+++ b/embassy-stm32/src/rcc/l0/mod.rs
@@ -170,7 +170,7 @@ impl<'d> Rcc<'d> {
     pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma: bool) {
         // NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
         unsafe {
-            pac::RCC.ahbenr().modify(|w| w.set_dmaen(enable_dma));
+            pac::RCC.ahbenr().modify(|w| w.set_dma1en(enable_dma));
 
             pac::DBGMCU.cr().modify(|w| {
                 w.set_dbg_sleep(true);
diff --git a/stm32-data b/stm32-data
index 5c3d2df91..9ff09761f 160000
--- a/stm32-data
+++ b/stm32-data
@@ -1 +1 @@
-Subproject commit 5c3d2df911c8530d4584c731a5de99951858fccd
+Subproject commit 9ff09761f32da472319756c1c2cd814fda10b571
diff --git a/stm32-metapac-gen/src/lib.rs b/stm32-metapac-gen/src/lib.rs
index 570a225c7..640d746e1 100644
--- a/stm32-metapac-gen/src/lib.rs
+++ b/stm32-metapac-gen/src/lib.rs
@@ -390,8 +390,8 @@ pub fn gen(options: Options) {
                     if let Some(clock_prefix) = clock_prefix {
                         // Workaround for clock registers being split on some chip families. Assume fields are
                         // named after peripheral and look for first field matching and use that register.
-                        let mut en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
-                        let mut rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
+                        let en = find_reg_for_field(&rcc, clock_prefix, &format!("{}EN", name));
+                        let rst = find_reg_for_field(&rcc, clock_prefix, &format!("{}RST", name));
 
                         match (en, rst) {
                             (Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => {