Added STM32 hash test.
This commit is contained in:
Caleb Garrett
parent
e1f6f4b31d
commit
079bb7b490
3 changed files with 88 additions and 8 deletions
tests/stm32
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@ -15,22 +15,23 @@ stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma"
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stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
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stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
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stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng", "fdcan"]
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stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
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stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan"]
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stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan"]
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stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "hash"]
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stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan", "hash"]
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stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan", "hash"]
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stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
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stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
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stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
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stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
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stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng"]
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stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng", "hash"]
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stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"]
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stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng"]
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stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng"]
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stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
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stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash"]
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stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng", "hash"]
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stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng", "hash"]
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stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
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stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng"]
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stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"]
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stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
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hash = []
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eth = ["embassy-executor/task-arena-size-16384"]
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rng = []
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sdmmc = []
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@ -74,6 +75,7 @@ static_cell = "2"
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portable-atomic = { version = "1.5", features = [] }
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chrono = { version = "^0.4", default-features = false, optional = true}
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sha2 = { version = "0.10.8", default-features = false }
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# BEGIN TESTS
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# Generated by gen_test.py. DO NOT EDIT.
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@ -107,6 +109,11 @@ name = "gpio"
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path = "src/bin/gpio.rs"
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required-features = []
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[[bin]]
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name = "hash"
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path = "src/bin/hash.rs"
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required-features = [ "hash",]
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[[bin]]
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name = "rng"
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path = "src/bin/rng.rs"
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66
tests/stm32/src/bin/hash.rs
Normal file
66
tests/stm32/src/bin/hash.rs
Normal file
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@ -0,0 +1,66 @@
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// required-features: hash
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#![no_std]
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#![no_main]
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#[path = "../common.rs"]
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mod common;
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use common::*;
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use embassy_executor::Spawner;
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use embassy_stm32::hash::*;
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use embassy_stm32::{bind_interrupts, peripherals, hash};
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use sha2::{Digest, Sha224, Sha256};
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use {defmt_rtt as _, panic_probe as _};
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bind_interrupts!(struct Irqs {
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HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
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});
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
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let dma = peri!(p, HASH_DMA);
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let mut hw_hasher = Hash::new(p.HASH, dma);
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let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
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let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
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let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
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// Start an SHA-256 digest.
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let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
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hw_hasher.update(&mut sha256context, test_1).await;
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// Interrupt the SHA-256 digest to compute an SHA-224 digest.
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let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8).await;
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hw_hasher.update(&mut sha224context, test_3).await;
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let mut sha224_digest_buffer: [u8; 64] = [0; 64];
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let sha224_digest = hw_hasher.finish(sha224context, &mut sha224_digest_buffer).await;
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// Finish the SHA-256 digest.
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hw_hasher.update(&mut sha256context, test_2).await;
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let mut sha_256_digest_buffer: [u8; 64] = [0; 64];
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let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await;
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// Compute the SHA-256 digest in software.
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let mut sw_sha256_hasher = Sha256::new();
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sw_sha256_hasher.update(test_1);
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sw_sha256_hasher.update(test_2);
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let sw_sha256_digest = sw_sha256_hasher.finalize();
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//Compute the SHA-224 digest in software.
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let mut sw_sha224_hasher = Sha224::new();
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sw_sha224_hasher.update(test_3);
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let sw_sha224_digest = sw_sha224_hasher.finalize();
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// Compare the SHA-256 digests.
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info!("Hardware SHA-256 Digest: {:?}", sha256_digest);
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info!("Software SHA-256 Digest: {:?}", sw_sha256_digest[..]);
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defmt::assert!(*sha256_digest == sw_sha256_digest[..]);
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// Compare the SHA-224 digests.
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info!("Hardware SHA-256 Digest: {:?}", sha224_digest);
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info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
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defmt::assert!(*sha224_digest == sw_sha224_digest[..]);
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info!("Test OK");
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cortex_m::asm::bkpt();
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}
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@ -128,6 +128,7 @@ define_peris!(
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);
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#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
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define_peris!(
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HASH_DMA = DMA1_CH0,
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UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
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ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
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@ -141,18 +142,21 @@ define_peris!(
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);
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#[cfg(feature = "stm32u585ai")]
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define_peris!(
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HASH_DMA = GPDMA1_CH0,
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32u5a5zj")]
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define_peris!(
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HASH_DMA = GPDMA1_CH0,
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UART = LPUART1, UART_TX = PG7, UART_RX = PG8, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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);
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#[cfg(feature = "stm32h563zi")]
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define_peris!(
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HASH_DMA = GPDMA1_CH0,
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UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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@ -171,6 +175,7 @@ define_peris!(
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);
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#[cfg(feature = "stm32l4a6zg")]
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define_peris!(
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HASH_DMA = DMA2_CH7,
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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@ -196,6 +201,7 @@ define_peris!(
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);
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#[cfg(feature = "stm32l552ze")]
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define_peris!(
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HASH_DMA = DMA1_CH0,
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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@ -226,6 +232,7 @@ define_peris!(
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);
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#[cfg(feature = "stm32wba52cg")]
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define_peris!(
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HASH_DMA = GPDMA1_CH0,
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UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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