Add PLL config support for F2
This commit is contained in:
Joonas Javanainen
parent
0cfe1dc9df
commit
07ad52162b
2 changed files with 227 additions and 21 deletions
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@ -1,7 +1,8 @@
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use core::ops::Div;
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use core::convert::TryFrom;
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use core::ops::{Div, Mul};
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use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
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use crate::pac::rcc::vals::{Hpre, Pllp, Pllsrc, Ppre, Sw};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -20,6 +21,7 @@ pub struct HSEConfig {
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pub enum ClockSrc {
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HSE,
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HSI,
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PLL,
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}
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/// HSE clock source
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@ -31,6 +33,170 @@ pub enum HSESrc {
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Bypass,
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}
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#[derive(Clone, Copy)]
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pub struct PLLConfig {
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pub pre_div: PLLPreDiv,
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pub mul: PLLMul,
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pub main_div: PLLMainDiv,
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pub pll48_div: PLL48Div,
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}
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impl Default for PLLConfig {
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fn default() -> Self {
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PLLConfig {
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pre_div: PLLPreDiv(16),
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mul: PLLMul(192),
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main_div: PLLMainDiv::Div2,
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pll48_div: PLL48Div(4),
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}
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}
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}
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impl PLLConfig {
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pub fn clocks(&self, src_freq: Hertz) -> PLLClocks {
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let in_freq = src_freq / self.pre_div;
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let vco_freq = src_freq * self.mul / self.pre_div;
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let main_freq = vco_freq / self.main_div;
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let pll48_freq = vco_freq / self.pll48_div;
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PLLClocks {
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in_freq,
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vco_freq,
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main_freq,
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pll48_freq,
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}
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}
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}
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/// Clock source for both main PLL and PLLI2S
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#[derive(Clone, Copy, PartialEq)]
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pub enum PLLSrc {
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HSE,
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HSI,
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}
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impl Into<Pllsrc> for PLLSrc {
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fn into(self) -> Pllsrc {
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match self {
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PLLSrc::HSE => Pllsrc::HSE,
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PLLSrc::HSI => Pllsrc::HSI,
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}
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}
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}
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/// Division factor for both main PLL and PLLI2S
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#[derive(Clone, Copy, PartialEq)]
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#[repr(transparent)]
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pub struct PLLPreDiv(u8);
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impl TryFrom<u8> for PLLPreDiv {
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type Error = &'static str;
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fn try_from(value: u8) -> Result<Self, Self::Error> {
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match value {
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2..=63 => Ok(PLLPreDiv(value)),
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_ => Err("PLLPreDiv must be within range 2..=63"),
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}
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}
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}
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impl Div<PLLPreDiv> for Hertz {
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type Output = Hertz;
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fn div(self, rhs: PLLPreDiv) -> Self::Output {
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Hertz(self.0 / u32::from(rhs.0))
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}
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}
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/// Multiplication factor for main PLL
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#[derive(Clone, Copy, PartialEq)]
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#[repr(transparent)]
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pub struct PLLMul(u16);
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impl Mul<PLLMul> for Hertz {
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type Output = Hertz;
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fn mul(self, rhs: PLLMul) -> Self::Output {
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Hertz(self.0 * u32::from(rhs.0))
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}
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}
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impl TryFrom<u16> for PLLMul {
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type Error = &'static str;
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fn try_from(value: u16) -> Result<Self, Self::Error> {
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match value {
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192..=432 => Ok(PLLMul(value)),
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_ => Err("PLLMul must be within range 192..=432"),
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}
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}
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}
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/// PLL division factor for the main system clock
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#[derive(Clone, Copy, PartialEq)]
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pub enum PLLMainDiv {
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Div2,
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Div4,
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Div6,
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Div8,
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}
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impl Into<Pllp> for PLLMainDiv {
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fn into(self) -> Pllp {
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match self {
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PLLMainDiv::Div2 => Pllp::DIV2,
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PLLMainDiv::Div4 => Pllp::DIV4,
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PLLMainDiv::Div6 => Pllp::DIV8,
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PLLMainDiv::Div8 => Pllp::DIV8,
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}
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}
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}
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impl Div<PLLMainDiv> for Hertz {
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type Output = Hertz;
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fn div(self, rhs: PLLMainDiv) -> Self::Output {
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let divisor = match rhs {
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PLLMainDiv::Div2 => 2,
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PLLMainDiv::Div4 => 4,
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PLLMainDiv::Div6 => 6,
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PLLMainDiv::Div8 => 8,
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};
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Hertz(self.0 / divisor)
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}
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}
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/// PLL division factor for USB OTG FS / SDIO / RNG
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#[derive(Clone, Copy, PartialEq)]
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#[repr(transparent)]
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pub struct PLL48Div(u8);
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impl Div<PLL48Div> for Hertz {
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type Output = Hertz;
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fn div(self, rhs: PLL48Div) -> Self::Output {
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Hertz(self.0 / u32::from(rhs.0))
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}
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}
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impl TryFrom<u8> for PLL48Div {
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type Error = &'static str;
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fn try_from(value: u8) -> Result<Self, Self::Error> {
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match value {
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2..=15 => Ok(PLL48Div(value)),
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_ => Err("PLL48Div must be within range 2..=15"),
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}
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}
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}
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#[derive(Clone, Copy, PartialEq)]
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pub struct PLLClocks {
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pub in_freq: Hertz,
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pub vco_freq: Hertz,
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pub main_freq: Hertz,
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pub pll48_freq: Hertz,
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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@ -213,6 +379,9 @@ impl VoltageRange {
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/// Clocks configuration
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pub struct Config {
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pub hse: Option<HSEConfig>,
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pub hsi: bool,
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pub pll_mux: PLLSrc,
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pub pll: PLLConfig,
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pub mux: ClockSrc,
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pub voltage: VoltageRange,
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pub ahb_pre: AHBPrescaler,
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@ -225,6 +394,9 @@ impl Default for Config {
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fn default() -> Config {
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Config {
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hse: None,
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hsi: true,
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pll_mux: PLLSrc::HSI,
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pll: PLLConfig::default(),
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voltage: VoltageRange::Min1V8,
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mux: ClockSrc::HSI,
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ahb_pre: AHBPrescaler::NotDivided,
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@ -234,31 +406,53 @@ impl Default for Config {
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}
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}
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#[inline]
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unsafe fn enable_hse(source: HSESrc) {
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RCC.cr().write(|w| {
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w.set_hsebyp(match source {
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HSESrc::Bypass => true,
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HSESrc::Crystal => false,
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});
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w.set_hseon(true)
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});
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while !RCC.cr().read().hserdy() {}
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}
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#[inline]
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unsafe fn enable_hsi() {
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pub(crate) unsafe fn init(config: Config) {
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// Make sure HSI is enabled
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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}
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pub(crate) unsafe fn init(config: Config) {
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if let Some(hse_config) = config.hse {
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enable_hse(hse_config.source);
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RCC.cr().modify(|w| {
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w.set_hsebyp(match hse_config.source {
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HSESrc::Bypass => true,
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HSESrc::Crystal => false,
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});
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w.set_hseon(true)
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});
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while !RCC.cr().read().hserdy() {}
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}
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let pll_src_freq = match config.pll_mux {
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PLLSrc::HSE => {
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config
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.hse
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.expect("HSE must be configured to be used as PLL input")
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.frequency
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}
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PLLSrc::HSI => HSI,
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};
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// Reference: STM32F215xx/217xx datasheet Table 33. Main PLL characteristics
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let pll_clocks = config.pll.clocks(pll_src_freq);
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assert!(Hertz(950_000) <= pll_clocks.in_freq && pll_clocks.in_freq <= Hertz(2_100_000));
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assert!(Hertz(192_000_000) <= pll_clocks.vco_freq && pll_clocks.vco_freq <= Hertz(432_000_000));
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assert!(
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Hertz(24_000_000) <= pll_clocks.main_freq && pll_clocks.main_freq <= Hertz(120_000_000)
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);
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// USB actually requires == 48 MHz, but other PLL48 peripherals are fine with <= 48MHz
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assert!(pll_clocks.pll48_freq <= Hertz(48_000_000));
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RCC.pllcfgr().write(|w| {
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w.set_pllsrc(config.pll_mux.into());
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w.set_pllm(config.pll.pre_div.0);
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w.set_plln(config.pll.mul.0);
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w.set_pllp(config.pll.main_div.into());
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w.set_pllq(config.pll.pll48_div.0);
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});
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let (sys_clk, sw) = match config.mux {
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ClockSrc::HSI => {
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enable_hsi();
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assert!(config.hsi, "HSI must be enabled to be used as system clock");
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(HSI, Sw::HSI)
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}
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ClockSrc::HSE => {
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@ -267,6 +461,11 @@ pub(crate) unsafe fn init(config: Config) {
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.expect("HSE must be configured to be used as system clock");
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(hse_config.frequency, Sw::HSE)
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}
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ClockSrc::PLL => {
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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(pll_clocks.main_freq, Sw::PLL)
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}
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};
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// RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL
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// max output to be 120 MHz, so there's no way to get higher frequencies
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@ -285,6 +484,12 @@ pub(crate) unsafe fn init(config: Config) {
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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while RCC.cfgr().read().sws() != sw.0 {}
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// Turn off HSI to save power if we don't need it
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if !config.hsi {
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RCC.cr().modify(|w| w.set_hsion(false));
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}
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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@ -315,5 +520,6 @@ pub(crate) unsafe fn init(config: Config) {
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apb1_tim: apb1_tim_freq,
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apb2: apb2_freq,
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apb2_tim: apb2_tim_freq,
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pll48: Some(pll_clocks.pll48_freq),
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});
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}
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@ -53,7 +53,7 @@ pub struct Clocks {
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#[cfg(any(rcc_h7, rcc_h7ab))]
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pub ahb4: Hertz,
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#[cfg(any(rcc_f4, rcc_f410, rcc_f7))]
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#[cfg(any(rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
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pub pll48: Option<Hertz>,
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#[cfg(rcc_f1)]
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