stm32: add disable_ucpdx_dead_battery
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1 changed files with 46 additions and 0 deletions
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@ -189,6 +189,18 @@ pub struct Config {
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/// Defaults to P0 (highest).
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#[cfg(gpdma)]
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pub gpdma_interrupt_priority: Priority,
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/// Disables UCPD1 dead battery functionality.
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///
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/// Defaults to true (disabled).
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#[cfg(ucpd)]
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pub disable_ucpd1_dead_battery: bool,
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/// Disables UCPD2 dead battery functionality.
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///
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/// Defaults to true (disabled).
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#[cfg(all(ucpd, stm32g0x1))]
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pub disable_ucpd2_dead_battery: bool,
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}
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impl Default for Config {
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@ -203,6 +215,10 @@ impl Default for Config {
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dma_interrupt_priority: Priority::P0,
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#[cfg(gpdma)]
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gpdma_interrupt_priority: Priority::P0,
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#[cfg(ucpd)]
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disable_ucpd1_dead_battery: true,
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#[cfg(all(ucpd, stm32g0x1))]
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uisable_ucpd2_dead_battery: true,
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}
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}
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}
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@ -254,6 +270,36 @@ pub fn init(config: Config) -> Peripherals {
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#[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
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peripherals::FLASH::enable_and_reset_with_cs(cs);
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// dead battery IOs are still present on g0x0 despite not having UCPD
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#[cfg(any(stm32g070, stm32g0b0))]
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let (disable_ucpd1_dead_battery, disable_ucpd2_dead_battery) = (true, true);
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#[cfg(ucpd)]
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let disable_ucpd1_dead_battery = config.disable_ucpd1_dead_battery;
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#[cfg(all(ucpd, stm32g0x1))]
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let disable_ucpd2_dead_battery = config.disable_ucpd2_dead_battery;
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#[cfg(any(stm32g070, stm32g0b0, all(ucpd, stm32g0x1)))]
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{
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crate::pac::SYSCFG.cfgr1().modify(|w| {
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w.set_ucpd1_strobe(disable_ucpd1_dead_battery);
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w.set_ucpd2_strobe(disable_ucpd2_dead_battery);
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});
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}
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#[cfg(all(ucpd, any(stm32g4, stm32l5)))]
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{
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crate::pac::PWR
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.cr3()
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.modify(|w| w.set_ucpd1_dbdis(disable_ucpd1_dead_battery))
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}
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#[cfg(all(ucpd, any(stm32h5, stm32u5)))]
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{
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crate::pac::PWR
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.ucpdr()
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.modify(|w| w.set_ucpd1_dbdis(disable_ucpd1_dead_battery))
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}
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unsafe {
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#[cfg(feature = "_split-pins-enabled")]
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crate::pac::SYSCFG.pmcr().modify(|pmcr| {
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