nrf/uart: add support for tx-only and rx-only uart.
Allow creating UarteRx/UarteTx directly. This allows using uart unidirectionally (rx-only or tx-only), without having to 'waste' a pin for the unused direction.
This commit is contained in:
Dario Nieuwenhuis
parent
a51df0dec6
commit
0beea82f40
1 changed files with 149 additions and 27 deletions
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@ -19,9 +19,10 @@ use core::task::Poll;
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::unborrow;
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use futures::future::poll_fn; // Re-export SVD variants to allow user to directly set values.
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pub use pac::uarte0::baudrate::BAUDRATE_A as Baudrate;
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pub use pac::uarte0::config::PARITY_A as Parity;
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use futures::future::poll_fn;
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use pac::uarte0::RegisterBlock;
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// Re-export SVD variants to allow user to directly set values.
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pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
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use crate::gpio::sealed::Pin as _;
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@ -32,6 +33,7 @@ use crate::timer::{Frequency, Instance as TimerInstance, Timer};
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use crate::util::slice_in_ram_or;
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use crate::{pac, Unborrow};
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#[derive(Clone)]
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#[non_exhaustive]
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pub struct Config {
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pub parity: Parity,
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@ -144,37 +146,18 @@ impl<'d, T: Instance> Uarte<'d, T> {
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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// Configure
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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let hardware_flow_control = match (rts.is_some(), cts.is_some()) {
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(false, false) => false,
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(true, true) => true,
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_ => panic!("RTS and CTS pins must be either both set or none set."),
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};
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r.config.write(|w| {
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w.hwfc().bit(hardware_flow_control);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// Disable all interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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// Reset rxstarted, txstarted. These are used by drop to know whether a transfer was
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// stopped midway or not.
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r.events_rxstarted.reset();
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r.events_txstarted.reset();
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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// Enable
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apply_workaround_for_enable_anomaly(&r);
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r.enable.write(|w| w.enable().enabled());
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configure(r, config, hardware_flow_control);
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let s = T::state();
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s.tx_rx_refcount.store(2, Ordering::Relaxed);
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Self {
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@ -238,7 +221,87 @@ impl<'d, T: Instance> Uarte<'d, T> {
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}
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}
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fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
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r.config.write(|w| {
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w.hwfc().bit(hardware_flow_control);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// Disable all interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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// Reset rxstarted, txstarted. These are used by drop to know whether a transfer was
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// stopped midway or not.
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r.events_rxstarted.reset();
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r.events_txstarted.reset();
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// Enable
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apply_workaround_for_enable_anomaly(&r);
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r.enable.write(|w| w.enable().enabled());
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}
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impl<'d, T: Instance> UarteTx<'d, T> {
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/// Create a new tx-only UARTE without hardware flow control
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pub fn new(
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uarte: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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txd: impl Unborrow<Target = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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unborrow!(txd);
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Self::new_inner(uarte, irq, txd.degrade(), None, config)
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}
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/// Create a new tx-only UARTE with hardware flow control (RTS/CTS)
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pub fn new_with_rtscts(
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uarte: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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txd: impl Unborrow<Target = impl GpioPin> + 'd,
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cts: impl Unborrow<Target = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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unborrow!(txd, cts);
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Self::new_inner(uarte, irq, txd.degrade(), Some(cts.degrade()), config)
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}
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fn new_inner(
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_uarte: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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txd: AnyPin,
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cts: Option<AnyPin>,
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config: Config,
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) -> Self {
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unborrow!(irq);
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let r = T::regs();
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().s0s1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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r.psel.rxd.write(|w| w.connect().disconnected());
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r.psel.rts.write(|w| w.connect().disconnected());
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let hardware_flow_control = cts.is_some();
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configure(r, config, hardware_flow_control);
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irq.set_handler(Uarte::<T>::on_interrupt);
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irq.unpend();
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irq.enable();
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let s = T::state();
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s.tx_rx_refcount.store(1, Ordering::Relaxed);
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Self { phantom: PhantomData }
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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match self.write_from_ram(buffer).await {
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Ok(_) => Ok(()),
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@ -372,6 +435,65 @@ impl<'a, T: Instance> Drop for UarteTx<'a, T> {
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}
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impl<'d, T: Instance> UarteRx<'d, T> {
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/// Create a new rx-only UARTE without hardware flow control
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pub fn new(
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uarte: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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rxd: impl Unborrow<Target = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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unborrow!(rxd);
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Self::new_inner(uarte, irq, rxd.degrade(), None, config)
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}
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/// Create a new rx-only UARTE with hardware flow control (RTS/CTS)
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pub fn new_with_rtscts(
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uarte: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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rxd: impl Unborrow<Target = impl GpioPin> + 'd,
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rts: impl Unborrow<Target = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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unborrow!(rxd, rts);
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Self::new_inner(uarte, irq, rxd.degrade(), Some(rts.degrade()), config)
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}
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fn new_inner(
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_uarte: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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rxd: AnyPin,
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rts: Option<AnyPin>,
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config: Config,
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) -> Self {
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unborrow!(irq);
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let r = T::regs();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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if let Some(pin) = &rts {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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r.psel.txd.write(|w| w.connect().disconnected());
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r.psel.cts.write(|w| w.connect().disconnected());
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irq.set_handler(Uarte::<T>::on_interrupt);
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irq.unpend();
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irq.enable();
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let hardware_flow_control = rts.is_some();
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configure(r, config, hardware_flow_control);
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let s = T::state();
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s.tx_rx_refcount.store(1, Ordering::Relaxed);
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Self { phantom: PhantomData }
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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if buffer.len() == 0 {
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return Err(Error::BufferZeroLength);
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