From 15c533fe2a7fe2adad3aff186a3d57332eb014fb Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Mon, 14 Mar 2022 18:04:31 -0500 Subject: [PATCH] Fix async `write` bug --- embassy-stm32/src/spi/mod.rs | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 3b39f0fd2..1b2cdf19e 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -418,10 +418,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { }); } - // TODO: This is unnecessary in some versions because - // clearing SPE automatically clears the fifos - flush_rx_fifo(T::REGS); - let tx_request = self.txdma.request(); let tx_dst = T::REGS.tx_ptr(); unsafe { self.txdma.start_write(tx_request, data, tx_dst) } @@ -440,6 +436,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { tx_f.await; + // flush here otherwise `finish_dma` hangs waiting for the rx fifo to empty + flush_rx_fifo(T::REGS); + finish_dma(T::REGS); Ok(())