usb: associate ControlHandlers with interfaces, automatically route requests.
This commit is contained in:
parent
3412e5dc4a
commit
15cc97d794
4 changed files with 94 additions and 109 deletions
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@ -1,11 +1,11 @@
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use heapless::Vec;
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use super::class::UsbClass;
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use super::class::ControlHandler;
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use super::descriptor::{BosWriter, DescriptorWriter};
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use super::driver::{Driver, EndpointAllocError};
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use super::types::*;
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use super::UsbDevice;
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use super::MAX_CLASS_COUNT;
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use super::MAX_INTERFACE_COUNT;
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#[derive(Debug, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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@ -119,7 +119,7 @@ impl<'a> Config<'a> {
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/// Used to build new [`UsbDevice`]s.
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pub struct UsbDeviceBuilder<'d, D: Driver<'d>> {
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config: Config<'d>,
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classes: Vec<&'d mut dyn UsbClass, MAX_CLASS_COUNT>,
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interfaces: Vec<(u8, &'d mut dyn ControlHandler), MAX_INTERFACE_COUNT>,
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bus: D,
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next_interface_number: u8,
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@ -169,7 +169,7 @@ impl<'d, D: Driver<'d>> UsbDeviceBuilder<'d, D> {
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UsbDeviceBuilder {
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bus,
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config,
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classes: Vec::new(),
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interfaces: Vec::new(),
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next_interface_number: 0,
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next_string_index: 4,
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@ -190,16 +190,10 @@ impl<'d, D: Driver<'d>> UsbDeviceBuilder<'d, D> {
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self.device_descriptor.into_buf(),
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self.config_descriptor.into_buf(),
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self.bos_descriptor.writer.into_buf(),
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self.classes,
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self.interfaces,
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)
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}
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pub fn add_class(&mut self, class: &'d mut dyn UsbClass) {
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if self.classes.push(class).is_err() {
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panic!("max class count reached")
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}
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}
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/// Allocates a new interface number.
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pub fn alloc_interface(&mut self) -> InterfaceNumber {
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let number = self.next_interface_number;
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@ -208,6 +202,22 @@ impl<'d, D: Driver<'d>> UsbDeviceBuilder<'d, D> {
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InterfaceNumber::new(number)
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}
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/// Allocates a new interface number, with a handler that will be called
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/// for all the control requests directed to it.
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pub fn alloc_interface_with_handler(
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&mut self,
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handler: &'d mut dyn ControlHandler,
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) -> InterfaceNumber {
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let number = self.next_interface_number;
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self.next_interface_number += 1;
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if self.interfaces.push((number, handler)).is_err() {
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panic!("max class count reached")
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}
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InterfaceNumber::new(number)
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}
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/// Allocates a new string index.
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pub fn alloc_string(&mut self) -> StringIndex {
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let index = self.next_string_index;
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@ -3,22 +3,15 @@ use crate::control::Request;
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#[derive(Copy, Clone, Eq, PartialEq, Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum RequestStatus {
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Unhandled,
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Accepted,
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Rejected,
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}
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impl Default for RequestStatus {
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fn default() -> Self {
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RequestStatus::Unhandled
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}
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}
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/// A trait for implementing USB classes.
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///
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/// All methods are optional callbacks that will be called by
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/// [`UsbDevice::run()`](crate::UsbDevice::run)
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pub trait UsbClass {
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pub trait ControlHandler {
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/// Called after a USB reset after the bus reset sequence is complete.
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fn reset(&mut self) {}
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@ -35,7 +28,9 @@ pub trait UsbClass {
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///
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/// * `req` - The request from the SETUP packet.
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/// * `data` - The data from the request.
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fn control_out(&mut self, req: Request, data: &[u8]) -> RequestStatus;
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fn control_out(&mut self, req: Request, data: &[u8]) -> RequestStatus {
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RequestStatus::Rejected
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}
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/// Called when a control request is received with direction DeviceToHost.
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///
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@ -56,7 +51,9 @@ pub trait UsbClass {
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&mut self,
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req: Request,
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control: ControlIn<'a>,
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) -> ControlInRequestStatus<'a>;
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) -> ControlInRequestStatus<'a> {
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control.reject()
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}
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}
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/// Handle for a control IN transfer. When implementing a class, use the methods of this object to
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@ -84,14 +81,6 @@ impl<'a> ControlIn<'a> {
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ControlIn { buf }
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}
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/// Ignores the request and leaves it unhandled.
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pub fn ignore(self) -> ControlInRequestStatus<'a> {
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ControlInRequestStatus {
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status: RequestStatus::Unhandled,
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data: &[],
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}
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}
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/// Accepts the transfer with the supplied buffer.
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pub fn accept(self, data: &[u8]) -> ControlInRequestStatus<'a> {
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assert!(data.len() < self.buf.len());
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@ -108,7 +97,7 @@ impl<'a> ControlIn<'a> {
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/// Rejects the transfer by stalling the pipe.
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pub fn reject(self) -> ControlInRequestStatus<'a> {
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ControlInRequestStatus {
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status: RequestStatus::Unhandled,
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status: RequestStatus::Rejected,
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data: &[],
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}
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}
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@ -13,10 +13,9 @@ pub mod driver;
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pub mod types;
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mod util;
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use class::ControlInRequestStatus;
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use heapless::Vec;
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use self::class::{RequestStatus, UsbClass};
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use self::class::{ControlHandler, RequestStatus};
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use self::control::*;
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use self::descriptor::*;
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use self::driver::*;
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@ -54,7 +53,7 @@ pub const CONFIGURATION_VALUE: u8 = 1;
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/// The default value for bAlternateSetting for all interfaces.
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pub const DEFAULT_ALTERNATE_SETTING: u8 = 0;
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pub const MAX_CLASS_COUNT: usize = 4;
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pub const MAX_INTERFACE_COUNT: usize = 4;
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pub struct UsbDevice<'d, D: Driver<'d>> {
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bus: D::Bus,
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@ -70,7 +69,7 @@ pub struct UsbDevice<'d, D: Driver<'d>> {
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self_powered: bool,
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pending_address: u8,
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classes: Vec<&'d mut dyn UsbClass, MAX_CLASS_COUNT>,
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interfaces: Vec<(u8, &'d mut dyn ControlHandler), MAX_INTERFACE_COUNT>,
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}
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impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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@ -80,7 +79,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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device_descriptor: &'d [u8],
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config_descriptor: &'d [u8],
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bos_descriptor: &'d [u8],
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classes: Vec<&'d mut dyn UsbClass, MAX_CLASS_COUNT>,
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interfaces: Vec<(u8, &'d mut dyn ControlHandler), MAX_INTERFACE_COUNT>,
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) -> Self {
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let control = driver
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.alloc_control_pipe(config.max_packet_size_0 as u16)
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@ -101,7 +100,7 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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remote_wakeup_enabled: false,
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self_powered: false,
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pending_address: 0,
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classes,
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interfaces,
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}
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}
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@ -118,8 +117,8 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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self.remote_wakeup_enabled = false;
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self.pending_address = 0;
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for c in self.classes.iter_mut() {
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c.reset();
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for (_, h) in self.interfaces.iter_mut() {
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h.reset();
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}
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}
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Event::Resume => {}
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@ -153,24 +152,6 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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}
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async fn handle_control_out(&mut self, req: Request) {
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{
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let mut buf = [0; 128];
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let data = if req.length > 0 {
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let size = self.control.data_out(&mut buf).await.unwrap();
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&buf[0..size]
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} else {
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&[]
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};
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for c in self.classes.iter_mut() {
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match c.control_out(req, data) {
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RequestStatus::Accepted => return self.control.accept(),
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RequestStatus::Rejected => return self.control.reject(),
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RequestStatus::Unhandled => (),
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}
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}
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}
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const CONFIGURATION_NONE_U16: u16 = CONFIGURATION_NONE as u16;
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const CONFIGURATION_VALUE_U16: u16 = CONFIGURATION_VALUE as u16;
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const DEFAULT_ALTERNATE_SETTING_U16: u16 = DEFAULT_ALTERNATE_SETTING as u16;
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@ -224,29 +205,33 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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}
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_ => self.control.reject(),
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},
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(RequestType::Class, Recipient::Interface) => {
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let mut buf = [0; 128];
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let data = if req.length > 0 {
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let size = self.control.data_out(&mut buf).await.unwrap();
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&buf[0..size]
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} else {
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&[]
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};
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let handler = self
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.interfaces
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.iter_mut()
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.find(|(i, _)| req.index == *i as _)
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.map(|(_, h)| h);
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match handler {
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Some(handler) => match handler.control_out(req, data) {
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RequestStatus::Accepted => return self.control.accept(),
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RequestStatus::Rejected => return self.control.reject(),
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},
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None => self.control.reject(),
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}
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}
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_ => self.control.reject(),
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}
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}
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async fn handle_control_in(&mut self, req: Request) {
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let mut buf = [0; 128];
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for c in self.classes.iter_mut() {
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match c.control_in(req, class::ControlIn::new(&mut buf)) {
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ControlInRequestStatus {
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status: RequestStatus::Accepted,
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data,
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} => return self.control.accept_in(data).await,
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ControlInRequestStatus {
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status: RequestStatus::Rejected,
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..
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} => return self.control.reject(),
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ControlInRequestStatus {
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status: RequestStatus::Unhandled,
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..
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} => (),
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}
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}
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match (req.request_type, req.recipient) {
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(RequestType::Standard, Recipient::Device) => match req.request {
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Request::GET_STATUS => {
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@ -294,6 +279,24 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
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}
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_ => self.control.reject(),
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},
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(RequestType::Class, Recipient::Interface) => {
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let mut buf = [0; 128];
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let handler = self
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.interfaces
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.iter_mut()
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.find(|(i, _)| req.index == *i as _)
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.map(|(_, h)| h);
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match handler {
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Some(handler) => {
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let resp = handler.control_in(req, class::ControlIn::new(&mut buf));
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match resp.status {
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RequestStatus::Accepted => self.control.accept_in(resp.data).await,
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RequestStatus::Rejected => self.control.reject(),
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}
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}
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None => self.control.reject(),
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}
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}
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_ => self.control.reject(),
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}
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}
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@ -3,7 +3,7 @@ use core::mem::{self, MaybeUninit};
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use core::sync::atomic::{AtomicBool, Ordering};
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use defmt::info;
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use embassy::blocking_mutex::CriticalSectionMutex;
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use embassy_usb::class::{ControlInRequestStatus, RequestStatus, UsbClass};
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use embassy_usb::class::{ControlHandler, ControlInRequestStatus, RequestStatus};
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use embassy_usb::control::{self, Request};
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use embassy_usb::driver::{Endpoint, EndpointIn, EndpointOut, ReadError, WriteError};
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use embassy_usb::{driver::Driver, types::*, UsbDeviceBuilder};
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@ -64,7 +64,6 @@ pub struct CdcAcmClass<'d, D: Driver<'d>> {
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}
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struct Control {
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comm_if: InterfaceNumber,
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shared: UnsafeCell<ControlShared>,
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}
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@ -80,7 +79,7 @@ impl Control {
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unsafe { &*(self.shared.get() as *const _) }
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}
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}
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impl UsbClass for Control {
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impl ControlHandler for Control {
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fn reset(&mut self) {
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let shared = self.shared();
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shared.line_coding.lock(|x| x.set(LineCoding::default()));
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@ -89,13 +88,6 @@ impl UsbClass for Control {
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}
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fn control_out(&mut self, req: control::Request, data: &[u8]) -> RequestStatus {
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if !(req.request_type == control::RequestType::Class
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&& req.recipient == control::Recipient::Interface
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&& req.index == u8::from(self.comm_if) as u16)
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{
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return RequestStatus::Unhandled;
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}
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match req.request {
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REQ_SEND_ENCAPSULATED_COMMAND => {
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// We don't actually support encapsulated commands but pretend we do for standards
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@ -134,13 +126,6 @@ impl UsbClass for Control {
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req: Request,
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control: embassy_usb::class::ControlIn<'a>,
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) -> ControlInRequestStatus<'a> {
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if !(req.request_type == control::RequestType::Class
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&& req.recipient == control::Recipient::Interface
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&& req.index == u8::from(self.comm_if) as u16)
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{
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return control.ignore();
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}
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match req.request {
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// REQ_GET_ENCAPSULATED_COMMAND is not really supported - it will be rejected below.
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REQ_GET_LINE_CODING if req.length == 7 => {
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@ -166,7 +151,22 @@ impl<'d, D: Driver<'d>> CdcAcmClass<'d, D> {
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state: &'d mut State,
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max_packet_size: u16,
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) -> Self {
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let comm_if = builder.alloc_interface();
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let control = state.control.write(Control {
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shared: UnsafeCell::new(ControlShared {
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dtr: AtomicBool::new(false),
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rts: AtomicBool::new(false),
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line_coding: CriticalSectionMutex::new(Cell::new(LineCoding {
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stop_bits: StopBits::One,
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data_bits: 8,
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parity_type: ParityType::None,
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data_rate: 8_000,
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})),
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}),
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});
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let control_shared = unsafe { &*(control.shared.get() as *const _) };
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let comm_if = builder.alloc_interface_with_handler(control);
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let comm_ep = builder.alloc_interrupt_endpoint_in(8, 255);
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let data_if = builder.alloc_interface();
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let read_ep = builder.alloc_bulk_endpoint_out(max_packet_size);
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@ -245,23 +245,6 @@ impl<'d, D: Driver<'d>> CdcAcmClass<'d, D> {
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builder.config_descriptor.endpoint(write_ep.info()).unwrap();
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builder.config_descriptor.endpoint(read_ep.info()).unwrap();
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let control = state.control.write(Control {
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comm_if,
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shared: UnsafeCell::new(ControlShared {
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dtr: AtomicBool::new(false),
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rts: AtomicBool::new(false),
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line_coding: CriticalSectionMutex::new(Cell::new(LineCoding {
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stop_bits: StopBits::One,
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data_bits: 8,
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parity_type: ParityType::None,
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data_rate: 8_000,
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})),
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}),
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});
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let control_shared = unsafe { &*(control.shared.get() as *const _) };
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builder.add_class(control);
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CdcAcmClass {
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comm_ep,
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data_if,
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