From 17d6e4eefeb9bdc9d7c3776afb815298be5b468c Mon Sep 17 00:00:00 2001 From: Andres Vahter Date: Tue, 9 Jan 2024 09:25:10 +0200 Subject: [PATCH] stm32 uart: do not wake after sending each byte usart_v4 uses TC interrupt to see if all bytes are sent out from the FIFO and waker is called from this interrupt. This minimises unnecessary wakeups during sending. --- embassy-stm32/src/usart/buffered.rs | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs index e050f8e0f..211091c38 100644 --- a/embassy-stm32/src/usart/buffered.rs +++ b/embassy-stm32/src/usart/buffered.rs @@ -62,8 +62,8 @@ impl interrupt::typelevel::Handler for Interrupt state.rx_waker.wake(); } - // With `usart_v4` hardware FIFO is enabled, making `state.tx_buf` - // insufficient to determine if all bytes are sent out. + // With `usart_v4` hardware FIFO is enabled, making `state.tx_buf` insufficient + // to determine if all bytes are sent out. // Transmission complete (TC) interrupt here indicates that all bytes are pushed out from the FIFO. #[cfg(usart_v4)] if sr_val.tc() { @@ -90,9 +90,12 @@ impl interrupt::typelevel::Handler for Interrupt tdr(r).write_volatile(buf[0].into()); tx_reader.pop_done(1); + + // Notice that in case of `usart_v4` waker is called when TC interrupt happens. + #[cfg(not(usart_v4))] state.tx_waker.wake(); } else { - // Disable interrupt until we have something to transmit again + // Disable interrupt until we have something to transmit again. r.cr1().modify(|w| { w.set_txeie(false); });