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Support PLLXTPRE switch.

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See figure 2. Clock tree page 12 DS5319 Rev 18
https://www.st.com/resource/en/datasheet/stm32f103cb.pdf
This commit is contained in:
Marco Pastrello 2023-05-04 21:32:37 +02:00
parent 72e36d8997
commit 1cc61dc68a
1 changed files with 7 additions and 1 deletions
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8
embassy-stm32/src/rcc/f1.rs
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@ -24,10 +24,15 @@ pub struct Config {
pub pclk1: Option<Hertz>, pub pclk1: Option<Hertz>,
pub pclk2: Option<Hertz>, pub pclk2: Option<Hertz>,
pub adcclk: Option<Hertz>, pub adcclk: Option<Hertz>,
pub pllxtpre: Option<bool>,
} }
pub(crate) unsafe fn init(config: Config) { pub(crate) unsafe fn init(config: Config) {
let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0 / 2); let pllsrcclk = config.hse.map(|hse| hse.0 / match config.pllxtpre {
Some(b) => if b {2} else {1},
None => {1},
}).unwrap_or(HSI_FREQ.0 / 2);
let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
let pllmul = sysclk / pllsrcclk; let pllmul = sysclk / pllsrcclk;
@ -143,6 +148,7 @@ pub(crate) unsafe fn init(config: Config) {
} }
if let Some(pllmul_bits) = pllmul_bits { if let Some(pllmul_bits) = pllmul_bits {
RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(config.pllxtpre.is_some() as u8)));
// enable PLL and wait for it to be ready // enable PLL and wait for it to be ready
RCC.cfgr().modify(|w| { RCC.cfgr().modify(|w| {
w.set_pllmul(Pllmul(pllmul_bits)); w.set_pllmul(Pllmul(pllmul_bits));