Support PLLXTPRE switch.
See figure 2. Clock tree page 12 DS5319 Rev 18 https://www.st.com/resource/en/datasheet/stm32f103cb.pdf
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1 changed files with 7 additions and 1 deletions
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@ -24,10 +24,15 @@ pub struct Config {
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub adcclk: Option<Hertz>,
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pub pllxtpre: Option<bool>,
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}
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pub(crate) unsafe fn init(config: Config) {
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let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0 / 2);
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let pllsrcclk = config.hse.map(|hse| hse.0 / match config.pllxtpre {
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Some(b) => if b {2} else {1},
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None => {1},
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}).unwrap_or(HSI_FREQ.0 / 2);
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let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
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let pllmul = sysclk / pllsrcclk;
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@ -143,6 +148,7 @@ pub(crate) unsafe fn init(config: Config) {
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}
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if let Some(pllmul_bits) = pllmul_bits {
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RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(config.pllxtpre.is_some() as u8)));
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// enable PLL and wait for it to be ready
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RCC.cfgr().modify(|w| {
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w.set_pllmul(Pllmul(pllmul_bits));
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