Initial FDCAN driver implementation.
Original author:
Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Cleanup and documentaion by:
Tomasz bla Fortuna <bla@reactor.local>
Corey Schuhen <cschuhen@gmail.com>
Use new PAC method now that the names are common.
Use broken out definitions that can be shared with bxcan
Populate Rx struct with an embassy timestamp.
Remove use of RefCell.
As per review comment. - THis will probably get squashed down.
Fix
This commit is contained in:
Corey Schuhen
Corey Schuhen
parent
03ba45065e
commit
1de78d0490
2 changed files with 706 additions and 15 deletions
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@ -1,14 +1,577 @@
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use crate::peripherals;
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::ops::{Deref, DerefMut};
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use core::task::Poll;
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use cfg_if::cfg_if;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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pub use fdcan::frame::{FrameFormat, RxFrameInfo, TxFrameHeader};
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pub use fdcan::id::{ExtendedId, Id, StandardId};
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use fdcan::message_ram::RegisterBlock;
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use fdcan::{self, LastErrorCode};
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pub use fdcan::{config, filter};
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use crate::gpio::sealed::AFType;
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use crate::interrupt::typelevel::Interrupt;
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use crate::rcc::RccPeripheral;
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use crate::{interrupt, peripherals, Peripheral};
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pub mod enums;
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use enums::*;
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pub mod util;
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/// CAN Frame returned by read
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pub struct RxFrame {
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/// CAN Header info: frame ID, data length and other meta
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pub header: RxFrameInfo,
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/// CAN(0-8 bytes) or FDCAN(0-64 bytes) Frame data
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pub data: Data,
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/// Reception time.
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#[cfg(feature = "time")]
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pub timestamp: embassy_time::Instant,
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}
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/// CAN frame used for write
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pub struct TxFrame {
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/// CAN Header info: frame ID, data length and other meta
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pub header: TxFrameHeader,
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/// CAN(0-8 bytes) or FDCAN(0-64 bytes) Frame data
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pub data: Data,
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}
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impl TxFrame {
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/// Create new TX frame from header and data
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pub fn new(header: TxFrameHeader, data: &[u8]) -> Option<Self> {
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if data.len() < header.len as usize {
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return None;
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}
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let Some(data) = Data::new(data) else { return None };
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Some(TxFrame { header, data })
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}
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fn from_preserved(header: TxFrameHeader, data32: &[u32]) -> Option<Self> {
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let mut data = [0u8; 64];
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for i in 0..data32.len() {
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data[4 * i..][..4].copy_from_slice(&data32[i].to_le_bytes());
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}
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let Some(data) = Data::new(&data) else { return None };
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Some(TxFrame { header, data })
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}
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/// Access frame data. Slice length will match header.
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pub fn data(&self) -> &[u8] {
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&self.data.bytes[..(self.header.len as usize)]
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}
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}
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impl RxFrame {
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pub(crate) fn new(
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header: RxFrameInfo,
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data: &[u8],
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#[cfg(feature = "time")] timestamp: embassy_time::Instant,
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) -> Self {
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let data = Data::new(&data).unwrap_or_else(|| Data::empty());
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RxFrame {
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header,
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data,
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#[cfg(feature = "time")]
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timestamp,
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}
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}
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/// Access frame data. Slice length will match header.
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pub fn data(&self) -> &[u8] {
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&self.data.bytes[..(self.header.len as usize)]
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}
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}
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/// Payload of a (FD)CAN data frame.
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///
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/// Contains 0 to 64 Bytes of data.
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#[derive(Debug, Copy, Clone)]
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pub struct Data {
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pub(crate) bytes: [u8; 64],
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}
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impl Data {
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/// Creates a data payload from a raw byte slice.
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///
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/// Returns `None` if `data` is more than 64 bytes (which is the maximum) or
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/// cannot be represented with an FDCAN DLC.
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pub fn new(data: &[u8]) -> Option<Self> {
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if !Data::is_valid_len(data.len()) {
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return None;
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}
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let mut bytes = [0; 64];
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bytes[..data.len()].copy_from_slice(data);
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Some(Self { bytes })
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}
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/// Raw read access to data.
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pub fn raw(&self) -> &[u8] {
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&self.bytes
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}
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/// Checks if the length can be encoded in FDCAN DLC field.
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pub const fn is_valid_len(len: usize) -> bool {
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match len {
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0..=8 => true,
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12 => true,
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16 => true,
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20 => true,
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24 => true,
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32 => true,
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48 => true,
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64 => true,
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_ => false,
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}
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}
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/// Creates an empty data payload containing 0 bytes.
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#[inline]
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pub const fn empty() -> Self {
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Self { bytes: [0; 64] }
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}
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}
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/// Interrupt handler channel 0.
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pub struct IT0InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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// We use IT0 for everything currently
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impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let regs = T::regs();
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let ir = regs.ir().read();
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if ir.tc() {
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regs.ir().write(|w| w.set_tc(true));
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T::state().tx_waker.wake();
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}
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if ir.tefn() {
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regs.ir().write(|w| w.set_tefn(true));
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T::state().tx_waker.wake();
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}
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if ir.ped() || ir.pea() {
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regs.ir().write(|w| {
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w.set_ped(true);
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w.set_pea(true);
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});
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}
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if ir.rfn(0) {
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regs.ir().write(|w| w.set_rfn(0, true));
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T::state().rx_waker.wake();
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}
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if ir.rfn(1) {
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regs.ir().write(|w| w.set_rfn(1, true));
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T::state().rx_waker.wake();
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}
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}
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}
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/// Interrupt handler channel 1.
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pub struct IT1InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::IT1Interrupt> for IT1InterruptHandler<T> {
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unsafe fn on_interrupt() {}
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}
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impl BusError {
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fn try_from(lec: LastErrorCode) -> Option<BusError> {
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match lec {
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LastErrorCode::AckError => Some(BusError::Acknowledge),
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// `0` data bit encodes a dominant state. `1` data bit is recessive.
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// Bit0Error: During transmit, the node wanted to send a 0 but monitored a 1
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LastErrorCode::Bit0Error => Some(BusError::BitRecessive),
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LastErrorCode::Bit1Error => Some(BusError::BitDominant),
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LastErrorCode::CRCError => Some(BusError::Crc),
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LastErrorCode::FormError => Some(BusError::Form),
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LastErrorCode::StuffError => Some(BusError::Stuff),
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_ => None,
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}
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}
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}
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/// Operating modes trait
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pub trait FdcanOperatingMode {}
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impl FdcanOperatingMode for fdcan::PoweredDownMode {}
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impl FdcanOperatingMode for fdcan::ConfigMode {}
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impl FdcanOperatingMode for fdcan::InternalLoopbackMode {}
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impl FdcanOperatingMode for fdcan::ExternalLoopbackMode {}
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impl FdcanOperatingMode for fdcan::NormalOperationMode {}
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impl FdcanOperatingMode for fdcan::RestrictedOperationMode {}
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impl FdcanOperatingMode for fdcan::BusMonitoringMode {}
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impl FdcanOperatingMode for fdcan::TestMode {}
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/// FDCAN Instance
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pub struct Fdcan<'d, T: Instance, M: FdcanOperatingMode> {
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/// Reference to internals.
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pub can: fdcan::FdCan<FdcanInstance<'d, T>, M>,
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ns_per_timer_tick: u64, // For FDCAN internal timer
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}
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fn calc_ns_per_timer_tick<T: Instance>(mode: config::FrameTransmissionConfig) -> u64 {
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match mode {
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// Use timestamp from Rx FIFO to adjust timestamp reported to user
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config::FrameTransmissionConfig::ClassicCanOnly => {
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let freq = T::frequency();
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let prescale: u64 =
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({ T::regs().nbtp().read().nbrp() } + 1) as u64 * ({ T::regs().tscc().read().tcp() } + 1) as u64;
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1_000_000_000 as u64 / (freq.0 as u64 * prescale)
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}
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// For VBR this is too hard because the FDCAN timer switches clock rate you need to configure to use
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// timer3 instead which is too hard to do from this module.
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_ => 0,
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}
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}
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#[cfg(feature = "time")]
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fn calc_timestamp<T: Instance>(ns_per_timer_tick: u64, ts_val: u16) -> embassy_time::Instant {
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let now_embassy = embassy_time::Instant::now();
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if ns_per_timer_tick == 0 {
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return now_embassy;
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}
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let now_can = { T::regs().tscv().read().tsc() };
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let delta = now_can.overflowing_sub(ts_val).0 as u64;
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let ns = ns_per_timer_tick * delta as u64;
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now_embassy - embassy_time::Duration::from_nanos(ns)
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}
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fn curr_error<T: Instance>() -> Option<BusError> {
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let err = { T::regs().psr().read() };
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if err.bo() {
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return Some(BusError::BusOff);
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} else if err.ep() {
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return Some(BusError::BusPassive);
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} else if err.ew() {
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return Some(BusError::BusWarning);
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} else {
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cfg_if! {
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if #[cfg(stm32h7)] {
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let lec = err.lec();
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} else {
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let lec = err.lec().to_bits();
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}
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}
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if let Ok(err) = LastErrorCode::try_from(lec) {
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return BusError::try_from(err);
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}
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}
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None
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}
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impl<'d, T: Instance> Fdcan<'d, T, fdcan::ConfigMode> {
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/// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
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/// You must call [Fdcan::enable_non_blocking] to use the peripheral.
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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_irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
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+ interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
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+ 'd,
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) -> Fdcan<'d, T, fdcan::ConfigMode> {
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into_ref!(peri, rx, tx);
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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T::enable_and_reset();
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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let mut can = fdcan::FdCan::new(FdcanInstance(peri)).into_config_mode();
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T::configure_msg_ram();
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unsafe {
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// Enable timestamping
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#[cfg(not(stm32h7))]
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T::regs()
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.tscc()
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.write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
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#[cfg(stm32h7)]
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T::regs().tscc().write(|w| w.set_tss(0x01));
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T::IT0Interrupt::unpend(); // Not unsafe
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T::IT0Interrupt::enable();
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T::IT1Interrupt::unpend(); // Not unsafe
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T::IT1Interrupt::enable();
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// this isn't really documented in the reference manual
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// but corresponding txbtie bit has to be set for the TC (TxComplete) interrupt to fire
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T::regs().txbtie().write(|w| w.0 = 0xffff_ffff);
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}
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can.enable_interrupt(fdcan::interrupt::Interrupt::RxFifo0NewMsg);
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can.enable_interrupt(fdcan::interrupt::Interrupt::RxFifo1NewMsg);
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can.enable_interrupt(fdcan::interrupt::Interrupt::TxComplete);
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can.enable_interrupt_line(fdcan::interrupt::InterruptLine::_0, true);
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can.enable_interrupt_line(fdcan::interrupt::InterruptLine::_1, true);
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let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(can.get_config().frame_transmit);
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Self { can, ns_per_timer_tick }
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}
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/// Configures the bit timings calculated from supplied bitrate.
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pub fn set_bitrate(&mut self, bitrate: u32) {
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let bit_timing = util::calc_can_timings(T::frequency(), bitrate).unwrap();
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self.can.set_nominal_bit_timing(config::NominalBitTiming {
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sync_jump_width: bit_timing.sync_jump_width,
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prescaler: bit_timing.prescaler,
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seg1: bit_timing.seg1,
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seg2: bit_timing.seg2,
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});
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}
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}
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macro_rules! impl_transition {
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($from_mode:ident, $to_mode:ident, $name:ident, $func: ident) => {
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impl<'d, T: Instance> Fdcan<'d, T, fdcan::$from_mode> {
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/// Transition from $from_mode:ident mode to $to_mode:ident mode
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pub fn $name(self) -> Fdcan<'d, T, fdcan::$to_mode> {
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let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(self.can.get_config().frame_transmit);
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Fdcan {
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can: self.can.$func(),
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ns_per_timer_tick,
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}
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}
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}
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};
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}
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impl_transition!(PoweredDownMode, ConfigMode, into_config_mode, into_config_mode);
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impl_transition!(InternalLoopbackMode, ConfigMode, into_config_mode, into_config_mode);
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impl_transition!(ConfigMode, NormalOperationMode, into_normal_mode, into_normal);
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impl_transition!(
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ConfigMode,
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ExternalLoopbackMode,
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into_external_loopback_mode,
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into_external_loopback
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);
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impl_transition!(
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ConfigMode,
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InternalLoopbackMode,
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into_internal_loopback_mode,
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into_internal_loopback
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);
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impl<'d, T: Instance, M: FdcanOperatingMode> Fdcan<'d, T, M>
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where
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M: fdcan::Transmit,
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M: fdcan::Receive,
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{
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/// Queues the message to be sent but exerts backpressure. If a lower-priority
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/// frame is dropped from the mailbox, it is returned. If no lower-priority frames
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/// can be replaced, this call asynchronously waits for a frame to be successfully
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/// transmitted, then tries again.
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pub async fn write(&mut self, frame: &TxFrame) -> Option<TxFrame> {
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poll_fn(|cx| {
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T::state().tx_waker.register(cx.waker());
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if let Ok(dropped) = self
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.can
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.transmit_preserve(frame.header, &frame.data.bytes, &mut |_, hdr, data32| {
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TxFrame::from_preserved(hdr, data32)
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})
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{
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return Poll::Ready(dropped.flatten());
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}
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// Couldn't replace any lower priority frames. Need to wait for some mailboxes
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// to clear.
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Poll::Pending
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})
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.await
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}
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/// Flush one of the TX mailboxes.
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pub async fn flush(&self, mb: fdcan::Mailbox) {
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poll_fn(|cx| {
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T::state().tx_waker.register(cx.waker());
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let idx: u8 = mb.into();
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let idx = 1 << idx;
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if !T::regs().txbrp().read().trp(idx) {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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}
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/// Returns the next received message frame
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pub async fn read(&mut self) -> Result<RxFrame, BusError> {
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poll_fn(|cx| {
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T::state().err_waker.register(cx.waker());
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T::state().rx_waker.register(cx.waker());
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let mut buffer: [u8; 64] = [0; 64];
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if let Ok(rx) = self.can.receive0(&mut buffer) {
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// rx: fdcan::ReceiveOverrun<RxFrameInfo>
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// TODO: report overrun?
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// for now we just drop it
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let frame: RxFrame = RxFrame::new(
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rx.unwrap(),
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&buffer,
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#[cfg(feature = "time")]
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calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
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);
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return Poll::Ready(Ok(frame));
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} else if let Ok(rx) = self.can.receive1(&mut buffer) {
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// rx: fdcan::ReceiveOverrun<RxFrameInfo>
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// TODO: report overrun?
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// for now we just drop it
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let frame: RxFrame = RxFrame::new(
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rx.unwrap(),
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&buffer,
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#[cfg(feature = "time")]
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calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
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);
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return Poll::Ready(Ok(frame));
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} else if let Some(err) = curr_error::<T>() {
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||||
// TODO: this is probably wrong
|
||||
return Poll::Ready(Err(err));
|
||||
}
|
||||
Poll::Pending
|
||||
})
|
||||
.await
|
||||
}
|
||||
|
||||
/// Split instance into separate Tx(write) and Rx(read) portions
|
||||
pub fn split<'c>(&'c mut self) -> (FdcanTx<'c, 'd, T, M>, FdcanRx<'c, 'd, T, M>) {
|
||||
let (mut _control, tx, rx0, rx1) = self.can.split_by_ref();
|
||||
(
|
||||
FdcanTx { _control, tx },
|
||||
FdcanRx {
|
||||
rx0,
|
||||
rx1,
|
||||
ns_per_timer_tick: self.ns_per_timer_tick,
|
||||
},
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
/// FDCAN Tx only Instance
|
||||
pub struct FdcanTx<'c, 'd, T: Instance, M: fdcan::Transmit> {
|
||||
_control: &'c mut fdcan::FdCanControl<FdcanInstance<'d, T>, M>,
|
||||
tx: &'c mut fdcan::Tx<FdcanInstance<'d, T>, M>,
|
||||
}
|
||||
|
||||
impl<'c, 'd, T: Instance, M: fdcan::Transmit> FdcanTx<'c, 'd, T, M> {
|
||||
/// Queues the message to be sent but exerts backpressure. If a lower-priority
|
||||
/// frame is dropped from the mailbox, it is returned. If no lower-priority frames
|
||||
/// can be replaced, this call asynchronously waits for a frame to be successfully
|
||||
/// transmitted, then tries again.
|
||||
pub async fn write(&mut self, frame: &TxFrame) -> Option<TxFrame> {
|
||||
poll_fn(|cx| {
|
||||
T::state().tx_waker.register(cx.waker());
|
||||
if let Ok(dropped) = self
|
||||
.tx
|
||||
.transmit_preserve(frame.header, &frame.data.bytes, &mut |_, hdr, data32| {
|
||||
TxFrame::from_preserved(hdr, data32)
|
||||
})
|
||||
{
|
||||
return Poll::Ready(dropped.flatten());
|
||||
}
|
||||
|
||||
// Couldn't replace any lower priority frames. Need to wait for some mailboxes
|
||||
// to clear.
|
||||
Poll::Pending
|
||||
})
|
||||
.await
|
||||
}
|
||||
}
|
||||
|
||||
/// FDCAN Rx only Instance
|
||||
#[allow(dead_code)]
|
||||
pub struct FdcanRx<'c, 'd, T: Instance, M: fdcan::Receive> {
|
||||
rx0: &'c mut fdcan::Rx<FdcanInstance<'d, T>, M, fdcan::Fifo0>,
|
||||
rx1: &'c mut fdcan::Rx<FdcanInstance<'d, T>, M, fdcan::Fifo1>,
|
||||
ns_per_timer_tick: u64, // For FDCAN internal timer
|
||||
}
|
||||
|
||||
impl<'c, 'd, T: Instance, M: fdcan::Receive> FdcanRx<'c, 'd, T, M> {
|
||||
/// Returns the next received message frame
|
||||
pub async fn read(&mut self) -> Result<RxFrame, BusError> {
|
||||
poll_fn(|cx| {
|
||||
T::state().err_waker.register(cx.waker());
|
||||
T::state().rx_waker.register(cx.waker());
|
||||
|
||||
let mut buffer: [u8; 64] = [0; 64];
|
||||
if let Ok(rx) = self.rx0.receive(&mut buffer) {
|
||||
// rx: fdcan::ReceiveOverrun<RxFrameInfo>
|
||||
// TODO: report overrun?
|
||||
// for now we just drop it
|
||||
let frame: RxFrame = RxFrame::new(
|
||||
rx.unwrap(),
|
||||
&buffer,
|
||||
#[cfg(feature = "time")]
|
||||
calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
|
||||
);
|
||||
return Poll::Ready(Ok(frame));
|
||||
} else if let Ok(rx) = self.rx1.receive(&mut buffer) {
|
||||
// rx: fdcan::ReceiveOverrun<RxFrameInfo>
|
||||
// TODO: report overrun?
|
||||
// for now we just drop it
|
||||
let frame: RxFrame = RxFrame::new(
|
||||
rx.unwrap(),
|
||||
&buffer,
|
||||
#[cfg(feature = "time")]
|
||||
calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
|
||||
);
|
||||
return Poll::Ready(Ok(frame));
|
||||
} else if let Some(err) = curr_error::<T>() {
|
||||
// TODO: this is probably wrong
|
||||
return Poll::Ready(Err(err));
|
||||
}
|
||||
|
||||
Poll::Pending
|
||||
})
|
||||
.await
|
||||
}
|
||||
}
|
||||
impl<'d, T: Instance, M: FdcanOperatingMode> Deref for Fdcan<'d, T, M> {
|
||||
type Target = fdcan::FdCan<FdcanInstance<'d, T>, M>;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.can
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, M: FdcanOperatingMode> DerefMut for Fdcan<'d, T, M> {
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.can
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
|
||||
use embassy_sync::channel::Channel;
|
||||
use embassy_sync::waitqueue::AtomicWaker;
|
||||
|
||||
pub struct State {
|
||||
pub tx_waker: AtomicWaker,
|
||||
pub err_waker: AtomicWaker,
|
||||
pub rx_queue: Channel<CriticalSectionRawMutex, (u16, bxcan::Frame), 32>,
|
||||
pub rx_waker: AtomicWaker,
|
||||
}
|
||||
|
||||
impl State {
|
||||
|
|
@ -16,25 +579,122 @@ pub(crate) mod sealed {
|
|||
Self {
|
||||
tx_waker: AtomicWaker::new(),
|
||||
err_waker: AtomicWaker::new(),
|
||||
rx_queue: Channel::new(),
|
||||
rx_waker: AtomicWaker::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Instance {
|
||||
const REGISTERS: *mut fdcan::RegisterBlock;
|
||||
const MSG_RAM: *mut fdcan::message_ram::RegisterBlock;
|
||||
const MSG_RAM_OFFSET: usize;
|
||||
|
||||
fn regs() -> &'static crate::pac::can::Fdcan;
|
||||
fn state() -> &'static State;
|
||||
|
||||
#[cfg(not(stm32h7))]
|
||||
fn configure_msg_ram() {}
|
||||
|
||||
#[cfg(stm32h7)]
|
||||
fn configure_msg_ram() {
|
||||
let r = Self::regs();
|
||||
|
||||
use fdcan::message_ram::*;
|
||||
let mut offset_words = Self::MSG_RAM_OFFSET as u16;
|
||||
|
||||
// 11-bit filter
|
||||
r.sidfc().modify(|w| w.set_flssa(offset_words));
|
||||
offset_words += STANDARD_FILTER_MAX as u16;
|
||||
|
||||
// 29-bit filter
|
||||
r.xidfc().modify(|w| w.set_flesa(offset_words));
|
||||
offset_words += 2 * EXTENDED_FILTER_MAX as u16;
|
||||
|
||||
// Rx FIFO 0 and 1
|
||||
for i in 0..=1 {
|
||||
r.rxfc(i).modify(|w| {
|
||||
w.set_fsa(offset_words);
|
||||
w.set_fs(RX_FIFO_MAX);
|
||||
w.set_fwm(RX_FIFO_MAX);
|
||||
});
|
||||
offset_words += 18 * RX_FIFO_MAX as u16;
|
||||
}
|
||||
|
||||
// Rx buffer - see below
|
||||
// Tx event FIFO
|
||||
r.txefc().modify(|w| {
|
||||
w.set_efsa(offset_words);
|
||||
w.set_efs(TX_EVENT_MAX);
|
||||
w.set_efwm(TX_EVENT_MAX);
|
||||
});
|
||||
offset_words += 2 * TX_EVENT_MAX as u16;
|
||||
|
||||
// Tx buffers
|
||||
r.txbc().modify(|w| {
|
||||
w.set_tbsa(offset_words);
|
||||
w.set_tfqs(TX_FIFO_MAX);
|
||||
});
|
||||
offset_words += 18 * TX_FIFO_MAX as u16;
|
||||
|
||||
// Rx Buffer - not used
|
||||
r.rxbc().modify(|w| {
|
||||
w.set_rbsa(offset_words);
|
||||
});
|
||||
|
||||
// TX event FIFO?
|
||||
// Trigger memory?
|
||||
|
||||
// Set the element sizes to 16 bytes
|
||||
r.rxesc().modify(|w| {
|
||||
w.set_rbds(0b111);
|
||||
for i in 0..=1 {
|
||||
w.set_fds(i, 0b111);
|
||||
}
|
||||
});
|
||||
r.txesc().modify(|w| {
|
||||
w.set_tbds(0b111);
|
||||
})
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Interruptable FDCAN instance.
|
||||
pub trait InterruptableInstance {}
|
||||
/// FDCAN instance.
|
||||
pub trait Instance: sealed::Instance + InterruptableInstance + 'static {}
|
||||
/// Trait for FDCAN interrupt channel 0
|
||||
pub trait IT0Instance {
|
||||
/// Type for FDCAN interrupt channel 0
|
||||
type IT0Interrupt: crate::interrupt::typelevel::Interrupt;
|
||||
}
|
||||
|
||||
foreach_peripheral!(
|
||||
(can, $inst:ident) => {
|
||||
/// Trait for FDCAN interrupt channel 1
|
||||
pub trait IT1Instance {
|
||||
/// Type for FDCAN interrupt channel 1
|
||||
type IT1Interrupt: crate::interrupt::typelevel::Interrupt;
|
||||
}
|
||||
|
||||
/// InterruptableInstance trait
|
||||
pub trait InterruptableInstance: IT0Instance + IT1Instance {}
|
||||
/// Instance trait
|
||||
pub trait Instance: sealed::Instance + RccPeripheral + InterruptableInstance + 'static {}
|
||||
/// Fdcan Instance struct
|
||||
pub struct FdcanInstance<'a, T>(PeripheralRef<'a, T>);
|
||||
|
||||
unsafe impl<'d, T: Instance> fdcan::message_ram::Instance for FdcanInstance<'d, T> {
|
||||
const MSG_RAM: *mut RegisterBlock = T::MSG_RAM;
|
||||
}
|
||||
|
||||
unsafe impl<'d, T: Instance> fdcan::Instance for FdcanInstance<'d, T>
|
||||
where
|
||||
FdcanInstance<'d, T>: fdcan::message_ram::Instance,
|
||||
{
|
||||
const REGISTERS: *mut fdcan::RegisterBlock = T::REGISTERS;
|
||||
}
|
||||
|
||||
macro_rules! impl_fdcan {
|
||||
($inst:ident, $msg_ram_inst:ident, $msg_ram_offset:literal) => {
|
||||
impl sealed::Instance for peripherals::$inst {
|
||||
const REGISTERS: *mut fdcan::RegisterBlock = crate::pac::$inst.as_ptr() as *mut _;
|
||||
const MSG_RAM: *mut fdcan::message_ram::RegisterBlock = crate::pac::$msg_ram_inst.as_ptr() as *mut _;
|
||||
const MSG_RAM_OFFSET: usize = $msg_ram_offset;
|
||||
|
||||
fn regs() -> &'static crate::pac::can::Fdcan {
|
||||
&crate::pac::$inst
|
||||
}
|
||||
|
|
@ -47,8 +707,40 @@ foreach_peripheral!(
|
|||
|
||||
impl Instance for peripherals::$inst {}
|
||||
|
||||
foreach_interrupt!(
|
||||
($inst,can,FDCAN,IT0,$irq:ident) => {
|
||||
impl IT0Instance for peripherals::$inst {
|
||||
type IT0Interrupt = crate::interrupt::typelevel::$irq;
|
||||
}
|
||||
};
|
||||
($inst,can,FDCAN,IT1,$irq:ident) => {
|
||||
impl IT1Instance for peripherals::$inst {
|
||||
type IT1Interrupt = crate::interrupt::typelevel::$irq;
|
||||
}
|
||||
};
|
||||
);
|
||||
|
||||
impl InterruptableInstance for peripherals::$inst {}
|
||||
};
|
||||
|
||||
($inst:ident, $msg_ram_inst:ident) => {
|
||||
impl_fdcan!($inst, $msg_ram_inst, 0);
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(not(stm32h7))]
|
||||
foreach_peripheral!(
|
||||
(can, FDCAN) => { impl_fdcan!(FDCAN, FDCANRAM); };
|
||||
(can, FDCAN1) => { impl_fdcan!(FDCAN1, FDCANRAM1); };
|
||||
(can, FDCAN2) => { impl_fdcan!(FDCAN2, FDCANRAM2); };
|
||||
(can, FDCAN3) => { impl_fdcan!(FDCAN3, FDCANRAM3); };
|
||||
);
|
||||
|
||||
#[cfg(stm32h7)]
|
||||
foreach_peripheral!(
|
||||
(can, FDCAN1) => { impl_fdcan!(FDCAN1, FDCANRAM, 0x0000); };
|
||||
(can, FDCAN2) => { impl_fdcan!(FDCAN2, FDCANRAM, 0x0C00); };
|
||||
(can, FDCAN3) => { impl_fdcan!(FDCAN3, FDCANRAM, 0x1800); };
|
||||
);
|
||||
|
||||
pin_trait!(RxPin, Instance);
|
||||
|
|
|
|||
|
|
@ -6,10 +6,9 @@ use crate::pac::pwr::vals::Vos;
|
|||
pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
|
||||
#[cfg(stm32h7)]
|
||||
pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
|
||||
pub use crate::pac::rcc::vals::Fdcansel as FdCanClockSource;
|
||||
pub use crate::pac::rcc::vals::{
|
||||
Ckpersel as PerClockSource, Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
|
||||
Pllsrc as PllSource, Sw as Sysclk,
|
||||
Ckpersel as PerClockSource, Fdcansel as FdCanClockSource, Hsidiv as HSIPrescaler, Plldiv as PllDiv,
|
||||
Pllm as PllPreDiv, Plln as PllMul, Pllsrc as PllSource, Sw as Sysclk,
|
||||
};
|
||||
use crate::pac::rcc::vals::{Ckpersel, Pllrge, Pllvcosel, Timpre};
|
||||
use crate::pac::{FLASH, PWR, RCC};
|
||||
|
|
@ -591,7 +590,7 @@ pub(crate) unsafe fn init(config: Config) {
|
|||
RCC.ccipr5().modify(|w| {
|
||||
w.set_ckpersel(config.per_clock_source);
|
||||
w.set_adcdacsel(config.adc_clock_source);
|
||||
w.set_fdcan1sel(config.fdcan_clock_source)
|
||||
w.set_fdcan12sel(config.fdcan_clock_source)
|
||||
});
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue