nrf/buffered_uart: refactor so rx/tx halves are independent.
This commit is contained in:
Dario Nieuwenhuis
parent
c2e429205d
commit
1f17fdf84e
4 changed files with 269 additions and 231 deletions
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@ -1,6 +1,6 @@
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//! Atomic reusable ringbuffer.
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use core::slice;
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use core::sync::atomic::{AtomicPtr, AtomicUsize, Ordering};
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use core::{ptr, slice};
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/// Atomic reusable ringbuffer
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///
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@ -73,6 +73,7 @@ impl RingBuffer {
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pub unsafe fn deinit(&self) {
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// Ordering: it's OK to use `Relaxed` because this is not called
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// concurrently with other methods.
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self.buf.store(ptr::null_mut(), Ordering::Relaxed);
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self.len.store(0, Ordering::Relaxed);
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self.start.store(0, Ordering::Relaxed);
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self.end.store(0, Ordering::Relaxed);
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@ -82,20 +83,46 @@ impl RingBuffer {
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///
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/// # Safety
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///
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/// Only one reader can exist at a time.
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/// - Only one reader can exist at a time.
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/// - Ringbuffer must be initialized.
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pub unsafe fn reader(&self) -> Reader<'_> {
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Reader(self)
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}
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/// Try creating a reader, fails if not initialized.
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///
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/// # Safety
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///
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/// Only one reader can exist at a time.
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pub unsafe fn try_reader(&self) -> Option<Reader<'_>> {
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if self.buf.load(Ordering::Relaxed).is_null() {
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return None;
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}
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Some(Reader(self))
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}
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/// Create a writer.
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///
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/// # Safety
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///
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/// Only one writer can exist at a time.
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/// - Only one writer can exist at a time.
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/// - Ringbuffer must be initialized.
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pub unsafe fn writer(&self) -> Writer<'_> {
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Writer(self)
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}
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/// Try creating a writer, fails if not initialized.
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///
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/// # Safety
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///
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/// Only one writer can exist at a time.
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pub unsafe fn try_writer(&self) -> Option<Writer<'_>> {
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if self.buf.load(Ordering::Relaxed).is_null() {
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return None;
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}
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Some(Writer(self))
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}
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/// Return length of buffer.
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pub fn len(&self) -> usize {
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self.len.load(Ordering::Relaxed)
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@ -22,13 +22,13 @@ use embassy_sync::waitqueue::AtomicWaker;
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pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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use crate::gpio::sealed::Pin;
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use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
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use crate::gpio::{AnyPin, Pin as GpioPin, PselBits};
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use crate::interrupt::typelevel::Interrupt;
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use crate::ppi::{
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self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
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};
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use crate::timer::{Instance as TimerInstance, Timer};
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use crate::uarte::{apply_workaround_for_enable_anomaly, Config, Instance as UarteInstance};
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use crate::uarte::{apply_workaround_for_enable_anomaly, drop_tx_rx, Config, Instance as UarteInstance};
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use crate::{interrupt, pac, Peripheral};
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mod sealed {
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@ -86,126 +86,128 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
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let r = U::regs();
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let s = U::buffered_state();
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let buf_len = s.rx_buf.len();
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let half_len = buf_len / 2;
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let mut tx = unsafe { s.tx_buf.reader() };
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let mut rx = unsafe { s.rx_buf.writer() };
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if let Some(mut rx) = unsafe { s.rx_buf.try_writer() } {
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let buf_len = s.rx_buf.len();
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let half_len = buf_len / 2;
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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let errs = r.errorsrc.read();
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r.errorsrc.write(|w| unsafe { w.bits(errs.bits()) });
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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let errs = r.errorsrc.read();
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r.errorsrc.write(|w| unsafe { w.bits(errs.bits()) });
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if errs.overrun().bit() {
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panic!("BufferedUarte overrun");
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if errs.overrun().bit() {
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panic!("BufferedUarte overrun");
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}
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}
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}
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// Received some bytes, wake task.
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if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
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r.intenclr.write(|w| w.rxdrdy().clear());
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r.events_rxdrdy.reset();
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s.rx_waker.wake();
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}
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// Received some bytes, wake task.
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if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
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r.intenclr.write(|w| w.rxdrdy().clear());
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r.events_rxdrdy.reset();
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s.rx_waker.wake();
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}
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if r.events_endrx.read().bits() != 0 {
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//trace!(" irq_rx: endrx");
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r.events_endrx.reset();
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if r.events_endrx.read().bits() != 0 {
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//trace!(" irq_rx: endrx");
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r.events_endrx.reset();
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let val = s.rx_ended_count.load(Ordering::Relaxed);
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s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
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}
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let val = s.rx_ended_count.load(Ordering::Relaxed);
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s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
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}
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if r.events_rxstarted.read().bits() != 0 || !s.rx_started.load(Ordering::Relaxed) {
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//trace!(" irq_rx: rxstarted");
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let (ptr, len) = rx.push_buf();
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if len >= half_len {
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r.events_rxstarted.reset();
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if r.events_rxstarted.read().bits() != 0 || !s.rx_started.load(Ordering::Relaxed) {
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//trace!(" irq_rx: rxstarted");
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let (ptr, len) = rx.push_buf();
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if len >= half_len {
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r.events_rxstarted.reset();
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//trace!(" irq_rx: starting second {:?}", half_len);
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//trace!(" irq_rx: starting second {:?}", half_len);
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// Set up the DMA read
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
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// Set up the DMA read
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
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let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
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let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
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// Enable endrx -> startrx PPI channel.
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// From this point on, if endrx happens, startrx is automatically fired.
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ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
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// Enable endrx -> startrx PPI channel.
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// From this point on, if endrx happens, startrx is automatically fired.
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ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
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// It is possible that endrx happened BEFORE enabling the PPI. In this case
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// the PPI channel doesn't trigger, and we'd hang. We have to detect this
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// and manually start.
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// It is possible that endrx happened BEFORE enabling the PPI. In this case
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// the PPI channel doesn't trigger, and we'd hang. We have to detect this
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// and manually start.
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// check again in case endrx has happened between the last check and now.
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if r.events_endrx.read().bits() != 0 {
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//trace!(" irq_rx: endrx");
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r.events_endrx.reset();
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// check again in case endrx has happened between the last check and now.
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if r.events_endrx.read().bits() != 0 {
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//trace!(" irq_rx: endrx");
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r.events_endrx.reset();
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let val = s.rx_ended_count.load(Ordering::Relaxed);
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s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
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let val = s.rx_ended_count.load(Ordering::Relaxed);
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s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
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}
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let rx_ended = s.rx_ended_count.load(Ordering::Relaxed);
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let rx_started = s.rx_started_count.load(Ordering::Relaxed);
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// If we started the same amount of transfers as ended, the last rxend has
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// already occured.
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let rxend_happened = rx_started == rx_ended;
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// Check if the PPI channel is still enabled. The PPI channel disables itself
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// when it fires, so if it's still enabled it hasn't fired.
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let ppi_ch_enabled = ppi::regs().chen.read().bits() & (1 << chn) != 0;
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// if rxend happened, and the ppi channel hasn't fired yet, the rxend got missed.
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// this condition also naturally matches if `!started`, needed to kickstart the DMA.
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if rxend_happened && ppi_ch_enabled {
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//trace!("manually starting.");
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// disable the ppi ch, it's of no use anymore.
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ppi::regs().chenclr.write(|w| unsafe { w.bits(1 << chn) });
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// manually start
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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}
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rx.push_done(half_len);
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s.rx_started_count.store(rx_started.wrapping_add(1), Ordering::Relaxed);
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s.rx_started.store(true, Ordering::Relaxed);
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} else {
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//trace!(" irq_rx: rxstarted no buf");
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r.intenclr.write(|w| w.rxstarted().clear());
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}
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let rx_ended = s.rx_ended_count.load(Ordering::Relaxed);
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let rx_started = s.rx_started_count.load(Ordering::Relaxed);
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// If we started the same amount of transfers as ended, the last rxend has
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// already occured.
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let rxend_happened = rx_started == rx_ended;
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// Check if the PPI channel is still enabled. The PPI channel disables itself
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// when it fires, so if it's still enabled it hasn't fired.
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let ppi_ch_enabled = ppi::regs().chen.read().bits() & (1 << chn) != 0;
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// if rxend happened, and the ppi channel hasn't fired yet, the rxend got missed.
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// this condition also naturally matches if `!started`, needed to kickstart the DMA.
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if rxend_happened && ppi_ch_enabled {
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//trace!("manually starting.");
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// disable the ppi ch, it's of no use anymore.
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ppi::regs().chenclr.write(|w| unsafe { w.bits(1 << chn) });
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// manually start
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r.tasks_startrx.write(|w| unsafe { w.bits(1) });
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}
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rx.push_done(half_len);
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s.rx_started_count.store(rx_started.wrapping_add(1), Ordering::Relaxed);
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s.rx_started.store(true, Ordering::Relaxed);
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} else {
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//trace!(" irq_rx: rxstarted no buf");
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r.intenclr.write(|w| w.rxstarted().clear());
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}
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}
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// =============================
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// TX end
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if r.events_endtx.read().bits() != 0 {
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r.events_endtx.reset();
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if let Some(mut tx) = unsafe { s.tx_buf.try_reader() } {
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// TX end
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if r.events_endtx.read().bits() != 0 {
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r.events_endtx.reset();
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let n = s.tx_count.load(Ordering::Relaxed);
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//trace!(" irq_tx: endtx {:?}", n);
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tx.pop_done(n);
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s.tx_waker.wake();
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s.tx_count.store(0, Ordering::Relaxed);
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}
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let n = s.tx_count.load(Ordering::Relaxed);
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//trace!(" irq_tx: endtx {:?}", n);
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tx.pop_done(n);
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s.tx_waker.wake();
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s.tx_count.store(0, Ordering::Relaxed);
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}
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// If not TXing, start.
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if s.tx_count.load(Ordering::Relaxed) == 0 {
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let (ptr, len) = tx.pop_buf();
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if len != 0 {
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//trace!(" irq_tx: starting {:?}", len);
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s.tx_count.store(len, Ordering::Relaxed);
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// If not TXing, start.
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if s.tx_count.load(Ordering::Relaxed) == 0 {
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let (ptr, len) = tx.pop_buf();
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if len != 0 {
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//trace!(" irq_tx: starting {:?}", len);
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s.tx_count.store(len, Ordering::Relaxed);
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// Set up the DMA write
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Set up the DMA write
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Start UARTE Transmit transaction
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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// Start UARTE Transmit transaction
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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}
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}
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}
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@ -215,11 +217,8 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
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/// Buffered UARTE driver.
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pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
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_peri: PeripheralRef<'d, U>,
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timer: Timer<'d, T>,
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_ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
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_ppi_group: PpiGroup<'d, AnyGroup>,
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tx: BufferedUarteTx<'d, U>,
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rx: BufferedUarteRx<'d, U, T>,
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}
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impl<'d, U: UarteInstance, T: TimerInstance> Unpin for BufferedUarte<'d, U, T> {}
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@ -404,17 +403,21 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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U::Interrupt::pend();
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unsafe { U::Interrupt::enable() };
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Self {
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_peri: peri,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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_ppi_group: ppi_group,
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}
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}
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let s = U::state();
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s.tx_rx_refcount.store(2, Ordering::Relaxed);
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fn pend_irq() {
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U::Interrupt::pend()
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Self {
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tx: BufferedUarteTx {
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_peri: unsafe { peri.clone_unchecked() },
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},
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rx: BufferedUarteRx {
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_peri: peri,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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_ppi_group: ppi_group,
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},
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}
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}
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/// Adjust the baud rate to the provided value.
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@ -426,19 +429,52 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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/// Split the UART in reader and writer parts.
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///
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/// This allows reading and writing concurrently from independent tasks.
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pub fn split(&mut self) -> (BufferedUarteRx<'_, U, T>, BufferedUarteTx<'_, U, T>) {
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(BufferedUarteRx { inner: self }, BufferedUarteTx { inner: self })
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pub fn split(self) -> (BufferedUarteRx<'d, U, T>, BufferedUarteTx<'d, U>) {
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(self.rx, self.tx)
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}
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async fn inner_read(&self, buf: &mut [u8]) -> Result<usize, Error> {
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let data = self.inner_fill_buf().await?;
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let n = data.len().min(buf.len());
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buf[..n].copy_from_slice(&data[..n]);
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self.inner_consume(n);
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Ok(n)
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/// Split the UART in reader and writer parts, by reference.
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///
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/// The returned halves borrow from `self`, so you can drop them and go back to using
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/// the "un-split" `self`. This allows temporarily splitting the UART.
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pub fn split_by_ref(&mut self) -> (&mut BufferedUarteRx<'d, U, T>, &mut BufferedUarteTx<'d, U>) {
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(&mut self.rx, &mut self.tx)
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}
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async fn inner_write<'a>(&'a self, buf: &'a [u8]) -> Result<usize, Error> {
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/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
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pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
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self.rx.read(buf).await
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}
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/// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
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pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
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self.rx.fill_buf().await
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}
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/// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
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pub fn consume(&mut self, amt: usize) {
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self.rx.consume(amt)
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}
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/// Write a buffer into this writer, returning how many bytes were written.
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pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
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self.tx.write(buf).await
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}
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/// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
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pub async fn flush(&mut self) -> Result<(), Error> {
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self.tx.flush().await
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}
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}
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/// Reader part of the buffered UARTE driver.
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pub struct BufferedUarteTx<'d, U: UarteInstance> {
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_peri: PeripheralRef<'d, U>,
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}
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impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
|
||||
/// Write a buffer into this writer, returning how many bytes were written.
|
||||
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
|
||||
poll_fn(move |cx| {
|
||||
//trace!("poll_write: {:?}", buf.len());
|
||||
let s = U::buffered_state();
|
||||
|
|
@ -458,14 +494,15 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
|
|||
//trace!("poll_write: queued {:?}", n);
|
||||
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
Self::pend_irq();
|
||||
U::Interrupt::pend();
|
||||
|
||||
Poll::Ready(Ok(n))
|
||||
})
|
||||
.await
|
||||
}
|
||||
|
||||
async fn inner_flush<'a>(&'a self) -> Result<(), Error> {
|
||||
/// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
|
||||
pub async fn flush(&mut self) -> Result<(), Error> {
|
||||
poll_fn(move |cx| {
|
||||
//trace!("poll_flush");
|
||||
let s = U::buffered_state();
|
||||
|
|
@ -479,8 +516,51 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
|
|||
})
|
||||
.await
|
||||
}
|
||||
}
|
||||
|
||||
async fn inner_fill_buf<'a>(&'a self) -> Result<&'a [u8], Error> {
|
||||
impl<'a, U: UarteInstance> Drop for BufferedUarteTx<'a, U> {
|
||||
fn drop(&mut self) {
|
||||
let r = U::regs();
|
||||
|
||||
r.intenclr.write(|w| {
|
||||
w.txdrdy().set_bit();
|
||||
w.txstarted().set_bit();
|
||||
w.txstopped().set_bit();
|
||||
w
|
||||
});
|
||||
r.events_txstopped.reset();
|
||||
r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
|
||||
while r.events_txstopped.read().bits() == 0 {}
|
||||
|
||||
let s = U::buffered_state();
|
||||
unsafe { s.tx_buf.deinit() }
|
||||
|
||||
let s = U::state();
|
||||
drop_tx_rx(r, s);
|
||||
}
|
||||
}
|
||||
|
||||
/// Reader part of the buffered UARTE driver.
|
||||
pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
|
||||
_peri: PeripheralRef<'d, U>,
|
||||
timer: Timer<'d, T>,
|
||||
_ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
|
||||
_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
|
||||
_ppi_group: PpiGroup<'d, AnyGroup>,
|
||||
}
|
||||
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
|
||||
/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
|
||||
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
|
||||
let data = self.fill_buf().await?;
|
||||
let n = data.len().min(buf.len());
|
||||
buf[..n].copy_from_slice(&data[..n]);
|
||||
self.consume(n);
|
||||
Ok(n)
|
||||
}
|
||||
|
||||
/// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
|
||||
pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
|
||||
poll_fn(move |cx| {
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
//trace!("poll_read");
|
||||
|
|
@ -532,7 +612,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
|
|||
.await
|
||||
}
|
||||
|
||||
fn inner_consume(&self, amt: usize) {
|
||||
/// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
|
||||
pub fn consume(&mut self, amt: usize) {
|
||||
if amt == 0 {
|
||||
return;
|
||||
}
|
||||
|
|
@ -542,69 +623,31 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
|
|||
rx.pop_done(amt);
|
||||
U::regs().intenset.write(|w| w.rxstarted().set());
|
||||
}
|
||||
|
||||
/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
|
||||
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
|
||||
self.inner_read(buf).await
|
||||
}
|
||||
|
||||
/// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
|
||||
pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
|
||||
self.inner_fill_buf().await
|
||||
}
|
||||
|
||||
/// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
|
||||
pub fn consume(&mut self, amt: usize) {
|
||||
self.inner_consume(amt)
|
||||
}
|
||||
|
||||
/// Write a buffer into this writer, returning how many bytes were written.
|
||||
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
|
||||
self.inner_write(buf).await
|
||||
}
|
||||
|
||||
/// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
|
||||
pub async fn flush(&mut self) -> Result<(), Error> {
|
||||
self.inner_flush().await
|
||||
}
|
||||
}
|
||||
|
||||
/// Reader part of the buffered UARTE driver.
|
||||
pub struct BufferedUarteTx<'d, U: UarteInstance, T: TimerInstance> {
|
||||
inner: &'d BufferedUarte<'d, U, T>,
|
||||
}
|
||||
impl<'a, U: UarteInstance, T: TimerInstance> Drop for BufferedUarteRx<'a, U, T> {
|
||||
fn drop(&mut self) {
|
||||
self._ppi_group.disable_all();
|
||||
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteTx<'d, U, T> {
|
||||
/// Write a buffer into this writer, returning how many bytes were written.
|
||||
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
|
||||
self.inner.inner_write(buf).await
|
||||
}
|
||||
let r = U::regs();
|
||||
|
||||
/// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
|
||||
pub async fn flush(&mut self) -> Result<(), Error> {
|
||||
self.inner.inner_flush().await
|
||||
}
|
||||
}
|
||||
self.timer.stop();
|
||||
|
||||
/// Writer part of the buffered UARTE driver.
|
||||
pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
|
||||
inner: &'d BufferedUarte<'d, U, T>,
|
||||
}
|
||||
r.intenclr.write(|w| {
|
||||
w.rxdrdy().set_bit();
|
||||
w.rxstarted().set_bit();
|
||||
w.rxto().set_bit();
|
||||
w
|
||||
});
|
||||
r.events_rxto.reset();
|
||||
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
||||
while r.events_rxto.read().bits() == 0 {}
|
||||
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
|
||||
/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
|
||||
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
|
||||
self.inner.inner_read(buf).await
|
||||
}
|
||||
let s = U::buffered_state();
|
||||
unsafe { s.rx_buf.deinit() }
|
||||
|
||||
/// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
|
||||
pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
|
||||
self.inner.inner_fill_buf().await
|
||||
}
|
||||
|
||||
/// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
|
||||
pub fn consume(&mut self, amt: usize) {
|
||||
self.inner.inner_consume(amt)
|
||||
let s = U::state();
|
||||
drop_tx_rx(r, s);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -625,91 +668,59 @@ mod _embedded_io {
|
|||
type Error = Error;
|
||||
}
|
||||
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteTx<'d, U, T> {
|
||||
impl<'d, U: UarteInstance> embedded_io_async::ErrorType for BufferedUarteTx<'d, U> {
|
||||
type Error = Error;
|
||||
}
|
||||
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarte<'d, U, T> {
|
||||
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
||||
self.inner_read(buf).await
|
||||
self.read(buf).await
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarteRx<'d, U, T> {
|
||||
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
||||
self.inner.inner_read(buf).await
|
||||
self.read(buf).await
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarte<'d, U, T> {
|
||||
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
||||
self.inner_fill_buf().await
|
||||
self.fill_buf().await
|
||||
}
|
||||
|
||||
fn consume(&mut self, amt: usize) {
|
||||
self.inner_consume(amt)
|
||||
self.consume(amt)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarteRx<'d, U, T> {
|
||||
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
||||
self.inner.inner_fill_buf().await
|
||||
self.fill_buf().await
|
||||
}
|
||||
|
||||
fn consume(&mut self, amt: usize) {
|
||||
self.inner.inner_consume(amt)
|
||||
self.consume(amt)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarte<'d, U, T> {
|
||||
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
||||
self.inner_write(buf).await
|
||||
self.write(buf).await
|
||||
}
|
||||
|
||||
async fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
self.inner_flush().await
|
||||
self.flush().await
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarteTx<'d, U, T> {
|
||||
impl<'d: 'd, U: UarteInstance> embedded_io_async::Write for BufferedUarteTx<'d, U> {
|
||||
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
||||
self.inner.inner_write(buf).await
|
||||
self.write(buf).await
|
||||
}
|
||||
|
||||
async fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
self.inner.inner_flush().await
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, U: UarteInstance, T: TimerInstance> Drop for BufferedUarte<'a, U, T> {
|
||||
fn drop(&mut self) {
|
||||
self._ppi_group.disable_all();
|
||||
|
||||
let r = U::regs();
|
||||
|
||||
self.timer.stop();
|
||||
|
||||
r.inten.reset();
|
||||
r.events_rxto.reset();
|
||||
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
||||
r.events_txstopped.reset();
|
||||
r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
|
||||
|
||||
while r.events_txstopped.read().bits() == 0 {}
|
||||
while r.events_rxto.read().bits() == 0 {}
|
||||
|
||||
r.enable.write(|w| w.enable().disabled());
|
||||
|
||||
gpio::deconfigure_pin(r.psel.rxd.read().bits());
|
||||
gpio::deconfigure_pin(r.psel.txd.read().bits());
|
||||
gpio::deconfigure_pin(r.psel.rts.read().bits());
|
||||
gpio::deconfigure_pin(r.psel.cts.read().bits());
|
||||
|
||||
let s = U::buffered_state();
|
||||
unsafe {
|
||||
s.rx_buf.deinit();
|
||||
s.tx_buf.deinit();
|
||||
self.flush().await
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
|
|||
let mut tx_buffer = [0u8; 1024];
|
||||
let mut rx_buffer = [0u8; 1024];
|
||||
|
||||
let mut u = BufferedUarte::new(
|
||||
let u = BufferedUarte::new(
|
||||
p.UARTE0,
|
||||
p.TIMER0,
|
||||
p.PPI_CH0,
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
|
|||
let mut tx_buffer = [0u8; 1024];
|
||||
let mut rx_buffer = [0u8; 1024];
|
||||
|
||||
let mut u = BufferedUarte::new(
|
||||
let u = BufferedUarte::new(
|
||||
p.UARTE0,
|
||||
p.TIMER0,
|
||||
p.PPI_CH0,
|
||||
|
|
|
|||
Loading…
Reference in a new issue