From 34713b4910d2d94a632ff8e3a161ab982fdab2ba Mon Sep 17 00:00:00 2001
From: Adin Ackerman <adinackerman@gmail.com>
Date: Tue, 2 Jan 2024 16:03:23 -0800
Subject: [PATCH 1/2] fix g0 being left out of some clock controls
---
embassy-stm32/build.rs | 4 ++--
embassy-stm32/src/rcc/g0.rs | 27 +++++++++++++++++++++++----
embassy-stm32/src/rcc/mod.rs | 10 +++++-----
3 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index de03827e9..ef152acd1 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -505,7 +505,7 @@ fn main() {
(TokenStream::new(), TokenStream::new())
};
- let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g4", "l4"])
+ let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g0", "g4", "l4"])
.contains(rcc_registers.version);
let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
// restrict mux implementation to supported versions
@@ -534,7 +534,7 @@ fn main() {
let variant_name = format_ident!("{}", v.name);
let clock_name = format_ident!("{}", v.name.to_ascii_lowercase());
- if v.name.starts_with("HCLK") || v.name.starts_with("PCLK") || v.name == "SYS" {
+ if v.name.starts_with("HCLK") || v.name.starts_with("PCLK") || v.name == "SYS" {
quote! {
#enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name },
}
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index d3367b049..7f62031e5 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -95,7 +95,7 @@ impl Default for Config {
}
impl PllConfig {
- pub(crate) fn init(self) -> Hertz {
+ pub(crate) fn init(self) -> (Hertz, Option<Hertz>, Option<Hertz>) {
let (src, input_freq) = match self.source {
PllSource::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
PllSource::HSE(freq, _) => (vals::Pllsrc::HSE, freq),
@@ -118,6 +118,9 @@ impl PllConfig {
// > Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.
debug_assert!(r_freq.0 <= 64_000_000);
+ let q_freq = self.q.map(|q| n_freq / q);
+ let p_freq = self.p.map(|p| n_freq / p);
+
// RM0454 ยง 5.2.3:
// > To modify the PLL configuration, proceed as follows:
// > 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
@@ -172,11 +175,14 @@ impl PllConfig {
w.set_pllpen(self.p.is_some());
});
- r_freq
+ (r_freq, q_freq, p_freq)
}
}
pub(crate) unsafe fn init(config: Config) {
+ let mut pll1_q_freq = None;
+ let mut pll1_p_freq = None;
+
let (sys_clk, sw) = match config.mux {
ClockSrc::HSI(div) => {
// Enable HSI
@@ -199,8 +205,12 @@ pub(crate) unsafe fn init(config: Config) {
(freq, Sw::HSE)
}
ClockSrc::PLL(pll) => {
- let freq = pll.init();
- (freq, Sw::PLL1_R)
+ let (r_freq, q_freq, p_freq) = pll.init();
+
+ pll1_q_freq = q_freq;
+ pll1_p_freq = p_freq;
+
+ (r_freq, Sw::PLL1_R)
}
ClockSrc::LSI => {
// Enable LSI
@@ -286,12 +296,21 @@ pub(crate) unsafe fn init(config: Config) {
}
let rtc = config.ls.init();
+ let lse_freq = config.ls.lse.map(|lse| lse.frequency);
+
+ let hsi_freq = (sw == Sw::HSI).then_some(HSI_FREQ);
+ let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
set_freqs(Clocks {
sys: sys_clk,
hclk1: ahb_freq,
pclk1: apb_freq,
pclk1_tim: apb_tim_freq,
+ hsi: hsi_freq,
+ lse: lse_freq,
+ lsi: lsi_freq,
+ pll1_q: pll1_q_freq,
+ pll1_p: pll1_p_freq,
rtc,
});
}
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 04a51110c..c4bee4c95 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -121,9 +121,9 @@ pub struct Clocks {
#[cfg(rcc_l4)]
pub pllsai2_p: Option<Hertz>,
- #[cfg(any(stm32g4, rcc_l4))]
+ #[cfg(any(stm32g0, stm32g4, rcc_l4))]
pub pll1_p: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7, stm32f2, stm32f4, stm32f7, rcc_l4, stm32g4))]
+ #[cfg(any(stm32h5, stm32h7, stm32f2, stm32f4, stm32f7, rcc_l4, stm32g0, stm32g4))]
pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>,
@@ -160,16 +160,16 @@ pub struct Clocks {
pub rtc: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
+ #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub hsi: Option<Hertz>,
#[cfg(stm32h5)]
pub hsi48: Option<Hertz>,
- #[cfg(stm32h5)]
+ #[cfg(any(stm32g0, stm32h5))]
pub lsi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub csi: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0))]
+ #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub lse: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7, stm32g4))]
pub hse: Option<Hertz>,
From d372cba266c7a110f314e74dfee589987b892383 Mon Sep 17 00:00:00 2001
From: Adin Ackerman <adinackerman@gmail.com>
Date: Tue, 2 Jan 2024 16:25:51 -0800
Subject: [PATCH 2/2] additional chip variants required more clocks
---
embassy-stm32/src/rcc/g0.rs | 5 +++++
embassy-stm32/src/rcc/mod.rs | 6 ++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 7f62031e5..aedc95bf3 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -299,7 +299,9 @@ pub(crate) unsafe fn init(config: Config) {
let lse_freq = config.ls.lse.map(|lse| lse.frequency);
let hsi_freq = (sw == Sw::HSI).then_some(HSI_FREQ);
+ let hsi_div_8_freq = hsi_freq.map(|f| f / 8u32);
let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
+ let hse_freq = (sw == Sw::HSE).then_some(sys_clk);
set_freqs(Clocks {
sys: sys_clk,
@@ -307,6 +309,9 @@ pub(crate) unsafe fn init(config: Config) {
pclk1: apb_freq,
pclk1_tim: apb_tim_freq,
hsi: hsi_freq,
+ hsi48: None,
+ hsi_div_8: hsi_div_8_freq,
+ hse: hse_freq,
lse: lse_freq,
lsi: lsi_freq,
pll1_q: pll1_q_freq,
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index c4bee4c95..240ffc6d2 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -162,8 +162,10 @@ pub struct Clocks {
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub hsi: Option<Hertz>,
- #[cfg(stm32h5)]
+ #[cfg(any(stm32h5, stm32g0))]
pub hsi48: Option<Hertz>,
+ #[cfg(stm32g0)]
+ pub hsi_div_8: Option<Hertz>,
#[cfg(any(stm32g0, stm32h5))]
pub lsi: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
@@ -171,7 +173,7 @@ pub struct Clocks {
#[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
pub lse: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7, stm32g4))]
+ #[cfg(any(stm32h5, stm32h7, stm32g0, stm32g4))]
pub hse: Option<Hertz>,
#[cfg(stm32h5)]