fix(stm32): Align FMC with new versions from stm32-data
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1 changed files with 7 additions and 3 deletions
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@ -27,9 +27,13 @@ where
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}
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fn memory_controller_enable(&mut self) {
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// The FMCEN bit of the FMC_BCR2..4 registers is don’t
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// care. It is only enabled through the FMC_BCR1 register.
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unsafe { T::regs().bcr1().modify(|r| r.set_fmcen(true)) };
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// fmc v1 and v2 does not have the fmcen bit
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// fsmc v1 and v2 does not have the fmcen bit
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// This is a "not" because it is expected that all future versions have this bit
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#[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x3, fsmc_v2x1)))]
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unsafe {
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T::regs().bcr1().modify(|r| r.set_fmcen(true))
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};
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}
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fn source_clock_hz(&self) -> u32 {
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