diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index b6641d71d..6137e3c02 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -59,7 +59,7 @@ sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ff45aa382efb704dd2275dd69e71af73343f149d" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9f45b0c48cc3de71ec6a66fe7e871b21aef0940c" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -77,7 +77,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ff45aa382efb704dd2275dd69e71af73343f149d", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9f45b0c48cc3de71ec6a66fe7e871b21aef0940c", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 9c784c3a3..c18e92bc8 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -163,7 +163,7 @@ impl BackupDomain {
}
// If not OK, reset backup domain and configure it.
- #[cfg(not(any(rcc_l0, rcc_l1)))]
+ #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1)))]
{
Self::modify(|w| w.set_bdrst(true));
Self::modify(|w| w.set_bdrst(false));
diff --git a/embassy-stm32/src/rcc/l0.rs b/embassy-stm32/src/rcc/l0l1.rs
similarity index 91%
rename from embassy-stm32/src/rcc/l0.rs
rename to embassy-stm32/src/rcc/l0l1.rs
index 3fd8074d7..4b1acae5d 100644
--- a/embassy-stm32/src/rcc/l0.rs
+++ b/embassy-stm32/src/rcc/l0l1.rs
@@ -95,7 +95,7 @@ pub(crate) unsafe fn init(config: Config) {
ClockSrc::HSI16 => {
// Enable HSI16
RCC.cr().write(|w| w.set_hsi16on(true));
- while !RCC.cr().read().hsi16rdyf() {}
+ while !RCC.cr().read().hsi16rdy() {}
(HSI_FREQ, Sw::HSI16)
}
@@ -117,7 +117,7 @@ pub(crate) unsafe fn init(config: Config) {
PLLSource::HSI16 => {
// Enable HSI
RCC.cr().write(|w| w.set_hsi16on(true));
- while !RCC.cr().read().hsi16rdyf() {}
+ while !RCC.cr().read().hsi16rdy() {}
HSI_FREQ
}
};
@@ -150,21 +150,17 @@ pub(crate) unsafe fn init(config: Config) {
config.lse.map(|_| Default::default()),
);
- let wait_states = match config.voltage_scale {
- VoltageScale::RANGE1 => match sys_clk.0 {
- ..=16_000_000 => 0,
- _ => 1,
- },
- VoltageScale::RANGE2 => match sys_clk.0 {
- ..=8_000_000 => 0,
- _ => 1,
- },
- VoltageScale::RANGE3 => 0,
- _ => unreachable!(),
+ let wait_states = match (config.voltage_scale, sys_clk.0) {
+ (VoltageScale::RANGE1, ..=16_000_000) => 0,
+ (VoltageScale::RANGE2, ..=8_000_000) => 0,
+ (VoltageScale::RANGE3, ..=4_200_000) => 0,
+ _ => 1,
};
- FLASH.acr().modify(|w| {
- w.set_latency(wait_states != 0);
- });
+
+ #[cfg(stm32l1)]
+ FLASH.acr().write(|w| w.set_acc64(true));
+ FLASH.acr().modify(|w| w.set_prften(true));
+ FLASH.acr().modify(|w| w.set_latency(wait_states != 0));
RCC.cfgr().modify(|w| {
w.set_sw(sw);
diff --git a/embassy-stm32/src/rcc/l1.rs b/embassy-stm32/src/rcc/l1.rs
deleted file mode 100644
index 7c75b888d..000000000
--- a/embassy-stm32/src/rcc/l1.rs
+++ /dev/null
@@ -1,198 +0,0 @@
-pub use crate::pac::rcc::vals::{
- Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PLLDiv, Pllmul as PLLMul, Ppre as APBPrescaler,
-};
-use crate::pac::rcc::vals::{Pllsrc, Sw};
-use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-/// LSI speed
-pub const LSI_FREQ: Hertz = Hertz(32_000);
-
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum ClockSrc {
- MSI(MSIRange),
- PLL(PLLSource, PLLMul, PLLDiv),
- HSE(Hertz),
- HSI,
-}
-
-/// PLL clock input source
-#[derive(Clone, Copy)]
-pub enum PLLSource {
- HSI,
- HSE(Hertz),
-}
-
-impl From<PLLSource> for Pllsrc {
- fn from(val: PLLSource) -> Pllsrc {
- match val {
- PLLSource::HSI => Pllsrc::HSI,
- PLLSource::HSE(_) => Pllsrc::HSE,
- }
- }
-}
-
-/// Clocks configutation
-pub struct Config {
- pub mux: ClockSrc,
- pub ahb_pre: AHBPrescaler,
- pub apb1_pre: APBPrescaler,
- pub apb2_pre: APBPrescaler,
-}
-
-impl Default for Config {
- #[inline]
- fn default() -> Config {
- Config {
- mux: ClockSrc::MSI(MSIRange::RANGE5),
- ahb_pre: AHBPrescaler::DIV1,
- apb1_pre: APBPrescaler::DIV1,
- apb2_pre: APBPrescaler::DIV1,
- }
- }
-}
-
-pub(crate) unsafe fn init(config: Config) {
- let (sys_clk, sw) = match config.mux {
- ClockSrc::MSI(range) => {
- // Set MSI range
- RCC.icscr().write(|w| w.set_msirange(range));
-
- // Enable MSI
- RCC.cr().write(|w| w.set_msion(true));
- while !RCC.cr().read().msirdy() {}
-
- let freq = 32_768 * (1 << (range as u8 + 1));
- (Hertz(freq), Sw::MSI)
- }
- ClockSrc::HSI => {
- // Enable HSI
- RCC.cr().write(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
-
- (HSI_FREQ, Sw::HSI)
- }
- ClockSrc::HSE(freq) => {
- // Enable HSE
- RCC.cr().write(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
-
- (freq, Sw::HSE)
- }
- ClockSrc::PLL(src, mul, div) => {
- let freq = match src {
- PLLSource::HSE(freq) => {
- // Enable HSE
- RCC.cr().write(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
- freq
- }
- PLLSource::HSI => {
- // Enable HSI
- RCC.cr().write(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
- HSI_FREQ
- }
- };
-
- // Disable PLL
- RCC.cr().modify(|w| w.set_pllon(false));
- while RCC.cr().read().pllrdy() {}
-
- let freq = freq * mul / div;
-
- assert!(freq <= Hertz(32_000_000));
-
- RCC.cfgr().write(move |w| {
- w.set_pllmul(mul);
- w.set_plldiv(div);
- w.set_pllsrc(src.into());
- });
-
- // Enable PLL
- RCC.cr().modify(|w| w.set_pllon(true));
- while !RCC.cr().read().pllrdy() {}
-
- (freq, Sw::PLL)
- }
- };
-
- // Set flash 64-bit access, prefetch and wait states
- if sys_clk >= Hertz(16_000_000) {
- FLASH.acr().write(|w| w.set_acc64(true));
- FLASH.acr().modify(|w| w.set_prften(true));
- FLASH.acr().modify(|w| w.set_latency(true));
- }
-
- RCC.cfgr().modify(|w| {
- w.set_sw(sw);
- w.set_hpre(config.ahb_pre);
- w.set_ppre1(config.apb1_pre);
- w.set_ppre2(config.apb2_pre);
- });
-
- let ahb_freq = sys_clk / config.ahb_pre;
-
- let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
-
- let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
-
- #[cfg(crs)]
- if config.enable_hsi48 {
- // Reset CRS peripheral
- RCC.apb1rstr().modify(|w| w.set_crsrst(true));
- RCC.apb1rstr().modify(|w| w.set_crsrst(false));
-
- // Enable CRS peripheral
- RCC.apb1enr().modify(|w| w.set_crsen(true));
-
- // Initialize CRS
- CRS.cfgr().write(|w|
-
- // Select LSE as synchronization source
- w.set_syncsrc(crs::vals::Syncsrc::LSE));
- CRS.cr().modify(|w| {
- w.set_autotrimen(true);
- w.set_cen(true);
- });
-
- // Enable VREFINT reference for HSI48 oscillator
- SYSCFG.cfgr3().modify(|w| {
- w.set_enref_hsi48(true);
- w.set_en_vrefint(true);
- });
-
- // Select HSI48 as USB clock
- RCC.ccipr().modify(|w| w.set_hsi48msel(true));
-
- // Enable dedicated USB clock
- RCC.crrcr().modify(|w| w.set_hsi48on(true));
- while !RCC.crrcr().read().hsi48rdy() {}
- }
-
- set_freqs(Clocks {
- sys: sys_clk,
- ahb1: ahb_freq,
- apb1: apb1_freq,
- apb2: apb2_freq,
- apb1_tim: apb1_tim_freq,
- apb2_tim: apb2_tim_freq,
- });
-}
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 52dc386b4..3d4de0e6e 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -19,8 +19,7 @@ pub use mco::*;
#[cfg_attr(rcc_g0, path = "g0.rs")]
#[cfg_attr(rcc_g4, path = "g4.rs")]
#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab), path = "h.rs")]
-#[cfg_attr(rcc_l0, path = "l0.rs")]
-#[cfg_attr(rcc_l1, path = "l1.rs")]
+#[cfg_attr(any(rcc_l0, rcc_l0_v2, rcc_l1), path = "l0l1.rs")]
#[cfg_attr(rcc_l4, path = "l4.rs")]
#[cfg_attr(rcc_l5, path = "l5.rs")]
#[cfg_attr(rcc_u5, path = "u5.rs")]
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index f2ba5f7fc..2bf500798 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -332,7 +332,7 @@ pub fn config() -> Config {
use embassy_stm32::rcc::*;
config.rcc.mux = ClockSrc::PLL(
// 32Mhz clock (16 * 4 / 2)
- PLLSource::HSI,
+ PLLSource::HSI16,
PLLMul::MUL4,
PLLDiv::DIV2,
);