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net-enc28j60: fix PHY read unreliable due to missing dummy byte.

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This commit is contained in:
Dario Nieuwenhuis 2023-08-12 03:07:13 +02:00
parent 4af1cf88d2
commit 253b28deba
2 changed files with 13 additions and 9 deletions
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19
embassy-net-enc28j60/src/lib.rs
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@ -361,10 +361,16 @@ where
fn _read_control_register(&mut self, register: Register) -> u8 { fn _read_control_register(&mut self, register: Register) -> u8 {
self.change_bank(register); self.change_bank(register);
let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0]; if register.is_eth_register() {
self.spi.transfer_in_place(&mut buffer).unwrap(); let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0];
self.spi.transfer_in_place(&mut buffer).unwrap();
buffer[1] buffer[1]
} else {
// MAC, MII regs need a dummy byte.
let mut buffer = [Instruction::RCR.opcode() | register.addr(), 0, 0];
self.spi.transfer_in_place(&mut buffer).unwrap();
buffer[2]
}
} }
fn read_phy_register(&mut self, register: phy::Register) -> u16 { fn read_phy_register(&mut self, register: phy::Register) -> u16 {
@ -379,11 +385,10 @@ where
// wait until the read operation finishes // wait until the read operation finishes
while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {} while self.read_control_register(bank3::Register::MISTAT) & 0b1 != 0 {}
let h = self.read_control_register(bank2::Register::MIRDH);
let l = self.read_control_register(bank2::Register::MIRDL);
self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(0).bits()); self.write_control_register(bank2::Register::MICMD, bank2::MICMD::default().miird(0).bits());
let l = self.read_control_register(bank2::Register::MIRDL);
let h = self.read_control_register(bank2::Register::MIRDH);
(l as u16) | (h as u16) << 8 (l as u16) | (h as u16) << 8
} }

3
embassy-net-enc28j60/src/phy.rs
View file

@ -30,7 +30,6 @@ register!(PHCON2, 0, u16, {
}); });
register!(PHSTAT2, 0, u16, { register!(PHSTAT2, 0, u16, {
// Datasheet says it's bit 10, but it's actually bit 2 ?!?!
#[doc = "Link Status bit"] #[doc = "Link Status bit"]
lstat @ 2, lstat @ 10,
}); });