From 25a95503f661f064e57854df8f831ad681868a4c Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 16 Feb 2024 20:41:04 +0100
Subject: [PATCH] Configured HSI48 if enabled, assert is enabled if chosen as
 clk48 source

---
 embassy-stm32/src/rcc/g4.rs | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 7ca741fc7..22dfa25c6 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -145,6 +145,11 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
+    // Configure HSI48 if required
+    if let Some(hsi48_config) = config.hsi48 {
+        super::init_hsi48(hsi48_config);
+    }
+
     let pll_freq = config.pll.map(|pll_config| {
         let src_freq = match pll_config.source {
             Pllsrc::HSI => unwrap!(hsi),
@@ -272,7 +277,7 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
-    // Setup the 48 MHz clock if needed
+    // Configure the 48MHz clock source for USB and RNG peripherals.
     {
         let source = match config.clk48_src {
             Clk48Src::PLL1_Q => {
@@ -282,7 +287,11 @@ pub(crate) unsafe fn init(config: Config) {
 
                 crate::pac::rcc::vals::Clk48sel::PLL1_Q
             }
-            Clk48Src::HSI48 => crate::pac::rcc::vals::Clk48sel::HSI48,
+            Clk48Src::HSI48 => {
+                // Make sure HSI48 is enabled
+                assert!(config.hsi48.is_some());
+                crate::pac::rcc::vals::Clk48sel::HSI48
+            }
             _ => unreachable!(),
         };