Configured HSI48 if enabled, assert is enabled if chosen as clk48 source
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ae74833999
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25a95503f6
1 changed files with 11 additions and 2 deletions
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@ -145,6 +145,11 @@ pub(crate) unsafe fn init(config: Config) {
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}
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};
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// Configure HSI48 if required
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if let Some(hsi48_config) = config.hsi48 {
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super::init_hsi48(hsi48_config);
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}
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let pll_freq = config.pll.map(|pll_config| {
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let src_freq = match pll_config.source {
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Pllsrc::HSI => unwrap!(hsi),
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@ -272,7 +277,7 @@ pub(crate) unsafe fn init(config: Config) {
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}
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};
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// Setup the 48 MHz clock if needed
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// Configure the 48MHz clock source for USB and RNG peripherals.
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{
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let source = match config.clk48_src {
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Clk48Src::PLL1_Q => {
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@ -282,7 +287,11 @@ pub(crate) unsafe fn init(config: Config) {
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crate::pac::rcc::vals::Clk48sel::PLL1_Q
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}
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Clk48Src::HSI48 => crate::pac::rcc::vals::Clk48sel::HSI48,
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Clk48Src::HSI48 => {
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// Make sure HSI48 is enabled
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assert!(config.hsi48.is_some());
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crate::pac::rcc::vals::Clk48sel::HSI48
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}
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_ => unreachable!(),
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};
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