Merge pull request #1792 from vDorst/adin1110-pr
Added support and example for Analog ADIN1110 SPE SPI ethernet chip.
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
295542f4d3
13 changed files with 2730 additions and 3 deletions
1
.github/ci/doc.sh
vendored
1
.github/ci/doc.sh
vendored
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@ -39,6 +39,7 @@ docserver-builder -i ./embassy-net-wiznet -o webroot/crates/embassy-net-wiznet/g
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docserver-builder -i ./embassy-net-enc28j60 -o webroot/crates/embassy-net-enc28j60/git.zup
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docserver-builder -i ./embassy-net-esp-hosted -o webroot/crates/embassy-net-esp-hosted/git.zup
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docserver-builder -i ./embassy-stm32-wpan -o webroot/crates/embassy-stm32-wpan/git.zup --output-static webroot/static
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docserver-builder -i ./embassy-net-adin1110 -o webroot/crates/embassy-net-adin1110/git.zup
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export KUBECONFIG=/ci/secrets/kubeconfig.yml
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POD=$(kubectl -n embassy get po -l app=docserver -o jsonpath={.items[0].metadata.name})
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2
.github/ci/test.sh
vendored
2
.github/ci/test.sh
vendored
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@ -28,3 +28,5 @@ cargo test --manifest-path ./embassy-rp/Cargo.toml --no-default-features --featu
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cargo test --manifest-path ./embassy-stm32/Cargo.toml --no-default-features --features nightly,stm32f429vg,exti,time-driver-any,exti
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cargo test --manifest-path ./embassy-stm32/Cargo.toml --no-default-features --features nightly,stm32f732ze,exti,time-driver-any,exti
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cargo test --manifest-path ./embassy-stm32/Cargo.toml --no-default-features --features nightly,stm32f769ni,exti,time-driver-any,exti
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cargo test --manifest-path ./embassy-net-adin1110/Cargo.toml
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41
embassy-net-adin1110/Cargo.toml
Normal file
41
embassy-net-adin1110/Cargo.toml
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@ -0,0 +1,41 @@
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[package]
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name = "embassy-net-adin1110"
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version = "0.1.0"
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description = "embassy-net driver for the ADIN1110 ethernet chip"
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keywords = ["embedded", "ADIN1110", "embassy-net", "embedded-hal-async", "ethernet", "async"]
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categories = ["embedded", "hardware-support", "no-std", "network-programming", "async"]
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license = "MIT OR Apache-2.0"
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edition = "2021"
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[dependencies]
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heapless = "0.7.16"
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defmt = { version = "0.3", optional = true }
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log = { version = "0.4.4", default-features = false, optional = true }
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embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
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embedded-hal-async = { version = "=1.0.0-rc.1" }
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embedded-hal-bus = { version = "=0.1.0-rc.1", features = ["async"] }
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embassy-net-driver-channel = { version = "0.1.0", path = "../embassy-net-driver-channel" }
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embassy-time = { version = "0.1.0" }
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embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
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bitfield = "0.14.0"
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[dev-dependencies]
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# reenable when https://github.com/dbrgn/embedded-hal-mock/pull/86 is merged.
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#embedded-hal-mock = { git = "https://github.com/dbrgn/embedded-hal-mock", branch = "1-alpha", features = ["embedded-hal-async", "eh1"] }] }
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embedded-hal-mock = { git = "https://github.com/newAM/embedded-hal-mock", branch = "eh1-rc.1", features = ["embedded-hal-async", "eh1"] }
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crc = "3.0.1"
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env_logger = "0.10"
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critical-section = { version = "1.1.1", features = ["std"] }
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futures-test = "0.3.17"
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[features]
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default = [ ]
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defmt = [ "dep:defmt" ]
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[package.metadata.embassy_docs]
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src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-adin1110-v$VERSION/embassy-net-adin1110/src/"
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src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net-adin1110/src/"
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target = "thumbv7em-none-eabi"
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55
embassy-net-adin1110/README.md
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55
embassy-net-adin1110/README.md
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@ -0,0 +1,55 @@
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# SPE ADIN1110 `embassy-net` integration
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[`embassy-net`](https://crates.io/crates/embassy-net) integration for the `Analog ADIN1110` SPI SPE ethernet chips.
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## What is SPE or Single Pair Ethernet / 10 BASE-T1L
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SPE stands for Single Pair Ethernet. As the names implies, SPE uses differential signalling with 2 wires (a twisted-pair) in a cable as the physical medium.
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SPE is full-duplex - it can transmit and receive ethernet packets at the same time. SPE is still ethernet, only the physical layer is different.
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SPE also supports [`PoDL (Power over Data Line)`](https://www.ti.com/lit/an/snla395/snla395.pdf), power delivery from 0.5 up to 50 Watts, similar to [`PoE`](https://en.wikipedia.org/wiki/Power_over_Ethernet), but an additional hardware and handshake protocol are needed.
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SPE has many link speeds but only `10 BASE-T1L` is able to reach cable lengths up to 1000 meters in `2.4 Vpp` transmit amplitude.
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Currently in 2023, none of the standards are compatible with each other.
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Thus `10 BASE-T1L` won't work with a `10 BASE-T1S`, `100 BASE-T1` or any standard `x BASE-T`.
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In the industry SPE is also called [`APL (Advanced Physical Layer)`](https://www.ethernet-apl.org), and is based on the `10 BASE-T1L` standard.
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APL can be used in [`intrinsic safety applications/explosion hazardous areas`](https://en.wikipedia.org/wiki/Electrical_equipment_in_hazardous_areas) which has its own name and standard called [`2-WISE (2-wire intrinsically safe ethernet) IEC TS 60079-47:2021`](https://webstore.iec.ch/publication/64292).
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`10 BASE-T1L` and `ADIN1110` are designed to support intrinsic safety applications. The power supply energy is fixed and PDoL is not supported.
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## Supported SPI modes
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`ADIN1110` supports two SPI modes. `Generic` and [`OPEN Alliance 10BASE-T1x MAC-PHY serial interface`](https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf)
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Both modes support with and without additional CRC.
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Currently only `Generic` SPI with or without CRC is supported.
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*NOTE:* SPI Mode is selected by the hardware pins `SPI_CFG0` and `SPI_CFG1`. Software can't detect nor change the mode.
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## Hardware
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- Tested on [`Analog Devices EVAL-ADIN1110EBZ`](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin1110.html) with an `STM32L4S5QII3P`, see [`spe_adin1110_http_server`](../examples/stm32l4/src/bin/spe_adin1110_http_server.rs) dor an example.
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- [`SparkFun MicroMod Single Pair Ethernet Function Board`](https://www.sparkfun.com/products/19038) or [`SparkFun MicroMod Single Pair Ethernet Kit`](https://www.sparkfun.com/products/19628), supporting multiple microcontrollers. **Make sure to check if it's a microcontroller that is supported by Embassy!**
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## Other SPE chips
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* [`Analog ADIN2111`](https://www.analog.com/en/products/adin2111.html) 2 Port SPI version. Can work with this driver.
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* [`Analog ADIN1100`](https://www.analog.com/en/products/adin1100.html) RGMII version.
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## Testing
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ADIN1110 library can tested on the host with a mock SPI driver.
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$ `cargo test --target x86_64-unknown-linux-gnu`
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## License
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This work is licensed under either of
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- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
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http://www.apache.org/licenses/LICENSE-2.0)
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- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
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at your option.
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358
embassy-net-adin1110/src/crc32.rs
Normal file
358
embassy-net-adin1110/src/crc32.rs
Normal file
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@ -0,0 +1,358 @@
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pub const CRC32R_LOOKUP_TABLE: [u32; 256] = [
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0x0000_0000,
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0x7707_3096,
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0xEE0E_612C,
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0x9909_51BA,
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||||
0x076D_C419,
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||||
0x706A_F48F,
|
||||
0xE963_A535,
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||||
0x9E64_95A3,
|
||||
0x0EDB_8832,
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||||
0x79DC_B8A4,
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||||
0xE0D5_E91E,
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||||
0x97D2_D988,
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||||
0x09B6_4C2B,
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||||
0x7EB1_7CBD,
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||||
0xE7B8_2D07,
|
||||
0x90BF_1D91,
|
||||
0x1DB7_1064,
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||||
0x6AB0_20F2,
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||||
0xF3B9_7148,
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||||
0x84BE_41DE,
|
||||
0x1ADA_D47D,
|
||||
0x6DDD_E4EB,
|
||||
0xF4D4_B551,
|
||||
0x83D3_85C7,
|
||||
0x136C_9856,
|
||||
0x646B_A8C0,
|
||||
0xFD62_F97A,
|
||||
0x8A65_C9EC,
|
||||
0x1401_5C4F,
|
||||
0x6306_6CD9,
|
||||
0xFA0F_3D63,
|
||||
0x8D08_0DF5,
|
||||
0x3B6E_20C8,
|
||||
0x4C69_105E,
|
||||
0xD560_41E4,
|
||||
0xA267_7172,
|
||||
0x3C03_E4D1,
|
||||
0x4B04_D447,
|
||||
0xD20D_85FD,
|
||||
0xA50A_B56B,
|
||||
0x35B5_A8FA,
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||||
0x42B2_986C,
|
||||
0xDBBB_C9D6,
|
||||
0xACBC_F940,
|
||||
0x32D8_6CE3,
|
||||
0x45DF_5C75,
|
||||
0xDCD6_0DCF,
|
||||
0xABD1_3D59,
|
||||
0x26D9_30AC,
|
||||
0x51DE_003A,
|
||||
0xC8D7_5180,
|
||||
0xBFD0_6116,
|
||||
0x21B4_F4B5,
|
||||
0x56B3_C423,
|
||||
0xCFBA_9599,
|
||||
0xB8BD_A50F,
|
||||
0x2802_B89E,
|
||||
0x5F05_8808,
|
||||
0xC60C_D9B2,
|
||||
0xB10B_E924,
|
||||
0x2F6F_7C87,
|
||||
0x5868_4C11,
|
||||
0xC161_1DAB,
|
||||
0xB666_2D3D,
|
||||
0x76DC_4190,
|
||||
0x01DB_7106,
|
||||
0x98D2_20BC,
|
||||
0xEFD5_102A,
|
||||
0x71B1_8589,
|
||||
0x06B6_B51F,
|
||||
0x9FBF_E4A5,
|
||||
0xE8B8_D433,
|
||||
0x7807_C9A2,
|
||||
0x0F00_F934,
|
||||
0x9609_A88E,
|
||||
0xE10E_9818,
|
||||
0x7F6A_0DBB,
|
||||
0x086D_3D2D,
|
||||
0x9164_6C97,
|
||||
0xE663_5C01,
|
||||
0x6B6B_51F4,
|
||||
0x1C6C_6162,
|
||||
0x8565_30D8,
|
||||
0xF262_004E,
|
||||
0x6C06_95ED,
|
||||
0x1B01_A57B,
|
||||
0x8208_F4C1,
|
||||
0xF50F_C457,
|
||||
0x65B0_D9C6,
|
||||
0x12B7_E950,
|
||||
0x8BBE_B8EA,
|
||||
0xFCB9_887C,
|
||||
0x62DD_1DDF,
|
||||
0x15DA_2D49,
|
||||
0x8CD3_7CF3,
|
||||
0xFBD4_4C65,
|
||||
0x4DB2_6158,
|
||||
0x3AB5_51CE,
|
||||
0xA3BC_0074,
|
||||
0xD4BB_30E2,
|
||||
0x4ADF_A541,
|
||||
0x3DD8_95D7,
|
||||
0xA4D1_C46D,
|
||||
0xD3D6_F4FB,
|
||||
0x4369_E96A,
|
||||
0x346E_D9FC,
|
||||
0xAD67_8846,
|
||||
0xDA60_B8D0,
|
||||
0x4404_2D73,
|
||||
0x3303_1DE5,
|
||||
0xAA0A_4C5F,
|
||||
0xDD0D_7CC9,
|
||||
0x5005_713C,
|
||||
0x2702_41AA,
|
||||
0xBE0B_1010,
|
||||
0xC90C_2086,
|
||||
0x5768_B525,
|
||||
0x206F_85B3,
|
||||
0xB966_D409,
|
||||
0xCE61_E49F,
|
||||
0x5EDE_F90E,
|
||||
0x29D9_C998,
|
||||
0xB0D0_9822,
|
||||
0xC7D7_A8B4,
|
||||
0x59B3_3D17,
|
||||
0x2EB4_0D81,
|
||||
0xB7BD_5C3B,
|
||||
0xC0BA_6CAD,
|
||||
0xEDB8_8320,
|
||||
0x9ABF_B3B6,
|
||||
0x03B6_E20C,
|
||||
0x74B1_D29A,
|
||||
0xEAD5_4739,
|
||||
0x9DD2_77AF,
|
||||
0x04DB_2615,
|
||||
0x73DC_1683,
|
||||
0xE363_0B12,
|
||||
0x9464_3B84,
|
||||
0x0D6D_6A3E,
|
||||
0x7A6A_5AA8,
|
||||
0xE40E_CF0B,
|
||||
0x9309_FF9D,
|
||||
0x0A00_AE27,
|
||||
0x7D07_9EB1,
|
||||
0xF00F_9344,
|
||||
0x8708_A3D2,
|
||||
0x1E01_F268,
|
||||
0x6906_C2FE,
|
||||
0xF762_575D,
|
||||
0x8065_67CB,
|
||||
0x196C_3671,
|
||||
0x6E6B_06E7,
|
||||
0xFED4_1B76,
|
||||
0x89D3_2BE0,
|
||||
0x10DA_7A5A,
|
||||
0x67DD_4ACC,
|
||||
0xF9B9_DF6F,
|
||||
0x8EBE_EFF9,
|
||||
0x17B7_BE43,
|
||||
0x60B0_8ED5,
|
||||
0xD6D6_A3E8,
|
||||
0xA1D1_937E,
|
||||
0x38D8_C2C4,
|
||||
0x4FDF_F252,
|
||||
0xD1BB_67F1,
|
||||
0xA6BC_5767,
|
||||
0x3FB5_06DD,
|
||||
0x48B2_364B,
|
||||
0xD80D_2BDA,
|
||||
0xAF0A_1B4C,
|
||||
0x3603_4AF6,
|
||||
0x4104_7A60,
|
||||
0xDF60_EFC3,
|
||||
0xA867_DF55,
|
||||
0x316E_8EEF,
|
||||
0x4669_BE79,
|
||||
0xCB61_B38C,
|
||||
0xBC66_831A,
|
||||
0x256F_D2A0,
|
||||
0x5268_E236,
|
||||
0xCC0C_7795,
|
||||
0xBB0B_4703,
|
||||
0x2202_16B9,
|
||||
0x5505_262F,
|
||||
0xC5BA_3BBE,
|
||||
0xB2BD_0B28,
|
||||
0x2BB4_5A92,
|
||||
0x5CB3_6A04,
|
||||
0xC2D7_FFA7,
|
||||
0xB5D0_CF31,
|
||||
0x2CD9_9E8B,
|
||||
0x5BDE_AE1D,
|
||||
0x9B64_C2B0,
|
||||
0xEC63_F226,
|
||||
0x756A_A39C,
|
||||
0x026D_930A,
|
||||
0x9C09_06A9,
|
||||
0xEB0E_363F,
|
||||
0x7207_6785,
|
||||
0x0500_5713,
|
||||
0x95BF_4A82,
|
||||
0xE2B8_7A14,
|
||||
0x7BB1_2BAE,
|
||||
0x0CB6_1B38,
|
||||
0x92D2_8E9B,
|
||||
0xE5D5_BE0D,
|
||||
0x7CDC_EFB7,
|
||||
0x0BDB_DF21,
|
||||
0x86D3_D2D4,
|
||||
0xF1D4_E242,
|
||||
0x68DD_B3F8,
|
||||
0x1FDA_836E,
|
||||
0x81BE_16CD,
|
||||
0xF6B9_265B,
|
||||
0x6FB0_77E1,
|
||||
0x18B7_4777,
|
||||
0x8808_5AE6,
|
||||
0xFF0F_6A70,
|
||||
0x6606_3BCA,
|
||||
0x1101_0B5C,
|
||||
0x8F65_9EFF,
|
||||
0xF862_AE69,
|
||||
0x616B_FFD3,
|
||||
0x166C_CF45,
|
||||
0xA00A_E278,
|
||||
0xD70D_D2EE,
|
||||
0x4E04_8354,
|
||||
0x3903_B3C2,
|
||||
0xA767_2661,
|
||||
0xD060_16F7,
|
||||
0x4969_474D,
|
||||
0x3E6E_77DB,
|
||||
0xAED1_6A4A,
|
||||
0xD9D6_5ADC,
|
||||
0x40DF_0B66,
|
||||
0x37D8_3BF0,
|
||||
0xA9BC_AE53,
|
||||
0xDEBB_9EC5,
|
||||
0x47B2_CF7F,
|
||||
0x30B5_FFE9,
|
||||
0xBDBD_F21C,
|
||||
0xCABA_C28A,
|
||||
0x53B3_9330,
|
||||
0x24B4_A3A6,
|
||||
0xBAD0_3605,
|
||||
0xCDD7_0693,
|
||||
0x54DE_5729,
|
||||
0x23D9_67BF,
|
||||
0xB366_7A2E,
|
||||
0xC461_4AB8,
|
||||
0x5D68_1B02,
|
||||
0x2A6F_2B94,
|
||||
0xB40B_BE37,
|
||||
0xC30C_8EA1,
|
||||
0x5A05_DF1B,
|
||||
0x2D02_EF8D,
|
||||
];
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[derive(Debug)]
|
||||
pub struct ETH_FSC(pub u32);
|
||||
|
||||
impl ETH_FSC {
|
||||
pub const CRC32_OK: u32 = 0x2144_df1c;
|
||||
|
||||
#[must_use]
|
||||
pub fn new(data: &[u8]) -> Self {
|
||||
let fsc = data.iter().fold(u32::MAX, |crc, byte| {
|
||||
let idx = u8::try_from(crc & 0xFF).unwrap() ^ byte;
|
||||
CRC32R_LOOKUP_TABLE[usize::from(idx)] ^ (crc >> 8)
|
||||
}) ^ u32::MAX;
|
||||
Self(fsc)
|
||||
}
|
||||
|
||||
#[must_use]
|
||||
pub fn update(self, data: &[u8]) -> Self {
|
||||
let fsc = data.iter().fold(self.0 ^ u32::MAX, |crc, byte| {
|
||||
let idx = u8::try_from(crc & 0xFF).unwrap() ^ byte;
|
||||
CRC32R_LOOKUP_TABLE[usize::from(idx)] ^ (crc >> 8)
|
||||
}) ^ u32::MAX;
|
||||
Self(fsc)
|
||||
}
|
||||
|
||||
#[must_use]
|
||||
pub fn crc_ok(&self) -> bool {
|
||||
self.0 == Self::CRC32_OK
|
||||
}
|
||||
|
||||
#[must_use]
|
||||
pub fn hton_bytes(&self) -> [u8; 4] {
|
||||
self.0.to_le_bytes()
|
||||
}
|
||||
|
||||
#[must_use]
|
||||
pub fn hton(&self) -> u32 {
|
||||
self.0.to_le()
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
|
||||
#[test]
|
||||
fn crc32_ethernet_frame() {
|
||||
let packet_a = &[
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xe0, 0x4c, 0x68, 0xee, 0xee, 0xff, 0x06, 0x00, 0x01, 0x08, 0x00,
|
||||
0x06, 0x04, 0x00, 0x01, 0x00, 0xe0, 0x4c, 0x68, 0x0e, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0xc0, 0xa8, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf2, 0x65, 0x90, 0x3d,
|
||||
];
|
||||
|
||||
let packet_b = &[
|
||||
0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0x00, 0xe0, 0x4c, 0x68, 0xee, 0xee, 0xdd, 0x06, 0x00, 0x01, 0x08, 0x00,
|
||||
0x06, 0x04, 0x00, 0x02, 0x00, 0xe0, 0x4c, 0x68, 0x09, 0xde, 0xc0, 0xa8, 0x01, 0x02, 0x12, 0x34, 0x56, 0x78,
|
||||
0x9a, 0xbc, 0xc0, 0xa8, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x3d, 0x67, 0x7c,
|
||||
];
|
||||
|
||||
// Packet A
|
||||
let own_crc = ETH_FSC::new(&packet_a[0..60]);
|
||||
let crc_bytes = own_crc.hton_bytes();
|
||||
println!("{:08x} {:02x?}", own_crc.0, crc_bytes);
|
||||
assert_eq!(&crc_bytes, &packet_a[60..64]);
|
||||
|
||||
let own_crc = ETH_FSC::new(packet_a);
|
||||
println!("{:08x}", own_crc.0);
|
||||
assert_eq!(own_crc.0, ETH_FSC::CRC32_OK);
|
||||
|
||||
// Packet B
|
||||
let own_crc = ETH_FSC::new(&packet_b[0..60]);
|
||||
let crc_bytes = own_crc.hton_bytes();
|
||||
println!("{:08x} {:02x?}", own_crc.0, crc_bytes);
|
||||
assert_eq!(&crc_bytes, &packet_b[60..64]);
|
||||
|
||||
let own_crc = ETH_FSC::new(packet_b);
|
||||
println!("{:08x}", own_crc.0);
|
||||
assert_eq!(own_crc.0, ETH_FSC::CRC32_OK);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn crc32_update() {
|
||||
let full_data = &[
|
||||
0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0x00, 0xe0, 0x4c, 0x68, 0xee, 0xee, 0xdd, 0x06, 0x00, 0x01, 0x08, 0x00,
|
||||
0x06, 0x04, 0x00, 0x02, 0x00, 0xe0, 0x4c, 0x68, 0x09, 0xde, 0xc0, 0xa8, 0x01, 0x02, 0x12, 0x34, 0x56, 0x78,
|
||||
0x9a, 0xbc, 0xc0, 0xa8, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x3d, 0x67, 0x7c,
|
||||
];
|
||||
|
||||
let (part_a, part_b) = full_data.split_at(16);
|
||||
let crc_partially = ETH_FSC::new(part_a).update(part_b);
|
||||
|
||||
let crc_full = ETH_FSC::new(full_data);
|
||||
|
||||
assert_eq!(crc_full.0, crc_partially.0);
|
||||
}
|
||||
}
|
||||
53
embassy-net-adin1110/src/crc8.rs
Normal file
53
embassy-net-adin1110/src/crc8.rs
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/// CRC-8/ITU
|
||||
const CRC8X_TABLE: [u8; 256] = [
|
||||
0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d, 0x70, 0x77, 0x7e,
|
||||
0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d, 0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb,
|
||||
0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd, 0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8,
|
||||
0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd, 0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6,
|
||||
0xe3, 0xe4, 0xed, 0xea, 0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d,
|
||||
0x9a, 0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0d, 0x0a, 0x57, 0x50,
|
||||
0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a, 0x89, 0x8e, 0x87, 0x80, 0x95,
|
||||
0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4, 0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec,
|
||||
0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4, 0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f,
|
||||
0x58, 0x4d, 0x4a, 0x43, 0x44, 0x19, 0x1e, 0x17, 0x10, 0x05, 0x02, 0x0b, 0x0c, 0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a,
|
||||
0x33, 0x34, 0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63, 0x3e,
|
||||
0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x06, 0x01, 0x08, 0x0f, 0x1a, 0x1d, 0x14, 0x13, 0xae, 0xa9, 0xa0, 0xa7,
|
||||
0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83, 0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc,
|
||||
0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3,
|
||||
];
|
||||
|
||||
/// Calculate the crc of a pease of data.
|
||||
pub fn crc8(data: &[u8]) -> u8 {
|
||||
data.iter().fold(0, |crc, &byte| CRC8X_TABLE[usize::from(byte ^ crc)])
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use ::crc::{Crc, CRC_8_SMBUS};
|
||||
|
||||
use super::crc8;
|
||||
|
||||
#[test]
|
||||
fn spi_header_crc8() {
|
||||
let data = &[0x80, 0x00];
|
||||
|
||||
let c = Crc::<u8>::new(&CRC_8_SMBUS);
|
||||
let mut dig = c.digest();
|
||||
dig.update(data);
|
||||
let sw_crc = dig.finalize();
|
||||
|
||||
let own_crc = crc8(data);
|
||||
|
||||
assert_eq!(own_crc, sw_crc);
|
||||
assert_eq!(own_crc, 182);
|
||||
|
||||
let data = &[0x80, 0x01];
|
||||
let mut dig = c.digest();
|
||||
dig.update(data);
|
||||
let sw_crc = dig.finalize();
|
||||
let own_crc = crc8(data);
|
||||
|
||||
assert_eq!(own_crc, sw_crc);
|
||||
assert_eq!(own_crc, 177);
|
||||
}
|
||||
}
|
||||
1046
embassy-net-adin1110/src/lib.rs
Normal file
1046
embassy-net-adin1110/src/lib.rs
Normal file
File diff suppressed because it is too large
Load diff
175
embassy-net-adin1110/src/mdio.rs
Normal file
175
embassy-net-adin1110/src/mdio.rs
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
/// PHY Address: (0..=0x1F), 5-bits long.
|
||||
#[allow(dead_code)]
|
||||
type PhyAddr = u8;
|
||||
|
||||
/// PHY Register: (0..=0x1F), 5-bits long.
|
||||
#[allow(dead_code)]
|
||||
type RegC22 = u8;
|
||||
|
||||
/// PHY Register Clause 45.
|
||||
#[allow(dead_code)]
|
||||
type RegC45 = u16;
|
||||
|
||||
/// PHY Register Value
|
||||
#[allow(dead_code)]
|
||||
type RegVal = u16;
|
||||
|
||||
#[allow(dead_code)]
|
||||
const REG13: RegC22 = 13;
|
||||
#[allow(dead_code)]
|
||||
const REG14: RegC22 = 14;
|
||||
|
||||
#[allow(dead_code)]
|
||||
const PHYADDR_MASK: u8 = 0x1f;
|
||||
#[allow(dead_code)]
|
||||
const DEV_MASK: u8 = 0x1f;
|
||||
|
||||
#[allow(dead_code)]
|
||||
#[repr(u16)]
|
||||
enum Reg13Op {
|
||||
Addr = 0b00 << 14,
|
||||
Write = 0b01 << 14,
|
||||
PostReadIncAddr = 0b10 << 14,
|
||||
Read = 0b11 << 14,
|
||||
}
|
||||
/// `MdioBus` trait
|
||||
/// Driver needs to implement the Clause 22
|
||||
/// Optional Clause 45 is the device supports this.
|
||||
///
|
||||
/// Claus 45 methodes are bases on <https://www.ieee802.org/3/efm/public/nov02/oam/pannell_oam_1_1102.pdf>
|
||||
pub trait MdioBus {
|
||||
type Error;
|
||||
|
||||
/// Read, Clause 22
|
||||
async fn read_cl22(&mut self, phy_id: PhyAddr, reg: RegC22) -> Result<RegVal, Self::Error>;
|
||||
|
||||
/// Write, Clause 22
|
||||
async fn write_cl22(&mut self, phy_id: PhyAddr, reg: RegC22, reg_val: RegVal) -> Result<(), Self::Error>;
|
||||
|
||||
/// Read, Clause 45
|
||||
/// This is the default implementation.
|
||||
/// Many hardware these days support direct Clause 45 operations.
|
||||
/// Implement this function when your hardware supports it.
|
||||
async fn read_cl45(&mut self, phy_id: PhyAddr, regc45: (u8, RegC45)) -> Result<RegVal, Self::Error> {
|
||||
// Write FN
|
||||
let val = (Reg13Op::Addr as RegVal) | RegVal::from(regc45.0 & DEV_MASK);
|
||||
|
||||
self.write_cl22(phy_id, REG13, val).await?;
|
||||
// Write Addr
|
||||
self.write_cl22(phy_id, REG14, regc45.1).await?;
|
||||
|
||||
// Write FN
|
||||
let val = (Reg13Op::Read as RegVal) | RegVal::from(regc45.0 & DEV_MASK);
|
||||
self.write_cl22(phy_id, REG13, val).await?;
|
||||
// Write Addr
|
||||
self.read_cl22(phy_id, REG14).await
|
||||
}
|
||||
|
||||
/// Write, Clause 45
|
||||
/// This is the default implementation.
|
||||
/// Many hardware these days support direct Clause 45 operations.
|
||||
/// Implement this function when your hardware supports it.
|
||||
async fn write_cl45(&mut self, phy_id: PhyAddr, regc45: (u8, RegC45), reg_val: RegVal) -> Result<(), Self::Error> {
|
||||
let dev_addr = RegVal::from(regc45.0 & DEV_MASK);
|
||||
let reg = regc45.1;
|
||||
|
||||
// Write FN
|
||||
let val = (Reg13Op::Addr as RegVal) | dev_addr;
|
||||
self.write_cl22(phy_id, REG13, val).await?;
|
||||
// Write Addr
|
||||
self.write_cl22(phy_id, REG14, reg).await?;
|
||||
|
||||
// Write FN
|
||||
let val = (Reg13Op::Write as RegVal) | dev_addr;
|
||||
self.write_cl22(phy_id, REG13, val).await?;
|
||||
// Write Addr
|
||||
self.write_cl22(phy_id, REG14, reg_val).await
|
||||
}
|
||||
}
|
||||
|
||||
// #[cfg(test)]
|
||||
// mod tests {
|
||||
// use core::convert::Infallible;
|
||||
|
||||
// use super::{MdioBus, PhyAddr, RegC22, RegVal};
|
||||
|
||||
// #[derive(Debug, PartialEq, Eq)]
|
||||
// enum A {
|
||||
// Read(PhyAddr, RegC22),
|
||||
// Write(PhyAddr, RegC22, RegVal),
|
||||
// }
|
||||
|
||||
// struct MockMdioBus(Vec<A>);
|
||||
|
||||
// impl MockMdioBus {
|
||||
// pub fn clear(&mut self) {
|
||||
// self.0.clear();
|
||||
// }
|
||||
// }
|
||||
|
||||
// impl MdioBus for MockMdioBus {
|
||||
// type Error = Infallible;
|
||||
|
||||
// fn write_cl22(
|
||||
// &mut self,
|
||||
// phy_id: super::PhyAddr,
|
||||
// reg: super::RegC22,
|
||||
// reg_val: super::RegVal,
|
||||
// ) -> Result<(), Self::Error> {
|
||||
// self.0.push(A::Write(phy_id, reg, reg_val));
|
||||
// Ok(())
|
||||
// }
|
||||
|
||||
// fn read_cl22(
|
||||
// &mut self,
|
||||
// phy_id: super::PhyAddr,
|
||||
// reg: super::RegC22,
|
||||
// ) -> Result<super::RegVal, Self::Error> {
|
||||
// self.0.push(A::Read(phy_id, reg));
|
||||
// Ok(0)
|
||||
// }
|
||||
// }
|
||||
|
||||
// #[test]
|
||||
// fn read_test() {
|
||||
// let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
|
||||
|
||||
// mdiobus.clear();
|
||||
// mdiobus.read_cl22(0x01, 0x00).unwrap();
|
||||
// assert_eq!(mdiobus.0, vec![A::Read(0x01, 0x00)]);
|
||||
|
||||
// mdiobus.clear();
|
||||
// mdiobus.read_cl45(0x01, (0xBB, 0x1234)).unwrap();
|
||||
// assert_eq!(
|
||||
// mdiobus.0,
|
||||
// vec![
|
||||
// #[allow(clippy::identity_op)]
|
||||
// A::Write(0x01, 13, (0b00 << 14) | 27),
|
||||
// A::Write(0x01, 14, 0x1234),
|
||||
// A::Write(0x01, 13, (0b11 << 14) | 27),
|
||||
// A::Read(0x01, 14)
|
||||
// ]
|
||||
// );
|
||||
// }
|
||||
|
||||
// #[test]
|
||||
// fn write_test() {
|
||||
// let mut mdiobus = MockMdioBus(Vec::with_capacity(20));
|
||||
|
||||
// mdiobus.clear();
|
||||
// mdiobus.write_cl22(0x01, 0x00, 0xABCD).unwrap();
|
||||
// assert_eq!(mdiobus.0, vec![A::Write(0x01, 0x00, 0xABCD)]);
|
||||
|
||||
// mdiobus.clear();
|
||||
// mdiobus.write_cl45(0x01, (0xBB, 0x1234), 0xABCD).unwrap();
|
||||
// assert_eq!(
|
||||
// mdiobus.0,
|
||||
// vec![
|
||||
// A::Write(0x01, 13, 27),
|
||||
// A::Write(0x01, 14, 0x1234),
|
||||
// A::Write(0x01, 13, (0b01 << 14) | 27),
|
||||
// A::Write(0x01, 14, 0xABCD)
|
||||
// ]
|
||||
// );
|
||||
// }
|
||||
// }
|
||||
142
embassy-net-adin1110/src/phy.rs
Normal file
142
embassy-net-adin1110/src/phy.rs
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
use crate::mdio::MdioBus;
|
||||
|
||||
#[allow(dead_code, non_camel_case_types, clippy::upper_case_acronyms)]
|
||||
#[repr(u8)]
|
||||
/// Clause 22 Registers
|
||||
pub enum RegsC22 {
|
||||
/// MII Control Register
|
||||
CONTROL = 0x00,
|
||||
/// MII Status Register
|
||||
STATUS = 0x01,
|
||||
/// PHY Identifier 1 Register
|
||||
PHY_ID1 = 0x02,
|
||||
/// PHY Identifier 2 Register.
|
||||
PHY_ID2 = 0x03,
|
||||
}
|
||||
|
||||
/// Clause 45 Registers
|
||||
#[allow(non_snake_case, dead_code)]
|
||||
pub mod RegsC45 {
|
||||
/// Device Address: 0x01
|
||||
#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
|
||||
#[repr(u16)]
|
||||
pub enum DA1 {
|
||||
/// PMA/PMD Control 1 Register
|
||||
PMA_PMD_CNTRL1 = 0x0000,
|
||||
/// PMA/PMD Status 1 Register
|
||||
PMA_PMD_STAT1 = 0x0001,
|
||||
/// MSE Value Register
|
||||
MSE_VAL = 0x830B,
|
||||
}
|
||||
|
||||
impl DA1 {
|
||||
#[must_use]
|
||||
pub fn into(self) -> (u8, u16) {
|
||||
(0x01, self as u16)
|
||||
}
|
||||
}
|
||||
|
||||
/// Device Address: 0x03
|
||||
#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
|
||||
#[repr(u16)]
|
||||
pub enum DA3 {
|
||||
/// PCS Control 1 Register
|
||||
PCS_CNTRL1 = 0x0000,
|
||||
/// PCS Status 1 Register
|
||||
PCS_STAT1 = 0x0001,
|
||||
/// PCS Status 2 Register
|
||||
PCS_STAT2 = 0x0008,
|
||||
}
|
||||
|
||||
impl DA3 {
|
||||
#[must_use]
|
||||
pub fn into(self) -> (u8, u16) {
|
||||
(0x03, self as u16)
|
||||
}
|
||||
}
|
||||
|
||||
/// Device Address: 0x07
|
||||
#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
|
||||
#[repr(u16)]
|
||||
pub enum DA7 {
|
||||
/// Extra Autonegotiation Status Register
|
||||
AN_STATUS_EXTRA = 0x8001,
|
||||
}
|
||||
|
||||
impl DA7 {
|
||||
#[must_use]
|
||||
pub fn into(self) -> (u8, u16) {
|
||||
(0x07, self as u16)
|
||||
}
|
||||
}
|
||||
|
||||
/// Device Address: 0x1E
|
||||
#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
|
||||
#[repr(u16)]
|
||||
pub enum DA1E {
|
||||
/// System Interrupt Status Register
|
||||
CRSM_IRQ_STATUS = 0x0010,
|
||||
/// System Interrupt Mask Register
|
||||
CRSM_IRQ_MASK = 0x0020,
|
||||
/// Pin Mux Configuration 1 Register
|
||||
DIGIO_PINMUX = 0x8c56,
|
||||
/// LED Control Register.
|
||||
LED_CNTRL = 0x8C82,
|
||||
/// LED Polarity Register
|
||||
LED_POLARITY = 0x8C83,
|
||||
}
|
||||
|
||||
impl DA1E {
|
||||
#[must_use]
|
||||
pub fn into(self) -> (u8, u16) {
|
||||
(0x1e, self as u16)
|
||||
}
|
||||
}
|
||||
|
||||
/// Device Address: 0x1F
|
||||
#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
|
||||
#[repr(u16)]
|
||||
pub enum DA1F {
|
||||
/// PHY Subsystem Interrupt Status Register
|
||||
PHY_SYBSYS_IRQ_STATUS = 0x0011,
|
||||
/// PHY Subsystem Interrupt Mask Register
|
||||
PHY_SYBSYS_IRQ_MASK = 0x0021,
|
||||
}
|
||||
|
||||
impl DA1F {
|
||||
#[must_use]
|
||||
pub fn into(self) -> (u8, u16) {
|
||||
(0x1f, self as u16)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Phy10BaseT1x(u8);
|
||||
|
||||
impl Default for Phy10BaseT1x {
|
||||
fn default() -> Self {
|
||||
Self(0x01)
|
||||
}
|
||||
}
|
||||
|
||||
impl Phy10BaseT1x {
|
||||
/// Get the both parts of the PHYID.
|
||||
pub async fn get_id<MDIOBUS, MDE>(&self, mdiobus: &mut MDIOBUS) -> Result<u32, MDE>
|
||||
where
|
||||
MDIOBUS: MdioBus<Error = MDE>,
|
||||
MDE: core::fmt::Debug,
|
||||
{
|
||||
let mut phyid = u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID1 as u8).await?) << 16;
|
||||
phyid |= u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID2 as u8).await?);
|
||||
Ok(phyid)
|
||||
}
|
||||
|
||||
/// Get the Mean Squared Error Value.
|
||||
pub async fn get_sqi<MDIOBUS, MDE>(&self, mdiobus: &mut MDIOBUS) -> Result<u16, MDE>
|
||||
where
|
||||
MDIOBUS: MdioBus<Error = MDE>,
|
||||
MDE: core::fmt::Debug,
|
||||
{
|
||||
mdiobus.read_cl45(self.0, RegsC45::DA1::MSE_VAL.into()).await
|
||||
}
|
||||
}
|
||||
408
embassy-net-adin1110/src/regs.rs
Normal file
408
embassy-net-adin1110/src/regs.rs
Normal file
|
|
@ -0,0 +1,408 @@
|
|||
use bitfield::{bitfield, bitfield_bitrange, bitfield_fields};
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[repr(u16)]
|
||||
/// SPI REGISTER DETAILS
|
||||
/// Table 38.
|
||||
pub enum SpiRegisters {
|
||||
IDVER = 0x00,
|
||||
PHYID = 0x01,
|
||||
CAPABILITY = 0x02,
|
||||
RESET = 0x03,
|
||||
CONFIG0 = 0x04,
|
||||
CONFIG2 = 0x06,
|
||||
STATUS0 = 0x08,
|
||||
STATUS1 = 0x09,
|
||||
IMASK0 = 0x0C,
|
||||
IMASK1 = 0x0D,
|
||||
MDIO_ACC = 0x20,
|
||||
TX_FSIZE = 0x30,
|
||||
TX = 0x31,
|
||||
TX_SPACE = 0x32,
|
||||
FIFO_CLR = 0x36,
|
||||
ADDR_FILT_UPR0 = 0x50,
|
||||
ADDR_FILT_LWR0 = 0x51,
|
||||
ADDR_FILT_UPR1 = 0x52,
|
||||
ADDR_FILT_LWR1 = 0x53,
|
||||
ADDR_MSK_LWR0 = 0x70,
|
||||
ADDR_MSK_UPR0 = 0x71,
|
||||
ADDR_MSK_LWR1 = 0x72,
|
||||
ADDR_MSK_UPR1 = 0x73,
|
||||
RX_FSIZE = 0x90,
|
||||
RX = 0x91,
|
||||
}
|
||||
|
||||
impl From<SpiRegisters> for u16 {
|
||||
fn from(val: SpiRegisters) -> Self {
|
||||
val as u16
|
||||
}
|
||||
}
|
||||
|
||||
impl From<u16> for SpiRegisters {
|
||||
fn from(value: u16) -> Self {
|
||||
match value {
|
||||
0x00 => Self::IDVER,
|
||||
0x01 => Self::PHYID,
|
||||
0x02 => Self::CAPABILITY,
|
||||
0x03 => Self::RESET,
|
||||
0x04 => Self::CONFIG0,
|
||||
0x06 => Self::CONFIG2,
|
||||
0x08 => Self::STATUS0,
|
||||
0x09 => Self::STATUS1,
|
||||
0x0C => Self::IMASK0,
|
||||
0x0D => Self::IMASK1,
|
||||
0x20 => Self::MDIO_ACC,
|
||||
0x30 => Self::TX_FSIZE,
|
||||
0x31 => Self::TX,
|
||||
0x32 => Self::TX_SPACE,
|
||||
0x36 => Self::FIFO_CLR,
|
||||
0x50 => Self::ADDR_FILT_UPR0,
|
||||
0x51 => Self::ADDR_FILT_LWR0,
|
||||
0x52 => Self::ADDR_FILT_UPR1,
|
||||
0x53 => Self::ADDR_FILT_LWR1,
|
||||
0x70 => Self::ADDR_MSK_LWR0,
|
||||
0x71 => Self::ADDR_MSK_UPR0,
|
||||
0x72 => Self::ADDR_MSK_LWR1,
|
||||
0x73 => Self::ADDR_MSK_UPR1,
|
||||
0x90 => Self::RX_FSIZE,
|
||||
0x91 => Self::RX,
|
||||
e => panic!("Unknown value {e}"),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Register definitions
|
||||
bitfield! {
|
||||
/// Status0 Register bits
|
||||
pub struct Status0(u32);
|
||||
impl Debug;
|
||||
u32;
|
||||
/// Control Data Protection Error
|
||||
pub cdpe, _ : 12;
|
||||
/// Transmit Frame Check Squence Error
|
||||
pub txfcse, _: 11;
|
||||
/// Transmit Time Stamp Capture Available C
|
||||
pub ttscac, _ : 10;
|
||||
/// Transmit Time Stamp Capture Available B
|
||||
pub ttscab, _ : 9;
|
||||
/// Transmit Time Stamp Capture Available A
|
||||
pub ttscaa, _ : 8;
|
||||
/// PHY Interrupt for Port 1
|
||||
pub phyint, _ : 7;
|
||||
/// Reset Complete
|
||||
pub resetc, _ : 6;
|
||||
/// Header error
|
||||
pub hdre, _ : 5;
|
||||
/// Loss of Frame Error
|
||||
pub lofe, _ : 4;
|
||||
/// Receiver Buffer Overflow Error
|
||||
pub rxboe, _ : 3;
|
||||
/// Host Tx FIFO Under Run Error
|
||||
pub txbue, _ : 2;
|
||||
/// Host Tx FIFO Overflow
|
||||
pub txboe, _ : 1;
|
||||
/// Transmit Protocol Error
|
||||
pub txpe, _ : 0;
|
||||
}
|
||||
|
||||
bitfield! {
|
||||
/// Status1 Register bits
|
||||
pub struct Status1(u32);
|
||||
impl Debug;
|
||||
u32;
|
||||
/// ECC Error on Reading the Frame Size from a Tx FIFO
|
||||
pub tx_ecc_err, set_tx_ecc_err: 12;
|
||||
/// ECC Error on Reading the Frame Size from an Rx FIFO
|
||||
pub rx_ecc_err, set_rx_ecc_err : 11;
|
||||
/// Detected an Error on an SPI Transaction
|
||||
pub spi_err, set_spi_err: 10;
|
||||
/// Rx MAC Interframe Gap Error
|
||||
pub p1_rx_ifg_err, set_p1_rx_ifg_err : 8;
|
||||
/// Port1 Rx Ready High Priority
|
||||
pub p1_rx_rdy_hi, set_p1_rx_rdy_hi : 5;
|
||||
/// Port 1 Rx FIFO Contains Data
|
||||
pub p1_rx_rdy, set_p1_rx_rdy : 4;
|
||||
/// Tx Ready
|
||||
pub tx_rdy, set_tx_rdy : 3;
|
||||
/// Link Status Changed
|
||||
pub link_change, set_link_change : 1;
|
||||
/// Port 1 Link Status
|
||||
pub p1_link_status, _ : 0;
|
||||
}
|
||||
|
||||
bitfield! {
|
||||
/// Config0 Register bits
|
||||
pub struct Config0(u32);
|
||||
impl Debug;
|
||||
u32;
|
||||
/// Configuration Synchronization
|
||||
pub sync, set_sync : 15;
|
||||
/// Transmit Frame Check Sequence Validation Enable
|
||||
pub txfcsve, set_txfcsve : 14;
|
||||
/// !CS Align Receive Frame Enable
|
||||
pub csarfe, set_csarfe : 13;
|
||||
/// Zero Align Receive Frame Enable
|
||||
pub zarfe, set_zarfe : 12;
|
||||
/// Transmit Credit Threshold
|
||||
pub tcxthresh, set_tcxthresh : 11, 10;
|
||||
/// Transmit Cut Through Enable
|
||||
pub txcte, set_txcte : 9;
|
||||
/// Receive Cut Through Enable
|
||||
pub rxcte, set_rxcte : 8;
|
||||
/// Frame Time Stamp Enable
|
||||
pub ftse, set_ftse : 7;
|
||||
/// Receive Frame Time Stamp Select
|
||||
pub ftss, set_ftss : 6;
|
||||
/// Enable Control Data Read Write Protection
|
||||
pub prote, set_prote : 5;
|
||||
/// Enable TX Data Chunk Sequence and Retry
|
||||
pub seqe, set_seqe : 4;
|
||||
/// Chunk Payload Selector (N).
|
||||
pub cps, set_cps : 2, 0;
|
||||
}
|
||||
|
||||
bitfield! {
|
||||
/// Config2 Register bits
|
||||
pub struct Config2(u32);
|
||||
impl Debug;
|
||||
u32;
|
||||
/// Assert TX_RDY When the Tx FIFO is Empty
|
||||
pub tx_rdy_on_empty, set_tx_rdy_on_empty : 8;
|
||||
/// Determines If the SFD is Detected in the PHY or MAC
|
||||
pub sdf_detect_src, set_sdf_detect_src : 7;
|
||||
/// Statistics Clear on Reading
|
||||
pub stats_clr_on_rd, set_stats_clr_on_rd : 6;
|
||||
/// Enable CRC Append
|
||||
pub crc_append, set_crc_append : 5;
|
||||
/// Admit Frames with IFG Errors on Port 1 (P1)
|
||||
pub p1_rcv_ifg_err_frm, set_p1_rcv_ifg_err_frm : 4;
|
||||
/// Forward Frames Not Matching Any MAC Address to the Host
|
||||
pub p1_fwd_unk2host, set_p1_fwd_unk2host : 2;
|
||||
/// SPI to MDIO Bridge MDC Clock Speed
|
||||
pub mspeed, set_mspeed : 0;
|
||||
}
|
||||
|
||||
bitfield! {
|
||||
/// IMASK0 Register bits
|
||||
pub struct IMask0(u32);
|
||||
impl Debug;
|
||||
u32;
|
||||
/// Control Data Protection Error Mask
|
||||
pub cppem, set_cppem : 12;
|
||||
/// Transmit Frame Check Sequence Error Mask
|
||||
pub txfcsem, set_txfcsem : 11;
|
||||
/// Transmit Time Stamp Capture Available C Mask
|
||||
pub ttscacm, set_ttscacm : 10;
|
||||
/// Transmit Time Stamp Capture Available B Mask
|
||||
pub ttscabm, set_ttscabm : 9;
|
||||
/// Transmit Time Stamp Capture Available A Mask
|
||||
pub ttscaam, set_ttscaam : 8;
|
||||
/// Physical Layer Interrupt Mask
|
||||
pub phyintm, set_phyintm : 7;
|
||||
/// RESET Complete Mask
|
||||
pub resetcm, set_resetcm : 6;
|
||||
/// Header Error Mask
|
||||
pub hdrem, set_hdrem : 5;
|
||||
/// Loss of Frame Error Mask
|
||||
pub lofem, set_lofem : 4;
|
||||
/// Receive Buffer Overflow Error Mask
|
||||
pub rxboem, set_rxboem : 3;
|
||||
/// Transmit Buffer Underflow Error Mask
|
||||
pub txbuem, set_txbuem : 2;
|
||||
/// Transmit Buffer Overflow Error Mask
|
||||
pub txboem, set_txboem : 1;
|
||||
/// Transmit Protocol Error Mask
|
||||
pub txpem, set_txpem : 0;
|
||||
}
|
||||
|
||||
bitfield! {
|
||||
/// IMASK1 Register bits
|
||||
pub struct IMask1(u32);
|
||||
impl Debug;
|
||||
u32;
|
||||
/// Mask Bit for TXF_ECC_ERR
|
||||
pub tx_ecc_err_mask, set_tx_ecc_err_mask : 12;
|
||||
/// Mask Bit for RXF_ECC_ERR
|
||||
pub rx_ecc_err_mask, set_rx_ecc_err_mask : 11;
|
||||
/// Mask Bit for SPI_ERR
|
||||
/// This field is only used with the generic SPI protocol
|
||||
pub spi_err_mask, set_spi_err_mask : 10;
|
||||
/// Mask Bit for RX_IFG_ERR
|
||||
pub p1_rx_ifg_err_mask, set_p1_rx_ifg_err_mask : 8;
|
||||
/// Mask Bit for P1_RX_RDY
|
||||
/// This field is only used with the generic SPI protocol
|
||||
pub p1_rx_rdy_mask, set_p1_rx_rdy_mask : 4;
|
||||
/// Mask Bit for TX_FRM_DONE
|
||||
/// This field is only used with the generic SPI protocol
|
||||
pub tx_rdy_mask, set_tx_rdy_mask : 3;
|
||||
/// Mask Bit for LINK_CHANGE
|
||||
pub link_change_mask, set_link_change_mask : 1;
|
||||
}
|
||||
|
||||
/// LED Functions
|
||||
#[repr(u8)]
|
||||
pub enum LedFunc {
|
||||
LinkupTxRxActicity = 0,
|
||||
LinkupTxActicity,
|
||||
LinkupRxActicity,
|
||||
LinkupOnly,
|
||||
TxRxActivity,
|
||||
TxActivity,
|
||||
RxActivity,
|
||||
LinkupRxEr,
|
||||
LinkupRxTxEr,
|
||||
RxEr,
|
||||
RxTxEr,
|
||||
TxSop,
|
||||
RxSop,
|
||||
On,
|
||||
Off,
|
||||
Blink,
|
||||
TxLevel2P4,
|
||||
TxLevel1P0,
|
||||
Master,
|
||||
Slave,
|
||||
IncompatiableLinkCfg,
|
||||
AnLinkGood,
|
||||
AnComplete,
|
||||
TsTimer,
|
||||
LocRcvrStatus,
|
||||
RemRcvrStatus,
|
||||
Clk25Ref,
|
||||
TxTCLK,
|
||||
Clk120MHz,
|
||||
}
|
||||
|
||||
impl From<LedFunc> for u8 {
|
||||
fn from(val: LedFunc) -> Self {
|
||||
val as u8
|
||||
}
|
||||
}
|
||||
|
||||
impl From<u8> for LedFunc {
|
||||
fn from(value: u8) -> Self {
|
||||
match value {
|
||||
0 => LedFunc::LinkupTxRxActicity,
|
||||
1 => LedFunc::LinkupTxActicity,
|
||||
2 => LedFunc::LinkupRxActicity,
|
||||
3 => LedFunc::LinkupOnly,
|
||||
4 => LedFunc::TxRxActivity,
|
||||
5 => LedFunc::TxActivity,
|
||||
6 => LedFunc::RxActivity,
|
||||
7 => LedFunc::LinkupRxEr,
|
||||
8 => LedFunc::LinkupRxTxEr,
|
||||
9 => LedFunc::RxEr,
|
||||
10 => LedFunc::RxTxEr,
|
||||
11 => LedFunc::TxSop,
|
||||
12 => LedFunc::RxSop,
|
||||
13 => LedFunc::On,
|
||||
14 => LedFunc::Off,
|
||||
15 => LedFunc::Blink,
|
||||
16 => LedFunc::TxLevel2P4,
|
||||
17 => LedFunc::TxLevel1P0,
|
||||
18 => LedFunc::Master,
|
||||
19 => LedFunc::Slave,
|
||||
20 => LedFunc::IncompatiableLinkCfg,
|
||||
21 => LedFunc::AnLinkGood,
|
||||
22 => LedFunc::AnComplete,
|
||||
23 => LedFunc::TsTimer,
|
||||
24 => LedFunc::LocRcvrStatus,
|
||||
25 => LedFunc::RemRcvrStatus,
|
||||
26 => LedFunc::Clk25Ref,
|
||||
27 => LedFunc::TxTCLK,
|
||||
28 => LedFunc::Clk120MHz,
|
||||
e => panic!("Invalid value {e}"),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// LED Control Register
|
||||
#[derive(Copy, Clone, PartialEq, Eq, Hash)]
|
||||
pub struct LedCntrl(pub u16);
|
||||
bitfield_bitrange! {struct LedCntrl(u16)}
|
||||
|
||||
impl LedCntrl {
|
||||
bitfield_fields! {
|
||||
u8;
|
||||
/// LED 0 Pin Function
|
||||
pub from into LedFunc, led0_function, set_led0_function: 4, 0;
|
||||
/// LED 0 Mode Selection
|
||||
pub led0_mode, set_led0_mode: 5;
|
||||
/// Qualify Certain LED 0 Options with Link Status.
|
||||
pub led0_link_st_qualify, set_led0_link_st_qualify: 6;
|
||||
/// LED 0 Enable
|
||||
pub led0_en, set_led0_en: 7;
|
||||
/// LED 1 Pin Function
|
||||
pub from into LedFunc, led1_function, set_led1_function: 12, 8;
|
||||
/// /// LED 1 Mode Selection
|
||||
pub led1_mode, set_led1_mode: 13;
|
||||
/// Qualify Certain LED 1 Options with Link Status.
|
||||
pub led1_link_st_qualify, set_led1_link_st_qualify: 14;
|
||||
/// LED 1 Enable
|
||||
pub led1_en, set_led1_en: 15;
|
||||
}
|
||||
|
||||
pub fn new() -> Self {
|
||||
LedCntrl(0)
|
||||
}
|
||||
}
|
||||
|
||||
// LED Polarity
|
||||
#[repr(u8)]
|
||||
pub enum LedPol {
|
||||
AutoSense = 0,
|
||||
ActiveHigh,
|
||||
ActiveLow,
|
||||
}
|
||||
|
||||
impl From<LedPol> for u8 {
|
||||
fn from(val: LedPol) -> Self {
|
||||
val as u8
|
||||
}
|
||||
}
|
||||
|
||||
impl From<u8> for LedPol {
|
||||
fn from(value: u8) -> Self {
|
||||
match value {
|
||||
0 => LedPol::AutoSense,
|
||||
1 => LedPol::ActiveHigh,
|
||||
2 => LedPol::ActiveLow,
|
||||
e => panic!("Invalid value {e}"),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// LED Control Register
|
||||
#[derive(Copy, Clone, PartialEq, Eq, Hash)]
|
||||
pub struct LedPolarity(pub u16);
|
||||
bitfield_bitrange! {struct LedPolarity(u16)}
|
||||
|
||||
impl LedPolarity {
|
||||
bitfield_fields! {
|
||||
u8;
|
||||
/// LED 1 Polarity
|
||||
pub from into LedPol, led1_polarity, set_led1_polarity: 3, 2;
|
||||
/// LED 0 Polarity
|
||||
pub from into LedPol, led0_polarity, set_led0_polarity: 1, 0;
|
||||
}
|
||||
}
|
||||
|
||||
/// SPI Header
|
||||
#[derive(Copy, Clone, PartialEq, Eq, Hash)]
|
||||
pub struct SpiHeader(pub u16);
|
||||
bitfield_bitrange! {struct SpiHeader(u16)}
|
||||
|
||||
impl SpiHeader {
|
||||
bitfield_fields! {
|
||||
u16;
|
||||
/// Mask Bit for TXF_ECC_ERR
|
||||
pub control, set_control : 15;
|
||||
pub full_duplex, set_full_duplex : 14;
|
||||
/// Read or Write to register
|
||||
pub write, set_write : 13;
|
||||
/// Registers ID/addr
|
||||
pub from into SpiRegisters, addr, set_addr: 11, 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
|
||||
#runner = "probe-rs run --chip STM32L475VGT6"
|
||||
#runner = "probe-rs run --chip STM32L475VG"
|
||||
runner = "probe-rs run --chip STM32L4S5VI"
|
||||
runner = "probe-run --chip STM32L4S5QI"
|
||||
|
||||
[build]
|
||||
target = "thumbv7em-none-eabi"
|
||||
|
|
|
|||
|
|
@ -6,12 +6,17 @@ license = "MIT OR Apache-2.0"
|
|||
|
||||
[dependencies]
|
||||
# Change stm32l4s5vi to your chip name, if necessary.
|
||||
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "unstable-pac", "stm32l4s5vi", "memory-x", "time-driver-any", "exti", "unstable-traits", "chrono"] }
|
||||
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "unstable-pac", "stm32l4s5qi", "memory-x", "time-driver-any", "exti", "unstable-traits", "chrono"] }
|
||||
embassy-sync = { version = "0.2.0", path = "../../embassy-sync", features = ["defmt"] }
|
||||
embassy-executor = { version = "0.3.0", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
|
||||
embassy-time = { version = "0.1.2", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
|
||||
embassy-time = { version = "0.1.2", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768", "unstable-traits", "nightly"] }
|
||||
embassy-embedded-hal = { version = "0.1.0", path = "../../embassy-embedded-hal" }
|
||||
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
|
||||
embassy-net-adin1110 = { version = "0.1.0", path = "../../embassy-net-adin1110", default-features = false }
|
||||
embassy-net = { version = "0.1.0", path = "../../embassy-net", features = ["defmt", "nightly", "udp", "tcp", "dhcpv4", "medium-ethernet"] }
|
||||
embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
|
||||
embedded-io-async = { version = "0.5.0", features = ["defmt-03"] }
|
||||
embedded-io = { version = "0.5.0", features = ["defmt-03"] }
|
||||
|
||||
defmt = "0.3"
|
||||
defmt-rtt = "0.4"
|
||||
|
|
@ -21,10 +26,13 @@ cortex-m-rt = "0.7.0"
|
|||
embedded-hal = "0.2.6"
|
||||
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
|
||||
embedded-hal-async = { version = "=1.0.0-rc.1" }
|
||||
embedded-hal-bus = { version = "=0.1.0-rc.1", features = ["async"] }
|
||||
panic-probe = { version = "0.3", features = ["print-defmt"] }
|
||||
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
|
||||
heapless = { version = "0.7.5", default-features = false }
|
||||
chrono = { version = "^0.4", default-features = false }
|
||||
rand = { version = "0.8.5", default-features = false }
|
||||
static_cell = {version = "1.1", features = ["nightly"]}
|
||||
|
||||
micromath = "2.0.0"
|
||||
|
||||
|
|
|
|||
438
examples/stm32l4/src/bin/spe_adin1110_http_server.rs
Normal file
438
examples/stm32l4/src/bin/spe_adin1110_http_server.rs
Normal file
|
|
@ -0,0 +1,438 @@
|
|||
#![deny(clippy::pedantic)]
|
||||
#![allow(clippy::doc_markdown)]
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
// Needed unitl https://github.com/rust-lang/rust/issues/63063 is stablised.
|
||||
#![feature(type_alias_impl_trait)]
|
||||
#![feature(associated_type_bounds)]
|
||||
#![allow(clippy::missing_errors_doc)]
|
||||
|
||||
// This example works on a ANALOG DEVICE EVAL-ADIN110EBZ board.
|
||||
// Settings switch S201 "HW CFG":
|
||||
// - Without SPI CRC: OFF-ON-OFF-OFF-OFF
|
||||
// - With SPI CRC: ON -ON-OFF-OFF-OFF
|
||||
// Settings switch S303 "uC CFG": CFG0: On = static ip, Off = Dhcp
|
||||
// The webserver shows the actual temperature of the onboard i2c temp sensor.
|
||||
|
||||
use core::marker::PhantomData;
|
||||
use core::sync::atomic::{AtomicI32, Ordering};
|
||||
|
||||
use defmt::{error, info, println, unwrap, Format};
|
||||
use defmt_rtt as _; // global logger
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_futures::select::{select, Either};
|
||||
use embassy_futures::yield_now;
|
||||
use embassy_net::tcp::TcpSocket;
|
||||
use embassy_net::{Ipv4Address, Ipv4Cidr, Stack, StackResources, StaticConfigV4};
|
||||
use embassy_time::{Delay, Duration, Ticker, Timer};
|
||||
use embedded_hal_async::i2c::I2c as I2cBus;
|
||||
use embedded_io::Write as bWrite;
|
||||
use embedded_io_async::Write;
|
||||
use hal::gpio::{Input, Level, Output, Speed};
|
||||
use hal::i2c::{self, I2c};
|
||||
use hal::rcc::{self};
|
||||
use hal::rng::{self, Rng};
|
||||
use hal::{bind_interrupts, exti, pac, peripherals};
|
||||
use heapless::Vec;
|
||||
use rand::RngCore;
|
||||
use static_cell::make_static;
|
||||
use {embassy_stm32 as hal, panic_probe as _};
|
||||
|
||||
bind_interrupts!(struct Irqs {
|
||||
I2C3_EV => i2c::InterruptHandler<peripherals::I2C3>;
|
||||
RNG => rng::InterruptHandler<peripherals::RNG>;
|
||||
});
|
||||
|
||||
use embassy_net_adin1110::{self, Device, Runner, ADIN1110};
|
||||
use embedded_hal_bus::spi::ExclusiveDevice;
|
||||
use hal::gpio::Pull;
|
||||
use hal::i2c::Config as I2C_Config;
|
||||
use hal::rcc::{ClockSrc, PLLClkDiv, PLLMul, PLLSource, PLLSrcDiv};
|
||||
use hal::spi::{Config as SPI_Config, Spi};
|
||||
use hal::time::Hertz;
|
||||
|
||||
// Basic settings
|
||||
// MAC-address used by the adin1110
|
||||
const MAC: [u8; 6] = [0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff];
|
||||
// Static IP settings
|
||||
const IP_ADDRESS: Ipv4Cidr = Ipv4Cidr::new(Ipv4Address([192, 168, 1, 5]), 24);
|
||||
// Listen port for the webserver
|
||||
const HTTP_LISTEN_PORT: u16 = 80;
|
||||
|
||||
pub type SpeSpi = Spi<'static, peripherals::SPI2, peripherals::DMA1_CH1, peripherals::DMA1_CH2>;
|
||||
pub type SpeSpiCs = ExclusiveDevice<SpeSpi, Output<'static, peripherals::PB12>, Delay>;
|
||||
pub type SpeInt = exti::ExtiInput<'static, peripherals::PB11>;
|
||||
pub type SpeRst = Output<'static, peripherals::PC7>;
|
||||
pub type Adin1110T = ADIN1110<SpeSpiCs>;
|
||||
pub type TempSensI2c = I2c<'static, peripherals::I2C3, peripherals::DMA1_CH6, peripherals::DMA1_CH7>;
|
||||
|
||||
static TEMP: AtomicI32 = AtomicI32::new(0);
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(spawner: Spawner) {
|
||||
defmt::println!("Start main()");
|
||||
|
||||
let mut config = embassy_stm32::Config::default();
|
||||
|
||||
// 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
|
||||
// 80MHz highest frequency for flash 0 wait.
|
||||
config.rcc.mux = ClockSrc::PLL(
|
||||
PLLSource::HSE(Hertz(8_000_000)),
|
||||
PLLClkDiv::Div2,
|
||||
PLLSrcDiv::Div1,
|
||||
PLLMul::Mul20,
|
||||
None,
|
||||
);
|
||||
config.rcc.hsi48 = true; // needed for rng
|
||||
config.rcc.rtc_mux = rcc::RtcClockSource::LSI32;
|
||||
|
||||
let dp = embassy_stm32::init(config);
|
||||
|
||||
// RM0432rev9, 5.1.2: Independent I/O supply rail
|
||||
// After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and
|
||||
// therefore are not available. The isolation must be removed before using any I/O from
|
||||
// PG[15:2], by setting the IOSV bit in the PWR_CR2 register, once the VDDIO2 supply is present
|
||||
pac::PWR.cr2().modify(|w| w.set_iosv(true));
|
||||
|
||||
let reset_status = pac::RCC.bdcr().read().0;
|
||||
defmt::println!("bdcr before: 0x{:X}", reset_status);
|
||||
|
||||
defmt::println!("Setup IO pins");
|
||||
|
||||
// Setup LEDs
|
||||
let _led_uc1_green = Output::new(dp.PC13, Level::Low, Speed::Low);
|
||||
let mut led_uc2_red = Output::new(dp.PE2, Level::High, Speed::Low);
|
||||
let led_uc3_yellow = Output::new(dp.PE6, Level::High, Speed::Low);
|
||||
let led_uc4_blue = Output::new(dp.PG15, Level::High, Speed::Low);
|
||||
|
||||
// Read the uc_cfg switches
|
||||
let uc_cfg0 = Input::new(dp.PB2, Pull::None);
|
||||
let _uc_cfg1 = Input::new(dp.PF11, Pull::None);
|
||||
let _uc_cfg2 = Input::new(dp.PG6, Pull::None);
|
||||
let _uc_cfg3 = Input::new(dp.PG11, Pull::None);
|
||||
|
||||
// Setup I2C pins
|
||||
let temp_sens_i2c = I2c::new(
|
||||
dp.I2C3,
|
||||
dp.PG7,
|
||||
dp.PG8,
|
||||
Irqs,
|
||||
dp.DMA1_CH6,
|
||||
dp.DMA1_CH7,
|
||||
Hertz(100_000),
|
||||
I2C_Config::default(),
|
||||
);
|
||||
|
||||
// Setup IO and SPI for the SPE chip
|
||||
let spe_reset_n = Output::new(dp.PC7, Level::Low, Speed::Low);
|
||||
let spe_cfg0 = Input::new(dp.PC8, Pull::None);
|
||||
let spe_cfg1 = Input::new(dp.PC9, Pull::None);
|
||||
let _spe_ts_capt = Output::new(dp.PC6, Level::Low, Speed::Low);
|
||||
|
||||
let spe_int = Input::new(dp.PB11, Pull::None);
|
||||
let spe_int = exti::ExtiInput::new(spe_int, dp.EXTI11);
|
||||
|
||||
let spe_spi_cs_n = Output::new(dp.PB12, Level::High, Speed::High);
|
||||
let spe_spi_sclk = dp.PB13;
|
||||
let spe_spi_miso = dp.PB14;
|
||||
let spe_spi_mosi = dp.PB15;
|
||||
|
||||
// Don't turn the clock to high, clock must fit within the system clock as we get a runtime panic.
|
||||
let mut spi_config = SPI_Config::default();
|
||||
spi_config.frequency = Hertz(25_000_000);
|
||||
|
||||
let spe_spi: SpeSpi = Spi::new(
|
||||
dp.SPI2,
|
||||
spe_spi_sclk,
|
||||
spe_spi_mosi,
|
||||
spe_spi_miso,
|
||||
dp.DMA1_CH1,
|
||||
dp.DMA1_CH2,
|
||||
spi_config,
|
||||
);
|
||||
let spe_spi = SpeSpiCs::new(spe_spi, spe_spi_cs_n, Delay);
|
||||
|
||||
let cfg0_without_crc = spe_cfg0.is_high();
|
||||
let cfg1_spi_mode = spe_cfg1.is_high();
|
||||
|
||||
defmt::println!(
|
||||
"ADIN1110: CFG SPI-MODE 1-{}, CRC-bit 0-{}",
|
||||
cfg1_spi_mode,
|
||||
cfg0_without_crc
|
||||
);
|
||||
|
||||
// Check the SPI mode selected with the "HW CFG" dip-switch
|
||||
if !cfg1_spi_mode {
|
||||
error!("Driver doesn´t support SPI Protolcol \"OPEN Alliance\".\nplease use the \"Generic SPI\"! Turn On \"HW CFG\": \"SPI_CFG1\"");
|
||||
loop {
|
||||
led_uc2_red.toggle();
|
||||
Timer::after(Duration::from_hz(10)).await;
|
||||
}
|
||||
};
|
||||
|
||||
let state = make_static!(embassy_net_adin1110::State::<8, 8>::new());
|
||||
|
||||
let (device, runner) =
|
||||
embassy_net_adin1110::new(MAC, state, spe_spi, spe_int, spe_reset_n, !cfg0_without_crc).await;
|
||||
|
||||
// Start task blink_led
|
||||
unwrap!(spawner.spawn(heartbeat_led(led_uc3_yellow)));
|
||||
// Start task temperature measurement
|
||||
unwrap!(spawner.spawn(temp_task(temp_sens_i2c, led_uc4_blue)));
|
||||
// Start ethernet task
|
||||
unwrap!(spawner.spawn(ethernet_task(runner)));
|
||||
|
||||
let mut rng = Rng::new(dp.RNG, Irqs);
|
||||
// Generate random seed
|
||||
let seed = rng.next_u64();
|
||||
|
||||
let ip_cfg = if uc_cfg0.is_low() {
|
||||
println!("Waiting for DHCP...");
|
||||
let dhcp4_config = embassy_net::DhcpConfig::default();
|
||||
embassy_net::Config::dhcpv4(dhcp4_config)
|
||||
} else {
|
||||
embassy_net::Config::ipv4_static(StaticConfigV4 {
|
||||
address: IP_ADDRESS,
|
||||
gateway: None,
|
||||
dns_servers: Vec::new(),
|
||||
})
|
||||
};
|
||||
|
||||
// Init network stack
|
||||
let stack = &*make_static!(Stack::new(
|
||||
device,
|
||||
ip_cfg,
|
||||
make_static!(StackResources::<2>::new()),
|
||||
seed
|
||||
));
|
||||
|
||||
// Launch network task
|
||||
unwrap!(spawner.spawn(net_task(stack)));
|
||||
|
||||
let cfg = wait_for_config(stack).await;
|
||||
let local_addr = cfg.address.address();
|
||||
|
||||
// Then we can use it!
|
||||
let mut rx_buffer = [0; 4096];
|
||||
let mut tx_buffer = [0; 4096];
|
||||
let mut mb_buf = [0; 4096];
|
||||
loop {
|
||||
let mut socket = TcpSocket::new(stack, &mut rx_buffer, &mut tx_buffer);
|
||||
socket.set_timeout(Some(Duration::from_secs(1)));
|
||||
|
||||
info!("Listening on http://{}:{}...", local_addr, HTTP_LISTEN_PORT);
|
||||
if let Err(e) = socket.accept(HTTP_LISTEN_PORT).await {
|
||||
defmt::error!("accept error: {:?}", e);
|
||||
continue;
|
||||
}
|
||||
|
||||
loop {
|
||||
let _n = match socket.read(&mut mb_buf).await {
|
||||
Ok(0) => {
|
||||
defmt::info!("read EOF");
|
||||
break;
|
||||
}
|
||||
Ok(n) => n,
|
||||
Err(e) => {
|
||||
defmt::error!("{:?}", e);
|
||||
break;
|
||||
}
|
||||
};
|
||||
led_uc2_red.set_low();
|
||||
|
||||
let status_line = "HTTP/1.1 200 OK";
|
||||
let contents = PAGE;
|
||||
let length = contents.len();
|
||||
|
||||
let _ = write!(
|
||||
&mut mb_buf[..],
|
||||
"{status_line}\r\nContent-Length: {length}\r\n\r\n{contents}\r\n\0"
|
||||
);
|
||||
let loc = mb_buf.iter().position(|v| *v == b'#').unwrap();
|
||||
|
||||
let temp = TEMP.load(Ordering::Relaxed);
|
||||
let cel = temp / 1000;
|
||||
let mcel = temp % 1000;
|
||||
|
||||
info!("{}.{}", cel, mcel);
|
||||
|
||||
let _ = write!(&mut mb_buf[loc..loc + 7], "{cel}.{mcel}");
|
||||
|
||||
let n = mb_buf.iter().position(|v| *v == 0).unwrap();
|
||||
|
||||
if let Err(e) = socket.write_all(&mb_buf[..n]).await {
|
||||
error!("write error: {:?}", e);
|
||||
break;
|
||||
}
|
||||
|
||||
led_uc2_red.set_high();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
async fn wait_for_config(stack: &'static Stack<Device<'static>>) -> embassy_net::StaticConfigV4 {
|
||||
loop {
|
||||
if let Some(config) = stack.config_v4() {
|
||||
return config;
|
||||
}
|
||||
yield_now().await;
|
||||
}
|
||||
}
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn heartbeat_led(mut led: Output<'static, peripherals::PE6>) {
|
||||
let mut tmr = Ticker::every(Duration::from_hz(3));
|
||||
loop {
|
||||
led.toggle();
|
||||
tmr.next().await;
|
||||
}
|
||||
}
|
||||
|
||||
// ADT7422
|
||||
#[embassy_executor::task]
|
||||
async fn temp_task(temp_dev_i2c: TempSensI2c, mut led: Output<'static, peripherals::PG15>) -> ! {
|
||||
let mut tmr = Ticker::every(Duration::from_hz(1));
|
||||
let mut temp_sens = ADT7422::new(temp_dev_i2c, 0x48).unwrap();
|
||||
|
||||
loop {
|
||||
led.set_low();
|
||||
match select(temp_sens.read_temp(), Timer::after(Duration::from_millis(500))).await {
|
||||
Either::First(i2c_ret) => match i2c_ret {
|
||||
Ok(value) => {
|
||||
led.set_high();
|
||||
let temp = i32::from(value);
|
||||
println!("TEMP: {:04x}, {}", temp, temp * 78 / 10);
|
||||
TEMP.store(temp * 78 / 10, Ordering::Relaxed);
|
||||
}
|
||||
Err(e) => defmt::println!("ADT7422: {}", e),
|
||||
},
|
||||
Either::Second(_) => println!("Timeout"),
|
||||
}
|
||||
|
||||
tmr.next().await;
|
||||
}
|
||||
}
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn ethernet_task(runner: Runner<'static, SpeSpiCs, SpeInt, SpeRst>) -> ! {
|
||||
runner.run().await
|
||||
}
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn net_task(stack: &'static Stack<Device<'static>>) -> ! {
|
||||
stack.run().await
|
||||
}
|
||||
|
||||
// same panicking *behavior* as `panic-probe` but doesn't print a panic message
|
||||
// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
|
||||
#[defmt::panic_handler]
|
||||
fn panic() -> ! {
|
||||
cortex_m::asm::udf()
|
||||
}
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[repr(C)]
|
||||
pub enum Registers {
|
||||
Temp_MSB = 0x00,
|
||||
Temp_LSB,
|
||||
Status,
|
||||
Cfg,
|
||||
T_HIGH_MSB,
|
||||
T_HIGH_LSB,
|
||||
T_LOW_MSB,
|
||||
T_LOW_LSB,
|
||||
T_CRIT_MSB,
|
||||
T_CRIT_LSB,
|
||||
T_HYST,
|
||||
ID,
|
||||
SW_RESET = 0x2F,
|
||||
}
|
||||
|
||||
pub struct ADT7422<'d, BUS: I2cBus> {
|
||||
addr: u8,
|
||||
phantom: PhantomData<&'d ()>,
|
||||
bus: BUS,
|
||||
}
|
||||
|
||||
#[derive(Debug, Format)]
|
||||
pub enum Error<I2cError: Format> {
|
||||
I2c(I2cError),
|
||||
Address,
|
||||
}
|
||||
|
||||
impl<'d, BUS> ADT7422<'d, BUS>
|
||||
where
|
||||
BUS: I2cBus,
|
||||
BUS::Error: Format,
|
||||
{
|
||||
pub fn new(bus: BUS, addr: u8) -> Result<Self, Error<BUS::Error>> {
|
||||
if !(0x48..=0x4A).contains(&addr) {
|
||||
return Err(Error::Address);
|
||||
}
|
||||
|
||||
Ok(Self {
|
||||
bus,
|
||||
phantom: PhantomData,
|
||||
addr,
|
||||
})
|
||||
}
|
||||
|
||||
pub async fn init(&mut self) -> Result<(), Error<BUS::Error>> {
|
||||
let mut cfg = 0b000_0000;
|
||||
// if self.int.is_some() {
|
||||
// // Set 1 SPS mode
|
||||
// cfg |= 0b10 << 5;
|
||||
// } else {
|
||||
// One shot mode
|
||||
cfg |= 0b01 << 5;
|
||||
// }
|
||||
|
||||
self.write_cfg(cfg).await
|
||||
}
|
||||
|
||||
pub async fn read(&mut self, reg: Registers) -> Result<u8, Error<BUS::Error>> {
|
||||
let mut buffer = [0u8; 1];
|
||||
self.bus
|
||||
.write_read(self.addr, &[reg as u8], &mut buffer)
|
||||
.await
|
||||
.map_err(Error::I2c)?;
|
||||
Ok(buffer[0])
|
||||
}
|
||||
|
||||
pub async fn write_cfg(&mut self, cfg: u8) -> Result<(), Error<BUS::Error>> {
|
||||
let buf = [Registers::Cfg as u8, cfg];
|
||||
self.bus.write(self.addr, &buf).await.map_err(Error::I2c)
|
||||
}
|
||||
|
||||
pub async fn read_temp(&mut self) -> Result<i16, Error<BUS::Error>> {
|
||||
let mut buffer = [0u8; 2];
|
||||
|
||||
// if let Some(int) = &mut self.int {
|
||||
// // Wait for interrupt
|
||||
// int.wait_for_low().await.unwrap();
|
||||
// } else {
|
||||
// Start: One shot
|
||||
let cfg = 0b01 << 5;
|
||||
self.write_cfg(cfg).await?;
|
||||
Timer::after(Duration::from_millis(250)).await;
|
||||
self.bus
|
||||
.write_read(self.addr, &[Registers::Temp_MSB as u8], &mut buffer)
|
||||
.await
|
||||
.map_err(Error::I2c)?;
|
||||
Ok(i16::from_be_bytes(buffer))
|
||||
}
|
||||
}
|
||||
|
||||
// Web page
|
||||
const PAGE: &str = r#"<!DOCTYPE html>
|
||||
<html lang="en">
|
||||
<head>
|
||||
<meta charset="utf-8">
|
||||
<meta http-equiv="refresh" content="1" >
|
||||
<title>ADIN1110 with Rust</title>
|
||||
</head>
|
||||
<body>
|
||||
<p>EVAL-ADIN1110EBZ</p>
|
||||
<table><td>Temp Sensor ADT7422:</td><td> #00.00 °C</td></table>
|
||||
</body>
|
||||
</html>"#;
|
||||
Loading…
Reference in a new issue