From 2a349afea791d2cb262497433a2ad24c3010a696 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 17 Jan 2023 18:54:23 +0100 Subject: [PATCH] stm32: add stm32c0 support. --- ci.sh | 2 +- ci_stable.sh | 2 +- embassy-stm32/Cargo.toml | 21 ++-- embassy-stm32/src/exti.rs | 16 +-- embassy-stm32/src/lib.rs | 2 +- embassy-stm32/src/rcc/c0.rs | 233 +++++++++++++++++++++++++++++++++++ embassy-stm32/src/rcc/mod.rs | 5 +- stm32-data | 2 +- stm32-metapac-gen/Cargo.toml | 2 +- stm32-metapac/Cargo.toml | 21 ++-- 10 files changed, 277 insertions(+), 29 deletions(-) create mode 100644 embassy-stm32/src/rcc/c0.rs diff --git a/ci.sh b/ci.sh index 30e664a2b..fc802f858 100755 --- a/ci.sh +++ b/ci.sh @@ -76,7 +76,7 @@ cargo batch \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f217zg,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features nightly,stm32l552ze,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features nightly,stm32wl54jc-cm0p,defmt,exti,time-driver-any,unstable-traits \ - --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32wle5ub,defmt,exti,time-driver-any,unstable-traits \ + --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32wle5jb,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f107vc,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f103re,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f100c4,defmt,exti,time-driver-any,unstable-traits \ diff --git a/ci_stable.sh b/ci_stable.sh index 60ddb659d..b4b0b83e7 100755 --- a/ci_stable.sh +++ b/ci_stable.sh @@ -36,7 +36,7 @@ cargo batch \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g491re,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585zi,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55vy,defmt,exti,time-driver-any,unstable-traits \ - --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55uc-cm4,defmt,exti,time-driver-any,unstable-traits \ + --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55cc-cm4,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l4r9zi,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f303vc,defmt,exti,time-driver-any,unstable-traits \ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f411ce,defmt,time-driver-any \ diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml index 67996cca4..d9c1f6dcf 100644 --- a/embassy-stm32/Cargo.toml +++ b/embassy-stm32/Cargo.toml @@ -19,6 +19,7 @@ flavors = [ { regex_feature = "stm32f3.*", target = "thumbv7em-none-eabi" }, { regex_feature = "stm32f42.*", target = "thumbv7em-none-eabi" }, { regex_feature = "stm32f7.*", target = "thumbv7em-none-eabi" }, + { regex_feature = "stm32c0.*", target = "thumbv6m-none-eabi" }, { regex_feature = "stm32g0.*", target = "thumbv6m-none-eabi" }, { regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi" }, { regex_feature = "stm32h7.*", target = "thumbv7em-none-eabi" }, @@ -110,6 +111,19 @@ unstable-traits = ["embedded-hal-1", "dep:embedded-hal-nb"] # BEGIN GENERATED FEATURES # Generated by stm32-gen-features. DO NOT EDIT. +stm32c011d6 = [ "stm32-metapac/stm32c011d6" ] +stm32c011f4 = [ "stm32-metapac/stm32c011f4" ] +stm32c011f6 = [ "stm32-metapac/stm32c011f6" ] +stm32c011j4 = [ "stm32-metapac/stm32c011j4" ] +stm32c011j6 = [ "stm32-metapac/stm32c011j6" ] +stm32c031c4 = [ "stm32-metapac/stm32c031c4" ] +stm32c031c6 = [ "stm32-metapac/stm32c031c6" ] +stm32c031f4 = [ "stm32-metapac/stm32c031f4" ] +stm32c031f6 = [ "stm32-metapac/stm32c031f6" ] +stm32c031g4 = [ "stm32-metapac/stm32c031g4" ] +stm32c031g6 = [ "stm32-metapac/stm32c031g6" ] +stm32c031k4 = [ "stm32-metapac/stm32c031k4" ] +stm32c031k6 = [ "stm32-metapac/stm32c031k6" ] stm32f030c6 = [ "stm32-metapac/stm32f030c6" ] stm32f030c8 = [ "stm32-metapac/stm32f030c8" ] stm32f030cc = [ "stm32-metapac/stm32f030cc" ] @@ -1318,11 +1332,9 @@ stm32u575zi = [ "stm32-metapac/stm32u575zi" ] stm32u585ai = [ "stm32-metapac/stm32u585ai" ] stm32u585ci = [ "stm32-metapac/stm32u585ci" ] stm32u585oi = [ "stm32-metapac/stm32u585oi" ] -stm32u585qe = [ "stm32-metapac/stm32u585qe" ] stm32u585qi = [ "stm32-metapac/stm32u585qi" ] stm32u585ri = [ "stm32-metapac/stm32u585ri" ] stm32u585vi = [ "stm32-metapac/stm32u585vi" ] -stm32u585ze = [ "stm32-metapac/stm32u585ze" ] stm32u585zi = [ "stm32-metapac/stm32u585zi" ] stm32wb10cc = [ "stm32-metapac/stm32wb10cc" ] stm32wb15cc = [ "stm32-metapac/stm32wb15cc" ] @@ -1340,7 +1352,6 @@ stm32wb55vc = [ "stm32-metapac/stm32wb55vc" ] stm32wb55ve = [ "stm32-metapac/stm32wb55ve" ] stm32wb55vg = [ "stm32-metapac/stm32wb55vg" ] stm32wb55vy = [ "stm32-metapac/stm32wb55vy" ] -stm32wb5mmg = [ "stm32-metapac/stm32wb5mmg" ] stm32wl54cc-cm4 = [ "stm32-metapac/stm32wl54cc-cm4" ] stm32wl54cc-cm0p = [ "stm32-metapac/stm32wl54cc-cm0p" ] stm32wl54jc-cm4 = [ "stm32-metapac/stm32wl54jc-cm4" ] @@ -1349,8 +1360,6 @@ stm32wl55cc-cm4 = [ "stm32-metapac/stm32wl55cc-cm4" ] stm32wl55cc-cm0p = [ "stm32-metapac/stm32wl55cc-cm0p" ] stm32wl55jc-cm4 = [ "stm32-metapac/stm32wl55jc-cm4" ] stm32wl55jc-cm0p = [ "stm32-metapac/stm32wl55jc-cm0p" ] -stm32wl55uc-cm4 = [ "stm32-metapac/stm32wl55uc-cm4" ] -stm32wl55uc-cm0p = [ "stm32-metapac/stm32wl55uc-cm0p" ] stm32wle4c8 = [ "stm32-metapac/stm32wle4c8" ] stm32wle4cb = [ "stm32-metapac/stm32wle4cb" ] stm32wle4cc = [ "stm32-metapac/stm32wle4cc" ] @@ -1363,6 +1372,4 @@ stm32wle5cc = [ "stm32-metapac/stm32wle5cc" ] stm32wle5j8 = [ "stm32-metapac/stm32wle5j8" ] stm32wle5jb = [ "stm32-metapac/stm32wle5jb" ] stm32wle5jc = [ "stm32-metapac/stm32wle5jc" ] -stm32wle5u8 = [ "stm32-metapac/stm32wle5u8" ] -stm32wle5ub = [ "stm32-metapac/stm32wle5ub" ] # END GENERATED FEATURES diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs index f90785815..c9c3ef62a 100644 --- a/embassy-stm32/src/exti.rs +++ b/embassy-stm32/src/exti.rs @@ -25,11 +25,11 @@ fn cpu_regs() -> pac::exti::Exti { EXTI } -#[cfg(not(any(exti_g0, exti_l5, gpio_v1, exti_u5)))] +#[cfg(not(any(exti_c0, exti_g0, exti_l5, gpio_v1, exti_u5)))] fn exticr_regs() -> pac::syscfg::Syscfg { pac::SYSCFG } -#[cfg(any(exti_g0, exti_l5, exti_u5))] +#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))] fn exticr_regs() -> pac::exti::Exti { EXTI } @@ -39,9 +39,9 @@ fn exticr_regs() -> pac::afio::Afio { } pub unsafe fn on_irq() { - #[cfg(not(any(exti_g0, exti_l5, exti_u5)))] + #[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))] let bits = EXTI.pr(0).read().0; - #[cfg(any(exti_g0, exti_l5, exti_u5))] + #[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))] let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0; // Mask all the channels that fired. @@ -53,9 +53,9 @@ pub unsafe fn on_irq() { } // Clear pending - #[cfg(not(any(exti_g0, exti_l5, exti_u5)))] + #[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))] EXTI.pr(0).write_value(Lines(bits)); - #[cfg(any(exti_g0, exti_l5, exti_u5))] + #[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))] { EXTI.rpr(0).write_value(Lines(bits)); EXTI.fpr(0).write_value(Lines(bits)); @@ -212,9 +212,9 @@ impl<'a> ExtiInputFuture<'a> { EXTI.ftsr(0).modify(|w| w.set_line(pin, falling)); // clear pending bit - #[cfg(not(any(exti_g0, exti_l5, exti_u5)))] + #[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))] EXTI.pr(0).write(|w| w.set_line(pin, true)); - #[cfg(any(exti_g0, exti_l5, exti_u5))] + #[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))] { EXTI.rpr(0).write(|w| w.set_line(pin, true)); EXTI.fpr(0).write(|w| w.set_line(pin, true)); diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs index 610c24888..eeaa04f67 100644 --- a/embassy-stm32/src/lib.rs +++ b/embassy-stm32/src/lib.rs @@ -121,7 +121,7 @@ pub fn init(config: Config) -> Peripherals { #[cfg(dbgmcu)] if config.enable_debug_during_sleep { crate::pac::DBGMCU.cr().modify(|cr| { - #[cfg(any(dbgmcu_f0, dbgmcu_g0, dbgmcu_u5))] + #[cfg(any(dbgmcu_f0, dbgmcu_c0, dbgmcu_g0, dbgmcu_u5))] { cr.set_dbg_stop(true); cr.set_dbg_standby(true); diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs new file mode 100644 index 000000000..6c7b36647 --- /dev/null +++ b/embassy-stm32/src/rcc/c0.rs @@ -0,0 +1,233 @@ +use crate::pac::flash::vals::Latency; +use crate::pac::rcc::vals::{Hpre, Hsidiv, Ppre, Sw}; +use crate::pac::{FLASH, RCC}; +use crate::rcc::{set_freqs, Clocks}; +use crate::time::Hertz; + +/// HSI speed +pub const HSI_FREQ: Hertz = Hertz(48_000_000); + +/// LSI speed +pub const LSI_FREQ: Hertz = Hertz(32_000); + +/// System clock mux source +#[derive(Clone, Copy)] +pub enum ClockSrc { + HSE(Hertz), + HSI(HSIPrescaler), + LSI, +} + +#[derive(Clone, Copy)] +pub enum HSIPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, + Div32, + Div64, + Div128, +} + +impl Into for HSIPrescaler { + fn into(self) -> Hsidiv { + match self { + HSIPrescaler::NotDivided => Hsidiv::DIV1, + HSIPrescaler::Div2 => Hsidiv::DIV2, + HSIPrescaler::Div4 => Hsidiv::DIV4, + HSIPrescaler::Div8 => Hsidiv::DIV8, + HSIPrescaler::Div16 => Hsidiv::DIV16, + HSIPrescaler::Div32 => Hsidiv::DIV32, + HSIPrescaler::Div64 => Hsidiv::DIV64, + HSIPrescaler::Div128 => Hsidiv::DIV128, + } + } +} + +/// AHB prescaler +#[derive(Clone, Copy, PartialEq)] +pub enum AHBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, + Div64, + Div128, + Div256, + Div512, +} + +/// APB prescaler +#[derive(Clone, Copy)] +pub enum APBPrescaler { + NotDivided, + Div2, + Div4, + Div8, + Div16, +} + +impl Into for APBPrescaler { + fn into(self) -> Ppre { + match self { + APBPrescaler::NotDivided => Ppre::DIV1, + APBPrescaler::Div2 => Ppre::DIV2, + APBPrescaler::Div4 => Ppre::DIV4, + APBPrescaler::Div8 => Ppre::DIV8, + APBPrescaler::Div16 => Ppre::DIV16, + } + } +} + +impl Into for AHBPrescaler { + fn into(self) -> Hpre { + match self { + AHBPrescaler::NotDivided => Hpre::DIV1, + AHBPrescaler::Div2 => Hpre::DIV2, + AHBPrescaler::Div4 => Hpre::DIV4, + AHBPrescaler::Div8 => Hpre::DIV8, + AHBPrescaler::Div16 => Hpre::DIV16, + AHBPrescaler::Div64 => Hpre::DIV64, + AHBPrescaler::Div128 => Hpre::DIV128, + AHBPrescaler::Div256 => Hpre::DIV256, + AHBPrescaler::Div512 => Hpre::DIV512, + } + } +} + +/// Clocks configutation +pub struct Config { + pub mux: ClockSrc, + pub ahb_pre: AHBPrescaler, + pub apb_pre: APBPrescaler, +} + +impl Default for Config { + #[inline] + fn default() -> Config { + Config { + mux: ClockSrc::HSI(HSIPrescaler::NotDivided), + ahb_pre: AHBPrescaler::NotDivided, + apb_pre: APBPrescaler::NotDivided, + } + } +} + +pub(crate) unsafe fn init(config: Config) { + let (sys_clk, sw) = match config.mux { + ClockSrc::HSI(div) => { + // Enable HSI + let div: Hsidiv = div.into(); + RCC.cr().write(|w| { + w.set_hsidiv(div); + w.set_hsion(true) + }); + while !RCC.cr().read().hsirdy() {} + + (HSI_FREQ.0 >> div.0, Sw::HSI) + } + ClockSrc::HSE(freq) => { + // Enable HSE + RCC.cr().write(|w| w.set_hseon(true)); + while !RCC.cr().read().hserdy() {} + + (freq.0, Sw::HSE) + } + ClockSrc::LSI => { + // Enable LSI + RCC.csr2().write(|w| w.set_lsion(true)); + while !RCC.csr2().read().lsirdy() {} + (LSI_FREQ.0, Sw::LSI) + } + }; + + // Determine the flash latency implied by the target clock speed + // RM0454 § 3.3.4: + let target_flash_latency = if sys_clk <= 24_000_000 { + Latency::WS0 + } else { + Latency::WS1 + }; + + // Increase the number of cycles we wait for flash if the new value is higher + // There's no harm in waiting a little too much before the clock change, but we'll + // crash immediately if we don't wait enough after the clock change + let mut set_flash_latency_after = false; + FLASH.acr().modify(|w| { + // Is the current flash latency less than what we need at the new SYSCLK? + if w.latency().0 <= target_flash_latency.0 { + // We must increase the number of wait states now + w.set_latency(target_flash_latency) + } else { + // We may decrease the number of wait states later + set_flash_latency_after = true; + } + + // RM0490 § 3.3.4: + // > Prefetch is enabled by setting the PRFTEN bit of the FLASH access control register + // > (FLASH_ACR). This feature is useful if at least one wait state is needed to access the + // > Flash memory. + // + // Enable flash prefetching if we have at least one wait state, and disable it otherwise. + w.set_prften(target_flash_latency.0 > 0); + }); + + if !set_flash_latency_after { + // Spin until the effective flash latency is compatible with the clock change + while FLASH.acr().read().latency().0 < target_flash_latency.0 {} + } + + // Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once + let (sw, hpre, ppre) = (sw.into(), config.ahb_pre.into(), config.apb_pre.into()); + RCC.cfgr().modify(|w| { + w.set_sw(sw); + w.set_hpre(hpre); + w.set_ppre(ppre); + }); + + if set_flash_latency_after { + // We can make the flash require fewer wait states + // Spin until the SYSCLK changes have taken effect + loop { + let cfgr = RCC.cfgr().read(); + if cfgr.sw() == sw && cfgr.hpre() == hpre && cfgr.ppre() == ppre { + break; + } + } + + // Set the flash latency to require fewer wait states + FLASH.acr().modify(|w| w.set_latency(target_flash_latency)); + } + + let ahb_div = match config.ahb_pre { + AHBPrescaler::NotDivided => 1, + AHBPrescaler::Div2 => 2, + AHBPrescaler::Div4 => 4, + AHBPrescaler::Div8 => 8, + AHBPrescaler::Div16 => 16, + AHBPrescaler::Div64 => 64, + AHBPrescaler::Div128 => 128, + AHBPrescaler::Div256 => 256, + AHBPrescaler::Div512 => 512, + }; + let ahb_freq = sys_clk / ahb_div; + + let (apb_freq, apb_tim_freq) = match config.apb_pre { + APBPrescaler::NotDivided => (ahb_freq, ahb_freq), + pre => { + let pre: Ppre = pre.into(); + let pre: u8 = 1 << (pre.0 - 3); + let freq = ahb_freq / pre as u32; + (freq, freq * 2) + } + }; + + set_freqs(Clocks { + sys: Hertz(sys_clk), + ahb1: Hertz(ahb_freq), + apb1: Hertz(apb_freq), + apb1_tim: Hertz(apb_tim_freq), + }); +} diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs index 1b1180c03..0a52089d1 100644 --- a/embassy-stm32/src/rcc/mod.rs +++ b/embassy-stm32/src/rcc/mod.rs @@ -10,6 +10,7 @@ use crate::time::Hertz; #[cfg_attr(rcc_f3, path = "f3.rs")] #[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")] #[cfg_attr(rcc_f7, path = "f7.rs")] +#[cfg_attr(rcc_c0, path = "c0.rs")] #[cfg_attr(rcc_g0, path = "g0.rs")] #[cfg_attr(rcc_g4, path = "g4.rs")] #[cfg_attr(any(rcc_h7, rcc_h7ab), path = "h7.rs")] @@ -30,9 +31,9 @@ pub struct Clocks { // APB pub apb1: Hertz, pub apb1_tim: Hertz, - #[cfg(not(rcc_g0))] + #[cfg(not(any(rcc_c0, rcc_g0)))] pub apb2: Hertz, - #[cfg(not(rcc_g0))] + #[cfg(not(any(rcc_c0, rcc_g0)))] pub apb2_tim: Hertz, #[cfg(any(rcc_wl5, rcc_wle, rcc_u5))] pub apb3: Hertz, diff --git a/stm32-data b/stm32-data index 844793fc3..96decdd61 160000 --- a/stm32-data +++ b/stm32-data @@ -1 +1 @@ -Subproject commit 844793fc3da2ba3f12ab6a69b78cd8e6fb5497b4 +Subproject commit 96decdd6114d78813c1f748fb878a45e1b03bf73 diff --git a/stm32-metapac-gen/Cargo.toml b/stm32-metapac-gen/Cargo.toml index 9598a5945..6d136ba6b 100644 --- a/stm32-metapac-gen/Cargo.toml +++ b/stm32-metapac-gen/Cargo.toml @@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0" [dependencies] regex = "1.5.4" -chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "28ffa8a19d84914089547f52900ffb5877a5dc23" } +chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "1d9e0a39a6acc291e50cabc4ed617a87f06d5e89" } serde = { version = "1.0.130", features = [ "derive" ] } serde_json = "1.0.87" serde_yaml = "0.8.21" diff --git a/stm32-metapac/Cargo.toml b/stm32-metapac/Cargo.toml index 9d5aba0c0..2605cf3d3 100644 --- a/stm32-metapac/Cargo.toml +++ b/stm32-metapac/Cargo.toml @@ -27,6 +27,7 @@ flavors = [ { regex_feature = "stm32f3.*", target = "thumbv7em-none-eabi" }, { regex_feature = "stm32f4.*", target = "thumbv7em-none-eabi" }, { regex_feature = "stm32f7.*", target = "thumbv7em-none-eabi" }, + { regex_feature = "stm32c0.*", target = "thumbv6m-none-eabi" }, { regex_feature = "stm32g0.*", target = "thumbv6m-none-eabi" }, { regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi" }, { regex_feature = "stm32h7.*", target = "thumbv7em-none-eabi" }, @@ -67,6 +68,19 @@ memory-x = [] # BEGIN GENERATED FEATURES # Generated by stm32-gen-features. DO NOT EDIT. +stm32c011d6 = [] +stm32c011f4 = [] +stm32c011f6 = [] +stm32c011j4 = [] +stm32c011j6 = [] +stm32c031c4 = [] +stm32c031c6 = [] +stm32c031f4 = [] +stm32c031f6 = [] +stm32c031g4 = [] +stm32c031g6 = [] +stm32c031k4 = [] +stm32c031k6 = [] stm32f030c6 = [] stm32f030c8 = [] stm32f030cc = [] @@ -1275,11 +1289,9 @@ stm32u575zi = [] stm32u585ai = [] stm32u585ci = [] stm32u585oi = [] -stm32u585qe = [] stm32u585qi = [] stm32u585ri = [] stm32u585vi = [] -stm32u585ze = [] stm32u585zi = [] stm32wb10cc = [] stm32wb15cc = [] @@ -1297,7 +1309,6 @@ stm32wb55vc = [] stm32wb55ve = [] stm32wb55vg = [] stm32wb55vy = [] -stm32wb5mmg = [] stm32wl54cc-cm4 = [] stm32wl54cc-cm0p = [] stm32wl54jc-cm4 = [] @@ -1306,8 +1317,6 @@ stm32wl55cc-cm4 = [] stm32wl55cc-cm0p = [] stm32wl55jc-cm4 = [] stm32wl55jc-cm0p = [] -stm32wl55uc-cm4 = [] -stm32wl55uc-cm0p = [] stm32wle4c8 = [] stm32wle4cb = [] stm32wle4cc = [] @@ -1320,6 +1329,4 @@ stm32wle5cc = [] stm32wle5j8 = [] stm32wle5jb = [] stm32wle5jc = [] -stm32wle5u8 = [] -stm32wle5ub = [] # END GENERATED FEATURES