From 2dcbe75cca84cc44fc2357091aec20d2d9d5be00 Mon Sep 17 00:00:00 2001
From: Marco Pastrello <marco.pastrello@gmail.com>
Date: Thu, 4 May 2023 23:51:42 +0200
Subject: [PATCH] beautify

---
 embassy-stm32/src/rcc/f1.rs | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index 620638ab..106acb09 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -28,7 +28,10 @@ pub struct Config {
 }
 
 pub(crate) unsafe fn init(config: Config) {
-    let pllsrcclk = config.hse.map(|hse| hse.0 / if config.pllxtpre {2} else {1}).unwrap_or(HSI_FREQ.0 / 2);
+    let pllsrcclk = config
+        .hse
+        .map(|hse| if config.pllxtpre { hse.0 / 2 } else { hse.0 })
+        .unwrap_or(HSI_FREQ.0 / 2);
 
     let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
     let pllmul = sysclk / pllsrcclk;
@@ -145,7 +148,11 @@ pub(crate) unsafe fn init(config: Config) {
     }
 
     if let Some(pllmul_bits) = pllmul_bits {
-        RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(if config.pllxtpre {1u8} else {0u8})));
+        {
+            let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
+            RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag)));
+        }
+
         // enable PLL and wait for it to be ready
         RCC.cfgr().modify(|w| {
             w.set_pllmul(Pllmul(pllmul_bits));