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beautify

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This commit is contained in:
Marco Pastrello 2023-05-04 23:51:42 +02:00
parent 5158014f3f
commit 2dcbe75cca
1 changed files with 9 additions and 2 deletions
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11
embassy-stm32/src/rcc/f1.rs
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@ -28,7 +28,10 @@ pub struct Config {
} }
pub(crate) unsafe fn init(config: Config) { pub(crate) unsafe fn init(config: Config) {
let pllsrcclk = config.hse.map(|hse| hse.0 / if config.pllxtpre {2} else {1}).unwrap_or(HSI_FREQ.0 / 2); let pllsrcclk = config
.hse
.map(|hse| if config.pllxtpre { hse.0 / 2 } else { hse.0 })
.unwrap_or(HSI_FREQ.0 / 2);
let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk); let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
let pllmul = sysclk / pllsrcclk; let pllmul = sysclk / pllsrcclk;
@ -145,7 +148,11 @@ pub(crate) unsafe fn init(config: Config) {
} }
if let Some(pllmul_bits) = pllmul_bits { if let Some(pllmul_bits) = pllmul_bits {
RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(if config.pllxtpre {1u8} else {0u8}))); {
let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag)));
}
// enable PLL and wait for it to be ready // enable PLL and wait for it to be ready
RCC.cfgr().modify(|w| { RCC.cfgr().modify(|w| {
w.set_pllmul(Pllmul(pllmul_bits)); w.set_pllmul(Pllmul(pllmul_bits));