nrf/uart: Add support for rx-only or tx-only BufferedUart.
This commit is contained in:
Dario Nieuwenhuis
parent
4fbe18f821
commit
2feed96c91
2 changed files with 255 additions and 108 deletions
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@ -27,7 +27,7 @@ use crate::ppi::{
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self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
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};
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use crate::timer::{Instance as TimerInstance, Timer};
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use crate::uarte::{apply_workaround_for_enable_anomaly, drop_tx_rx, Config, Instance as UarteInstance};
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use crate::uarte::{configure, drop_tx_rx, Config, Instance as UarteInstance};
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use crate::{interrupt, pac, Peripheral};
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mod sealed {
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@ -238,7 +238,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
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into_ref!(uarte, timer, rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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@ -275,7 +275,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
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into_ref!(uarte, timer, rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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@ -293,8 +293,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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}
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fn new_inner(
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peri: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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peri: PeripheralRef<'d, U>,
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timer: PeripheralRef<'d, T>,
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ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_group: PeripheralRef<'d, AnyGroup>,
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@ -306,114 +306,17 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(peri, timer);
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configure(U::regs(), config, cts.is_some());
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assert!(rx_buffer.len() % 2 == 0);
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let r = U::regs();
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let hwfc = cts.is_some();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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if let Some(pin) = &rts {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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// Initialize state
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let s = U::buffered_state();
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s.tx_count.store(0, Ordering::Relaxed);
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s.rx_started_count.store(0, Ordering::Relaxed);
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s.rx_ended_count.store(0, Ordering::Relaxed);
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s.rx_started.store(false, Ordering::Relaxed);
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let len = tx_buffer.len();
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unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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// Configure
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r.config.write(|w| {
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w.hwfc().bit(hwfc);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// clear errors
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let errors = r.errorsrc.read().bits();
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r.errorsrc.write(|w| unsafe { w.bits(errors) });
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r.events_rxstarted.reset();
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r.events_txstarted.reset();
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r.events_error.reset();
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r.events_endrx.reset();
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r.events_endtx.reset();
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// Enable interrupts
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r.intenclr.write(|w| unsafe { w.bits(!0) });
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r.intenset.write(|w| {
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w.endtx().set();
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w.rxstarted().set();
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w.error().set();
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w.endrx().set();
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w
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});
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// Enable UARTE instance
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apply_workaround_for_enable_anomaly(r);
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r.enable.write(|w| w.enable().enabled());
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// Configure byte counter.
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let timer = Timer::new_counter(timer);
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timer.cc(1).write(rx_buffer.len() as u32 * 2);
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timer.cc(1).short_compare_clear();
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timer.clear();
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timer.start();
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let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_rxdrdy), timer.task_count());
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ppi_ch1.enable();
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s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
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let mut ppi_group = PpiGroup::new(ppi_group);
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let mut ppi_ch2 = Ppi::new_one_to_two(
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ppi_ch2,
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Event::from_reg(&r.events_endrx),
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Task::from_reg(&r.tasks_startrx),
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ppi_group.task_disable_all(),
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);
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ppi_ch2.disable();
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ppi_group.add_channel(&ppi_ch2);
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let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer);
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let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
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U::Interrupt::pend();
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unsafe { U::Interrupt::enable() };
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let s = U::state();
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s.tx_rx_refcount.store(2, Ordering::Relaxed);
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U::state().tx_rx_refcount.store(2, Ordering::Relaxed);
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Self {
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tx: BufferedUarteTx {
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_peri: unsafe { peri.clone_unchecked() },
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},
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rx: BufferedUarteRx {
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_peri: peri,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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_ppi_group: ppi_group,
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},
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}
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Self { tx, rx }
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}
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/// Adjust the baud rate to the provided value.
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@ -469,6 +372,88 @@ pub struct BufferedUarteTx<'d, U: UarteInstance> {
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}
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impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
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/// Create a new BufferedUarteTx without hardware flow control.
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pub fn new(
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uarte: impl Peripheral<P = U> + 'd,
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_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(uarte, txd);
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Self::new_inner(uarte, txd.map_into(), None, config, tx_buffer)
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}
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/// Create a new BufferedUarte with hardware flow control (RTS/CTS)
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new_with_cts(
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uarte: impl Peripheral<P = U> + 'd,
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_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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cts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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tx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(uarte, txd, cts);
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Self::new_inner(uarte, txd.map_into(), Some(cts.map_into()), config, tx_buffer)
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}
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fn new_inner(
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peri: PeripheralRef<'d, U>,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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tx_buffer: &'d mut [u8],
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) -> Self {
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configure(U::regs(), config, cts.is_some());
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let this = Self::new_innerer(peri, txd, cts, tx_buffer);
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U::Interrupt::pend();
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unsafe { U::Interrupt::enable() };
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U::state().tx_rx_refcount.store(1, Ordering::Relaxed);
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this
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}
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fn new_innerer(
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peri: PeripheralRef<'d, U>,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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tx_buffer: &'d mut [u8],
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) -> Self {
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let r = U::regs();
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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// Initialize state
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let s = U::buffered_state();
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s.tx_count.store(0, Ordering::Relaxed);
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let len = tx_buffer.len();
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unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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r.events_txstarted.reset();
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// Enable interrupts
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r.intenset.write(|w| {
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w.endtx().set();
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w
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});
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Self { _peri: peri }
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}
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/// Write a buffer into this writer, returning how many bytes were written.
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pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
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poll_fn(move |cx| {
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@ -548,6 +533,168 @@ pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
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}
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impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
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/// Create a new BufferedUarte without hardware flow control.
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(uarte, timer, rxd, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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rxd.map_into(),
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None,
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config,
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rx_buffer,
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)
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}
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/// Create a new BufferedUarte with hardware flow control (RTS/CTS)
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///
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/// # Panics
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///
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/// Panics if `rx_buffer.len()` is odd.
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pub fn new_with_rts(
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uarte: impl Peripheral<P = U> + 'd,
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timer: impl Peripheral<P = T> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
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ppi_group: impl Peripheral<P = impl Group> + 'd,
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_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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rts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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) -> Self {
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into_ref!(uarte, timer, rxd, rts, ppi_ch1, ppi_ch2, ppi_group);
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Self::new_inner(
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uarte,
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timer,
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ppi_ch1.map_into(),
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ppi_ch2.map_into(),
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ppi_group.map_into(),
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rxd.map_into(),
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Some(rts.map_into()),
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config,
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rx_buffer,
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)
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}
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fn new_inner(
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peri: PeripheralRef<'d, U>,
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timer: PeripheralRef<'d, T>,
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ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_group: PeripheralRef<'d, AnyGroup>,
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rxd: PeripheralRef<'d, AnyPin>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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rx_buffer: &'d mut [u8],
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) -> Self {
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configure(U::regs(), config, rts.is_some());
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let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
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U::Interrupt::pend();
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unsafe { U::Interrupt::enable() };
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U::state().tx_rx_refcount.store(1, Ordering::Relaxed);
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this
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}
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fn new_innerer(
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peri: PeripheralRef<'d, U>,
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timer: PeripheralRef<'d, T>,
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ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
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ppi_group: PeripheralRef<'d, AnyGroup>,
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rxd: PeripheralRef<'d, AnyPin>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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rx_buffer: &'d mut [u8],
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) -> Self {
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assert!(rx_buffer.len() % 2 == 0);
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let r = U::regs();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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if let Some(pin) = &rts {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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// Initialize state
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let s = U::buffered_state();
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s.rx_started_count.store(0, Ordering::Relaxed);
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s.rx_ended_count.store(0, Ordering::Relaxed);
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s.rx_started.store(false, Ordering::Relaxed);
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let len = rx_buffer.len();
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unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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// clear errors
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let errors = r.errorsrc.read().bits();
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r.errorsrc.write(|w| unsafe { w.bits(errors) });
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r.events_rxstarted.reset();
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r.events_error.reset();
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r.events_endrx.reset();
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// Enable interrupts
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r.intenset.write(|w| {
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w.endtx().set();
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w.rxstarted().set();
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w.error().set();
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w.endrx().set();
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w
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});
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// Configure byte counter.
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let timer = Timer::new_counter(timer);
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timer.cc(1).write(rx_buffer.len() as u32 * 2);
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timer.cc(1).short_compare_clear();
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timer.clear();
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timer.start();
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let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_rxdrdy), timer.task_count());
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ppi_ch1.enable();
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s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
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let mut ppi_group = PpiGroup::new(ppi_group);
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let mut ppi_ch2 = Ppi::new_one_to_two(
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ppi_ch2,
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Event::from_reg(&r.events_endrx),
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Task::from_reg(&r.tasks_startrx),
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ppi_group.task_disable_all(),
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);
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ppi_ch2.disable();
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ppi_group.add_channel(&ppi_ch2);
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Self {
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_peri: peri,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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_ppi_group: ppi_group,
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}
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}
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/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
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pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
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let data = self.fill_buf().await?;
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@ -299,7 +299,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
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}
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}
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fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
|
||||
pub(crate) fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
|
||||
r.config.write(|w| {
|
||||
w.hwfc().bit(hardware_flow_control);
|
||||
w.parity().variant(config.parity);
|
||||
|
|
|
|||
Loading…
Reference in a new issue