stm32/eth_v2: update to new embassy-net trait, remove PeripheralMutex.
This commit is contained in:
Dario Nieuwenhuis
parent
8f30652109
commit
3005ee0178
4 changed files with 289 additions and 487 deletions
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@ -1,19 +1,10 @@
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use core::sync::atomic::{fence, Ordering};
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use embassy_net::{Packet, PacketBox, PacketBoxExt, PacketBuf};
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use vcell::VolatileCell;
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use crate::eth::{Packet, RX_BUFFER_SIZE, TX_BUFFER_SIZE};
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use crate::pac::ETH;
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#[non_exhaustive]
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#[derive(Debug, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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NoBufferAvailable,
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// TODO: Break down this error into several others
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TransmissionError,
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}
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/// Transmit and Receive Descriptor fields
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#[allow(dead_code)]
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mod emac_consts {
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@ -41,7 +32,7 @@ use emac_consts::*;
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/// * tdes2: buffer lengths
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/// * tdes3: control and payload/frame length
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#[repr(C)]
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struct TDes {
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pub(crate) struct TDes {
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tdes0: VolatileCell<u32>,
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tdes1: VolatileCell<u32>,
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tdes2: VolatileCell<u32>,
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@ -59,41 +50,26 @@ impl TDes {
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}
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/// Return true if this TDes is not currently owned by the DMA
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pub fn available(&self) -> bool {
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fn available(&self) -> bool {
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self.tdes3.get() & EMAC_DES3_OWN == 0
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}
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}
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pub(crate) struct TDesRing<const N: usize> {
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td: [TDes; N],
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buffers: [Option<PacketBuf>; N],
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tdidx: usize,
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pub(crate) struct TDesRing<'a> {
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descriptors: &'a mut [TDes],
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buffers: &'a mut [Packet<TX_BUFFER_SIZE>],
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index: usize,
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}
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impl<const N: usize> TDesRing<N> {
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pub const fn new() -> Self {
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const TDES: TDes = TDes::new();
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const BUFFERS: Option<PacketBuf> = None;
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impl<'a> TDesRing<'a> {
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/// Initialise this TDesRing. Assume TDesRing is corrupt.
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pub fn new(descriptors: &'a mut [TDes], buffers: &'a mut [Packet<TX_BUFFER_SIZE>]) -> Self {
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assert!(descriptors.len() > 0);
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assert!(descriptors.len() == buffers.len());
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Self {
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td: [TDES; N],
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buffers: [BUFFERS; N],
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tdidx: 0,
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}
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}
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/// Initialise this TDesRing. Assume TDesRing is corrupt
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///
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/// The current memory address of the buffers inside this TDesRing
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/// will be stored in the descriptors, so ensure the TDesRing is
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/// not moved after initialisation.
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pub(crate) fn init(&mut self) {
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assert!(N > 0);
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for td in self.td.iter_mut() {
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for td in descriptors.iter_mut() {
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*td = TDes::new();
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}
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self.tdidx = 0;
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// Initialize the pointers in the DMA engine. (There will be a memory barrier later
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// before the DMA engine is enabled.)
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@ -101,80 +77,60 @@ impl<const N: usize> TDesRing<N> {
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmactx_dlar().write(|w| w.0 = &self.td as *const _ as u32);
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dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1));
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dma.dmactx_dtpr().write(|w| w.0 = &self.td[0] as *const _ as u32);
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dma.dmactx_dlar().write(|w| w.0 = descriptors.as_mut_ptr() as u32);
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dma.dmactx_rlr().write(|w| w.set_tdrl((descriptors.len() as u16) - 1));
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dma.dmactx_dtpr().write(|w| w.0 = 0);
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}
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Self {
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descriptors,
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buffers,
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index: 0,
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}
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}
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/// Return true if a TDes is available for use
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pub(crate) fn available(&self) -> bool {
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self.td[self.tdidx].available()
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pub(crate) fn len(&self) -> usize {
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self.descriptors.len()
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}
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pub(crate) fn transmit(&mut self, pkt: PacketBuf) -> Result<(), Error> {
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if !self.available() {
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return Err(Error::NoBufferAvailable);
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/// Return the next available packet buffer for transmitting, or None
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pub(crate) fn available(&mut self) -> Option<&mut [u8]> {
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let d = &mut self.descriptors[self.index];
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if d.available() {
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Some(&mut self.buffers[self.index].0)
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} else {
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None
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}
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}
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let x = self.tdidx;
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let td = &mut self.td[x];
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let pkt_len = pkt.len();
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assert!(pkt_len as u32 <= EMAC_TDES2_B1L);
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let address = pkt.as_ptr() as u32;
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/// Transmit the packet written in a buffer returned by `available`.
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pub(crate) fn transmit(&mut self, len: usize) {
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let td = &mut self.descriptors[self.index];
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assert!(td.available());
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assert!(len as u32 <= EMAC_TDES2_B1L);
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// Read format
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td.tdes0.set(address);
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td.tdes2.set(pkt_len as u32 & EMAC_TDES2_B1L | EMAC_TDES2_IOC);
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td.tdes0.set(self.buffers[self.index].0.as_ptr() as u32);
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td.tdes2.set(len as u32 & EMAC_TDES2_B1L | EMAC_TDES2_IOC);
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// FD: Contains first buffer of packet
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// LD: Contains last buffer of packet
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// Give the DMA engine ownership
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td.tdes3.set(EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_OWN);
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self.buffers[x].replace(pkt);
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// Ensure changes to the descriptor are committed before DMA engine sees tail pointer store.
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// This will generate an DMB instruction.
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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// Move the tail pointer (TPR) to the next descriptor
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let x = (x + 1) % N;
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self.index = self.index + 1;
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if self.index == self.descriptors.len() {
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self.index = 0;
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}
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// signal DMA it can try again.
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// NOTE(unsafe) Atomic write
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unsafe {
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ETH.ethernet_dma()
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.dmactx_dtpr()
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.write(|w| w.0 = &self.td[x] as *const _ as u32);
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}
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self.tdidx = x;
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Ok(())
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}
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pub(crate) fn on_interrupt(&mut self) -> Result<(), Error> {
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let previous = (self.tdidx + N - 1) % N;
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let td = &self.td[previous];
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// DMB to ensure that we are reading an updated value, probably not needed at the hardware
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// level, but this is also a hint to the compiler that we're syncing on the buffer.
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fence(Ordering::SeqCst);
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let tdes3 = td.tdes3.get();
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if tdes3 & EMAC_DES3_OWN != 0 {
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// Transmission isn't done yet, probably a receive interrupt that fired this
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return Ok(());
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}
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assert!(tdes3 & EMAC_DES3_CTXT == 0);
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// Release the buffer
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self.buffers[previous].take();
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if tdes3 & EMAC_DES3_ES != 0 {
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Err(Error::TransmissionError)
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} else {
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Ok(())
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}
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unsafe { ETH.ethernet_dma().dmactx_dtpr().write(|w| w.0 = 0) }
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}
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}
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@ -185,7 +141,7 @@ impl<const N: usize> TDesRing<N> {
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/// * rdes2:
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/// * rdes3: OWN and Status
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#[repr(C)]
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struct RDes {
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pub(crate) struct RDes {
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rdes0: VolatileCell<u32>,
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rdes1: VolatileCell<u32>,
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rdes2: VolatileCell<u32>,
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@ -204,7 +160,7 @@ impl RDes {
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/// Return true if this RDes is acceptable to us
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#[inline(always)]
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pub fn valid(&self) -> bool {
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fn valid(&self) -> bool {
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// Write-back descriptor is valid if:
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//
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// Contains first buffer of packet AND contains last buf of
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@ -215,177 +171,96 @@ impl RDes {
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/// Return true if this RDes is not currently owned by the DMA
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#[inline(always)]
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pub fn available(&self) -> bool {
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fn available(&self) -> bool {
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self.rdes3.get() & EMAC_DES3_OWN == 0 // Owned by us
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}
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#[inline(always)]
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pub fn set_ready(&mut self, buf_addr: u32) {
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self.rdes0.set(buf_addr);
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fn set_ready(&mut self, buf: *mut u8) {
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self.rdes0.set(buf as u32);
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self.rdes3.set(EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN);
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}
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}
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/// Rx ring of descriptors and packets
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///
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/// This ring has three major locations that work in lock-step. The DMA will never write to the tail
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/// index, so the `read_index` must never pass the tail index. The `next_tail_index` is always 1
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/// slot ahead of the real tail index, and it must never pass the `read_index` or it could overwrite
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/// a packet still to be passed to the application.
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///
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/// nt can't pass r (no alloc)
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/// +---+---+---+---+ Read ok +---+---+---+---+ No Read +---+---+---+---+
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/// | | | | | ------------> | | | | | ------------> | | | | |
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/// +---+---+---+---+ Allocation ok +---+---+---+---+ +---+---+---+---+
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/// ^ ^t ^t ^ ^t ^
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/// |r |r |r
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/// |nt |nt |nt
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///
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///
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/// +---+---+---+---+ Read ok +---+---+---+---+ Can't read +---+---+---+---+
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/// | | | | | ------------> | | | | | ------------> | | | | |
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/// +---+---+---+---+ Allocation fail +---+---+---+---+ Allocation ok +---+---+---+---+
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/// ^ ^t ^ ^t ^ ^ ^ ^t
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/// |r | |r | | |r
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/// |nt |nt |nt
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///
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pub(crate) struct RDesRing<const N: usize> {
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rd: [RDes; N],
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buffers: [Option<PacketBox>; N],
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read_idx: usize,
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next_tail_idx: usize,
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pub(crate) struct RDesRing<'a> {
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descriptors: &'a mut [RDes],
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buffers: &'a mut [Packet<RX_BUFFER_SIZE>],
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index: usize,
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}
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impl<const N: usize> RDesRing<N> {
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pub const fn new() -> Self {
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const RDES: RDes = RDes::new();
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const BUFFERS: Option<PacketBox> = None;
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impl<'a> RDesRing<'a> {
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pub(crate) fn new(descriptors: &'a mut [RDes], buffers: &'a mut [Packet<RX_BUFFER_SIZE>]) -> Self {
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assert!(descriptors.len() > 1);
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assert!(descriptors.len() == buffers.len());
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Self {
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rd: [RDES; N],
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buffers: [BUFFERS; N],
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read_idx: 0,
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next_tail_idx: 0,
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}
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}
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pub(crate) fn init(&mut self) {
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assert!(N > 1);
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for desc in self.rd.iter_mut() {
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for (i, desc) in descriptors.iter_mut().enumerate() {
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*desc = RDes::new();
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desc.set_ready(buffers[i].0.as_mut_ptr());
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}
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let mut last_index = 0;
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for (index, buf) in self.buffers.iter_mut().enumerate() {
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let pkt = match PacketBox::new(Packet::new()) {
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Some(p) => p,
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None => {
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if index == 0 {
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panic!("Could not allocate at least one buffer for Ethernet receiving");
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} else {
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break;
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}
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}
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};
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let addr = pkt.as_ptr() as u32;
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*buf = Some(pkt);
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self.rd[index].set_ready(addr);
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last_index = index;
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}
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self.next_tail_idx = (last_index + 1) % N;
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmacrx_dlar().write(|w| w.0 = self.rd.as_ptr() as u32);
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dma.dmacrx_rlr().write(|w| w.set_rdrl((N as u16) - 1));
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dma.dmacrx_dlar().write(|w| w.0 = descriptors.as_mut_ptr() as u32);
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dma.dmacrx_rlr().write(|w| w.set_rdrl((descriptors.len() as u16) - 1));
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dma.dmacrx_dtpr().write(|w| w.0 = 0);
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}
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// We manage to allocate all buffers, set the index to the last one, that means
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// that the DMA won't consider the last one as ready, because it (unfortunately)
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// stops at the tail ptr and wraps at the end of the ring, which means that we
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// can't tell it to stop after the last buffer.
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let tail_ptr = &self.rd[last_index] as *const _ as u32;
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fence(Ordering::Release);
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dma.dmacrx_dtpr().write(|w| w.0 = tail_ptr);
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Self {
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descriptors,
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buffers,
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index: 0,
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}
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}
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pub(crate) fn on_interrupt(&mut self) {
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// XXX: Do we need to do anything here ? Maybe we should try to advance the tail ptr, but it
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// would soon hit the read ptr anyway, and we will wake smoltcp's stack on the interrupt
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// which should try to pop a packet...
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}
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pub(crate) fn pop_packet(&mut self) -> Option<PacketBuf> {
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/// Get a received packet if any, or None.
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pub(crate) fn available(&mut self) -> Option<&mut [u8]> {
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// Not sure if the contents of the write buffer on the M7 can affects reads, so we are using
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// a DMB here just in case, it also serves as a hint to the compiler that we're syncing the
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// buffer (I think .-.)
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fence(Ordering::SeqCst);
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let read_available = self.rd[self.read_idx].available();
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let tail_index = (self.next_tail_idx + N - 1) % N;
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let pkt = if read_available && self.read_idx != tail_index {
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let pkt = self.buffers[self.read_idx].take();
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let len = (self.rd[self.read_idx].rdes3.get() & EMAC_RDES3_PKTLEN) as usize;
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assert!(pkt.is_some());
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let valid = self.rd[self.read_idx].valid();
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self.read_idx = (self.read_idx + 1) % N;
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if valid {
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pkt.map(|p| p.slice(0..len))
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} else {
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None
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// We might have to process many packets, in case some have been rx'd but are invalid.
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loop {
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let descriptor = &mut self.descriptors[self.index];
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if !descriptor.available() {
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return None;
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}
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} else {
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None
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};
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// Try to advance the tail_idx
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if self.next_tail_idx != self.read_idx {
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match PacketBox::new(Packet::new()) {
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Some(b) => {
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let addr = b.as_ptr() as u32;
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self.buffers[self.next_tail_idx].replace(b);
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self.rd[self.next_tail_idx].set_ready(addr);
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// If packet is invalid, pop it and try again.
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if !descriptor.valid() {
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warn!("invalid packet: {:08x}", descriptor.rdes0.get());
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self.pop_packet();
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continue;
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}
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break;
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}
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let descriptor = &mut self.descriptors[self.index];
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let len = (descriptor.rdes3.get() & EMAC_RDES3_PKTLEN) as usize;
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return Some(&mut self.buffers[self.index].0[..len]);
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}
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/// Pop the packet previously returned by `available`.
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pub(crate) fn pop_packet(&mut self) {
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let descriptor = &mut self.descriptors[self.index];
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assert!(descriptor.available());
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self.descriptors[self.index].set_ready(self.buffers[self.index].0.as_mut_ptr());
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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// NOTE(unsafe) atomic write
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unsafe {
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ETH.ethernet_dma()
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.dmacrx_dtpr()
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.write(|w| w.0 = &self.rd[self.next_tail_idx] as *const _ as u32);
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}
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// signal DMA it can try again.
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// NOTE(unsafe) Atomic write
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unsafe { ETH.ethernet_dma().dmacrx_dtpr().write(|w| w.0 = 0) }
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self.next_tail_idx = (self.next_tail_idx + 1) % N;
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}
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None => {}
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// Increment index.
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self.index += 1;
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if self.index == self.descriptors.len() {
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self.index = 0
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}
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}
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pkt
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}
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}
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pub struct DescriptorRing<const T: usize, const R: usize> {
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pub(crate) tx: TDesRing<T>,
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pub(crate) rx: RDesRing<R>,
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}
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impl<const T: usize, const R: usize> DescriptorRing<T, R> {
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pub const fn new() -> Self {
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Self {
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tx: TDesRing::new(),
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rx: RDesRing::new(),
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||||
}
|
||||
}
|
||||
|
||||
pub fn init(&mut self) {
|
||||
self.tx.init();
|
||||
self.rx.init();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,35 +1,28 @@
|
|||
use core::marker::PhantomData;
|
||||
mod descriptors;
|
||||
|
||||
use core::sync::atomic::{fence, Ordering};
|
||||
use core::task::Waker;
|
||||
|
||||
use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
|
||||
use embassy_cortex_m::interrupt::InterruptExt;
|
||||
use embassy_hal_common::{into_ref, PeripheralRef};
|
||||
use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
|
||||
use embassy_sync::waitqueue::AtomicWaker;
|
||||
|
||||
pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
|
||||
use super::*;
|
||||
use crate::gpio::sealed::{AFType, Pin as _};
|
||||
use crate::gpio::{AnyPin, Speed};
|
||||
use crate::pac::{ETH, RCC, SYSCFG};
|
||||
use crate::Peripheral;
|
||||
|
||||
mod descriptors;
|
||||
use descriptors::DescriptorRing;
|
||||
const MTU: usize = 1514; // 14 Ethernet header + 1500 IP packet
|
||||
|
||||
use super::*;
|
||||
|
||||
pub struct State<'d, T: Instance, const TX: usize, const RX: usize>(StateStorage<Inner<'d, T, TX, RX>>);
|
||||
impl<'d, T: Instance, const TX: usize, const RX: usize> State<'d, T, TX, RX> {
|
||||
pub const fn new() -> Self {
|
||||
Self(StateStorage::new())
|
||||
}
|
||||
}
|
||||
pub struct Ethernet<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> {
|
||||
state: PeripheralMutex<'d, Inner<'d, T, TX, RX>>,
|
||||
pub struct Ethernet<'d, T: Instance, P: PHY> {
|
||||
_peri: PeripheralRef<'d, T>,
|
||||
pub(crate) tx: TDesRing<'d>,
|
||||
pub(crate) rx: RDesRing<'d>,
|
||||
pins: [PeripheralRef<'d, AnyPin>; 9],
|
||||
_phy: P,
|
||||
clock_range: u8,
|
||||
phy_addr: u8,
|
||||
mac_addr: [u8; 6],
|
||||
pub(crate) mac_addr: [u8; 6],
|
||||
}
|
||||
|
||||
macro_rules! config_pins {
|
||||
|
|
@ -44,10 +37,9 @@ macro_rules! config_pins {
|
|||
};
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T, P, TX, RX> {
|
||||
/// safety: the returned instance is not leak-safe
|
||||
pub unsafe fn new(
|
||||
state: &'d mut State<'d, T, TX, RX>,
|
||||
impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
|
||||
pub fn new<const TX: usize, const RX: usize>(
|
||||
queue: &'d mut PacketQueue<TX, RX>,
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
interrupt: impl Peripheral<P = crate::interrupt::ETH> + 'd,
|
||||
ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
|
||||
|
|
@ -63,8 +55,9 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
|
|||
mac_addr: [u8; 6],
|
||||
phy_addr: u8,
|
||||
) -> Self {
|
||||
into_ref!(interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
|
||||
into_ref!(peri, interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
|
||||
|
||||
unsafe {
|
||||
// Enable the necessary Clocks
|
||||
// NOTE(unsafe) We have exclusive access to the registers
|
||||
critical_section::with(|_| {
|
||||
|
|
@ -81,9 +74,6 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
|
|||
|
||||
config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
|
||||
|
||||
// NOTE(unsafe) We are ourselves not leak-safe.
|
||||
let state = PeripheralMutex::new(interrupt, &mut state.0, || Inner::new(peri));
|
||||
|
||||
// NOTE(unsafe) We have exclusive access to the registers
|
||||
let dma = ETH.ethernet_dma();
|
||||
let mac = ETH.ethernet_mac();
|
||||
|
|
@ -173,7 +163,9 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
|
|||
];
|
||||
|
||||
let mut this = Self {
|
||||
state,
|
||||
_peri: peri,
|
||||
tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
|
||||
rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
|
||||
pins,
|
||||
_phy: phy,
|
||||
clock_range,
|
||||
|
|
@ -181,9 +173,6 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
|
|||
mac_addr,
|
||||
};
|
||||
|
||||
this.state.with(|s| {
|
||||
s.desc_ring.init();
|
||||
|
||||
fence(Ordering::SeqCst);
|
||||
|
||||
let mac = ETH.ethernet_mac();
|
||||
|
|
@ -205,17 +194,37 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
|
|||
w.set_rie(true);
|
||||
w.set_tie(true);
|
||||
});
|
||||
});
|
||||
|
||||
P::phy_reset(&mut this);
|
||||
P::phy_init(&mut this);
|
||||
|
||||
interrupt.set_handler(Self::on_interrupt);
|
||||
interrupt.enable();
|
||||
|
||||
this
|
||||
}
|
||||
}
|
||||
|
||||
unsafe impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> StationManagement
|
||||
for Ethernet<'d, T, P, TX, RX>
|
||||
{
|
||||
fn on_interrupt(_cx: *mut ()) {
|
||||
WAKER.wake();
|
||||
|
||||
// TODO: Check and clear more flags
|
||||
unsafe {
|
||||
let dma = ETH.ethernet_dma();
|
||||
|
||||
dma.dmacsr().modify(|w| {
|
||||
w.set_ti(true);
|
||||
w.set_ri(true);
|
||||
w.set_nis(true);
|
||||
});
|
||||
// Delay two peripheral's clock
|
||||
dma.dmacsr().read();
|
||||
dma.dmacsr().read();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unsafe impl<'d, T: Instance, P: PHY> StationManagement for Ethernet<'d, T, P> {
|
||||
fn smi_read(&mut self, reg: u8) -> u16 {
|
||||
// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
|
||||
unsafe {
|
||||
|
|
@ -251,44 +260,7 @@ unsafe impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> StationMa
|
|||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device for Ethernet<'d, T, P, TX, RX> {
|
||||
fn is_transmit_ready(&mut self) -> bool {
|
||||
self.state.with(|s| s.desc_ring.tx.available())
|
||||
}
|
||||
|
||||
fn transmit(&mut self, pkt: PacketBuf) {
|
||||
self.state.with(|s| unwrap!(s.desc_ring.tx.transmit(pkt)));
|
||||
}
|
||||
|
||||
fn receive(&mut self) -> Option<PacketBuf> {
|
||||
self.state.with(|s| s.desc_ring.rx.pop_packet())
|
||||
}
|
||||
|
||||
fn register_waker(&mut self, waker: &Waker) {
|
||||
WAKER.register(waker);
|
||||
}
|
||||
|
||||
fn capabilities(&self) -> DeviceCapabilities {
|
||||
let mut caps = DeviceCapabilities::default();
|
||||
caps.max_transmission_unit = MTU;
|
||||
caps.max_burst_size = Some(TX.min(RX));
|
||||
caps
|
||||
}
|
||||
|
||||
fn link_state(&mut self) -> LinkState {
|
||||
if P::poll_link(self) {
|
||||
LinkState::Up
|
||||
} else {
|
||||
LinkState::Down
|
||||
}
|
||||
}
|
||||
|
||||
fn ethernet_address(&self) -> [u8; 6] {
|
||||
self.mac_addr
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop for Ethernet<'d, T, P, TX, RX> {
|
||||
impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
|
||||
fn drop(&mut self) {
|
||||
// NOTE(unsafe) We have `&mut self` and the interrupt doesn't use this registers
|
||||
unsafe {
|
||||
|
|
@ -325,46 +297,3 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop for Etherne
|
|||
})
|
||||
}
|
||||
}
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
struct Inner<'d, T: Instance, const TX: usize, const RX: usize> {
|
||||
_peri: PhantomData<&'d mut T>,
|
||||
desc_ring: DescriptorRing<TX, RX>,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, const TX: usize, const RX: usize> Inner<'d, T, TX, RX> {
|
||||
pub fn new(_peri: impl Peripheral<P = T> + 'd) -> Self {
|
||||
Self {
|
||||
_peri: PhantomData,
|
||||
desc_ring: DescriptorRing::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, const TX: usize, const RX: usize> PeripheralState for Inner<'d, T, TX, RX> {
|
||||
type Interrupt = crate::interrupt::ETH;
|
||||
|
||||
fn on_interrupt(&mut self) {
|
||||
unwrap!(self.desc_ring.tx.on_interrupt());
|
||||
self.desc_ring.rx.on_interrupt();
|
||||
|
||||
WAKER.wake();
|
||||
|
||||
// TODO: Check and clear more flags
|
||||
unsafe {
|
||||
let dma = ETH.ethernet_dma();
|
||||
|
||||
dma.dmacsr().modify(|w| {
|
||||
w.set_ti(true);
|
||||
w.set_ri(true);
|
||||
w.set_nis(true);
|
||||
});
|
||||
// Delay two peripheral's clock
|
||||
dma.dmacsr().read();
|
||||
dma.dmacsr().read();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static WAKER: AtomicWaker = AtomicWaker::new();
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ use embassy_executor::Spawner;
|
|||
use embassy_net::tcp::TcpSocket;
|
||||
use embassy_net::{Ipv4Address, Stack, StackResources};
|
||||
use embassy_stm32::eth::generic_smi::GenericSMI;
|
||||
use embassy_stm32::eth::{Ethernet, State};
|
||||
use embassy_stm32::eth::{Ethernet, PacketQueue};
|
||||
use embassy_stm32::peripherals::ETH;
|
||||
use embassy_stm32::rng::Rng;
|
||||
use embassy_stm32::time::mhz;
|
||||
|
|
@ -22,11 +22,12 @@ macro_rules! singleton {
|
|||
($val:expr) => {{
|
||||
type T = impl Sized;
|
||||
static STATIC_CELL: StaticCell<T> = StaticCell::new();
|
||||
STATIC_CELL.init_with(move || $val)
|
||||
let (x,) = STATIC_CELL.init(($val,));
|
||||
x
|
||||
}};
|
||||
}
|
||||
|
||||
type Device = Ethernet<'static, ETH, GenericSMI, 4, 4>;
|
||||
type Device = Ethernet<'static, ETH, GenericSMI>;
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn net_task(stack: &'static Stack<Device>) -> ! {
|
||||
|
|
@ -51,9 +52,8 @@ async fn main(spawner: Spawner) -> ! {
|
|||
let eth_int = interrupt::take!(ETH);
|
||||
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
|
||||
|
||||
let device = unsafe {
|
||||
Ethernet::new(
|
||||
singleton!(State::new()),
|
||||
let device = Ethernet::new(
|
||||
singleton!(PacketQueue::<16, 16>::new()),
|
||||
p.ETH,
|
||||
eth_int,
|
||||
p.PA1,
|
||||
|
|
@ -68,8 +68,7 @@ async fn main(spawner: Spawner) -> ! {
|
|||
GenericSMI,
|
||||
mac_addr,
|
||||
0,
|
||||
)
|
||||
};
|
||||
);
|
||||
|
||||
let config = embassy_net::ConfigStrategy::Dhcp;
|
||||
//let config = embassy_net::ConfigStrategy::Static(embassy_net::Config {
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ use embassy_executor::Spawner;
|
|||
use embassy_net::tcp::client::{TcpClient, TcpClientState};
|
||||
use embassy_net::{Stack, StackResources};
|
||||
use embassy_stm32::eth::generic_smi::GenericSMI;
|
||||
use embassy_stm32::eth::{Ethernet, State};
|
||||
use embassy_stm32::eth::{Ethernet, PacketQueue};
|
||||
use embassy_stm32::peripherals::ETH;
|
||||
use embassy_stm32::rng::Rng;
|
||||
use embassy_stm32::time::mhz;
|
||||
|
|
@ -23,11 +23,12 @@ macro_rules! singleton {
|
|||
($val:expr) => {{
|
||||
type T = impl Sized;
|
||||
static STATIC_CELL: StaticCell<T> = StaticCell::new();
|
||||
STATIC_CELL.init_with(move || $val)
|
||||
let (x,) = STATIC_CELL.init(($val,));
|
||||
x
|
||||
}};
|
||||
}
|
||||
|
||||
type Device = Ethernet<'static, ETH, GenericSMI, 4, 4>;
|
||||
type Device = Ethernet<'static, ETH, GenericSMI>;
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn net_task(stack: &'static Stack<Device>) -> ! {
|
||||
|
|
@ -52,9 +53,8 @@ async fn main(spawner: Spawner) -> ! {
|
|||
let eth_int = interrupt::take!(ETH);
|
||||
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
|
||||
|
||||
let device = unsafe {
|
||||
Ethernet::new(
|
||||
singleton!(State::new()),
|
||||
let device = Ethernet::new(
|
||||
singleton!(PacketQueue::<16, 16>::new()),
|
||||
p.ETH,
|
||||
eth_int,
|
||||
p.PA1,
|
||||
|
|
@ -69,8 +69,7 @@ async fn main(spawner: Spawner) -> ! {
|
|||
GenericSMI,
|
||||
mac_addr,
|
||||
0,
|
||||
)
|
||||
};
|
||||
);
|
||||
|
||||
let config = embassy_net::ConfigStrategy::Dhcp;
|
||||
//let config = embassy_net::ConfigStrategy::Static(embassy_net::Config {
|
||||
|
|
|
|||
Loading…
Reference in a new issue