Apply cargo fmt
Formatting.
This commit is contained in:
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fecb65b988
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34687a0956
3 changed files with 32 additions and 90 deletions
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@ -286,12 +286,7 @@ impl<I: FilterOwner> MasterFilters<'_, I> {
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/// - `index`: the filter index.
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/// - `index`: the filter index.
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/// - `fifo`: the receive FIFO the filter should pass accepted messages to.
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/// - `fifo`: the receive FIFO the filter should pass accepted messages to.
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/// - `config`: the filter configuration.
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/// - `config`: the filter configuration.
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pub fn enable_bank(
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pub fn enable_bank(&mut self, index: u8, fifo: Fifo, config: impl Into<BankConfig>) -> &mut Self {
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&mut self,
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index: u8,
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fifo: Fifo,
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config: impl Into<BankConfig>,
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) -> &mut Self {
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self.banks_imm().enable(index, fifo, config.into());
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self.banks_imm().enable(index, fifo, config.into());
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self
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self
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}
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}
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@ -380,12 +375,7 @@ impl<I: Instance> SlaveFilters<'_, I> {
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/// - `index`: the filter index.
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/// - `index`: the filter index.
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/// - `fifo`: the receive FIFO the filter should pass accepted messages to.
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/// - `fifo`: the receive FIFO the filter should pass accepted messages to.
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/// - `config`: the filter configuration.
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/// - `config`: the filter configuration.
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pub fn enable_bank(
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pub fn enable_bank(&mut self, index: u8, fifo: Fifo, config: impl Into<BankConfig>) -> &mut Self {
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&mut self,
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index: u8,
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fifo: Fifo,
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config: impl Into<BankConfig>,
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) -> &mut Self {
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self.banks_imm().enable(index, fifo, config.into());
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self.banks_imm().enable(index, fifo, config.into());
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self
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self
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}
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}
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@ -415,9 +405,7 @@ impl FilterBanks<'_> {
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fn disable(&mut self, index: u8) {
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fn disable(&mut self, index: u8) {
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self.assert_bank_index(index);
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self.assert_bank_index(index);
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self.can
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self.can.fa1r.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << index)) })
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.fa1r
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.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << index)) })
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}
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}
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fn enable(&mut self, index: u8, fifo: Fifo, config: BankConfig) {
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fn enable(&mut self, index: u8, fifo: Fifo, config: BankConfig) {
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@ -482,9 +470,7 @@ impl FilterBanks<'_> {
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});
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});
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// Set active.
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// Set active.
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self.can
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self.can.fa1r.modify(|r, w| unsafe { w.bits(r.bits() | (1 << index)) })
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.fa1r
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.modify(|r, w| unsafe { w.bits(r.bits() | (1 << index)) })
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}
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}
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}
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}
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@ -22,10 +22,7 @@ impl Frame {
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Id::Extended(id) => IdReg::new_extended(id),
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Id::Extended(id) => IdReg::new_extended(id),
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};
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};
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Self {
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Self { id, data: data.into() }
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id,
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data: data.into(),
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}
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}
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}
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/// Creates a new remote frame with configurable data length code (DLC).
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/// Creates a new remote frame with configurable data length code (DLC).
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@ -182,10 +179,7 @@ impl Data {
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/// Creates an empty data payload containing 0 bytes.
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/// Creates an empty data payload containing 0 bytes.
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#[inline]
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#[inline]
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pub const fn empty() -> Self {
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pub const fn empty() -> Self {
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Self {
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Self { len: 0, bytes: [0; 8] }
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len: 0,
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bytes: [0; 8],
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}
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}
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}
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}
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}
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@ -19,21 +19,8 @@
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//!
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//!
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//! - Support for querying error states and handling error interrupts is incomplete.
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//! - Support for querying error states and handling error interrupts is incomplete.
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//!
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//!
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//! # Cargo Features
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//!
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//! | Feature | Description |
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//! |---------|-------------|
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//! | `defmt` | Implements [`defmt`]'s `Format` trait for the types in this crate.[^1] |
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//!
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//! [^1]: The specific version of defmt is unspecified and may be updated in a patch release.
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//!
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//! [`defmt`]: https://docs.rs/defmt
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//! [`embedded-hal`]: https://docs.rs/embedded-hal
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#![doc(html_root_url = "https://docs.rs/bxcan/0.7.0")]
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// Deny a few warnings in doctests, since rustdoc `allow`s many warnings by default
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// Deny a few warnings in doctests, since rustdoc `allow`s many warnings by default
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#![doc(test(attr(deny(unused_imports, unused_must_use))))]
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#![no_std]
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#![allow(clippy::unnecessary_operation)] // lint is bugged
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#![allow(clippy::unnecessary_operation)] // lint is bugged
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//mod embedded_hal;
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//mod embedded_hal;
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@ -45,20 +32,19 @@ mod interrupt;
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#[allow(clippy::all)] // generated code
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#[allow(clippy::all)] // generated code
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mod pac;
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mod pac;
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pub use id::{ExtendedId, Id, StandardId};
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pub use crate::can::bx::frame::{Data, Frame, FramePriority};
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pub use crate::can::bx::interrupt::{Interrupt, Interrupts};
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pub use crate::can::bx::pac::can::RegisterBlock;
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use crate::can::bx::filter::MasterFilters;
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use core::cmp::{Ord, Ordering};
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use core::cmp::{Ord, Ordering};
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use core::convert::{Infallible, TryInto};
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use core::convert::{Infallible, TryInto};
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use core::marker::PhantomData;
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use core::marker::PhantomData;
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use core::mem;
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use core::mem;
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use core::ptr::NonNull;
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use core::ptr::NonNull;
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use self::pac::generic::*; // To make the PAC extraction build
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pub use id::{ExtendedId, Id, StandardId};
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use self::pac::generic::*;
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use crate::can::bx::filter::MasterFilters;
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pub use crate::can::bx::frame::{Data, Frame, FramePriority};
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pub use crate::can::bx::interrupt::{Interrupt, Interrupts};
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pub use crate::can::bx::pac::can::RegisterBlock; // To make the PAC extraction build
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/// A bxCAN peripheral instance.
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/// A bxCAN peripheral instance.
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///
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///
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@ -186,9 +172,7 @@ impl IdReg {
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if self.is_extended() {
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if self.is_extended() {
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Id::Extended(unsafe { ExtendedId::new_unchecked(self.0 >> Self::EXTENDED_SHIFT) })
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Id::Extended(unsafe { ExtendedId::new_unchecked(self.0 >> Self::EXTENDED_SHIFT) })
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} else {
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} else {
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Id::Standard(unsafe {
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Id::Standard(unsafe { StandardId::new_unchecked((self.0 >> Self::STANDARD_SHIFT) as u16) })
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StandardId::new_unchecked((self.0 >> Self::STANDARD_SHIFT) as u16)
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})
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}
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}
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}
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}
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@ -229,12 +213,9 @@ impl Ord for IdReg {
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.reverse()
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.reverse()
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.then(Ordering::Greater)
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.then(Ordering::Greater)
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}
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}
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(Id::Extended(a), Id::Standard(b)) => a
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(Id::Extended(a), Id::Standard(b)) => {
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.standard_id()
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a.standard_id().as_raw().cmp(&b.as_raw()).reverse().then(Ordering::Less)
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.as_raw()
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}
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.cmp(&b.as_raw())
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.reverse()
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.then(Ordering::Less),
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}
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}
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}
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}
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}
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}
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@ -326,8 +307,7 @@ impl<I: Instance> CanConfig<'_, I> {
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/// Leaves initialization mode, enters sleep mode.
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/// Leaves initialization mode, enters sleep mode.
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fn leave_init_mode(&mut self) {
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fn leave_init_mode(&mut self) {
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let can = self.can.registers();
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let can = self.can.registers();
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can.mcr
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can.mcr.modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
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.modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
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loop {
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loop {
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let msr = can.msr.read();
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let msr = can.msr.read();
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if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
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if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
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@ -426,8 +406,7 @@ impl<I: Instance> CanBuilder<I> {
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/// Leaves initialization mode, enters sleep mode.
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/// Leaves initialization mode, enters sleep mode.
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fn leave_init_mode(&mut self) {
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fn leave_init_mode(&mut self) {
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let can = self.can.registers();
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let can = self.can.registers();
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can.mcr
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can.mcr.modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
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.modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
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loop {
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loop {
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let msr = can.msr.read();
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let msr = can.msr.read();
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if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
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if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
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@ -448,15 +427,11 @@ where
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{
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{
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/// Creates a [`CanBuilder`] for constructing a CAN interface.
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/// Creates a [`CanBuilder`] for constructing a CAN interface.
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pub fn builder(instance: I) -> CanBuilder<I> {
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pub fn builder(instance: I) -> CanBuilder<I> {
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let can_builder = CanBuilder {
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let can_builder = CanBuilder { can: Can { instance } };
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can: Can { instance },
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};
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let can_reg = can_builder.can.registers();
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let can_reg = can_builder.can.registers();
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// Enter init mode.
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// Enter init mode.
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can_reg
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can_reg.mcr.modify(|_, w| w.sleep().clear_bit().inrq().set_bit());
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.mcr
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.modify(|_, w| w.sleep().clear_bit().inrq().set_bit());
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loop {
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loop {
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let msr = can_reg.msr.read();
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let msr = can_reg.msr.read();
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if msr.slak().bit_is_clear() && msr.inak().bit_is_set() {
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if msr.slak().bit_is_clear() && msr.inak().bit_is_set() {
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@ -505,8 +480,7 @@ where
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let can = self.registers();
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let can = self.registers();
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// Enter init mode.
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// Enter init mode.
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can.mcr
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can.mcr.modify(|_, w| w.sleep().clear_bit().inrq().set_bit());
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.modify(|_, w| w.sleep().clear_bit().inrq().set_bit());
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loop {
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loop {
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let msr = can.msr.read();
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let msr = can.msr.read();
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if msr.slak().bit_is_clear() && msr.inak().bit_is_set() {
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if msr.slak().bit_is_clear() && msr.inak().bit_is_set() {
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@ -541,8 +515,7 @@ where
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let can = self.registers();
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let can = self.registers();
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let msr = can.msr.read();
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let msr = can.msr.read();
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if msr.slak().bit_is_set() {
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if msr.slak().bit_is_set() {
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can.mcr
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can.mcr.modify(|_, w| w.abom().set_bit().sleep().clear_bit());
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.modify(|_, w| w.abom().set_bit().sleep().clear_bit());
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Err(nb::Error::WouldBlock)
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Err(nb::Error::WouldBlock)
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} else {
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} else {
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Ok(())
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Ok(())
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@ -554,8 +527,7 @@ where
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/// While in sleep mode, an incoming CAN frame will trigger [`Interrupt::Wakeup`] if enabled.
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/// While in sleep mode, an incoming CAN frame will trigger [`Interrupt::Wakeup`] if enabled.
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pub fn sleep(&mut self) {
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pub fn sleep(&mut self) {
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let can = self.registers();
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let can = self.registers();
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can.mcr
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can.mcr.modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
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.modify(|_, w| w.sleep().set_bit().inrq().clear_bit());
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loop {
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loop {
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let msr = can.msr.read();
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let msr = can.msr.read();
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if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
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if msr.slak().bit_is_set() && msr.inak().bit_is_clear() {
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/// frame will cause that interrupt.
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/// frame will cause that interrupt.
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pub fn wakeup(&mut self) {
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pub fn wakeup(&mut self) {
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let can = self.registers();
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let can = self.registers();
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can.mcr
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can.mcr.modify(|_, w| w.sleep().clear_bit().inrq().clear_bit());
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.modify(|_, w| w.sleep().clear_bit().inrq().clear_bit());
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loop {
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loop {
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let msr = can.msr.read();
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let msr = can.msr.read();
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if msr.slak().bit_is_clear() && msr.inak().bit_is_clear() {
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if msr.slak().bit_is_clear() && msr.inak().bit_is_clear() {
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@ -791,8 +762,7 @@ where
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let tsr = can.tsr.read();
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let tsr = can.tsr.read();
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let idx = tsr.code().bits() as usize;
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let idx = tsr.code().bits() as usize;
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let frame_is_pending =
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let frame_is_pending = tsr.tme0().bit_is_clear() || tsr.tme1().bit_is_clear() || tsr.tme2().bit_is_clear();
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tsr.tme0().bit_is_clear() || tsr.tme1().bit_is_clear() || tsr.tme2().bit_is_clear();
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let pending_frame = if frame_is_pending {
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let pending_frame = if frame_is_pending {
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// High priority frames are transmitted first by the mailbox system.
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// High priority frames are transmitted first by the mailbox system.
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// Frames with identical identifier shall be transmitted in FIFO order.
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// Frames with identical identifier shall be transmitted in FIFO order.
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@ -860,20 +830,12 @@ where
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debug_assert!(idx < 3);
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debug_assert!(idx < 3);
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let mb = unsafe { &can.tx.get_unchecked(idx) };
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let mb = unsafe { &can.tx.get_unchecked(idx) };
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mb.tdtr
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mb.tdtr.write(|w| unsafe { w.dlc().bits(frame.dlc() as u8) });
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.write(|w| unsafe { w.dlc().bits(frame.dlc() as u8) });
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mb.tdlr
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mb.tdlr.write(|w| unsafe {
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.write(|w| unsafe { w.bits(u32::from_ne_bytes(frame.data.bytes[0..4].try_into().unwrap())) });
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w.bits(u32::from_ne_bytes(
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mb.tdhr
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frame.data.bytes[0..4].try_into().unwrap(),
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.write(|w| unsafe { w.bits(u32::from_ne_bytes(frame.data.bytes[4..8].try_into().unwrap())) });
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))
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mb.tir.write(|w| unsafe { w.bits(frame.id.0).txrq().set_bit() });
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});
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mb.tdhr.write(|w| unsafe {
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w.bits(u32::from_ne_bytes(
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frame.data.bytes[4..8].try_into().unwrap(),
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))
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});
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mb.tir
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.write(|w| unsafe { w.bits(frame.id.0).txrq().set_bit() });
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}
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}
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fn read_pending_mailbox(&mut self, idx: usize) -> Option<Frame> {
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fn read_pending_mailbox(&mut self, idx: usize) -> Option<Frame> {
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