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stm32: fix f100 build.

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This commit is contained in:
Dario Nieuwenhuis 2022-06-26 23:52:38 +02:00
parent ffc32d3ddb
commit 397722c328
2 changed files with 4 additions and 2 deletions
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4
embassy-stm32/src/rcc/f1.rs
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@ -2,7 +2,7 @@ use core::convert::TryFrom;
use super::{set_freqs, Clocks};
use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::{Adcpre, Hpre, Pllmul, Pllsrc, Ppre1, Sw, Usbpre};
use crate::pac::rcc::vals::*;
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
@ -110,6 +110,7 @@ pub(crate) unsafe fn init(config: Config) {
// the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
// PLL output frequency is a supported one.
// usbpre == false: divide clock by 1.5, otherwise no division
#[cfg(not(rcc_f100))]
let (usbpre, _usbclk_valid) = match (config.hse, pllmul_bits, real_sysclk) {
(Some(_), Some(_), 72_000_000) => (false, true),
(Some(_), Some(_), 48_000_000) => (true, true),
@ -154,6 +155,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre2(Ppre1(ppre2_bits));
w.set_ppre1(Ppre1(ppre1_bits));
w.set_hpre(Hpre(hpre_bits));
#[cfg(not(rcc_f100))]
w.set_usbpre(Usbpre(usbpre as u8));
w.set_sw(Sw(if pllmul_bits.is_some() {
// PLL

2
embassy-stm32/src/rcc/mod.rs
View file

@ -5,7 +5,7 @@ use core::mem::MaybeUninit;
use crate::time::Hertz;
#[cfg_attr(rcc_f0, path = "f0.rs")]
#[cfg_attr(any(rcc_f1, rcc_f1cl), path = "f1.rs")]
#[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
#[cfg_attr(rcc_f2, path = "f2.rs")]
#[cfg_attr(rcc_f3, path = "f3.rs")]
#[cfg_attr(any(rcc_f4, rcc_f410), path = "f4.rs")]