diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs
index 8a9b24c91..5b1909659 100644
--- a/embassy-stm32/src/rcc/wl.rs
+++ b/embassy-stm32/src/rcc/wl.rs
@@ -1,7 +1,7 @@
 pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale};
 use crate::pac::pwr::vals::Dbp;
 use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::bd::{BackupDomain, RtcClockSource as RCS};
+use crate::rcc::bd::{BackupDomain, RtcClockSource};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 
@@ -130,16 +130,11 @@ impl Default for Config {
             apb2_pre: APBPrescaler::NotDivided,
             enable_lsi: false,
             enable_rtc_apb: false,
-            rtc_mux: RtcClockSource::LSI32,
+            rtc_mux: RtcClockSource::LSI,
         }
     }
 }
 
-pub enum RtcClockSource {
-    LSE32,
-    LSI32,
-}
-
 #[repr(u8)]
 pub enum Lsedrv {
     Low = 0,
@@ -215,7 +210,7 @@ pub(crate) unsafe fn init(config: Config) {
     while FLASH.acr().read().latency() != ws {}
 
     match config.rtc_mux {
-        RtcClockSource::LSE32 => {
+        RtcClockSource::LSE => {
             // 1. Unlock the backup domain
             PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
 
@@ -231,17 +226,18 @@ pub(crate) unsafe fn init(config: Config) {
             // Wait until LSE is running
             while !RCC.bdcr().read().lserdy() {}
 
-            BackupDomain::set_rtc_clock_source(RCS::LSE);
+            BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
         }
-        RtcClockSource::LSI32 => {
+        RtcClockSource::LSI => {
             // Turn on the internal 32 kHz LSI oscillator
             RCC.csr().modify(|w| w.set_lsion(true));
 
             // Wait until LSI is running
             while !RCC.csr().read().lsirdy() {}
 
-            BackupDomain::set_rtc_clock_source(RCS::LSI);
+            BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
         }
+        _ => unreachable!(),
     }
 
     match config.mux {
@@ -266,7 +262,7 @@ pub(crate) unsafe fn init(config: Config) {
                 w.set_msirange(range.into());
                 w.set_msion(true);
 
-                if let RtcClockSource::LSE32 = config.rtc_mux {
+                if let RtcClockSource::LSE = config.rtc_mux {
                     // If LSE is enabled, enable calibration of MSI
                     w.set_msipllen(true);
                 } else {
diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs
index fb1bc6e3d..2be6c7b93 100644
--- a/examples/stm32wl/src/bin/rtc.rs
+++ b/examples/stm32wl/src/bin/rtc.rs
@@ -5,8 +5,8 @@
 use chrono::{NaiveDate, NaiveDateTime};
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{self, ClockSrc};
-use embassy_stm32::rtc::{Rtc, RtcConfig};
+use embassy_stm32::rcc::ClockSrc;
+use embassy_stm32::rtc::{Rtc, RtcClockSource, RtcConfig};
 use embassy_stm32::Config;
 use embassy_time::{Duration, Timer};
 use {defmt_rtt as _, panic_probe as _};
@@ -16,7 +16,7 @@ async fn main(_spawner: Spawner) {
     let p = {
         let mut config = Config::default();
         config.rcc.mux = ClockSrc::HSE32;
-        config.rcc.rtc_mux = rcc::RtcClockSource::LSE32;
+        config.rcc.rtc_mux = RtcClockSource::LSE;
         config.rcc.enable_rtc_apb = true;
         embassy_stm32::init(config)
     };