NaxdyOrg/embassy
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Merge pull request #273 from rukai/fix_warnings_again

Browse source 
fix stm32 warnings
This commit is contained in:
Dario Nieuwenhuis 2021-07-05 02:00:51 +02:00 committed by GitHub
commit 3ce32d6624
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
8 changed files with 24 additions and 54 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
embassy-stm32/src/adc/mod.rs
View file

@ -6,12 +6,9 @@ mod _version;
#[allow(unused)]
pub use _version::*;
use crate::gpio::NoPin;
use crate::peripherals;
pub(crate) mod sealed {
use crate::gpio::Pin;
pub trait Instance {
fn regs() -> &'static crate::pac::adc::Adc;
fn common_regs() -> &'static crate::pac::adccommon::AdcCommon;

8
embassy-stm32/src/adc/v3.rs
View file

@ -1,10 +1,9 @@
use crate::adc::{AdcPin, Instance};
use core::convert::Infallible;
use core::marker::PhantomData;
use cortex_m::delay::Delay;
use embassy::util::Unborrow;
use embassy_extras::unborrow;
use embedded_hal::blocking::delay::{DelayMs, DelayUs};
use embedded_hal::blocking::delay::DelayUs;
pub const VDDA_CALIB_MV: u32 = 3000;
@ -193,6 +192,7 @@ impl<'d, T: Instance> Adc<'d, T> {
/// Calculates the system VDDA by sampling the internal VREF channel and comparing
/// the result with the value stored at the factory. If the chip's VDDA is not stable, run
/// this before each ADC conversion.
#[allow(unused)] // TODO is this supposed to be public?
fn calibrate(&mut self, vref: &mut Vref) {
let vref_cal = unsafe { crate::pac::VREFINTCAL.data().read().value() };
let old_sample_time = self.sample_time;
@ -233,8 +233,6 @@ impl<'d, T: Instance> Adc<'d, T> {
*/
pub fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
let v = pin.channel();
unsafe {
// Make sure bits are off
while T::regs().cr().read().addis() {
@ -304,7 +302,7 @@ impl<'d, T: Instance> Adc<'d, T> {
}
unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
if ch >= 0 && ch <= 9 {
if ch <= 9 {
T::regs()
.smpr1()
.modify(|reg| reg.set_smp(ch as _, sample_time.sample_time()));

2
examples/stm32h7/src/bin/blinky.rs
View file

@ -28,7 +28,7 @@ fn main() -> ! {
let rcc = pp.RCC.constrain();
let ccdr = rcc
rcc
.sys_ck(96.mhz())
.pclk1(48.mhz())
.pclk2(48.mhz())

15
examples/stm32h7/src/bin/dac.rs
View file

@ -1,5 +1,6 @@
#![no_std]
#![no_main]
#![allow(incomplete_features)]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
@ -8,16 +9,12 @@
#[path = "../example_common.rs"]
mod example_common;
use embassy_stm32::gpio::{Level, Output, Input, Pull, NoPin};
use embedded_hal::digital::v2::{OutputPin, InputPin};
use embassy_stm32::gpio::NoPin;
use example_common::*;
use cortex_m_rt::entry;
use stm32h7::stm32h743 as pac;
use embassy_stm32::spi::{Spi, MODE_0, ByteOrder, Config};
use embassy_stm32::time::Hertz;
use embedded_hal::blocking::spi::Transfer;
use stm32h7xx_hal::{rcc, prelude::*};
use stm32h7xx_hal::prelude::*;
use embassy_stm32::dac::{Dac, Value, Channel};
#[entry]
@ -31,7 +28,7 @@ fn main() -> ! {
let rcc = pp.RCC.constrain();
let ccdr = rcc
rcc
.sys_ck(96.mhz())
.pclk1(48.mhz())
.pclk2(48.mhz())
@ -71,8 +68,8 @@ fn main() -> ! {
loop {
for v in 0..=255 {
dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v)));
dac.trigger( Channel::Ch1 );
unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
unwrap!(dac.trigger(Channel::Ch1));
}
}
}

1
examples/stm32h7/src/bin/eth.rs
View file

@ -1,5 +1,6 @@
#![no_std]
#![no_main]
#![allow(incomplete_features)]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]

2
examples/stm32h7/src/bin/usart.rs
View file

@ -59,7 +59,7 @@ fn main() -> ! {
let rcc = pp.RCC.constrain();
let ccdr = rcc
rcc
.sys_ck(96.mhz())
.pclk1(48.mhz())
.pclk2(48.mhz())

29
examples/stm32l4/src/bin/adc.rs
View file

@ -1,5 +1,6 @@
#![no_std]
#![no_main]
#![allow(incomplete_features)]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
@ -8,23 +9,15 @@
#[path = "../example_common.rs"]
mod example_common;
use embassy_stm32::gpio::{Input, Level, NoPin, Output, Pull};
use embedded_hal::digital::v2::{InputPin, OutputPin};
use example_common::*;
use cortex_m_rt::entry;
//use stm32f4::stm32f429 as pac;
use cortex_m::delay::Delay;
use embassy_stm32::adc::{Adc, Resolution};
use embassy_stm32::dac::{Channel, Dac, Value};
use embassy_stm32::spi::{ByteOrder, Config, Spi, MODE_0};
use embassy_stm32::time::Hertz;
use embedded_hal::blocking::spi::Transfer;
use micromath::F32Ext;
use stm32l4::stm32l4x5 as pac;
use stm32l4xx_hal::gpio::PA4;
use stm32l4xx_hal::rcc::PllSource;
use stm32l4xx_hal::{prelude::*, rcc};
use stm32l4xx_hal::prelude::*;
#[entry]
fn main() -> ! {
@ -36,11 +29,11 @@ fn main() -> ! {
let mut rcc = pp.RCC.constrain();
let mut pwr = pp.PWR.constrain(&mut rcc.apb1r1);
let mut delay = Delay::new(cp.SYST, 80_000_000);
let delay = Delay::new(cp.SYST, 80_000_000);
// TRY the other clock configuration
// let clocks = rcc.cfgr.freeze(&mut flash.acr);
let clocks = rcc
rcc
.cfgr
.sysclk(80.mhz())
.pclk1(80.mhz())
@ -76,7 +69,7 @@ fn main() -> ! {
let p = embassy_stm32::init(Default::default());
let (mut adc, mut delay) = Adc::new(p.ADC1, delay);
let (mut adc, _) = Adc::new(p.ADC1, delay);
//adc.enable_vref();
adc.set_resolution(Resolution::EightBit);
let mut channel = p.PC0;
@ -86,15 +79,3 @@ fn main() -> ! {
info!("--> {}", v);
}
}
fn to_sine_wave(v: u8) -> u8 {
if v >= 128 {
// top half
let r = 3.14 * ((v - 128) as f32 / 128.0);
(r.sin() * 128.0 + 127.0) as u8
} else {
// bottom half
let r = 3.14 + 3.14 * (v as f32 / 128.0);
(r.sin() * 128.0 + 127.0) as u8
}
}

16
examples/stm32l4/src/bin/dac.rs
View file

@ -1,5 +1,6 @@
#![no_std]
#![no_main]
#![allow(incomplete_features)]
#![feature(trait_alias)]
#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
@ -8,20 +9,15 @@
#[path = "../example_common.rs"]
mod example_common;
use embassy_stm32::gpio::{Input, Level, NoPin, Output, Pull};
use embedded_hal::digital::v2::{InputPin, OutputPin};
use embassy_stm32::gpio::NoPin;
use example_common::*;
use cortex_m_rt::entry;
//use stm32f4::stm32f429 as pac;
use embassy_stm32::dac::{Channel, Dac, Value};
use embassy_stm32::spi::{ByteOrder, Config, Spi, MODE_0};
use embassy_stm32::time::Hertz;
use embedded_hal::blocking::spi::Transfer;
use stm32l4::stm32l4x5 as pac;
use stm32l4xx_hal::gpio::PA4;
use stm32l4xx_hal::rcc::PllSource;
use stm32l4xx_hal::{prelude::*, rcc};
use stm32l4xx_hal::{prelude::*};
#[entry]
fn main() -> ! {
@ -34,7 +30,7 @@ fn main() -> ! {
// TRY the other clock configuration
// let clocks = rcc.cfgr.freeze(&mut flash.acr);
let clocks = rcc
rcc
.cfgr
.sysclk(80.mhz())
.pclk1(80.mhz())
@ -71,8 +67,8 @@ fn main() -> ! {
loop {
for v in 0..=255 {
dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v)));
dac.trigger(Channel::Ch1);
unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
unwrap!(dac.trigger(Channel::Ch1));
}
}
}