Merge commit '8d7abeb06fbe3e19db3cae3f5220725969ecbb81' of https://github.com/Lytehorse/embassy into can
This commit is contained in:
xoviat
commit
403cbb1dc9
2 changed files with 371 additions and 4 deletions
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@ -69,6 +69,7 @@ cfg-if = "1.0.0"
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embedded-io = { version = "0.4.0", features = ["async"], optional = true }
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chrono = { version = "^0.4", default-features = false, optional = true}
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bit_field = "0.10.2"
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heapless = { version = "0.7.5", default-features = false }
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[dev-dependencies]
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critical-section = { version = "1.1", features = ["std"] }
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@ -1,16 +1,41 @@
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use core::future::poll_fn;
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use core::ops::{Deref, DerefMut};
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use core::task::Poll;
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pub use bxcan;
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use bxcan::{Data, ExtendedId, Frame, Id, StandardId};
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::gpio::sealed::AFType;
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use crate::interrupt::InterruptExt;
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use crate::pac::can::vals::{Lec, RirIde};
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use crate::rcc::RccPeripheral;
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use crate::time::Hertz;
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use crate::{peripherals, Peripheral};
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pub struct Can<'d, T: Instance> {
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can: bxcan::Can<BxcanInstance<'d, T>>,
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}
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#[derive(Debug)]
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pub enum BusError {
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Stuff,
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Form,
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Acknowledge,
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BitRecessive,
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BitDominant,
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Crc,
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Software,
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BusOff,
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BusPassive,
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BusWarning,
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}
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pub enum FrameOrError {
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Frame(Frame),
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Error(BusError),
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}
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impl<'d, T: Instance> Can<'d, T> {
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/// Creates a new Bxcan instance, blocking for 11 recessive bits to sync with the CAN bus.
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pub fn new(
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@ -39,8 +64,12 @@ impl<'d, T: Instance> Can<'d, T> {
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peri: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_irq: impl Peripheral<P = T::TXInterrupt> + 'd,
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rx0_irq: impl Peripheral<P = T::RX0Interrupt> + 'd,
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rx1_irq: impl Peripheral<P = T::RX1Interrupt> + 'd,
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sce_irq: impl Peripheral<P = T::SCEInterrupt> + 'd,
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) -> Self {
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into_ref!(peri, rx, tx);
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into_ref!(peri, rx, tx, tx_irq, rx0_irq, rx1_irq, sce_irq);
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unsafe {
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rx.set_as_af(rx.af_num(), AFType::Input);
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@ -50,10 +79,246 @@ impl<'d, T: Instance> Can<'d, T> {
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T::enable();
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T::reset();
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Self {
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can: bxcan::Can::builder(BxcanInstance(peri)).leave_disabled(),
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tx_irq.unpend();
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tx_irq.set_handler(Self::tx_interrupt);
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tx_irq.enable();
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rx0_irq.unpend();
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rx0_irq.set_handler(Self::rx0_interrupt);
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rx0_irq.enable();
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rx1_irq.unpend();
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rx1_irq.set_handler(Self::rx1_interrupt);
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rx1_irq.enable();
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sce_irq.unpend();
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sce_irq.set_handler(Self::sce_interrupt);
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sce_irq.enable();
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let can = bxcan::Can::builder(BxcanInstance(peri)).leave_disabled();
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Self { can }
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}
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pub fn set_bitrate(&mut self, bitrate: u32) {
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let bit_timing = Self::calc_bxcan_timings(T::frequency(), bitrate).unwrap();
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self.can.modify_config().set_bit_timing(bit_timing).leave_disabled();
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}
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pub async fn transmit(&mut self, frame: &Frame) {
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let tx_status = self.queue_transmit(frame).await;
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self.wait_transission(tx_status.mailbox()).await;
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}
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async fn queue_transmit(&mut self, frame: &Frame) -> bxcan::TransmitStatus {
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poll_fn(|cx| {
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if let Ok(status) = self.can.transmit(frame) {
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return Poll::Ready(status);
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}
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T::state().tx_waker.register(cx.waker());
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Poll::Pending
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})
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.await
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}
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async fn wait_transission(&self, mb: bxcan::Mailbox) {
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poll_fn(|cx| unsafe {
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if T::regs().tsr().read().tme(mb.index()) {
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return Poll::Ready(());
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}
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T::state().tx_waker.register(cx.waker());
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Poll::Pending
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})
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.await;
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}
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pub async fn receive_frame_or_error(&mut self) -> FrameOrError {
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poll_fn(|cx| {
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if let Some(frame) = T::state().rx_queue.dequeue() {
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return Poll::Ready(FrameOrError::Frame(frame));
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} else if let Some(err) = self.curr_error() {
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return Poll::Ready(FrameOrError::Error(err));
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}
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T::state().rx_waker.register(cx.waker());
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T::state().err_waker.register(cx.waker());
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Poll::Pending
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})
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.await
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}
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fn curr_error(&self) -> Option<BusError> {
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let err = unsafe { T::regs().esr().read() };
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if err.boff() {
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return Some(BusError::BusOff);
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} else if err.epvf() {
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return Some(BusError::BusPassive);
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} else if err.ewgf() {
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return Some(BusError::BusWarning);
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} else if let Some(err) = err.lec().into_bus_err() {
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return Some(err);
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}
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None
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}
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unsafe fn sce_interrupt(_: *mut ()) {
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let msr = T::regs().msr();
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let msr_val = msr.read();
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if msr_val.erri() {
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msr.modify(|v| v.set_erri(true));
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T::state().err_waker.wake();
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return;
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}
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}
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unsafe fn tx_interrupt(_: *mut ()) {
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T::regs().tsr().write(|v| {
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v.set_rqcp(0, true);
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v.set_rqcp(1, true);
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v.set_rqcp(2, true);
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});
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T::state().tx_waker.wake();
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}
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unsafe fn rx0_interrupt(_: *mut ()) {
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Self::receive_fifo(RxFifo::Fifo0);
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}
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unsafe fn rx1_interrupt(_: *mut ()) {
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Self::receive_fifo(RxFifo::Fifi1);
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}
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unsafe fn receive_fifo(fifo: RxFifo) {
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let state = T::state();
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let regs = T::regs();
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let fifo_idx = match fifo {
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RxFifo::Fifo0 => 0usize,
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RxFifo::Fifi1 => 1usize,
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};
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let rfr = regs.rfr(fifo_idx);
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let fifo = regs.rx(fifo_idx);
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// If there are no pending messages, there is nothing to do
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if rfr.read().fmp() == 0 {
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return;
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}
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let rir = fifo.rir().read();
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let id = if rir.ide() == RirIde::STANDARD {
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Id::from(StandardId::new_unchecked(rir.stid()))
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} else {
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Id::from(ExtendedId::new_unchecked(rir.exid()))
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};
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let data_len = fifo.rdtr().read().dlc() as usize;
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let mut data: [u8; 8] = [0; 8];
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data[0..4].copy_from_slice(&fifo.rdlr().read().0.to_ne_bytes());
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data[4..8].copy_from_slice(&fifo.rdhr().read().0.to_ne_bytes());
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let frame = Frame::new_data(id, Data::new(&data[0..data_len]).unwrap());
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rfr.modify(|v| v.set_rfom(true));
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match state.rx_queue.enqueue(frame) {
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Ok(_) => {}
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Err(_) => defmt::error!("RX queue overflow"),
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}
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state.rx_waker.wake();
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}
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pub fn calc_bxcan_timings(periph_clock: Hertz, can_bitrate: u32) -> Option<u32> {
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const BS1_MAX: u8 = 16;
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const BS2_MAX: u8 = 8;
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const MAX_SAMPLE_POINT_PERMILL: u16 = 900;
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let periph_clock = periph_clock.0;
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if can_bitrate < 1000 {
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return None;
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}
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// Ref. "Automatic Baudrate Detection in CANopen Networks", U. Koppe, MicroControl GmbH & Co. KG
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// CAN in Automation, 2003
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//
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// According to the source, optimal quanta per bit are:
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// Bitrate Optimal Maximum
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// 1000 kbps 8 10
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// 500 kbps 16 17
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// 250 kbps 16 17
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// 125 kbps 16 17
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let max_quanta_per_bit: u8 = if can_bitrate >= 1_000_000 { 10 } else { 17 };
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// Computing (prescaler * BS):
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// BITRATE = 1 / (PRESCALER * (1 / PCLK) * (1 + BS1 + BS2)) -- See the Reference Manual
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// BITRATE = PCLK / (PRESCALER * (1 + BS1 + BS2)) -- Simplified
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// let:
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// BS = 1 + BS1 + BS2 -- Number of time quanta per bit
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// PRESCALER_BS = PRESCALER * BS
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// ==>
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// PRESCALER_BS = PCLK / BITRATE
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let prescaler_bs = periph_clock / can_bitrate;
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// Searching for such prescaler value so that the number of quanta per bit is highest.
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let mut bs1_bs2_sum = max_quanta_per_bit - 1;
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while (prescaler_bs % (1 + bs1_bs2_sum) as u32) != 0 {
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if bs1_bs2_sum <= 2 {
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return None; // No solution
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}
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bs1_bs2_sum -= 1;
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}
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let prescaler = prescaler_bs / (1 + bs1_bs2_sum) as u32;
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if (prescaler < 1) || (prescaler > 1024) {
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return None; // No solution
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}
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// Now we have a constraint: (BS1 + BS2) == bs1_bs2_sum.
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// We need to find such values so that the sample point is as close as possible to the optimal value,
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// which is 87.5%, which is 7/8.
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//
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// Solve[(1 + bs1)/(1 + bs1 + bs2) == 7/8, bs2] (* Where 7/8 is 0.875, the recommended sample point location *)
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// {{bs2 -> (1 + bs1)/7}}
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//
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// Hence:
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// bs2 = (1 + bs1) / 7
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// bs1 = (7 * bs1_bs2_sum - 1) / 8
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//
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// Sample point location can be computed as follows:
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// Sample point location = (1 + bs1) / (1 + bs1 + bs2)
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//
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// Since the optimal solution is so close to the maximum, we prepare two solutions, and then pick the best one:
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// - With rounding to nearest
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// - With rounding to zero
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let mut bs1 = ((7 * bs1_bs2_sum - 1) + 4) / 8; // Trying rounding to nearest first
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let mut bs2 = bs1_bs2_sum - bs1;
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assert!(bs1_bs2_sum > bs1);
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let sample_point_permill = 1000 * ((1 + bs1) / (1 + bs1 + bs2)) as u16;
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if sample_point_permill > MAX_SAMPLE_POINT_PERMILL {
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// Nope, too far; now rounding to zero
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bs1 = (7 * bs1_bs2_sum - 1) / 8;
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bs2 = bs1_bs2_sum - bs1;
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}
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// Check is BS1 and BS2 are in range
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if (bs1 < 1) || (bs1 > BS1_MAX) || (bs2 < 1) || (bs2 > BS2_MAX) {
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return None;
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}
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// Check if final bitrate matches the requested
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if can_bitrate != (periph_clock / (prescaler * (1 + bs1 + bs2) as u32)) {
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return None;
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}
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// One is recommended by DS-015, CANOpen, and DeviceNet
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let sjw = 1;
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// Pack into BTR register values
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Some((sjw - 1) << 24 | (bs1 as u32 - 1) << 16 | (bs2 as u32 - 1) << 20 | (prescaler as u32 - 1))
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}
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}
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enum RxFifo {
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Fifo0,
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Fifi1,
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}
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impl<'d, T: Instance> Drop for Can<'d, T> {
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@ -80,14 +345,53 @@ impl<'d, T: Instance> DerefMut for Can<'d, T> {
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}
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pub(crate) mod sealed {
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use embassy_sync::waitqueue::AtomicWaker;
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use heapless::mpmc::Q8;
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pub struct State {
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pub tx_waker: AtomicWaker,
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pub rx_waker: AtomicWaker,
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pub err_waker: AtomicWaker,
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pub rx_queue: Q8<bxcan::Frame>,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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tx_waker: AtomicWaker::new(),
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rx_waker: AtomicWaker::new(),
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err_waker: AtomicWaker::new(),
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rx_queue: Q8::new(),
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}
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}
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}
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pub trait Instance {
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const REGISTERS: *mut bxcan::RegisterBlock;
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fn regs() -> &'static crate::pac::can::Can;
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fn state() -> &'static State;
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}
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}
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pub trait Instance: sealed::Instance + RccPeripheral {}
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pub trait TXInstance {
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type TXInterrupt: crate::interrupt::Interrupt;
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}
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pub trait RX0Instance {
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type RX0Interrupt: crate::interrupt::Interrupt;
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}
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pub trait RX1Instance {
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type RX1Interrupt: crate::interrupt::Interrupt;
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}
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pub trait SCEInstance {
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type SCEInterrupt: crate::interrupt::Interrupt;
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}
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pub trait InterruptableInstance: TXInstance + RX0Instance + RX1Instance + SCEInstance {}
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pub trait Instance: sealed::Instance + RccPeripheral + InterruptableInstance + 'static {}
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pub struct BxcanInstance<'a, T>(PeripheralRef<'a, T>);
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@ -103,10 +407,39 @@ foreach_peripheral!(
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fn regs() -> &'static crate::pac::can::Can {
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&crate::pac::$inst
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}
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fn state() -> &'static sealed::State {
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static STATE: sealed::State = sealed::State::new();
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&STATE
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}
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}
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impl Instance for peripherals::$inst {}
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foreach_interrupt!(
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($inst,can,CAN,TX,$irq:ident) => {
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impl TXInstance for peripherals::$inst {
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type TXInterrupt = crate::interrupt::$irq;
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}
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};
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($inst,can,CAN,RX0,$irq:ident) => {
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impl RX0Instance for peripherals::$inst {
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type RX0Interrupt = crate::interrupt::$irq;
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}
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};
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($inst,can,CAN,RX1,$irq:ident) => {
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impl RX1Instance for peripherals::$inst {
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type RX1Interrupt = crate::interrupt::$irq;
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}
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};
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($inst,can,CAN,SCE,$irq:ident) => {
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impl SCEInstance for peripherals::$inst {
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type SCEInterrupt = crate::interrupt::$irq;
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}
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};
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);
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impl InterruptableInstance for peripherals::$inst {}
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};
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);
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@ -147,3 +480,36 @@ foreach_peripheral!(
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pin_trait!(RxPin, Instance);
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pin_trait!(TxPin, Instance);
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trait Index {
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fn index(&self) -> usize;
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}
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impl Index for bxcan::Mailbox {
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fn index(&self) -> usize {
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match self {
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bxcan::Mailbox::Mailbox0 => 0,
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bxcan::Mailbox::Mailbox1 => 1,
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bxcan::Mailbox::Mailbox2 => 2,
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}
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}
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}
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trait IntoBusError {
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fn into_bus_err(self) -> Option<BusError>;
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}
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impl IntoBusError for Lec {
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fn into_bus_err(self) -> Option<BusError> {
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match self {
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Lec::STUFF => Some(BusError::Stuff),
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Lec::FORM => Some(BusError::Form),
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Lec::ACK => Some(BusError::Acknowledge),
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Lec::BITRECESSIVE => Some(BusError::BitRecessive),
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Lec::BITDOMINANT => Some(BusError::BitDominant),
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Lec::CRC => Some(BusError::Crc),
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Lec::CUSTOM => Some(BusError::Software),
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_ => None,
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}
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}
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}
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