diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs
index 853f639ad..9c9674fd8 100644
--- a/embassy-stm32/src/spi/v1.rs
+++ b/embassy-stm32/src/spi/v1.rs
@@ -31,6 +31,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
+            T::regs().cr1().modify(|w| {
+                w.set_cstart(true);
+            });
         }
 
         tx_f.await;
@@ -76,6 +80,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
+            T::regs().cr1().modify(|w| {
+                w.set_cstart(true);
+            });
         }
 
         join(tx_f, rx_f).await;
@@ -125,6 +133,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
+            T::regs().cr1().modify(|w| {
+                w.set_cstart(true);
+            });
         }
 
         join(tx_f, rx_f).await;
diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index 853f639ad..9c9674fd8 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -31,6 +31,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
+            T::regs().cr1().modify(|w| {
+                w.set_cstart(true);
+            });
         }
 
         tx_f.await;
@@ -76,6 +80,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
+            T::regs().cr1().modify(|w| {
+                w.set_cstart(true);
+            });
         }
 
         join(tx_f, rx_f).await;
@@ -125,6 +133,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
+            T::regs().cr1().modify(|w| {
+                w.set_cstart(true);
+            });
         }
 
         join(tx_f, rx_f).await;
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index 5a19355f9..9c9674fd8 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -31,6 +31,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
             T::regs().cr1().modify(|w| {
                 w.set_cstart(true);
             });
@@ -79,6 +80,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
             T::regs().cr1().modify(|w| {
                 w.set_cstart(true);
             });
@@ -131,6 +133,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(true);
             });
+            #[cfg(spi_v3)]
             T::regs().cr1().modify(|w| {
                 w.set_cstart(true);
             });