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This commit is contained in:
Grant Miller 2022-03-14 15:22:52 -05:00
parent 7cd6f00a90
commit 406b1b3dd2
3 changed files with 27 additions and 0 deletions
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12
embassy-stm32/src/spi/v1.rs
View file

@ -31,6 +31,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
} }
tx_f.await; tx_f.await;
@ -76,6 +80,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
} }
join(tx_f, rx_f).await; join(tx_f, rx_f).await;
@ -125,6 +133,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
} }
join(tx_f, rx_f).await; join(tx_f, rx_f).await;

12
embassy-stm32/src/spi/v2.rs
View file

@ -31,6 +31,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
} }
tx_f.await; tx_f.await;
@ -76,6 +80,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
} }
join(tx_f, rx_f).await; join(tx_f, rx_f).await;
@ -125,6 +133,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| {
w.set_cstart(true);
});
} }
join(tx_f, rx_f).await; join(tx_f, rx_f).await;

3
embassy-stm32/src/spi/v3.rs
View file

@ -31,6 +31,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_cstart(true); w.set_cstart(true);
}); });
@ -79,6 +80,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_cstart(true); w.set_cstart(true);
}); });
@ -131,6 +133,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_spe(true); w.set_spe(true);
}); });
#[cfg(spi_v3)]
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_cstart(true); w.set_cstart(true);
}); });