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Adjust how we deal with read/write being different length.

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Including some docs about it.
Removing the Rx-enablement for write-only operations.
This commit is contained in:
Bob McWhirter 2021-07-22 09:28:42 -04:00
parent 67283c0cbd
commit 473a83a937
4 changed files with 11 additions and 9 deletions
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7
embassy-stm32/src/spi/v1.rs
View file

@ -151,9 +151,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
self.set_word_size(WordSize::EightBit);
@ -233,6 +230,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
assert!(read.len() >= write.len());
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
@ -245,7 +244,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let rx_f = self.rxdma.read(rx_request, rx_src, read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;

7
embassy-stm32/src/spi/v2.rs
View file

@ -163,9 +163,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
Self::set_word_size(WordSize::EightBit);
@ -245,6 +242,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
assert!(read.len() >= write.len());
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
@ -257,7 +256,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().dr().ptr() as *mut u8;
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let rx_f = self.rxdma.read(rx_request, rx_src, read[0..write.len()]);
let tx_request = self.txdma.request();
let tx_dst = T::regs().dr().ptr() as *mut u8;

3
embassy-stm32/src/spi/v3.rs
View file

@ -207,7 +207,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
f.await;
unsafe {
T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(false);
reg.set_txdmaen(false);
});
T::regs().cr1().modify(|w| {
@ -278,6 +277,8 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
assert!(read.len() >= write.len());
Self::set_word_size(WordSize::EightBit);
unsafe {
T::regs().cr1().modify(|w| {

3
embassy-traits/src/spi.rs
View file

@ -29,6 +29,9 @@ pub trait FullDuplex<Word>: Spi<Word> + Write<Word> + Read<Word> {
where
Self: 'a;
/// The `read` array must be at least as long as the `write` array,
/// but is guaranteed to only be filled with bytes equal to the
/// length of the `write` array.
fn read_write<'a>(
&'a mut self,
read: &'a mut [Word],