NaxdyOrg/embassy
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

stm32/rcc: workaround nonsense RAM suicide errata on backup domain reset.

Browse source
This commit is contained in:
Dario Nieuwenhuis 2024-02-23 00:18:24 +01:00
parent 2cceeab564
commit 475dea0208
1 changed files with 12 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
embassy-stm32/src/rcc/bd.rs
View file

@ -201,11 +201,18 @@ impl LsConfig {
bdcr().modify(|w| w.set_bdrst(true)); bdcr().modify(|w| w.set_bdrst(true));
bdcr().modify(|w| w.set_bdrst(false)); bdcr().modify(|w| w.set_bdrst(false));
} }
#[cfg(any(stm32h5))] // H5 has a terrible, terrible errata: 'SRAM2 is erased when the backup domain is reset'
{ // pending a more sane sane way to handle this, just don't reset BD for now.
bdcr().modify(|w| w.set_vswrst(true)); // This means the RTCSEL write below will have no effect, only if it has already been written
bdcr().modify(|w| w.set_vswrst(false)); // after last power-on. Since it's uncommon to dynamically change RTCSEL, this is better than
} // letting half our RAM go magically *poof*.
// STM32H503CB/EB/KB/RB device errata - 2.2.8 SRAM2 unduly erased upon a backup domain reset
// STM32H562xx/563xx/573xx device errata - 2.2.14 SRAM2 is erased when the backup domain is reset
//#[cfg(any(stm32h5))]
//{
// bdcr().modify(|w| w.set_vswrst(true));
// bdcr().modify(|w| w.set_vswrst(false));
//}
#[cfg(any(stm32c0))] #[cfg(any(stm32c0))]
{ {
bdcr().modify(|w| w.set_rtcrst(true)); bdcr().modify(|w| w.set_rtcrst(true));