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update metapac

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This commit is contained in:
eZio Pan 2024-02-28 18:08:41 +08:00
parent 5ced938184
commit 47c579eba2
5 changed files with 15 additions and 11 deletions
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4
embassy-stm32/Cargo.toml
View file

@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0" sdio-host = "0.5.0"
critical-section = "1.1" critical-section = "1.1"
#stm32-metapac = { version = "15" } #stm32-metapac = { version = "15" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a" } stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-4a0bcec33362449fb733c066936d25cbabab396a" }
vcell = "0.1.3" vcell = "0.1.3"
bxcan = "0.7.0" bxcan = "0.7.0"
nb = "1.0.0" nb = "1.0.0"
@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36" proc-macro2 = "1.0.36"
quote = "1.0.15" quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]} #stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a", default-features = false, features = ["metadata"]} stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-4a0bcec33362449fb733c066936d25cbabab396a", default-features = false, features = ["metadata"]}
[features] [features]

4
embassy-stm32/src/can/fd/peripheral.rs
View file

@ -303,7 +303,9 @@ impl Registers {
// Framework specific settings are set here // Framework specific settings are set here
// set TxBuffer to Queue Mode // set TxBuffer to Queue Mode
self.regs.txbc().write(|w| w.set_tfqm(true)); self.regs
.txbc()
.write(|w| w.set_tfqm(crate::pac::can::vals::Tfqm::QUEUE));
// set standard filters list size to 28 // set standard filters list size to 28
// set extended filters list size to 8 // set extended filters list size to 8

2
embassy-stm32/src/opamp.rs
View file

@ -90,6 +90,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
in_pin.set_as_analog(); in_pin.set_as_analog();
out_pin.set_as_analog(); out_pin.set_as_analog();
// PGA_GAIN value may have different meaning in different MCU serials, use with caution.
let (vm_sel, pga_gain) = match gain { let (vm_sel, pga_gain) = match gain {
OpAmpGain::Mul1 => (0b11, 0b00), OpAmpGain::Mul1 => (0b11, 0b00),
OpAmpGain::Mul2 => (0b10, 0b00), OpAmpGain::Mul2 => (0b10, 0b00),
@ -127,6 +128,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
into_ref!(pin); into_ref!(pin);
pin.set_as_analog(); pin.set_as_analog();
// PGA_GAIN value may have different meaning in different MCU serials, use with caution.
let (vm_sel, pga_gain) = match gain { let (vm_sel, pga_gain) = match gain {
OpAmpGain::Mul1 => (0b11, 0b00), OpAmpGain::Mul1 => (0b11, 0b00),
OpAmpGain::Mul2 => (0b10, 0b00), OpAmpGain::Mul2 => (0b10, 0b00),

12
embassy-stm32/src/timer/mod.rs
View file

@ -379,7 +379,7 @@ pub(crate) mod sealed {
let regs = Self::regs_gp32(); let regs = Self::regs_gp32();
regs.psc().write(|r| r.set_psc(psc)); regs.psc().write(|r| r.set_psc(psc));
regs.arr().write(|r| r.set_arr(arr)); regs.arr().write_value(arr);
regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY)); regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
regs.egr().write(|r| r.set_ug(true)); regs.egr().write(|r| r.set_ug(true));
@ -391,7 +391,7 @@ pub(crate) mod sealed {
let timer_f = Self::frequency(); let timer_f = Self::frequency();
let regs = Self::regs_gp32(); let regs = Self::regs_gp32();
let arr = regs.arr().read().arr(); let arr = regs.arr().read();
let psc = regs.psc().read().psc(); let psc = regs.psc().read().psc();
timer_f / arr / (psc + 1) timer_f / arr / (psc + 1)
@ -399,22 +399,22 @@ pub(crate) mod sealed {
/// Set comapre value for a channel. /// Set comapre value for a channel.
fn set_compare_value(&self, channel: Channel, value: u32) { fn set_compare_value(&self, channel: Channel, value: u32) {
Self::regs_gp32().ccr(channel.index()).modify(|w| w.set_ccr(value)); Self::regs_gp32().ccr(channel.index()).write_value(value);
} }
/// Get capture value for a channel. /// Get capture value for a channel.
fn get_capture_value(&self, channel: Channel) -> u32 { fn get_capture_value(&self, channel: Channel) -> u32 {
Self::regs_gp32().ccr(channel.index()).read().ccr() Self::regs_gp32().ccr(channel.index()).read()
} }
/// Get max compare value. This depends on the timer frequency and the clock frequency from RCC. /// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
fn get_max_compare_value(&self) -> u32 { fn get_max_compare_value(&self) -> u32 {
Self::regs_gp32().arr().read().arr() Self::regs_gp32().arr().read()
} }
/// Get compare value for a channel. /// Get compare value for a channel.
fn get_compare_value(&self, channel: Channel) -> u32 { fn get_compare_value(&self, channel: Channel) -> u32 {
Self::regs_gp32().ccr(channel.index()).read().ccr() Self::regs_gp32().ccr(channel.index()).read()
} }
} }

4
examples/stm32h7/src/bin/low_level_timer_api.rs
View file

@ -113,11 +113,11 @@ impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> {
} }
pub fn get_max_duty(&self) -> u32 { pub fn get_max_duty(&self) -> u32 {
T::regs_gp32().arr().read().arr() T::regs_gp32().arr().read()
} }
pub fn set_duty(&mut self, channel: Channel, duty: u32) { pub fn set_duty(&mut self, channel: Channel, duty: u32) {
defmt::assert!(duty < self.get_max_duty()); defmt::assert!(duty < self.get_max_duty());
T::regs_gp32().ccr(channel.index()).modify(|w| w.set_ccr(duty)) T::regs_gp32().ccr(channel.index()).write_value(duty)
} }
} }