docs: document spi, rtc and rest of uart for embassy-rp
This commit is contained in:
Ulf Lilleengen
parent
e45e3e76b5
commit
486b67e895
4 changed files with 83 additions and 2 deletions
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@ -61,9 +61,13 @@ impl Default for Config {
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}
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}
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/// PWM input mode.
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pub enum InputMode {
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/// Level mode.
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Level,
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/// Rising edge mode.
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RisingEdge,
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/// Falling edge mode.
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FallingEdge,
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}
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@ -77,6 +81,7 @@ impl From<InputMode> for Divmode {
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}
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}
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/// PWM driver.
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pub struct Pwm<'d, T: Channel> {
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inner: PeripheralRef<'d, T>,
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pin_a: Option<PeripheralRef<'d, AnyPin>>,
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@ -194,6 +194,7 @@ mod sealed {
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}
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}
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/// RTC peripheral instance.
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pub trait Instance: sealed::Instance {}
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impl sealed::Instance for crate::peripherals::RTC {
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@ -11,6 +11,7 @@ use crate::gpio::sealed::Pin as _;
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::{pac, peripherals, Peripheral};
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/// SPI errors.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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@ -18,11 +19,15 @@ pub enum Error {
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// No errors for now
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}
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/// SPI configuration.
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#[non_exhaustive]
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#[derive(Clone)]
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pub struct Config {
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/// Frequency.
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pub frequency: u32,
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/// Phase.
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pub phase: Phase,
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/// Polarity.
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pub polarity: Polarity,
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}
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@ -36,6 +41,7 @@ impl Default for Config {
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}
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}
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/// SPI driver.
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pub struct Spi<'d, T: Instance, M: Mode> {
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inner: PeripheralRef<'d, T>,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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@ -119,6 +125,7 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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}
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}
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/// Write data to SPI blocking execution until done.
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pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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for &b in data {
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@ -131,6 +138,7 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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Ok(())
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}
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/// Transfer data in place to SPI blocking execution until done.
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pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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for b in data {
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@ -143,6 +151,7 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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Ok(())
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}
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/// Read data from SPI blocking execution until done.
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pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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for b in data {
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@ -155,6 +164,7 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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Ok(())
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}
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/// Transfer data to SPI blocking execution until done.
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pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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let len = read.len().max(write.len());
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@ -172,12 +182,14 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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Ok(())
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}
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/// Block execution until SPI is done.
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pub fn flush(&mut self) -> Result<(), Error> {
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let p = self.inner.regs();
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while p.sr().read().bsy() {}
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Ok(())
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}
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/// Set SPI frequency.
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pub fn set_frequency(&mut self, freq: u32) {
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let (presc, postdiv) = calc_prescs(freq);
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let p = self.inner.regs();
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@ -196,6 +208,7 @@ impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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}
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impl<'d, T: Instance> Spi<'d, T, Blocking> {
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/// Create an SPI driver in blocking mode.
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pub fn new_blocking(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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@ -216,6 +229,7 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> {
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)
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}
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/// Create an SPI driver in blocking mode supporting writes only.
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pub fn new_blocking_txonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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@ -235,6 +249,7 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> {
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)
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}
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/// Create an SPI driver in blocking mode supporting reads only.
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pub fn new_blocking_rxonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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@ -256,6 +271,7 @@ impl<'d, T: Instance> Spi<'d, T, Blocking> {
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}
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impl<'d, T: Instance> Spi<'d, T, Async> {
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/// Create an SPI driver in async mode supporting DMA operations.
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pub fn new(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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@ -278,6 +294,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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)
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}
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/// Create an SPI driver in async mode supporting DMA write operations only.
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pub fn new_txonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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@ -298,6 +315,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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)
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}
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/// Create an SPI driver in async mode supporting DMA read operations only.
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pub fn new_rxonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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@ -318,6 +336,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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)
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}
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/// Write data to SPI using DMA.
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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@ -340,6 +359,7 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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Ok(())
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}
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/// Read data from SPI using DMA.
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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// Start RX first. Transfer starts when TX starts, if RX
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// is not started yet we might lose bytes.
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@ -365,10 +385,12 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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Ok(())
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}
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/// Transfer data to SPI using DMA.
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pub async fn transfer(&mut self, rx_buffer: &mut [u8], tx_buffer: &[u8]) -> Result<(), Error> {
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self.transfer_inner(rx_buffer, tx_buffer).await
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}
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/// Transfer data in place to SPI using DMA.
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pub async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Error> {
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self.transfer_inner(words, words).await
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}
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@ -434,7 +456,10 @@ mod sealed {
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}
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}
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/// Mode.
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pub trait Mode: sealed::Mode {}
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/// SPI instance trait.
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pub trait Instance: sealed::Instance {}
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macro_rules! impl_instance {
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@ -454,9 +479,13 @@ macro_rules! impl_instance {
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impl_instance!(SPI0, Spi0, 16, 17);
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impl_instance!(SPI1, Spi1, 18, 19);
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/// CLK pin.
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pub trait ClkPin<T: Instance>: GpioPin {}
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/// CS pin.
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pub trait CsPin<T: Instance>: GpioPin {}
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/// MOSI pin.
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pub trait MosiPin<T: Instance>: GpioPin {}
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/// MISO pin.
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pub trait MisoPin<T: Instance>: GpioPin {}
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macro_rules! impl_pin {
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@ -503,7 +532,9 @@ macro_rules! impl_mode {
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};
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}
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/// Blocking mode.
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pub struct Blocking;
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/// Async mode.
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pub struct Async;
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impl_mode!(Blocking);
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@ -20,11 +20,16 @@ use crate::{interrupt, pac, peripherals, Peripheral, RegExt};
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mod buffered;
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pub use buffered::{BufferedInterruptHandler, BufferedUart, BufferedUartRx, BufferedUartTx};
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/// Word length.
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum DataBits {
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/// 5 bits.
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DataBits5,
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/// 6 bits.
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DataBits6,
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/// 7 bits.
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DataBits7,
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/// 8 bits.
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DataBits8,
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}
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@ -39,13 +44,18 @@ impl DataBits {
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}
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}
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/// Parity bit.
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum Parity {
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/// No parity.
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ParityNone,
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/// Even parity.
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ParityEven,
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/// Odd parity.
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ParityOdd,
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}
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/// Stop bits.
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum StopBits {
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#[doc = "1 stop bit"]
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@ -54,20 +64,25 @@ pub enum StopBits {
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STOP2,
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}
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/// UART config.
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#[non_exhaustive]
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub struct Config {
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/// Baud rate.
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pub baudrate: u32,
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/// Word length.
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pub data_bits: DataBits,
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/// Stop bits.
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pub stop_bits: StopBits,
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/// Parity bit.
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pub parity: Parity,
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/// Invert the tx pin output
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pub invert_tx: bool,
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/// Invert the rx pin input
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pub invert_rx: bool,
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// Invert the rts pin
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/// Invert the rts pin
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pub invert_rts: bool,
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// Invert the cts pin
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/// Invert the cts pin
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pub invert_cts: bool,
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}
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@ -102,21 +117,25 @@ pub enum Error {
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Framing,
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}
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/// Internal DMA state of UART RX.
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pub struct DmaState {
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rx_err_waker: AtomicWaker,
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rx_errs: AtomicU16,
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}
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/// UART driver.
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pub struct Uart<'d, T: Instance, M: Mode> {
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tx: UartTx<'d, T, M>,
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rx: UartRx<'d, T, M>,
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}
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/// UART TX driver.
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pub struct UartTx<'d, T: Instance, M: Mode> {
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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phantom: PhantomData<(&'d mut T, M)>,
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}
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/// UART RX driver.
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pub struct UartRx<'d, T: Instance, M: Mode> {
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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phantom: PhantomData<(&'d mut T, M)>,
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@ -142,6 +161,7 @@ impl<'d, T: Instance, M: Mode> UartTx<'d, T, M> {
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}
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}
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/// Transmit the provided buffer blocking execution until done.
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let r = T::regs();
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for &b in buffer {
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@ -151,12 +171,14 @@ impl<'d, T: Instance, M: Mode> UartTx<'d, T, M> {
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Ok(())
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}
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/// Flush UART TX blocking execution until done.
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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let r = T::regs();
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while !r.uartfr().read().txfe() {}
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Ok(())
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}
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/// Check if UART is busy transmitting.
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pub fn busy(&self) -> bool {
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T::regs().uartfr().read().busy()
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}
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@ -191,6 +213,8 @@ impl<'d, T: Instance, M: Mode> UartTx<'d, T, M> {
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}
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impl<'d, T: Instance> UartTx<'d, T, Blocking> {
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/// Convert this uart TX instance into a buffered uart using the provided
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/// irq and transmit buffer.
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pub fn into_buffered(
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self,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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@ -203,6 +227,7 @@ impl<'d, T: Instance> UartTx<'d, T, Blocking> {
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}
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impl<'d, T: Instance> UartTx<'d, T, Async> {
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/// Write to UART TX from the provided buffer using DMA.
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let ch = self.tx_dma.as_mut().unwrap();
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let transfer = unsafe {
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@ -246,6 +271,7 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
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}
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}
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/// Read from UART RX blocking execution until done.
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pub fn blocking_read(&mut self, mut buffer: &mut [u8]) -> Result<(), Error> {
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while buffer.len() > 0 {
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let received = self.drain_fifo(buffer)?;
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@ -294,6 +320,7 @@ impl<'d, T: Instance, M: Mode> Drop for UartRx<'d, T, M> {
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}
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impl<'d, T: Instance> UartRx<'d, T, Blocking> {
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/// Create a new UART RX instance for blocking mode operations.
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pub fn new_blocking(
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_uart: impl Peripheral<P = T> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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@ -304,6 +331,8 @@ impl<'d, T: Instance> UartRx<'d, T, Blocking> {
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Self::new_inner(false, None)
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}
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/// Convert this uart RX instance into a buffered uart using the provided
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/// irq and receive buffer.
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pub fn into_buffered(
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self,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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@ -315,6 +344,7 @@ impl<'d, T: Instance> UartRx<'d, T, Blocking> {
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}
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}
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_uart: PhantomData<T>,
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}
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@ -338,6 +368,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
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}
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impl<'d, T: Instance> UartRx<'d, T, Async> {
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/// Read from UART RX into the provided buffer.
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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// clear error flags before we drain the fifo. errors that have accumulated
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// in the flags will also be present in the fifo.
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@ -458,6 +489,8 @@ impl<'d, T: Instance> Uart<'d, T, Blocking> {
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)
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}
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/// Convert this uart instance into a buffered uart using the provided
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/// irq, transmit and receive buffers.
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pub fn into_buffered(
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self,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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@ -667,22 +700,27 @@ impl<'d, T: Instance + 'd, M: Mode> Uart<'d, T, M> {
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}
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impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
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/// Transmit the provided buffer blocking execution until done.
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.blocking_write(buffer)
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}
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/// Flush UART TX blocking execution until done.
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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self.tx.blocking_flush()
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}
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/// Read from UART RX blocking execution until done.
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.blocking_read(buffer)
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}
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/// Check if UART is busy transmitting.
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pub fn busy(&self) -> bool {
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self.tx.busy()
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}
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/// Wait until TX is empty and send break condition.
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pub async fn send_break(&mut self, bits: u32) {
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self.tx.send_break(bits).await
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}
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@ -695,10 +733,12 @@ impl<'d, T: Instance, M: Mode> Uart<'d, T, M> {
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}
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impl<'d, T: Instance> Uart<'d, T, Async> {
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/// Write to UART TX from the provided buffer.
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.write(buffer).await
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}
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/// Read from UART RX into the provided buffer.
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
||||
self.rx.read(buffer).await
|
||||
}
|
||||
|
|
@ -889,6 +929,7 @@ mod sealed {
|
|||
pub trait RtsPin<T: Instance> {}
|
||||
}
|
||||
|
||||
/// UART mode.
|
||||
pub trait Mode: sealed::Mode {}
|
||||
|
||||
macro_rules! impl_mode {
|
||||
|
|
@ -898,12 +939,15 @@ macro_rules! impl_mode {
|
|||
};
|
||||
}
|
||||
|
||||
/// Blocking mode.
|
||||
pub struct Blocking;
|
||||
/// Async mode.
|
||||
pub struct Async;
|
||||
|
||||
impl_mode!(Blocking);
|
||||
impl_mode!(Async);
|
||||
|
||||
/// UART instance trait.
|
||||
pub trait Instance: sealed::Instance {}
|
||||
|
||||
macro_rules! impl_instance {
|
||||
|
|
|
|||
Loading…
Reference in a new issue