From face0312451fd56fb5475472dc793e7397dce563 Mon Sep 17 00:00:00 2001 From: swanandx <73115739+swanandx@users.noreply.github.com> Date: Wed, 3 Jan 2024 19:22:01 +0530 Subject: [PATCH 1/4] feat: new_txonly_nosck in spis --- embassy-nrf/src/spis.rs | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs index e202c6c27..16ac82e5f 100644 --- a/embassy-nrf/src/spis.rs +++ b/embassy-nrf/src/spis.rs @@ -105,7 +105,7 @@ impl<'d, T: Instance> Spis<'d, T> { Self::new_inner( spis, cs.map_into(), - sck.map_into(), + Some(sck.map_into()), Some(miso.map_into()), Some(mosi.map_into()), config, @@ -122,7 +122,14 @@ impl<'d, T: Instance> Spis<'d, T> { config: Config, ) -> Self { into_ref!(cs, sck, miso); - Self::new_inner(spis, cs.map_into(), sck.map_into(), Some(miso.map_into()), None, config) + Self::new_inner( + spis, + cs.map_into(), + Some(sck.map_into()), + Some(miso.map_into()), + None, + config, + ) } /// Create a new SPIS driver, capable of RX only (MOSI only). @@ -135,13 +142,32 @@ impl<'d, T: Instance> Spis<'d, T> { config: Config, ) -> Self { into_ref!(cs, sck, mosi); - Self::new_inner(spis, cs.map_into(), sck.map_into(), None, Some(mosi.map_into()), config) + Self::new_inner( + spis, + cs.map_into(), + Some(sck.map_into()), + None, + Some(mosi.map_into()), + config, + ) + } + + /// Create a new SPIS driver, capable of TX only (MISO only) without SCK pin. + pub fn new_txonly_nosck( + spis: impl Peripheral

+ 'd, + _irq: impl interrupt::typelevel::Binding> + 'd, + cs: impl Peripheral

+ 'd, + miso: impl Peripheral

+ 'd, + config: Config, + ) -> Self { + into_ref!(cs, miso); + Self::new_inner(spis, cs.map_into(), None, Some(miso.map_into()), None, config) } fn new_inner( spis: impl Peripheral

+ 'd, cs: PeripheralRef<'d, AnyPin>, - sck: PeripheralRef<'d, AnyPin>, + sck: Option>, miso: Option>, mosi: Option>, config: Config, @@ -153,10 +179,12 @@ impl<'d, T: Instance> Spis<'d, T> { let r = T::regs(); // Configure pins. - sck.conf().write(|w| w.input().connect().drive().h0h1()); - r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) }); cs.conf().write(|w| w.input().connect().drive().h0h1()); r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) }); + if let Some(sck) = &sck { + sck.conf().write(|w| w.input().connect().drive().h0h1()); + r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) }); + } if let Some(mosi) = &mosi { mosi.conf().write(|w| w.input().connect().drive().h0h1()); r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) }); From 8352d13cfd7ea46abf8bd2bb460ff1ce32e7da8d Mon Sep 17 00:00:00 2001 From: swanandx <73115739+swanandx@users.noreply.github.com> Date: Wed, 3 Jan 2024 19:25:09 +0530 Subject: [PATCH 2/4] feat: new_txonly_nosck in spim --- embassy-nrf/src/spim.rs | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs index 5d3c3268c..ab16491a5 100644 --- a/embassy-nrf/src/spim.rs +++ b/embassy-nrf/src/spim.rs @@ -99,7 +99,7 @@ impl<'d, T: Instance> Spim<'d, T> { into_ref!(sck, miso, mosi); Self::new_inner( spim, - sck.map_into(), + Some(sck.map_into()), Some(miso.map_into()), Some(mosi.map_into()), config, @@ -115,7 +115,7 @@ impl<'d, T: Instance> Spim<'d, T> { config: Config, ) -> Self { into_ref!(sck, mosi); - Self::new_inner(spim, sck.map_into(), None, Some(mosi.map_into()), config) + Self::new_inner(spim, Some(sck.map_into()), None, Some(mosi.map_into()), config) } /// Create a new SPIM driver, capable of RX only (MISO only). @@ -127,12 +127,23 @@ impl<'d, T: Instance> Spim<'d, T> { config: Config, ) -> Self { into_ref!(sck, miso); - Self::new_inner(spim, sck.map_into(), Some(miso.map_into()), None, config) + Self::new_inner(spim, Some(sck.map_into()), Some(miso.map_into()), None, config) + } + + /// Create a new SPIM driver, capable of TX only (MOSI only), without SCK pin. + pub fn new_txonly_nosck( + spim: impl Peripheral

+ 'd, + _irq: impl interrupt::typelevel::Binding> + 'd, + mosi: impl Peripheral

+ 'd, + config: Config, + ) -> Self { + into_ref!(mosi); + Self::new_inner(spim, None, None, Some(mosi.map_into()), config) } fn new_inner( spim: impl Peripheral

+ 'd, - sck: PeripheralRef<'d, AnyPin>, + sck: Option>, miso: Option>, mosi: Option>, config: Config, @@ -142,7 +153,9 @@ impl<'d, T: Instance> Spim<'d, T> { let r = T::regs(); // Configure pins - sck.conf().write(|w| w.dir().output().drive().h0h1()); + if let Some(sck) = &sck { + sck.conf().write(|w| w.dir().output().drive().h0h1()); + } if let Some(mosi) = &mosi { mosi.conf().write(|w| w.dir().output().drive().h0h1()); } From 046af81a10a0e979d207706a59290151089f49ee Mon Sep 17 00:00:00 2001 From: swanandx <73115739+swanandx@users.noreply.github.com> Date: Wed, 3 Jan 2024 19:33:43 +0530 Subject: [PATCH 3/4] fix: info_ref! can't be called on Option --- embassy-nrf/src/spis.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs index 16ac82e5f..3aad25298 100644 --- a/embassy-nrf/src/spis.rs +++ b/embassy-nrf/src/spis.rs @@ -174,7 +174,7 @@ impl<'d, T: Instance> Spis<'d, T> { ) -> Self { compiler_fence(Ordering::SeqCst); - into_ref!(spis, cs, sck); + into_ref!(spis, cs); let r = T::regs(); From bdaf722cb899504032816d09de63c0f44b2776e8 Mon Sep 17 00:00:00 2001 From: swanandx <73115739+swanandx@users.noreply.github.com> Date: Wed, 3 Jan 2024 19:35:30 +0530 Subject: [PATCH 4/4] fix: check if sck is some before setting high or low --- embassy-nrf/src/spim.rs | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs index ab16491a5..b0723d495 100644 --- a/embassy-nrf/src/spim.rs +++ b/embassy-nrf/src/spim.rs @@ -165,13 +165,17 @@ impl<'d, T: Instance> Spim<'d, T> { match config.mode.polarity { Polarity::IdleHigh => { - sck.set_high(); + if let Some(sck) = &sck { + sck.set_high(); + } if let Some(mosi) = &mosi { mosi.set_high(); } } Polarity::IdleLow => { - sck.set_low(); + if let Some(sck) = &sck { + sck.set_low(); + } if let Some(mosi) = &mosi { mosi.set_low(); }