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fix: revert race condition introduced for riscv

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This commit is contained in:
Ulf Lilleengen 2022-11-23 13:17:05 +01:00
parent 2fa2c1a6fe
commit 50c5cc5db6
Failed to extract signature
1 changed files with 13 additions and 5 deletions
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18
embassy-executor/src/arch/riscv32.rs
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@ -55,11 +55,19 @@ impl Executor {
unsafe {
self.inner.poll();
// we do not care about race conditions between the load and store operations, interrupts
// will only set this value to true.
// if there is work to do, loop back to polling
if !SIGNAL_WORK_THREAD_MODE.fetch_and(false, Ordering::SeqCst) {
core::arch::asm!("wfi");
}
//will only set this value to true.
critical_section::with(|_| {
// if there is work to do, loop back to polling
// TODO can we relax this?
if SIGNAL_WORK_THREAD_MODE.load(Ordering::SeqCst) {
SIGNAL_WORK_THREAD_MODE.store(false, Ordering::SeqCst);
}
// if not, wait for interrupt
else {
core::arch::asm!("wfi");
}
});
// if an interrupt occurred while waiting, it will be serviced here
}
}
}