Add async API for I2C
This commit is contained in:
Mathias
Dario Nieuwenhuis
parent
be68d8ebb7
commit
53c34ccc39
1 changed files with 225 additions and 56 deletions
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@ -1,8 +1,13 @@
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use core::marker::PhantomData;
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use embassy_hal_common::into_ref;
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use atomic_polyfill::Ordering;
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use pac::i2c;
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use crate::dma::{AnyChannel, Channel};
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use crate::gpio::sealed::Pin;
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use crate::gpio::AnyPin;
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use crate::{pac, peripherals, Peripheral};
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/// I2C error abort reason
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@ -49,9 +54,165 @@ impl Default for Config {
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const FIFO_SIZE: u8 = 16;
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pub struct I2c<'d, T: Instance, M: Mode> {
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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dma_buf: [u16; 256],
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phantom: PhantomData<(&'d mut T, M)>,
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}
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impl<'d, T: Instance> I2c<'d, T, Async> {
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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tx_dma: impl Peripheral<P = impl Channel> + 'd,
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rx_dma: impl Peripheral<P = impl Channel> + 'd,
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config: Config,
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) -> Self {
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into_ref!(scl, sda, irq, tx_dma, rx_dma);
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// Enable interrupts
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unsafe {
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T::regs().ic_intr_mask().modify(|w| {
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w.set_m_rx_done(true);
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});
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}
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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Self::new_inner(
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_peri,
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scl.map_into(),
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sda.map_into(),
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Some(tx_dma.map_into()),
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Some(rx_dma.map_into()),
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config,
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)
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}
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unsafe fn on_interrupt(_: *mut ()) {
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let status = T::regs().ic_intr_stat().read();
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// FIXME:
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if status.tcr() || status.tc() {
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let state = T::state();
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state.chunks_transferred.fetch_add(1, Ordering::Relaxed);
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state.waker.wake();
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}
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// The flag can only be cleared by writting to nbytes, we won't do that here, so disable
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// the interrupt
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// critical_section::with(|_| {
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// regs.cr1().modify(|w| w.set_tcie(false));
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// });
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}
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async fn write_internal(&mut self, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
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let len = bytes.len();
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for (idx, chunk) in bytes.chunks(self.dma_buf.len()).enumerate() {
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let first = idx == 0;
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let last = idx * self.dma_buf.len() + chunk.len() == len;
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for (i, byte) in chunk.iter().enumerate() {
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let mut b = i2c::regs::IcDataCmd::default();
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b.set_dat(*byte);
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b.set_stop(send_stop && last);
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self.dma_buf[i] = b.0 as u16;
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}
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// Note(safety): Unwrap should be safe, as this can only be called
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// when `Mode == Async`, where we have dma channels.
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let ch = self.tx_dma.as_mut().unwrap();
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let transfer = unsafe {
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T::regs().ic_dma_cr().modify(|w| {
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w.set_tdmae(true);
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});
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crate::dma::write(ch, &self.dma_buf, T::regs().ic_data_cmd().ptr() as *mut _, T::TX_DREQ)
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};
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transfer.await;
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}
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Ok(())
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}
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async fn read_internal(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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let len = buffer.len();
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self.read_blocking_internal(&mut buffer[..1], true, len == 1)?;
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if len > 2 {
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// Note(safety): Unwrap should be safe, as this can only be called
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// when `Mode == Async`, where we have dma channels.
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let ch = self.rx_dma.as_mut().unwrap();
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let transfer = unsafe {
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T::regs().ic_data_cmd().modify(|w| {
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w.set_cmd(true);
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});
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T::regs().ic_dma_cr().modify(|reg| {
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reg.set_rdmae(true);
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(
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ch,
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T::regs().ic_data_cmd().ptr() as *const _,
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&mut buffer[1..len - 1],
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T::RX_DREQ,
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)
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};
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transfer.await;
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}
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if len > 2 {
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self.read_blocking_internal(&mut buffer[len - 1..], false, true)?;
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}
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Ok(())
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}
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// =========================
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// Async public API
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// =========================
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pub async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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if bytes.is_empty() {
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self.write_blocking_internal(bytes, true)
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} else {
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self.write_internal(bytes, true).await
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}
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}
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pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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if buffer.is_empty() {
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self.read_blocking_internal(buffer, true, true)
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} else {
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self.read_internal(buffer).await
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}
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}
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pub async fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(address.into())?;
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if bytes.is_empty() {
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self.write_blocking_internal(bytes, false)?;
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} else {
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self.write_internal(bytes, false).await?;
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}
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if buffer.is_empty() {
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self.read_blocking_internal(buffer, true, true)
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} else {
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self.read_internal(buffer).await
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}
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}
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}
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impl<'d, T: Instance> I2c<'d, T, Blocking> {
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pub fn new_blocking(
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_peri: impl Peripheral<P = T> + 'd,
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@ -59,7 +220,21 @@ impl<'d, T: Instance> I2c<'d, T, Blocking> {
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(_peri, scl, sda);
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into_ref!(scl, sda);
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Self::new_inner(_peri, scl.map_into(), sda.map_into(), None, None, config)
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}
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}
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impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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fn new_inner(
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_peri: impl Peripheral<P = T> + 'd,
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scl: PeripheralRef<'d, AnyPin>,
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sda: PeripheralRef<'d, AnyPin>,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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config: Config,
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) -> Self {
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into_ref!(_peri);
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assert!(config.frequency <= 1_000_000);
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assert!(config.frequency > 0);
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@ -152,11 +327,14 @@ impl<'d, T: Instance> I2c<'d, T, Blocking> {
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p.ic_enable().write(|w| w.set_enable(true));
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}
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Self { phantom: PhantomData }
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Self {
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tx_dma,
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rx_dma,
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dma_buf: [0; 256],
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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fn setup(addr: u16) -> Result<(), Error> {
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if addr >= 0x80 {
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return Err(Error::AddressOutOfRange(addr));
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@ -304,46 +482,6 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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}
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}
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// impl<'d, T: Instance> I2c<'d, T, Async> { // ========================= //
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// Async public API // =========================
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// pub async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(),
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// Error> { if bytes.is_empty() { self.write_blocking_internal(address,
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// bytes, true) } else { self.write_dma_internal(address, bytes,
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// true, true).await } }
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// pub async fn write_vectored(&mut self, address: u8, bytes: &[&[u8]]) ->
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// Result<(), Error> { if bytes.is_empty() { return
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// Err(Error::ZeroLengthTransfer); } let mut iter = bytes.iter();
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// let mut first = true; let mut current = iter.next(); while let
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// Some(c) = current { let next = iter.next(); let is_last =
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// next.is_none();
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// self.write_dma_internal(address, c, first, is_last).await?;
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// first = false;
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// current = next;
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// } Ok(())
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// }
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// pub async fn read(&mut self, address: u8, buffer: &mut [u8]) ->
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// Result<(), Error> { if buffer.is_empty() {
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// self.read_blocking_internal(address, buffer, false) } else {
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// self.read_dma_internal(address, buffer, false).await } }
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// pub async fn write_read(&mut self, address: u8, bytes: &[u8], buffer:
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// &mut [u8]) -> Result<(), Error> { if bytes.is_empty() {
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// self.write_blocking_internal(address, bytes, false)?; } else {
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// self.write_dma_internal(address, bytes, true, true).await?; }
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// if buffer.is_empty() { self.read_blocking_internal(address, buffer,
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// true)?; } else { self.read_dma_internal(address, buffer,
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// true).await?; }
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// Ok(())
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// }
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// }
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mod eh02 {
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use super::*;
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@ -478,7 +616,34 @@ fn i2c_reserved_addr(addr: u16) -> bool {
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}
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mod sealed {
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pub trait Instance {}
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use atomic_polyfill::AtomicUsize;
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use embassy_cortex_m::interrupt::Interrupt;
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use embassy_sync::waitqueue::AtomicWaker;
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pub(crate) struct State {
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pub(crate) waker: AtomicWaker,
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pub(crate) chunks_transferred: AtomicUsize,
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}
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impl State {
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pub(crate) const fn new() -> Self {
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Self {
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waker: AtomicWaker::new(),
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chunks_transferred: AtomicUsize::new(0),
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}
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}
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}
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pub trait Instance {
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const TX_DREQ: u8;
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const RX_DREQ: u8;
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type Interrupt: Interrupt;
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fn regs() -> crate::pac::i2c::I2c;
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fn state() -> &'static State;
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}
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pub trait Mode {}
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pub trait SdaPin<T: Instance> {}
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@ -500,27 +665,31 @@ pub struct Async;
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impl_mode!(Blocking);
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impl_mode!(Async);
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pub trait Instance: sealed::Instance {
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type Interrupt;
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fn regs() -> pac::i2c::I2c;
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}
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pub trait Instance: sealed::Instance {}
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macro_rules! impl_instance {
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($type:ident, $irq:ident) => {
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impl sealed::Instance for peripherals::$type {}
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impl Instance for peripherals::$type {
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($type:ident, $irq:ident, $tx_dreq:expr, $rx_dreq:expr) => {
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impl sealed::Instance for peripherals::$type {
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const TX_DREQ: u8 = $tx_dreq;
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const RX_DREQ: u8 = $rx_dreq;
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type Interrupt = crate::interrupt::$irq;
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fn regs() -> pac::i2c::I2c {
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pac::$type
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}
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fn state() -> &'static sealed::State {
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static STATE: sealed::State = sealed::State::new();
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&STATE
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}
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}
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impl Instance for peripherals::$type {}
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};
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}
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impl_instance!(I2C0, I2C0_IRQ);
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impl_instance!(I2C1, I2C1_IRQ);
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impl_instance!(I2C0, I2C0_IRQ, 32, 33);
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impl_instance!(I2C1, I2C1_IRQ, 34, 35);
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pub trait SdaPin<T: Instance>: sealed::SdaPin<T> + crate::gpio::Pin {}
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pub trait SclPin<T: Instance>: sealed::SclPin<T> + crate::gpio::Pin {}
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