From 58d503a77da73204f097fae1f1a2a1ce2cf90600 Mon Sep 17 00:00:00 2001
From: sodo <djdisodo@gmail.com>
Date: Sun, 10 Dec 2023 01:45:24 +0900
Subject: [PATCH 001/392] add avr support
---
embassy-executor-macros/src/lib.rs | 7 +++
embassy-executor-macros/src/macros/main.rs | 14 +++++
embassy-executor/Cargo.toml | 1 +
embassy-executor/src/arch/avr.rs | 60 ++++++++++++++++++++++
embassy-executor/src/lib.rs | 3 +-
5 files changed, 84 insertions(+), 1 deletion(-)
create mode 100644 embassy-executor/src/arch/avr.rs
diff --git a/embassy-executor-macros/src/lib.rs b/embassy-executor-macros/src/lib.rs
index c9d58746a..5461fe04c 100644
--- a/embassy-executor-macros/src/lib.rs
+++ b/embassy-executor-macros/src/lib.rs
@@ -62,6 +62,13 @@ pub fn task(args: TokenStream, item: TokenStream) -> TokenStream {
task::run(&args.meta, f).unwrap_or_else(|x| x).into()
}
+#[proc_macro_attribute]
+pub fn main_avr(args: TokenStream, item: TokenStream) -> TokenStream {
+ let args = syn::parse_macro_input!(args as Args);
+ let f = syn::parse_macro_input!(item as syn::ItemFn);
+ main::run(&args.meta, f, main::avr()).unwrap_or_else(|x| x).into()
+}
+
/// Creates a new `executor` instance and declares an application entry point for Cortex-M spawning the corresponding function body as an async task.
///
/// The following restrictions apply:
diff --git a/embassy-executor-macros/src/macros/main.rs b/embassy-executor-macros/src/macros/main.rs
index 3c0d58567..088e64d1c 100644
--- a/embassy-executor-macros/src/macros/main.rs
+++ b/embassy-executor-macros/src/macros/main.rs
@@ -12,6 +12,20 @@ struct Args {
entry: Option<String>,
}
+pub fn avr() -> TokenStream {
+ quote! {
+ #[avr_device::entry]
+ fn main() -> ! {
+ let mut executor = ::embassy_executor::Executor::new();
+ let executor = unsafe { __make_static(&mut executor) };
+
+ executor.run(|spawner| {
+ spawner.must_spawn(__embassy_main(spawner));
+ })
+ }
+ }
+}
+
pub fn riscv(args: &[NestedMeta]) -> TokenStream {
let maybe_entry = match Args::from_list(args) {
Ok(args) => args.entry,
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index ec5aca46d..ade37913b 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -55,6 +55,7 @@ critical-section = { version = "1.1", features = ["std"] }
# Architecture
_arch = [] # some arch was picked
+arch-avr = ["_arch", "dep:portable-atomic"]
arch-std = ["_arch", "critical-section/std"]
arch-cortex-m = ["_arch", "dep:cortex-m"]
arch-riscv32 = ["_arch", "dep:portable-atomic"]
diff --git a/embassy-executor/src/arch/avr.rs b/embassy-executor/src/arch/avr.rs
new file mode 100644
index 000000000..2c715f297
--- /dev/null
+++ b/embassy-executor/src/arch/avr.rs
@@ -0,0 +1,60 @@
+#[cfg(feature = "executor-interrupt")]
+compile_error!("`executor-interrupt` is not supported with `arch-avr`.");
+
+#[cfg(feature = "executor-thread")]
+pub use thread::*;
+#[cfg(feature = "executor-thread")]
+mod thread {
+ use core::marker::PhantomData;
+
+ pub use embassy_executor_macros::main_avr as main;
+
+ use crate::{raw, Spawner};
+
+ #[export_name = "__pender"]
+ fn __pender(_context: *mut ()) {}
+
+ /// avr Executor
+ pub struct Executor {
+ inner: raw::Executor,
+ not_send: PhantomData<*mut ()>,
+ }
+
+ impl Executor {
+ /// Create a new Executor.
+ pub fn new() -> Self {
+ Self {
+ inner: raw::Executor::new(core::ptr::null_mut()),
+ not_send: PhantomData,
+ }
+ }
+
+ /// Run the executor.
+ ///
+ /// The `init` closure is called with a [`Spawner`] that spawns tasks on
+ /// this executor. Use it to spawn the initial task(s). After `init` returns,
+ /// the executor starts running the tasks.
+ ///
+ /// To spawn more tasks later, you may keep copies of the [`Spawner`] (it is `Copy`),
+ /// for example by passing it as an argument to the initial tasks.
+ ///
+ /// This function requires `&'static mut self`. This means you have to store the
+ /// Executor instance in a place where it'll live forever and grants you mutable
+ /// access. There's a few ways to do this:
+ ///
+ /// - a [StaticCell](https://docs.rs/static_cell/latest/static_cell/) (safe)
+ /// - a `static mut` (unsafe)
+ /// - a local variable in a function you know never returns (like `fn main() -> !`), upgrading its lifetime with `transmute`. (unsafe)
+ ///
+ /// This function never returns.
+ pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
+ init(self.inner.spawner());
+
+ loop {
+ unsafe {
+ self.inner.poll();
+ }
+ }
+ }
+ }
+}
diff --git a/embassy-executor/src/lib.rs b/embassy-executor/src/lib.rs
index 4c6900a6d..834ebf16a 100644
--- a/embassy-executor/src/lib.rs
+++ b/embassy-executor/src/lib.rs
@@ -20,9 +20,10 @@ macro_rules! check_at_most_one {
check_at_most_one!(@amo [$($f)*] [$($f)*] []);
};
}
-check_at_most_one!("arch-cortex-m", "arch-riscv32", "arch-std", "arch-wasm",);
+check_at_most_one!("arch-avr", "arch-cortex-m", "arch-riscv32", "arch-std", "arch-wasm",);
#[cfg(feature = "_arch")]
+#[cfg_attr(feature = "arch-avr", path = "arch/avr.rs")]
#[cfg_attr(feature = "arch-cortex-m", path = "arch/cortex_m.rs")]
#[cfg_attr(feature = "arch-riscv32", path = "arch/riscv32.rs")]
#[cfg_attr(feature = "arch-std", path = "arch/std.rs")]
From 172ed52128e0da519c13b7a354aeb98c492be3c3 Mon Sep 17 00:00:00 2001
From: sodo <djdisodo@gmail.com>
Date: Tue, 12 Dec 2023 16:51:24 +0900
Subject: [PATCH 002/392] ci.sh: add avr
---
ci.sh | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/ci.sh b/ci.sh
index 8a5e206d2..a5ddda3a1 100755
--- a/ci.sh
+++ b/ci.sh
@@ -207,6 +207,10 @@ cargo batch \
--- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
$BUILD_EXTRA
+# walkaround: "-Z" option not working on cargo batch
+cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr
+cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr,integrated-timers
+
rm out/tests/stm32wb55rg/wpan_mac
rm out/tests/stm32wb55rg/wpan_ble
From 9ea7a245e9f74faa1ba1f35988d98fc914414609 Mon Sep 17 00:00:00 2001
From: Adin Ackerman <adinackerman@gmail.com>
Date: Sun, 24 Dec 2023 11:51:16 -0800
Subject: [PATCH 003/392] add some generation resources, add some feature
descriptions
---
docs/modules/ROOT/pages/new_project.adoc | 25 +++++++++++++------
.../modules/ROOT/pages/project_structure.adoc | 9 +++++--
2 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/docs/modules/ROOT/pages/new_project.adoc b/docs/modules/ROOT/pages/new_project.adoc
index ce139ed8d..320966bb6 100644
--- a/docs/modules/ROOT/pages/new_project.adoc
+++ b/docs/modules/ROOT/pages/new_project.adoc
@@ -1,6 +1,17 @@
= Starting a new Embassy project
-Once you’ve successfully xref:getting_started.adoc[run some example projects], the next step is to make a standalone Embassy project. The easiest way to do this is to adapt an example for a similar chip to the one you’re targeting.
+Once you’ve successfully xref:getting_started.adoc[run some example projects], the next step is to make a standalone Embassy project.
+
+There are some tools for generating Embassy projects: (WIP)
+
+==== CLI
+- link:https://github.com/adinack/cargo-embassy[cargo-embassy] (STM32 and NRF)
+
+==== cargo-generate
+- link:https://github.com/lulf/embassy-template[embassy-template] (STM32, NRF, and RP)
+- link:https://github.com/bentwire/embassy-rp2040-template[embassy-rp2040-template] (RP)
+
+But if you want to start from scratch:
As an example, let’s create a new embassy project from scratch for a STM32G474. The same instructions are applicable for any supported chip with some minor changes.
@@ -166,13 +177,13 @@ should result in a blinking LED (if there’s one attached to the pin in `src/ma
Erasing sectors ✔ [00:00:00] [#########################################################] 18.00 KiB/18.00 KiB @ 54.09 KiB/s (eta 0s )
Programming pages ✔ [00:00:00] [#########################################################] 17.00 KiB/17.00 KiB @ 35.91 KiB/s (eta 0s ) Finished in 0.817s
0.000000 TRACE BDCR configured: 00008200
-└─ embassy_stm32::rcc::bd::{impl#3}::init::{closure#4} @ /home/you/.cargo/git/checkouts/embassy-9312dcb0ed774b29/7703f47/embassy-stm32/src/fmt.rs:117
+└─ embassy_stm32::rcc::bd::{impl#3}::init::{closure#4} @ /home/you/.cargo/git/checkouts/embassy-9312dcb0ed774b29/7703f47/embassy-stm32/src/fmt.rs:117
0.000000 DEBUG rcc: Clocks { sys: Hertz(16000000), pclk1: Hertz(16000000), pclk1_tim: Hertz(16000000), pclk2: Hertz(16000000), pclk2_tim: Hertz(16000000), hclk1: Hertz(16000000), hclk2: Hertz(16000000), pll1_p: None, adc: None, adc34: None, rtc: Some(Hertz(32000)) }
-└─ embassy_stm32::rcc::set_freqs @ /home/you/.cargo/git/checkouts/embassy-9312dcb0ed774b29/7703f47/embassy-stm32/src/fmt.rs:130
+└─ embassy_stm32::rcc::set_freqs @ /home/you/.cargo/git/checkouts/embassy-9312dcb0ed774b29/7703f47/embassy-stm32/src/fmt.rs:130
0.000000 INFO Hello World!
-└─ embassy_stm32g474::____embassy_main_task::{async_fn#0} @ src/main.rs:14
+└─ embassy_stm32g474::____embassy_main_task::{async_fn#0} @ src/main.rs:14
0.000091 INFO high
-└─ embassy_stm32g474::____embassy_main_task::{async_fn#0} @ src/main.rs:19
+└─ embassy_stm32g474::____embassy_main_task::{async_fn#0} @ src/main.rs:19
0.300201 INFO low
-└─ embassy_stm32g474::____embassy_main_task::{async_fn#0} @ src/main.rs:23
-----
\ No newline at end of file
+└─ embassy_stm32g474::____embassy_main_task::{async_fn#0} @ src/main.rs:23
+----
diff --git a/docs/modules/ROOT/pages/project_structure.adoc b/docs/modules/ROOT/pages/project_structure.adoc
index 3e6008ec4..bdb41d328 100644
--- a/docs/modules/ROOT/pages/project_structure.adoc
+++ b/docs/modules/ROOT/pages/project_structure.adoc
@@ -38,13 +38,18 @@ DEFMT_LOG = "trace" # <- can change to info, warn, or error
=== build.rs
-This is the build script for your project. It links defmt (what is defmt?) and the `memory.x` file if needed. This file is pretty specific for each chipset, just copy and paste from the corresponding link:https://github.com/embassy-rs/embassy/tree/main/examples[example].
+This is the build script for your project. It links defmt (what is link:https://defmt.ferrous-systems.com[defmt]?) and the `memory.x` file if needed. This file is pretty specific for each chipset, just copy and paste from the corresponding link:https://github.com/embassy-rs/embassy/tree/main/examples[example].
=== Cargo.toml
This is your manifest file, where you can configure all of the embassy components to use the features you need.
-TODO: someone should exhaustively describe every feature for every component!
+==== Features
+===== Time
+- tick-hz-x: Configures the tick rate of `embassy-time`. Higher tick rate means higher precision, and higher CPU wakes.
+- defmt-timestamp-uptime: defmt log entries will display the uptime in seconds.
+
+...more to come
=== memory.x
From b7cd7952c890f585ff876c622482534e5d58d4a4 Mon Sep 17 00:00:00 2001
From: sodo <djdisodo@gmail.com>
Date: Mon, 1 Jan 2024 21:18:30 +0900
Subject: [PATCH 004/392] avr: support sleep
---
ci.sh | 4 ++--
embassy-executor/Cargo.toml | 8 ++++++--
embassy-executor/src/arch/avr.rs | 13 +++++++++++--
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/ci.sh b/ci.sh
index a5ddda3a1..a804647e1 100755
--- a/ci.sh
+++ b/ci.sh
@@ -208,8 +208,8 @@ cargo batch \
$BUILD_EXTRA
# walkaround: "-Z" option not working on cargo batch
-cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr
-cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr,integrated-timers
+cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr,avr-device/atmega328p
+cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr,integrated-timers,avr-device/atmega328p
rm out/tests/stm32wb55rg/wpan_mac
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index ade37913b..c937194ce 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -36,10 +36,11 @@ embassy-executor-macros = { version = "0.4.0", path = "../embassy-executor-macro
embassy-time = { version = "0.2", path = "../embassy-time", optional = true}
critical-section = "1.1"
-# needed for riscv
+# needed for riscv and avr
# remove when https://github.com/rust-lang/rust/pull/114499 is merged
portable-atomic = { version = "1.5", optional = true }
+
# arch-cortex-m dependencies
cortex-m = { version = "0.7.6", optional = true }
@@ -47,6 +48,9 @@ cortex-m = { version = "0.7.6", optional = true }
wasm-bindgen = { version = "0.2.82", optional = true }
js-sys = { version = "0.3", optional = true }
+# arch-avr dependencies
+avr-device = { version = "0.5.3", optional = true }
+
[dev-dependencies]
critical-section = { version = "1.1", features = ["std"] }
@@ -55,7 +59,7 @@ critical-section = { version = "1.1", features = ["std"] }
# Architecture
_arch = [] # some arch was picked
-arch-avr = ["_arch", "dep:portable-atomic"]
+arch-avr = ["_arch", "dep:portable-atomic", "dep:avr-device"]
arch-std = ["_arch", "critical-section/std"]
arch-cortex-m = ["_arch", "dep:cortex-m"]
arch-riscv32 = ["_arch", "dep:portable-atomic"]
diff --git a/embassy-executor/src/arch/avr.rs b/embassy-executor/src/arch/avr.rs
index 2c715f297..fa6afe762 100644
--- a/embassy-executor/src/arch/avr.rs
+++ b/embassy-executor/src/arch/avr.rs
@@ -8,11 +8,16 @@ mod thread {
use core::marker::PhantomData;
pub use embassy_executor_macros::main_avr as main;
+ use portable_atomic::{AtomicBool, Ordering};
use crate::{raw, Spawner};
+ static SIGNAL_WORK_THREAD_MODE: AtomicBool = AtomicBool::new(false);
+
#[export_name = "__pender"]
- fn __pender(_context: *mut ()) {}
+ fn __pender(_context: *mut ()) {
+ SIGNAL_WORK_THREAD_MODE.store(true, Ordering::SeqCst);
+ }
/// avr Executor
pub struct Executor {
@@ -52,7 +57,11 @@ mod thread {
loop {
unsafe {
- self.inner.poll();
+ if SIGNAL_WORK_THREAD_MODE.swap(false, Ordering::SeqCst) {
+ self.inner.poll();
+ } else {
+ avr_device::asm::sleep();
+ }
}
}
}
From b0071c5070f6b4c932e703f2539c2eef74f09338 Mon Sep 17 00:00:00 2001
From: sodo <djdisodo@gmail.com>
Date: Tue, 2 Jan 2024 14:48:27 +0900
Subject: [PATCH 005/392] avr: sleep fix
---
embassy-executor/src/arch/avr.rs | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/embassy-executor/src/arch/avr.rs b/embassy-executor/src/arch/avr.rs
index fa6afe762..11e81ed9a 100644
--- a/embassy-executor/src/arch/avr.rs
+++ b/embassy-executor/src/arch/avr.rs
@@ -57,10 +57,13 @@ mod thread {
loop {
unsafe {
+ avr_device::interrupt::disable();
if SIGNAL_WORK_THREAD_MODE.swap(false, Ordering::SeqCst) {
- self.inner.poll();
- } else {
+ avr_device::interrupt::enable();
avr_device::asm::sleep();
+ } else {
+ avr_device::interrupt::enable();
+ self.inner.poll();
}
}
}
From 162f356ece8533d326df4acf918b3c4462bf486c Mon Sep 17 00:00:00 2001
From: sodo <djdisodo@gmail.com>
Date: Tue, 2 Jan 2024 23:39:06 +0900
Subject: [PATCH 006/392] add avr to ci
---
ci-nightly.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/ci-nightly.sh b/ci-nightly.sh
index 1fc9692b5..46b19c5b7 100755
--- a/ci-nightly.sh
+++ b/ci-nightly.sh
@@ -28,3 +28,6 @@ cargo batch \
--- build --release --manifest-path embassy-executor/Cargo.toml --target riscv32imac-unknown-none-elf --features nightly,arch-riscv32,executor-thread,integrated-timers \
--- build --release --manifest-path examples/nrf52840-rtic/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/nrf52840-rtic \
+cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr,avr-device/atmega328p
+cargo build --release --manifest-path embassy-executor/Cargo.toml --target avr-unknown-gnu-atmega328 -Z build-std=core,alloc --features nightly,arch-avr,integrated-timers,avr-device/atmega328p
+
From 01dbe9278357296fe9fb99f5e6923e80067c4a98 Mon Sep 17 00:00:00 2001
From: sodo <djdisodo@gmail.com>
Date: Wed, 3 Jan 2024 12:35:07 +0900
Subject: [PATCH 007/392] fix
---
embassy-executor/src/arch/avr.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-executor/src/arch/avr.rs b/embassy-executor/src/arch/avr.rs
index 11e81ed9a..70085d04d 100644
--- a/embassy-executor/src/arch/avr.rs
+++ b/embassy-executor/src/arch/avr.rs
@@ -58,7 +58,7 @@ mod thread {
loop {
unsafe {
avr_device::interrupt::disable();
- if SIGNAL_WORK_THREAD_MODE.swap(false, Ordering::SeqCst) {
+ if !SIGNAL_WORK_THREAD_MODE.swap(false, Ordering::SeqCst) {
avr_device::interrupt::enable();
avr_device::asm::sleep();
} else {
From 994b77e6843d70db34c59c0723b7718d52f3fd52 Mon Sep 17 00:00:00 2001
From: Tyler Gilbert <tyler.w.gilbert@gmail.com>
Date: Wed, 3 Jan 2024 11:06:03 -0600
Subject: [PATCH 008/392] Add write_immediate() function to STM32 DMA
ringbuffer API to pre-fill the buffer before starting the DMA
---
embassy-stm32/src/dma/bdma.rs | 7 +++++++
embassy-stm32/src/dma/dma.rs | 7 +++++++
embassy-stm32/src/dma/ringbuffer.rs | 11 +++++++++++
3 files changed, 25 insertions(+)
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index a2b83716d..077cfdcd9 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -664,6 +664,13 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
}
+ /// Write elements directly to the raw buffer.
+ /// This can be used to fill the buffer before starting the DMA transfer.
+ #[allow(dead_code)]
+ pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
+ self.ringbuf.write_immediate(buf)
+ }
+
/// Write elements to the ring buffer
/// Return a tuple of the length written and the length remaining in the buffer
pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index 16d02f273..ef9bb3d78 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -934,6 +934,13 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
}
+ /// Write elements directly to the raw buffer.
+ /// This can be used to fill the buffer before starting the DMA transfer.
+ #[allow(dead_code)]
+ pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
+ self.ringbuf.write_immediate(buf)
+ }
+
/// Write elements from the ring buffer
/// Return a tuple of the length written and the length remaining in the buffer
pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs
index c9f7a3026..c5b42060a 100644
--- a/embassy-stm32/src/dma/ringbuffer.rs
+++ b/embassy-stm32/src/dma/ringbuffer.rs
@@ -263,6 +263,17 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
self.cap() - dma.get_remaining_transfers()
}
+ /// Write elements directly to the buffer. This must be done before the DMA is started
+ /// or after the buffer has been cleared using `clear()`.
+ pub fn write_immediate(&mut self, buffer: &[W]) -> Result<(usize, usize), OverrunError> {
+ if self.end != 0 {
+ return Err(OverrunError);
+ }
+ let written = self.copy_from(buffer, 0..self.cap());
+ self.end = written % self.cap();
+ Ok((written, self.cap() - written))
+ }
+
/// Write an exact number of elements to the ringbuffer.
pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, OverrunError> {
let mut written_data = 0;
From fe3973c513a71d20ec2bc2f7d3cefd414f405980 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Sat, 6 Jan 2024 11:59:55 +0800
Subject: [PATCH 009/392] mark json file inside .vscode folder as jsonc
---
.gitattributes | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/.gitattributes b/.gitattributes
index 4db9edae7..a51376f0d 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -15,6 +15,8 @@
*.x text
*.yml text
+.vscode/*.json linguist-language=JSON-with-Comments
+
*.raw binary
*.bin binary
*.png binary
@@ -38,4 +40,4 @@
*.pdf binary
*.ez binary
*.bz2 binary
-*.swp binary
\ No newline at end of file
+*.swp binary
From 424ddaf3d95417bcfe8b46475c8135aead3792d2 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Sat, 6 Jan 2024 22:22:38 +0800
Subject: [PATCH 010/392] impl waveform with TIM Channel
---
embassy-stm32/build.rs | 14 ++--
embassy-stm32/src/timer/mod.rs | 25 +++++++
embassy-stm32/src/timer/simple_pwm.rs | 90 +++++++++++++++++++++++++-
examples/stm32f4/src/bin/ws2812_pwm.rs | 2 +-
4 files changed, 119 insertions(+), 12 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index ef152acd1..7860ee2ff 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -1009,6 +1009,10 @@ fn main() {
(("dac", "CH1"), quote!(crate::dac::DacDma1)),
(("dac", "CH2"), quote!(crate::dac::DacDma2)),
(("timer", "UP"), quote!(crate::timer::UpDma)),
+ (("timer", "CH1"), quote!(crate::timer::Ch1Dma)),
+ (("timer", "CH2"), quote!(crate::timer::Ch2Dma)),
+ (("timer", "CH3"), quote!(crate::timer::Ch3Dma)),
+ (("timer", "CH4"), quote!(crate::timer::Ch4Dma)),
]
.into();
@@ -1024,16 +1028,6 @@ fn main() {
}
if let Some(tr) = signals.get(&(regs.kind, ch.signal)) {
- // TIM6 of stm32f334 is special, DMA channel for TIM6 depending on SYSCFG state
- if chip_name.starts_with("stm32f334") && p.name == "TIM6" {
- continue;
- }
-
- // TIM6 of stm32f378 is special, DMA channel for TIM6 depending on SYSCFG state
- if chip_name.starts_with("stm32f378") && p.name == "TIM6" {
- continue;
- }
-
let peri = format_ident!("{}", p.name);
let channel = if let Some(channel) = &ch.channel {
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index d07fd2776..957098cde 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -311,6 +311,26 @@ pub(crate) mod sealed {
.ccmr_output(channel_index / 2)
.modify(|w| w.set_ocpe(channel_index % 2, preload));
}
+
+ /// Get capture compare DMA selection
+ fn get_cc_dma_selection(&self) -> super::vals::Ccds {
+ Self::regs_gp16().cr2().read().ccds()
+ }
+
+ /// Set capture compare DMA selection
+ fn set_cc_dma_selection(&mut self, ccds: super::vals::Ccds) {
+ Self::regs_gp16().cr2().modify(|w| w.set_ccds(ccds))
+ }
+
+ /// Get capture compare DMA enable state
+ fn get_cc_dma_enable_state(&self, channel: Channel) -> bool {
+ Self::regs_gp16().dier().read().ccde(channel.index())
+ }
+
+ /// Set capture compare DMA enable state
+ fn set_cc_dma_enable_state(&mut self, channel: Channel, ccde: bool) {
+ Self::regs_gp16().dier().modify(|w| w.set_ccde(channel.index(), ccde))
+ }
}
/// Capture/Compare 16-bit timer instance with complementary pin support.
@@ -705,3 +725,8 @@ foreach_interrupt! {
// Update Event trigger DMA for every timer
dma_trait!(UpDma, Basic16bitInstance);
+
+dma_trait!(Ch1Dma, CaptureCompare16bitInstance);
+dma_trait!(Ch2Dma, CaptureCompare16bitInstance);
+dma_trait!(Ch3Dma, CaptureCompare16bitInstance);
+dma_trait!(Ch4Dma, CaptureCompare16bitInstance);
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 80f10424c..665557354 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -155,7 +155,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
///
/// Note:
/// you will need to provide corresponding TIMx_UP DMA channel to use this method.
- pub async fn gen_waveform(
+ pub async fn waveform_up(
&mut self,
dma: impl Peripheral<P = impl super::UpDma<T>>,
channel: Channel,
@@ -221,6 +221,94 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
}
}
+macro_rules! impl_waveform_chx {
+ ($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
+ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
+ /// Generate a sequence of PWM waveform
+ ///
+ /// Note:
+ /// you will need to provide corresponding TIMx_CHy DMA channel to use this method.
+ pub async fn $fn_name(&mut self, dma: impl Peripheral<P = impl super::$dma_ch<T>>, duty: &[u16]) {
+ use super::vals::Ccds;
+
+ assert!(duty.iter().all(|v| *v <= self.get_max_duty()));
+
+ into_ref!(dma);
+
+ #[allow(clippy::let_unit_value)] // eg. stm32f334
+ let req = dma.request();
+
+ let cc_channel = super::Channel::$cc_ch;
+
+ let original_duty_state = self.get_duty(cc_channel);
+ let original_enable_state = self.is_enabled(cc_channel);
+ let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ONUPDATE;
+ let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
+
+ if original_cc_dma_on_update {
+ self.inner.set_cc_dma_selection(Ccds::ONUPDATE)
+ }
+
+ if !original_cc_dma_enabled {
+ self.inner.set_cc_dma_enable_state(cc_channel, true);
+ }
+
+ if !original_enable_state {
+ self.enable(cc_channel);
+ }
+
+ unsafe {
+ #[cfg(not(any(bdma, gpdma)))]
+ use crate::dma::{Burst, FifoThreshold};
+ use crate::dma::{Transfer, TransferOptions};
+
+ let dma_transfer_option = TransferOptions {
+ #[cfg(not(any(bdma, gpdma)))]
+ fifo_threshold: Some(FifoThreshold::Full),
+ #[cfg(not(any(bdma, gpdma)))]
+ mburst: Burst::Incr8,
+ ..Default::default()
+ };
+
+ Transfer::new_write(
+ &mut dma,
+ req,
+ duty,
+ T::regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut _,
+ dma_transfer_option,
+ )
+ .await
+ };
+
+ // restore output compare state
+ if !original_enable_state {
+ self.disable(cc_channel);
+ }
+
+ self.set_duty(cc_channel, original_duty_state);
+
+ // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
+ // this can almost always trigger a DMA FIFO error.
+ //
+ // optional TODO:
+ // clean FEIF after disable UDE
+ if !original_cc_dma_enabled {
+ self.inner.set_cc_dma_enable_state(cc_channel, false);
+ }
+
+ if !original_cc_dma_on_update {
+ self.inner.set_cc_dma_selection(Ccds::ONCOMPARE)
+ }
+ }
+ }
+ };
+}
+
+impl_waveform_chx!(waveform_ch1, Ch1Dma, Ch1);
+impl_waveform_chx!(waveform_ch2, Ch2Dma, Ch2);
+impl_waveform_chx!(waveform_ch3, Ch3Dma, Ch3);
+impl_waveform_chx!(waveform_ch4, Ch4Dma, Ch4);
+
impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
type Channel = Channel;
type Time = Hertz;
diff --git a/examples/stm32f4/src/bin/ws2812_pwm.rs b/examples/stm32f4/src/bin/ws2812_pwm.rs
index 239709253..6122cea2d 100644
--- a/examples/stm32f4/src/bin/ws2812_pwm.rs
+++ b/examples/stm32f4/src/bin/ws2812_pwm.rs
@@ -91,7 +91,7 @@ async fn main(_spawner: Spawner) {
loop {
for &color in color_list {
// with &mut, we can easily reuse same DMA channel multiple times
- ws2812_pwm.gen_waveform(&mut dp.DMA1_CH2, pwm_channel, color).await;
+ ws2812_pwm.waveform_up(&mut dp.DMA1_CH2, pwm_channel, color).await;
// ws2812 need at least 50 us low level input to confirm the input data and change it's state
Timer::after_micros(50).await;
// wait until ticker tick
From 890a1269d05297993ffa7b537739926eb30d5436 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Sat, 6 Jan 2024 22:48:21 +0800
Subject: [PATCH 011/392] refactor with clippy
---
embassy-stm32/build.rs | 7 ++++---
embassy-stm32/src/timer/complementary_pwm.rs | 3 ++-
embassy-stm32/src/timer/mod.rs | 15 ++++++---------
embassy-stm32/src/timer/simple_pwm.rs | 2 +-
4 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 7860ee2ff..fc876afcc 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -936,9 +936,9 @@ fn main() {
} else if pin.signal.starts_with("INN") {
// TODO handle in the future when embassy supports differential measurements
None
- } else if pin.signal.starts_with("IN") && pin.signal.ends_with("b") {
+ } else if pin.signal.starts_with("IN") && pin.signal.ends_with('b') {
// we number STM32L1 ADC bank 1 as 0..=31, bank 2 as 32..=63
- let signal = pin.signal.strip_prefix("IN").unwrap().strip_suffix("b").unwrap();
+ let signal = pin.signal.strip_prefix("IN").unwrap().strip_suffix('b').unwrap();
Some(32u8 + signal.parse::<u8>().unwrap())
} else if pin.signal.starts_with("IN") {
Some(pin.signal.strip_prefix("IN").unwrap().parse().unwrap())
@@ -1186,7 +1186,7 @@ fn main() {
ADC3 and higher are assigned to the adc34 clock in the table
The adc3_common cfg directive is added if ADC3_COMMON exists
*/
- let has_adc3 = METADATA.peripherals.iter().find(|p| p.name == "ADC3_COMMON").is_some();
+ let has_adc3 = METADATA.peripherals.iter().any(|p| p.name == "ADC3_COMMON");
let set_adc345 = HashSet::from(["ADC3", "ADC4", "ADC5"]);
for m in METADATA
@@ -1370,6 +1370,7 @@ fn main() {
// =======
// ADC3_COMMON is present
+ #[allow(clippy::print_literal)]
if has_adc3 {
println!("cargo:rustc-cfg={}", "adc3_common");
}
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 71d7110b5..eddce0404 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -54,6 +54,7 @@ pub struct ComplementaryPwm<'d, T> {
impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
/// Create a new complementary PWM driver.
+ #[allow(clippy::too_many_arguments)]
pub fn new(
tim: impl Peripheral<P = T> + 'd,
_ch1: Option<PwmPin<'d, T, Ch1>>,
@@ -165,7 +166,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> embedded_hal_02::Pwm for C
}
fn get_period(&self) -> Self::Time {
- self.inner.get_frequency().into()
+ self.inner.get_frequency()
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 957098cde..210bf7153 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -470,20 +470,17 @@ pub enum CountingMode {
impl CountingMode {
/// Return whether this mode is edge-aligned (up or down).
pub fn is_edge_aligned(&self) -> bool {
- match self {
- CountingMode::EdgeAlignedUp | CountingMode::EdgeAlignedDown => true,
- _ => false,
- }
+ matches!(self, CountingMode::EdgeAlignedUp | CountingMode::EdgeAlignedDown)
}
/// Return whether this mode is center-aligned.
pub fn is_center_aligned(&self) -> bool {
- match self {
+ matches!(
+ self,
CountingMode::CenterAlignedDownInterrupts
- | CountingMode::CenterAlignedUpInterrupts
- | CountingMode::CenterAlignedBothInterrupts => true,
- _ => false,
- }
+ | CountingMode::CenterAlignedUpInterrupts
+ | CountingMode::CenterAlignedBothInterrupts
+ )
}
}
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 665557354..709278c0c 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -323,7 +323,7 @@ impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d,
}
fn get_period(&self) -> Self::Time {
- self.inner.get_frequency().into()
+ self.inner.get_frequency()
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
From 1f57692d042de781f884d50f0cbd9eea0c71626d Mon Sep 17 00:00:00 2001
From: "Jomer.Dev" <Jomer.Dev@posteo.de>
Date: Mon, 8 Jan 2024 00:20:40 +0100
Subject: [PATCH 012/392] Add function to create logger from class
---
embassy-usb-logger/src/lib.rs | 54 +++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/embassy-usb-logger/src/lib.rs b/embassy-usb-logger/src/lib.rs
index 45d780bf8..422cefb59 100644
--- a/embassy-usb-logger/src/lib.rs
+++ b/embassy-usb-logger/src/lib.rs
@@ -105,6 +105,34 @@ impl<const N: usize> UsbLogger<N> {
join(run_fut, join(log_fut, discard_fut)).await;
}
}
+
+ // Creates the futures needed for the logger from a given class
+ pub async fn create_future_from_class<'d, D>(&'d self, class: CdcAcmClass<'d, D> )
+ where
+ D: Driver<'d>,
+ {
+ const MAX_PACKET_SIZE: u8 = 64;
+ let (mut sender, mut receiver) = class.split();
+
+ loop {
+ let log_fut = async {
+ let mut rx: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
+ sender.wait_connection().await;
+ loop {
+ let len = self.buffer.read(&mut rx[..]).await;
+ let _ = sender.write_packet(&rx[..len]).await;
+ }
+ };
+ let discard_fut = async {
+ let mut discard_buf: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
+ receiver.wait_connection().await;
+ loop {
+ let _ = receiver.read_packet(&mut discard_buf).await;
+ }
+ };
+ join(log_fut, discard_fut).await;
+ }
+ }
}
impl<const N: usize> log::Log for UsbLogger<N> {
@@ -153,3 +181,29 @@ macro_rules! run {
let _ = LOGGER.run(&mut ::embassy_usb_logger::LoggerState::new(), $p).await;
};
}
+
+/// Initialize the USB serial logger from a serial class and return the future to run it.
+///
+/// Arguments specify the buffer size, log level and the serial class, respectively.
+///
+/// # Usage
+///
+/// ```
+/// embassy_usb_logger::with_class!(1024, log::LevelFilter::Info, class);
+/// ```
+///
+/// # Safety
+///
+/// This macro should only be invoked only once since it is setting the global logging state of the application.
+#[macro_export]
+macro_rules! with_class {
+ ( $x:expr, $l:expr, $p:ident ) => {
+ {
+ static LOGGER: ::embassy_usb_logger::UsbLogger<$x> = ::embassy_usb_logger::UsbLogger::new();
+ unsafe {
+ let _ = ::log::set_logger_racy(&LOGGER).map(|()| log::set_max_level_racy($l));
+ }
+ LOGGER.create_future_from_class($p)
+ }
+ };
+}
From 6f505feeb1640c3d76c47aa21160a5a802fb6b93 Mon Sep 17 00:00:00 2001
From: "Jomer.Dev" <Jomer.Dev@posteo.de>
Date: Mon, 8 Jan 2024 00:21:02 +0100
Subject: [PATCH 013/392] Add example
---
examples/rp/src/bin/usb_serial_with_logger.rs | 117 ++++++++++++++++++
1 file changed, 117 insertions(+)
create mode 100644 examples/rp/src/bin/usb_serial_with_logger.rs
diff --git a/examples/rp/src/bin/usb_serial_with_logger.rs b/examples/rp/src/bin/usb_serial_with_logger.rs
new file mode 100644
index 000000000..4ba4fc25c
--- /dev/null
+++ b/examples/rp/src/bin/usb_serial_with_logger.rs
@@ -0,0 +1,117 @@
+//! This example shows how to use USB (Universal Serial Bus) in the RP2040 chip as well as how to create multiple usb classes for one device
+//!
+//! This creates a USB serial port that echos. It will also print out logging information on a separate serial device
+
+#![no_std]
+#![no_main]
+
+use defmt::{info, panic};
+use embassy_executor::Spawner;
+use embassy_futures::join::join;
+use embassy_rp::bind_interrupts;
+use embassy_rp::peripherals::USB;
+use embassy_rp::usb::{Driver, Instance, InterruptHandler};
+use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
+use embassy_usb::driver::EndpointError;
+use embassy_usb::{Builder, Config};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ USBCTRL_IRQ => InterruptHandler<USB>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ info!("Hello there!");
+
+ let p = embassy_rp::init(Default::default());
+
+ // Create the driver, from the HAL.
+ let driver = Driver::new(p.USB, Irqs);
+
+ // Create embassy-usb Config
+ let mut config = Config::new(0xc0de, 0xcafe);
+ config.manufacturer = Some("Embassy");
+ config.product = Some("USB-serial example");
+ config.serial_number = Some("12345678");
+ config.max_power = 100;
+ config.max_packet_size_0 = 64;
+
+ // Required for windows compatibility.
+ // https://developer.nordicsemi.com/nRF_Connect_SDK/doc/1.9.1/kconfig/CONFIG_CDC_ACM_IAD.html#help
+ config.device_class = 0xEF;
+ config.device_sub_class = 0x02;
+ config.device_protocol = 0x01;
+ config.composite_with_iads = true;
+
+ // Create embassy-usb DeviceBuilder using the driver and config.
+ // It needs some buffers for building the descriptors.
+ let mut device_descriptor = [0; 256];
+ let mut config_descriptor = [0; 256];
+ let mut bos_descriptor = [0; 256];
+ let mut control_buf = [0; 64];
+
+ let mut state = State::new();
+ let mut logger_state = State::new();
+
+ let mut builder = Builder::new(
+ driver,
+ config,
+ &mut device_descriptor,
+ &mut config_descriptor,
+ &mut bos_descriptor,
+ &mut [], // no msos descriptors
+ &mut control_buf,
+ );
+
+ // Create classes on the builder.
+ let mut class = CdcAcmClass::new(&mut builder, &mut state, 64);
+
+ // Create a class for the logger
+ let logger_class = CdcAcmClass::new(&mut builder, &mut logger_state, 64);
+
+ // Creates the logger and returns the logger future
+ // Note: You'll need to use log::info! afterwards instead of info! for this to work (this also applies to all the other log::* macros)
+ let log_fut = embassy_usb_logger::with_class!(1024, log::LevelFilter::Info, logger_class);
+
+ // Build the builder.
+ let mut usb = builder.build();
+
+ // Run the USB device.
+ let usb_fut = usb.run();
+
+ // Do stuff with the class!
+ let echo_fut = async {
+ loop {
+ class.wait_connection().await;
+ log::info!("Connected");
+ let _ = echo(&mut class).await;
+ log::info!("Disconnected");
+ }
+ };
+
+ // Run everything concurrently.
+ // If we had made everything `'static` above instead, we could do this using separate tasks instead.
+ join(usb_fut, join(echo_fut, log_fut)).await;
+}
+
+struct Disconnected {}
+
+impl From<EndpointError> for Disconnected {
+ fn from(val: EndpointError) -> Self {
+ match val {
+ EndpointError::BufferOverflow => panic!("Buffer overflow"),
+ EndpointError::Disabled => Disconnected {},
+ }
+ }
+}
+
+async fn echo<'d, T: Instance + 'd>(class: &mut CdcAcmClass<'d, Driver<'d, T>>) -> Result<(), Disconnected> {
+ let mut buf = [0; 64];
+ loop {
+ let n = class.read_packet(&mut buf).await?;
+ let data = &buf[..n];
+ info!("data: {:x}", data);
+ class.write_packet(data).await?;
+ }
+}
From f0c750422970db71304101fca821a0c254571604 Mon Sep 17 00:00:00 2001
From: "Jomer.Dev" <Jomer.Dev@posteo.de>
Date: Mon, 8 Jan 2024 00:21:22 +0100
Subject: [PATCH 014/392] Fix log messages not always showing up straight away
---
embassy-usb-logger/src/lib.rs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/embassy-usb-logger/src/lib.rs b/embassy-usb-logger/src/lib.rs
index 422cefb59..5142d9073 100644
--- a/embassy-usb-logger/src/lib.rs
+++ b/embassy-usb-logger/src/lib.rs
@@ -93,6 +93,9 @@ impl<const N: usize> UsbLogger<N> {
loop {
let len = self.buffer.read(&mut rx[..]).await;
let _ = sender.write_packet(&rx[..len]).await;
+ if len as u8 == MAX_PACKET_SIZE {
+ let _ = sender.write_packet(&[]).await;
+ }
}
};
let discard_fut = async {
@@ -121,6 +124,9 @@ impl<const N: usize> UsbLogger<N> {
loop {
let len = self.buffer.read(&mut rx[..]).await;
let _ = sender.write_packet(&rx[..len]).await;
+ if len as u8 == MAX_PACKET_SIZE {
+ let _ = sender.write_packet(&[]).await;
+ }
}
};
let discard_fut = async {
From 03bf72f690f341b9ca7dbcd329df7571fe47d014 Mon Sep 17 00:00:00 2001
From: "Jomer.Dev" <Jomer.Dev@posteo.de>
Date: Mon, 8 Jan 2024 00:24:15 +0100
Subject: [PATCH 015/392] Better explanation
---
embassy-usb-logger/src/lib.rs | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/embassy-usb-logger/src/lib.rs b/embassy-usb-logger/src/lib.rs
index 5142d9073..f197c6874 100644
--- a/embassy-usb-logger/src/lib.rs
+++ b/embassy-usb-logger/src/lib.rs
@@ -109,7 +109,8 @@ impl<const N: usize> UsbLogger<N> {
}
}
- // Creates the futures needed for the logger from a given class
+ /// Creates the futures needed for the logger from a given class
+ /// This can be used in cases where the usb device is already in use for another connection
pub async fn create_future_from_class<'d, D>(&'d self, class: CdcAcmClass<'d, D> )
where
D: Driver<'d>,
From 2c6b475f4e663402fd87977d77dcfc4ccb70babb Mon Sep 17 00:00:00 2001
From: "Jomer.Dev" <Jomer.Dev@posteo.de>
Date: Mon, 8 Jan 2024 00:39:32 +0100
Subject: [PATCH 016/392] Fix formatting
---
embassy-usb-logger/src/lib.rs | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/embassy-usb-logger/src/lib.rs b/embassy-usb-logger/src/lib.rs
index f197c6874..a057fcf32 100644
--- a/embassy-usb-logger/src/lib.rs
+++ b/embassy-usb-logger/src/lib.rs
@@ -111,7 +111,7 @@ impl<const N: usize> UsbLogger<N> {
/// Creates the futures needed for the logger from a given class
/// This can be used in cases where the usb device is already in use for another connection
- pub async fn create_future_from_class<'d, D>(&'d self, class: CdcAcmClass<'d, D> )
+ pub async fn create_future_from_class<'d, D>(&'d self, class: CdcAcmClass<'d, D>)
where
D: Driver<'d>,
{
@@ -121,7 +121,7 @@ impl<const N: usize> UsbLogger<N> {
loop {
let log_fut = async {
let mut rx: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
- sender.wait_connection().await;
+ sender.wait_connection().await;
loop {
let len = self.buffer.read(&mut rx[..]).await;
let _ = sender.write_packet(&rx[..len]).await;
@@ -204,13 +204,11 @@ macro_rules! run {
/// This macro should only be invoked only once since it is setting the global logging state of the application.
#[macro_export]
macro_rules! with_class {
- ( $x:expr, $l:expr, $p:ident ) => {
- {
- static LOGGER: ::embassy_usb_logger::UsbLogger<$x> = ::embassy_usb_logger::UsbLogger::new();
- unsafe {
- let _ = ::log::set_logger_racy(&LOGGER).map(|()| log::set_max_level_racy($l));
- }
- LOGGER.create_future_from_class($p)
+ ( $x:expr, $l:expr, $p:ident ) => {{
+ static LOGGER: ::embassy_usb_logger::UsbLogger<$x> = ::embassy_usb_logger::UsbLogger::new();
+ unsafe {
+ let _ = ::log::set_logger_racy(&LOGGER).map(|()| log::set_max_level_racy($l));
}
- };
+ LOGGER.create_future_from_class($p)
+ }};
}
From b16cc04036da8bcbfe273cd796c092e8e2a074c9 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Mon, 8 Jan 2024 19:18:24 +0800
Subject: [PATCH 017/392] bug fix
---
embassy-stm32/src/timer/simple_pwm.rs | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 709278c0c..ba089ac8b 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -245,7 +245,8 @@ macro_rules! impl_waveform_chx {
let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ONUPDATE;
let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
- if original_cc_dma_on_update {
+ // redirect CC DMA request onto Update Event
+ if !original_cc_dma_on_update {
self.inner.set_cc_dma_selection(Ccds::ONUPDATE)
}
From 45b76455257c9b8f213b23f1164e71d8ad94446a Mon Sep 17 00:00:00 2001
From: Henk Oordt <hd@oordt.dev>
Date: Mon, 8 Jan 2024 13:56:21 +0100
Subject: [PATCH 018/392] Make adc::Resolution::to_max_count const
---
embassy-stm32/src/adc/resolution.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/adc/resolution.rs b/embassy-stm32/src/adc/resolution.rs
index 64c25a776..9513e1df7 100644
--- a/embassy-stm32/src/adc/resolution.rs
+++ b/embassy-stm32/src/adc/resolution.rs
@@ -56,7 +56,7 @@ impl Resolution {
/// Get the maximum reading value for this resolution.
///
/// This is `2**n - 1`.
- pub fn to_max_count(&self) -> u32 {
+ pub const fn to_max_count(&self) -> u32 {
match self {
#[cfg(adc_v4)]
Resolution::SixteenBit => (1 << 16) - 1,
From db776c9623428b539cf49bcca13361e11bc1129b Mon Sep 17 00:00:00 2001
From: Ralf <jr-oss@gmx.net>
Date: Fri, 20 Oct 2023 19:31:55 +0200
Subject: [PATCH 019/392] stm32/simple_pwm: add set_output_compare_mode
---
embassy-stm32/src/timer/simple_pwm.rs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 80f10424c..83a3e9291 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -151,6 +151,11 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
self.inner.set_output_polarity(channel, polarity);
}
+ /// Set the output compare mode for a given channel.
+ pub fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
+ self.inner.set_output_compare_mode(channel, mode);
+ }
+
/// Generate a sequence of PWM waveform
///
/// Note:
From 9fd49fb9d675f858691491a57ab50dd049168def Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Tue, 19 Dec 2023 00:11:35 +0100
Subject: [PATCH 020/392] Add a basic "read to break" function
---
embassy-rp/src/uart/mod.rs | 88 ++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 99fce0fc9..3488d6c73 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -443,6 +443,90 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
}
unreachable!("unrecognized rx error");
}
+
+ pub async fn read_to_break<'a>(&mut self, buffer: &'a mut [u8]) -> Result<&'a mut [u8], Error> {
+ // clear error flags before we drain the fifo. errors that have accumulated
+ // in the flags will also be present in the fifo.
+ T::dma_state().rx_errs.store(0, Ordering::Relaxed);
+ T::regs().uarticr().write(|w| {
+ w.set_oeic(true);
+ w.set_beic(true);
+ w.set_peic(true);
+ w.set_feic(true);
+ });
+
+ // then drain the fifo. we need to read at most 32 bytes. errors that apply
+ // to fifo bytes will be reported directly.
+ let sbuffer = match {
+ let limit = buffer.len().min(32);
+ self.drain_fifo(&mut buffer[0..limit])
+ } {
+ Ok(len) if len < buffer.len() => &mut buffer[len..],
+ Ok(_) => return Ok(buffer),
+ Err(e) => return Err(e),
+ };
+
+ // start a dma transfer. if errors have happened in the interim some error
+ // interrupt flags will have been raised, and those will be picked up immediately
+ // by the interrupt handler.
+ let mut ch = self.rx_dma.as_mut().unwrap();
+ T::regs().uartimsc().write_set(|w| {
+ w.set_oeim(true);
+ w.set_beim(true);
+ w.set_peim(true);
+ w.set_feim(true);
+ });
+ T::regs().uartdmacr().write_set(|reg| {
+ reg.set_rxdmae(true);
+ reg.set_dmaonerr(true);
+ });
+ let transfer = unsafe {
+ // If we don't assign future to a variable, the data register pointer
+ // is held across an await and makes the future non-Send.
+ crate::dma::read(&mut ch, T::regs().uartdr().as_ptr() as *const _, sbuffer, T::RX_DREQ)
+ };
+
+ // wait for either the transfer to complete or an error to happen.
+ let transfer_result = select(
+ transfer,
+ poll_fn(|cx| {
+ T::dma_state().rx_err_waker.register(cx.waker());
+ match T::dma_state().rx_errs.swap(0, Ordering::Relaxed) {
+ 0 => Poll::Pending,
+ e => Poll::Ready(Uartris(e as u32)),
+ }
+ }),
+ )
+ .await;
+
+ let errors = match transfer_result {
+ Either::First(()) => return Ok(buffer),
+ Either::Second(e) => e,
+ };
+
+ if errors.0 == 0 {
+ return Ok(buffer);
+ } else if errors.oeris() {
+ return Err(Error::Overrun);
+ } else if errors.beris() {
+ // Begin "James is a chicken" region - I'm not certain if there is ever
+ // a case where the write addr WOULDN'T exist between the start and end.
+ // This assert checks that and hasn't fired (yet).
+ let sval = buffer.as_ptr() as usize;
+ let eval = sval + buffer.len();
+ // Note: the `write_addr()` is where the NEXT write would be, BUT we also
+ // received one extra byte that represents the line break.
+ let val = ch.regs().write_addr().read() as usize - 1;
+ assert!((val >= sval) && (val <= eval));
+ let taken = val - sval;
+ return Ok(&mut buffer[..taken]);
+ } else if errors.peris() {
+ return Err(Error::Parity);
+ } else if errors.feris() {
+ return Err(Error::Framing);
+ }
+ unreachable!("unrecognized rx error");
+ }
}
impl<'d, T: Instance> Uart<'d, T, Blocking> {
@@ -743,6 +827,10 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
self.rx.read(buffer).await
}
+
+ pub async fn read_to_break<'a>(&mut self, buf: &'a mut [u8]) -> Result<&'a mut [u8], Error> {
+ self.rx.read_to_break(buf).await
+ }
}
impl<'d, T: Instance, M: Mode> embedded_hal_02::serial::Read<u8> for UartRx<'d, T, M> {
From 24fc12667dc3b929d4fef633cdf0c1ada9765484 Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Wed, 20 Dec 2023 14:14:14 +0100
Subject: [PATCH 021/392] Update with more docs and less panics
---
embassy-rp/src/uart/mod.rs | 118 +++++++++++++++++++++++++++++--------
1 file changed, 95 insertions(+), 23 deletions(-)
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 3488d6c73..a89cb5932 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -116,6 +116,10 @@ pub enum Error {
Parity,
/// Triggered when the received character didn't have a valid stop bit.
Framing,
+ /// There was an issue when calculating the number of transferred items
+ /// in an aborted DMA transaction. This is likely an error in the
+ /// driver implementation, please open an embassy issue.
+ Calculation,
}
/// Internal DMA state of UART RX.
@@ -275,13 +279,13 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
/// Read from UART RX blocking execution until done.
pub fn blocking_read(&mut self, mut buffer: &mut [u8]) -> Result<(), Error> {
while buffer.len() > 0 {
- let received = self.drain_fifo(buffer)?;
+ let received = self.drain_fifo(buffer).map_err(|(_i, e)| e)?;
buffer = &mut buffer[received..];
}
Ok(())
}
- fn drain_fifo(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+ fn drain_fifo(&mut self, buffer: &mut [u8]) -> Result<usize, (usize, Error)> {
let r = T::regs();
for (i, b) in buffer.iter_mut().enumerate() {
if r.uartfr().read().rxfe() {
@@ -291,13 +295,13 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
let dr = r.uartdr().read();
if dr.oe() {
- return Err(Error::Overrun);
+ return Err((i, Error::Overrun));
} else if dr.be() {
- return Err(Error::Break);
+ return Err((i, Error::Break));
} else if dr.pe() {
- return Err(Error::Parity);
+ return Err((i, Error::Parity));
} else if dr.fe() {
- return Err(Error::Framing);
+ return Err((i, Error::Framing));
} else {
*b = dr.data();
}
@@ -389,7 +393,7 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
} {
Ok(len) if len < buffer.len() => &mut buffer[len..],
Ok(_) => return Ok(()),
- Err(e) => return Err(e),
+ Err((_i, e)) => return Err(e),
};
// start a dma transfer. if errors have happened in the interim some error
@@ -425,14 +429,33 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
)
.await;
+ let mut did_finish = false;
let errors = match transfer_result {
- Either::First(()) => return Ok(()),
- Either::Second(e) => e,
+ Either::First(()) => {
+ // We're here because the DMA finished, BUT if an error occurred on the LAST
+ // byte, then we may still need to grab the error state!
+ did_finish = true;
+ Uartris(T::dma_state().rx_errs.swap(0, Ordering::Relaxed) as u32)
+ }
+ Either::Second(e) => {
+ // We're here because we errored, which means this is the error that
+ // was problematic.
+ e
+ }
};
+ // If we got no error, just return at this point
if errors.0 == 0 {
return Ok(());
- } else if errors.oeris() {
+ }
+
+ // If we DID get an error, and DID finish, we'll have one error byte left in the FIFO.
+ // Pop it since we are reporting the error on THIS transaction.
+ if did_finish {
+ let _ = T::regs().uartdr().read();
+ }
+
+ if errors.oeris() {
return Err(Error::Overrun);
} else if errors.beris() {
return Err(Error::Break);
@@ -444,6 +467,14 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
unreachable!("unrecognized rx error");
}
+ /// Read from the UART, until one of the following occurs:
+ ///
+ /// * We read `buffer.len()` bytes without a line break
+ /// * returns `Ok(buffer)`
+ /// * We read `n` bytes then a line break occurs
+ /// * returns `Ok(&mut buffer[..n])`
+ /// * We encounter some error OTHER than a line break
+ /// * returns `Err(Error)`
pub async fn read_to_break<'a>(&mut self, buffer: &'a mut [u8]) -> Result<&'a mut [u8], Error> {
// clear error flags before we drain the fifo. errors that have accumulated
// in the flags will also be present in the fifo.
@@ -461,9 +492,14 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
let limit = buffer.len().min(32);
self.drain_fifo(&mut buffer[0..limit])
} {
+ // Drained fifo, still some room left!
Ok(len) if len < buffer.len() => &mut buffer[len..],
+ // Drained (some/all of the fifo), no room left
Ok(_) => return Ok(buffer),
- Err(e) => return Err(e),
+ // We got a break WHILE draining the FIFO, return what we did get before the break
+ Err((i, Error::Break)) => return Ok(&mut buffer[..i]),
+ // Some other error, just return the error
+ Err((_i, e)) => return Err(e),
};
// start a dma transfer. if errors have happened in the interim some error
@@ -499,27 +535,62 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
)
.await;
+ let mut did_finish = false;
+
+ // Figure out our error state
let errors = match transfer_result {
- Either::First(()) => return Ok(buffer),
- Either::Second(e) => e,
+ Either::First(()) => {
+ // We're here because the DMA finished, BUT if an error occurred on the LAST
+ // byte, then we may still need to grab the error state!
+ did_finish = true;
+ Uartris(T::dma_state().rx_errs.swap(0, Ordering::Relaxed) as u32)
+ }
+ Either::Second(e) => {
+ // We're here because we errored, which means this is the error that
+ // was problematic.
+ e
+ }
};
if errors.0 == 0 {
+ // No errors? That means we filled the buffer without a line break.
return Ok(buffer);
- } else if errors.oeris() {
- return Err(Error::Overrun);
} else if errors.beris() {
- // Begin "James is a chicken" region - I'm not certain if there is ever
- // a case where the write addr WOULDN'T exist between the start and end.
- // This assert checks that and hasn't fired (yet).
+ // We got a Line Break! By this point, we've finished/aborted the DMA
+ // transaction, which means that we need to figure out where it left off
+ // by looking at the write_addr.
+ //
+ // First, we do a sanity check to make sure the write value is within the
+ // range of DMA we just did.
let sval = buffer.as_ptr() as usize;
let eval = sval + buffer.len();
- // Note: the `write_addr()` is where the NEXT write would be, BUT we also
- // received one extra byte that represents the line break.
- let val = ch.regs().write_addr().read() as usize - 1;
- assert!((val >= sval) && (val <= eval));
- let taken = val - sval;
+
+ // Note: the `write_addr()` is where the NEXT write would be.
+ let mut last_written = ch.regs().write_addr().read() as usize;
+
+ // Did we finish the whole DMA transfer?
+ if !did_finish {
+ // No, we did not! We stopped because we got a line break. That means the
+ // DMA transferred one "garbage byte" from the FIFO that held an error.
+ last_written -= 1;
+ } else {
+ // We did finish and got a "late break", where the interrupt error fired AFTER
+ // we got the last byte. Pop that from the FIFO so we don't trip on it next time.
+ let dr = T::regs().uartdr().read();
+ if !dr.be() {
+ // Got an error after DMA but no error in the FIFO?
+ return Err(Error::Calculation);
+ }
+ }
+
+ // If we DON'T end up inside the range, something has gone really wrong.
+ if (last_written < sval) || (last_written > eval) {
+ return Err(Error::Calculation);
+ }
+ let taken = last_written - sval;
return Ok(&mut buffer[..taken]);
+ } else if errors.oeris() {
+ return Err(Error::Overrun);
} else if errors.peris() {
return Err(Error::Parity);
} else if errors.feris() {
@@ -930,6 +1001,7 @@ impl embedded_hal_nb::serial::Error for Error {
Self::Break => embedded_hal_nb::serial::ErrorKind::Other,
Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
+ Self::Calculation => embedded_hal_nb::serial::ErrorKind::Other,
}
}
}
From fe172109be8644b1e0d86735f4bd267ef7180c36 Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Wed, 20 Dec 2023 14:17:24 +0100
Subject: [PATCH 022/392] A little more cleanup
---
embassy-rp/src/uart/mod.rs | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index a89cb5932..998f7ccac 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -278,13 +278,16 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
/// Read from UART RX blocking execution until done.
pub fn blocking_read(&mut self, mut buffer: &mut [u8]) -> Result<(), Error> {
- while buffer.len() > 0 {
+ while !buffer.is_empty() {
let received = self.drain_fifo(buffer).map_err(|(_i, e)| e)?;
buffer = &mut buffer[received..];
}
Ok(())
}
+ /// Returns Ok(len) if no errors occurred. Returns Err((len, err)) if an error was
+ /// encountered. in both cases, `len` is the number of *good* bytes copied into
+ /// `buffer`.
fn drain_fifo(&mut self, buffer: &mut [u8]) -> Result<usize, (usize, Error)> {
let r = T::regs();
for (i, b) in buffer.iter_mut().enumerate() {
From 94290981c359cfc4bb2355055a8a5d1497cf09aa Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Wed, 20 Dec 2023 17:06:57 +0100
Subject: [PATCH 023/392] Debugging RSR
---
embassy-rp/src/uart/mod.rs | 128 +++++++++++++++++++++++--------------
1 file changed, 80 insertions(+), 48 deletions(-)
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 998f7ccac..61d3af5de 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -116,10 +116,16 @@ pub enum Error {
Parity,
/// Triggered when the received character didn't have a valid stop bit.
Framing,
- /// There was an issue when calculating the number of transferred items
- /// in an aborted DMA transaction. This is likely an error in the
- /// driver implementation, please open an embassy issue.
- Calculation,
+}
+
+/// Read To Break error
+#[derive(Debug, Eq, PartialEq, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum ReadToBreakError {
+ /// Read this many bytes, but never received a line break.
+ MissingBreak(usize),
+ Other(Error),
}
/// Internal DMA state of UART RX.
@@ -432,12 +438,10 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
)
.await;
- let mut did_finish = false;
let errors = match transfer_result {
Either::First(()) => {
// We're here because the DMA finished, BUT if an error occurred on the LAST
// byte, then we may still need to grab the error state!
- did_finish = true;
Uartris(T::dma_state().rx_errs.swap(0, Ordering::Relaxed) as u32)
}
Either::Second(e) => {
@@ -452,12 +456,7 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
return Ok(());
}
- // If we DID get an error, and DID finish, we'll have one error byte left in the FIFO.
- // Pop it since we are reporting the error on THIS transaction.
- if did_finish {
- let _ = T::regs().uartdr().read();
- }
-
+ // If we DID get an error, we need to figure out which one it was.
if errors.oeris() {
return Err(Error::Overrun);
} else if errors.beris() {
@@ -470,15 +469,27 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
unreachable!("unrecognized rx error");
}
- /// Read from the UART, until one of the following occurs:
+ /// Read from the UART, waiting for a line break.
+ ///
+ /// We read until one of the following occurs:
///
/// * We read `buffer.len()` bytes without a line break
- /// * returns `Ok(buffer)`
+ /// * returns `Err(ReadToBreakError::MissingBreak(buffer.len()))`
/// * We read `n` bytes then a line break occurs
- /// * returns `Ok(&mut buffer[..n])`
+ /// * returns `Ok(n)`
/// * We encounter some error OTHER than a line break
- /// * returns `Err(Error)`
- pub async fn read_to_break<'a>(&mut self, buffer: &'a mut [u8]) -> Result<&'a mut [u8], Error> {
+ /// * returns `Err(ReadToBreakError::Other(error))`
+ ///
+ /// **NOTE**: you MUST provide a buffer one byte larger than your largest expected
+ /// message to reliably detect the framing on one single call to `read_to_break()`.
+ ///
+ /// * If you expect a message of 20 bytes + line break, and provide a 20-byte buffer:
+ /// * The first call to `read_to_break()` will return `Err(ReadToBreakError::MissingBreak(20))`
+ /// * The next call to `read_to_break()` will immediately return `Ok(0)`, from the "stale" line break
+ /// * If you expect a message of 20 bytes + line break, and provide a 21-byte buffer:
+ /// * The first call to `read_to_break()` will return `Ok(20)`.
+ /// * The next call to `read_to_break()` will work as expected
+ pub async fn read_to_break(&mut self, buffer: &mut [u8]) -> Result<usize, ReadToBreakError> {
// clear error flags before we drain the fifo. errors that have accumulated
// in the flags will also be present in the fifo.
T::dma_state().rx_errs.store(0, Ordering::Relaxed);
@@ -498,11 +509,11 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
// Drained fifo, still some room left!
Ok(len) if len < buffer.len() => &mut buffer[len..],
// Drained (some/all of the fifo), no room left
- Ok(_) => return Ok(buffer),
+ Ok(len) => return Err(ReadToBreakError::MissingBreak(len)),
// We got a break WHILE draining the FIFO, return what we did get before the break
- Err((i, Error::Break)) => return Ok(&mut buffer[..i]),
+ Err((i, Error::Break)) => return Ok(i),
// Some other error, just return the error
- Err((_i, e)) => return Err(e),
+ Err((_i, e)) => return Err(ReadToBreakError::Other(e)),
};
// start a dma transfer. if errors have happened in the interim some error
@@ -538,14 +549,11 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
)
.await;
- let mut did_finish = false;
-
// Figure out our error state
let errors = match transfer_result {
Either::First(()) => {
// We're here because the DMA finished, BUT if an error occurred on the LAST
// byte, then we may still need to grab the error state!
- did_finish = true;
Uartris(T::dma_state().rx_errs.swap(0, Ordering::Relaxed) as u32)
}
Either::Second(e) => {
@@ -557,7 +565,8 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
if errors.0 == 0 {
// No errors? That means we filled the buffer without a line break.
- return Ok(buffer);
+ // For THIS function, that's a problem.
+ return Err(ReadToBreakError::MissingBreak(buffer.len()));
} else if errors.beris() {
// We got a Line Break! By this point, we've finished/aborted the DMA
// transaction, which means that we need to figure out where it left off
@@ -568,36 +577,60 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
let sval = buffer.as_ptr() as usize;
let eval = sval + buffer.len();
- // Note: the `write_addr()` is where the NEXT write would be.
- let mut last_written = ch.regs().write_addr().read() as usize;
+ // Note: the `write_addr()` is where the NEXT write would be, but we ALSO
+ // got a line break, so take an offset of 1
+ let mut next_addr = ch.regs().write_addr().read() as usize;
- // Did we finish the whole DMA transfer?
- if !did_finish {
- // No, we did not! We stopped because we got a line break. That means the
- // DMA transferred one "garbage byte" from the FIFO that held an error.
- last_written -= 1;
- } else {
- // We did finish and got a "late break", where the interrupt error fired AFTER
- // we got the last byte. Pop that from the FIFO so we don't trip on it next time.
- let dr = T::regs().uartdr().read();
- if !dr.be() {
- // Got an error after DMA but no error in the FIFO?
- return Err(Error::Calculation);
+ // If we DON'T end up inside the range, something has gone really wrong.
+ if (next_addr < sval) || (next_addr > eval) {
+ unreachable!("UART DMA reported invalid `write_addr`");
+ }
+
+ // If we finished the full DMA, AND the FIFO is not-empty, AND that
+ // byte reports a break error, THAT byte caused the error, and not data
+ // in the DMA transfer! Otherwise: our DMA grabbed one "bad" byte.
+ //
+ // Note: even though we COULD detect this and return `Ok(buffer.len())`,
+ // we DON'T, as that is racy: if we read the error state AFTER the data
+ // was transferred but BEFORE the line break interrupt fired, we'd return
+ // `MissingBreak`. Ignoring the fact that there's a line break in the FIFO
+ // means callers consistently see the same error regardless of
+ let regs = T::regs();
+ let is_end = next_addr == eval;
+ let not_empty = !regs.uartfr().read().rxfe();
+ let is_break = regs.uartrsr().read().be();
+ let last_good = is_end && not_empty && is_break;
+
+ defmt::println!("next: {=usize}, sval: {=usize}, eval: {=usize}", next_addr, sval, eval);
+ defmt::println!("lg: {=bool}, is_end: {=bool}, not_empty: {=bool}, is_break: {=bool}", last_good, is_end, not_empty, is_break);
+
+ if is_end && not_empty && !is_break {
+ let val = regs.uartdr().read();
+ let tb = regs.uartrsr().read().be();
+ let te = regs.uartfr().read().rxfe();
+ defmt::println!("THEN: {=bool}, {=bool}", tb, te);
+ if val.be() {
+ panic!("Oh what the hell");
}
}
- // If we DON'T end up inside the range, something has gone really wrong.
- if (last_written < sval) || (last_written > eval) {
- return Err(Error::Calculation);
+ if !last_good {
+ defmt::println!("Last not good!");
+ // The last is NOT good (it's the line-break `0x00`), so elide it
+ next_addr -= 1;
+ } else {
+ defmt::println!("last good!");
}
- let taken = last_written - sval;
- return Ok(&mut buffer[..taken]);
+
+ defmt::println!("->{=usize}", next_addr - sval);
+
+ return Ok(next_addr - sval);
} else if errors.oeris() {
- return Err(Error::Overrun);
+ return Err(ReadToBreakError::Other(Error::Overrun));
} else if errors.peris() {
- return Err(Error::Parity);
+ return Err(ReadToBreakError::Other(Error::Parity));
} else if errors.feris() {
- return Err(Error::Framing);
+ return Err(ReadToBreakError::Other(Error::Framing));
}
unreachable!("unrecognized rx error");
}
@@ -902,7 +935,7 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
self.rx.read(buffer).await
}
- pub async fn read_to_break<'a>(&mut self, buf: &'a mut [u8]) -> Result<&'a mut [u8], Error> {
+ pub async fn read_to_break<'a>(&mut self, buf: &'a mut [u8]) -> Result<usize, ReadToBreakError> {
self.rx.read_to_break(buf).await
}
}
@@ -1004,7 +1037,6 @@ impl embedded_hal_nb::serial::Error for Error {
Self::Break => embedded_hal_nb::serial::ErrorKind::Other,
Self::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
Self::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
- Self::Calculation => embedded_hal_nb::serial::ErrorKind::Other,
}
}
}
From 1ce96f79fb356b29b882a3571415f347e48e89c9 Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Wed, 20 Dec 2023 17:27:58 +0100
Subject: [PATCH 024/392] Fun Learning about the RP2040 UART impl!
---
embassy-rp/src/uart/mod.rs | 77 +++++++++++++++++++-------------------
1 file changed, 39 insertions(+), 38 deletions(-)
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 61d3af5de..a9ae6c3f4 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -577,54 +577,55 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
let sval = buffer.as_ptr() as usize;
let eval = sval + buffer.len();
- // Note: the `write_addr()` is where the NEXT write would be, but we ALSO
- // got a line break, so take an offset of 1
- let mut next_addr = ch.regs().write_addr().read() as usize;
+ // This is the address where the DMA would write to next
+ let next_addr = ch.regs().write_addr().read() as usize;
// If we DON'T end up inside the range, something has gone really wrong.
+ // Note that it's okay that `eval` is one past the end of the slice, as
+ // this is where the write pointer will end up at the end of a full
+ // transfer.
if (next_addr < sval) || (next_addr > eval) {
unreachable!("UART DMA reported invalid `write_addr`");
}
- // If we finished the full DMA, AND the FIFO is not-empty, AND that
- // byte reports a break error, THAT byte caused the error, and not data
- // in the DMA transfer! Otherwise: our DMA grabbed one "bad" byte.
- //
- // Note: even though we COULD detect this and return `Ok(buffer.len())`,
- // we DON'T, as that is racy: if we read the error state AFTER the data
- // was transferred but BEFORE the line break interrupt fired, we'd return
- // `MissingBreak`. Ignoring the fact that there's a line break in the FIFO
- // means callers consistently see the same error regardless of
let regs = T::regs();
- let is_end = next_addr == eval;
- let not_empty = !regs.uartfr().read().rxfe();
- let is_break = regs.uartrsr().read().be();
- let last_good = is_end && not_empty && is_break;
+ let all_full = next_addr == eval;
- defmt::println!("next: {=usize}, sval: {=usize}, eval: {=usize}", next_addr, sval, eval);
- defmt::println!("lg: {=bool}, is_end: {=bool}, not_empty: {=bool}, is_break: {=bool}", last_good, is_end, not_empty, is_break);
+ // NOTE: This is off label usage of RSR! See the issue below for
+ // why I am not checking if there is an "extra" FIFO byte, and why
+ // I am checking RSR directly (it seems to report the status of the LAST
+ // POPPED value, rather than the NEXT TO POP value like the datasheet
+ // suggests!)
+ //
+ // issue: https://github.com/raspberrypi/pico-feedback/issues/367
+ let last_was_break = regs.uartrsr().read().be();
- if is_end && not_empty && !is_break {
- let val = regs.uartdr().read();
- let tb = regs.uartrsr().read().be();
- let te = regs.uartfr().read().rxfe();
- defmt::println!("THEN: {=bool}, {=bool}", tb, te);
- if val.be() {
- panic!("Oh what the hell");
+ return match (all_full, last_was_break) {
+ (true, true) | (false, _) => {
+ // We got less than the full amount + a break, or the full amount
+ // and the last byte was a break. Subtract the break off.
+ Ok((next_addr - 1) - sval)
}
- }
-
- if !last_good {
- defmt::println!("Last not good!");
- // The last is NOT good (it's the line-break `0x00`), so elide it
- next_addr -= 1;
- } else {
- defmt::println!("last good!");
- }
-
- defmt::println!("->{=usize}", next_addr - sval);
-
- return Ok(next_addr - sval);
+ (true, false) => {
+ // We finished the whole DMA, and the last DMA'd byte was NOT a break
+ // character. This is an error.
+ //
+ // NOTE: we COULD potentially return Ok(buffer.len()) here, since we
+ // know a line break occured at SOME POINT after the DMA completed.
+ //
+ // However, we have no way of knowing if there was extra data BEFORE
+ // that line break, so instead return an Err to signal to the caller
+ // that there are "leftovers", and they'll catch the actual line break
+ // on the next call.
+ //
+ // Doing it like this also avoids racyness: now whether you finished
+ // the full read BEFORE the line break occurred or AFTER the line break
+ // occurs, you still get `MissingBreak(buffer.len())` instead of sometimes
+ // getting `Ok(buffer.len())` if you were "late enough" to observe the
+ // line break.
+ Err(ReadToBreakError::MissingBreak(buffer.len()))
+ }
+ };
} else if errors.oeris() {
return Err(ReadToBreakError::Other(Error::Overrun));
} else if errors.peris() {
From 5e08bb8bc3a7e0e308cbada03c9c363cdf5223b9 Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Fri, 19 Jan 2024 15:46:36 +0100
Subject: [PATCH 025/392] A rebase ate my doc comment!
---
embassy-rp/src/uart/mod.rs | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index a9ae6c3f4..9f5ba4e8a 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -125,6 +125,7 @@ pub enum Error {
pub enum ReadToBreakError {
/// Read this many bytes, but never received a line break.
MissingBreak(usize),
+ /// Other, standard issue with the serial request
Other(Error),
}
@@ -936,6 +937,9 @@ impl<'d, T: Instance> Uart<'d, T, Async> {
self.rx.read(buffer).await
}
+ /// Read until the buffer is full or a line break occurs.
+ ///
+ /// See [`UartRx::read_to_break()`] for more details
pub async fn read_to_break<'a>(&mut self, buf: &'a mut [u8]) -> Result<usize, ReadToBreakError> {
self.rx.read_to_break(buf).await
}
From 5e158757b9922bff178541f8a50a3e87be8c1c2d Mon Sep 17 00:00:00 2001
From: "Christopher N. Hesse" <raymanfx@gmail.com>
Date: Mon, 15 Jan 2024 12:05:55 +0100
Subject: [PATCH 026/392] Add more fields to the BssInfo packet struct
Taken from the Infineon WHD repository:
https://github.com/Infineon/wifi-host-driver/blob/04ee318cc96bffa7d69a1e076c008e2364453f82/WiFi_Host_Driver/inc/whd_types.h#L814
Signed-off-by: Christopher N. Hesse <raymanfx@gmail.com>
---
cyw43/src/structs.rs | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/cyw43/src/structs.rs b/cyw43/src/structs.rs
index 5ea62d95b..ae7ef6038 100644
--- a/cyw43/src/structs.rs
+++ b/cyw43/src/structs.rs
@@ -491,6 +491,44 @@ pub struct BssInfo {
pub ssid_len: u8,
/// SSID.
pub ssid: [u8; 32],
+ reserved1: [u8; 1],
+ /// Number of rates in the rates field.
+ pub rateset_count: u32,
+ /// Rates in 500kpbs units.
+ pub rates: [u8; 16],
+ /// Channel specification.
+ pub chanspec: u16,
+ /// Announcement traffic indication message.
+ pub atim_window: u16,
+ /// Delivery traffic indication message.
+ pub dtim_period: u8,
+ reserved2: [u8; 1],
+ /// Receive signal strength (in dbM).
+ pub rssi: i16,
+ /// Received noise (in dbM).
+ pub phy_noise: i8,
+ /// 802.11n capability.
+ pub n_cap: u8,
+ reserved3: [u8; 2],
+ /// 802.11n BSS capabilities.
+ pub nbss_cap: u32,
+ /// 802.11n control channel number.
+ pub ctl_ch: u8,
+ reserved4: [u8; 3],
+ reserved32: [u32; 1],
+ /// Flags.
+ pub flags: u8,
+ /// VHT capability.
+ pub vht_cap: u8,
+ reserved5: [u8; 2],
+ /// 802.11n BSS required MCS.
+ pub basic_mcs: [u8; 16],
+ /// Information Elements (IE) offset.
+ pub ie_offset: u16,
+ /// Length of Information Elements (IE) in bytes.
+ pub ie_length: u32,
+ /// Average signal-to-noise (SNR) ratio during frame reception.
+ pub snr: i16,
// there will be more stuff here
}
impl_bytes!(BssInfo);
From 527005324889cc7ebc532e459c7de447336634cc Mon Sep 17 00:00:00 2001
From: Luca Barbato <lu_zero@gentoo.org>
Date: Fri, 19 Jan 2024 18:31:14 +0100
Subject: [PATCH 027/392] Fix a typo
---
embassy-usb/README.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-usb/README.md b/embassy-usb/README.md
index 7411fcf52..d2adae4f5 100644
--- a/embassy-usb/README.md
+++ b/embassy-usb/README.md
@@ -9,7 +9,7 @@ Async USB device stack for embedded devices in Rust.
- Suspend/resume, remote wakeup.
- USB composite devices.
- Ergonomic descriptor builder.
-- Ready-to-use implementations for a few USB classes (note you can still implement any class yourself oustide the crate).
+- Ready-to-use implementations for a few USB classes (note you can still implement any class yourself outside the crate).
- Serial ports (CDC ACM)
- Ethernet (CDC NCM)
- Human Interface Devices (HID)
From ace3280b644295549fbc516a7da36407b8b32135 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Tue, 28 Nov 2023 17:10:20 +0100
Subject: [PATCH 028/392] stm32/tests: enable f446 hil.
---
ci.sh | 3 ---
1 file changed, 3 deletions(-)
diff --git a/ci.sh b/ci.sh
index a1d0c8c26..c7c1755a0 100755
--- a/ci.sh
+++ b/ci.sh
@@ -222,9 +222,6 @@ rm out/tests/rpi-pico/i2c
rm out/tests/stm32wb55rg/wpan_mac
rm out/tests/stm32wb55rg/wpan_ble
-# not in CI yet.
-rm -rf out/tests/stm32f446re
-
# unstable, I think it's running out of RAM?
rm out/tests/stm32f207zg/eth
From d781e231cd8491e1985bf78374ba13038eb64081 Mon Sep 17 00:00:00 2001
From: Harry Brooke <harry.brooke1@hotmail.co.uk>
Date: Wed, 6 Dec 2023 10:49:28 +0000
Subject: [PATCH 029/392] make usart::State private
---
embassy-stm32/src/usart/buffered.rs | 34 +++++++++++++++--------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 962547bd7..f8e0bfda5 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -82,23 +82,25 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
}
}
-/// Buffered UART State
-pub struct State {
- rx_waker: AtomicWaker,
- rx_buf: RingBuffer,
+pub(crate) use sealed::State;
+pub(crate) mod sealed {
+ use super::*;
+ pub struct State {
+ pub(crate) rx_waker: AtomicWaker,
+ pub(crate) rx_buf: RingBuffer,
+ pub(crate) tx_waker: AtomicWaker,
+ pub(crate) tx_buf: RingBuffer,
+ }
- tx_waker: AtomicWaker,
- tx_buf: RingBuffer,
-}
-
-impl State {
- /// Create new state
- pub const fn new() -> Self {
- Self {
- rx_buf: RingBuffer::new(),
- tx_buf: RingBuffer::new(),
- rx_waker: AtomicWaker::new(),
- tx_waker: AtomicWaker::new(),
+ impl State {
+ /// Create new state
+ pub const fn new() -> Self {
+ Self {
+ rx_buf: RingBuffer::new(),
+ tx_buf: RingBuffer::new(),
+ rx_waker: AtomicWaker::new(),
+ tx_waker: AtomicWaker::new(),
+ }
}
}
}
From ea0ca181943fb4022c5569bc65de191499d7ac5f Mon Sep 17 00:00:00 2001
From: Christian Enderle <mail@chrenderle.de>
Date: Sat, 30 Dec 2023 16:54:00 +0100
Subject: [PATCH 030/392] ci.sh: add low-power feature for stm32l5
---
ci.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ci.sh b/ci.sh
index c7c1755a0..3322c60d1 100755
--- a/ci.sh
+++ b/ci.sh
@@ -120,7 +120,7 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f378cc,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g0c1ve,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f217zg,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti,time-driver-any,low-power,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32wl54jc-cm0p,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wle5jb,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32g474pe,defmt,exti,time-driver-any,time \
From 6ca43030db125bd440c8e7383a4fc9c93bea7a4e Mon Sep 17 00:00:00 2001
From: umgefahren <55623006+umgefahren@users.noreply.github.com>
Date: Fri, 19 Jan 2024 23:49:49 +0100
Subject: [PATCH 031/392] feat: Extended the Scan API
---
cyw43/Cargo.toml | 4 +-
cyw43/src/control.rs | 93 ++++++++++++++++++++++++++++----
cyw43/src/events.rs | 4 +-
examples/rp/src/bin/wifi_scan.rs | 2 +-
4 files changed, 89 insertions(+), 14 deletions(-)
diff --git a/cyw43/Cargo.toml b/cyw43/Cargo.toml
index c857f7378..64c38ea7a 100644
--- a/cyw43/Cargo.toml
+++ b/cyw43/Cargo.toml
@@ -10,7 +10,7 @@ repository = "https://github.com/embassy-rs/embassy"
documentation = "https://docs.embassy.dev/cyw43"
[features]
-defmt = ["dep:defmt"]
+defmt = ["dep:defmt", "heapless/defmt-03"]
log = ["dep:log"]
# Fetch console logs from the WiFi firmware and forward them to `log` or `defmt`.
@@ -32,6 +32,8 @@ futures = { version = "0.3.17", default-features = false, features = ["async-awa
embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
num_enum = { version = "0.5.7", default-features = false }
+heapless = "0.8.0"
+
[package.metadata.embassy_docs]
src_base = "https://github.com/embassy-rs/embassy/blob/cyw43-v$VERSION/cyw43/src/"
src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/cyw43/src/"
diff --git a/cyw43/src/control.rs b/cyw43/src/control.rs
index 311fcb08c..26d50d311 100644
--- a/cyw43/src/control.rs
+++ b/cyw43/src/control.rs
@@ -3,7 +3,7 @@ use core::iter::zip;
use embassy_net_driver_channel as ch;
use embassy_net_driver_channel::driver::{HardwareAddress, LinkState};
-use embassy_time::Timer;
+use embassy_time::{Duration, Timer};
use crate::consts::*;
use crate::events::{Event, EventSubscriber, Events};
@@ -35,6 +35,45 @@ pub struct Control<'a> {
ioctl_state: &'a IoctlState,
}
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ScanType {
+ Active {
+ /// Period of time to wait on each channel when active scanning.
+ dwell_time: Option<Duration>,
+ },
+ Passive {
+ /// Period of time to wait on each channel when passive scanning.
+ dwell_time: Option<Duration>,
+ },
+}
+
+#[derive(Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct ScanOptions {
+ pub ssid: Option<heapless::String<32>>,
+ /// If set to `None`, all APs will be returned. If set to `Some`, only APs
+ /// with the specified BSSID will be returned.
+ pub bssid: Option<[u8; 6]>,
+ /// Number of probes to send on each channel.
+ pub nprobes: Option<u16>,
+ /// Time to spend waiting on the home channel.
+ pub home_time: Option<Duration>,
+ pub scan_type: ScanType,
+}
+
+impl Default for ScanOptions {
+ fn default() -> Self {
+ Self {
+ ssid: None,
+ bssid: None,
+ nprobes: None,
+ home_time: None,
+ scan_type: ScanType::Passive { dwell_time: None },
+ }
+ }
+}
+
impl<'a> Control<'a> {
pub(crate) fn new(state_ch: ch::StateRunner<'a>, event_sub: &'a Events, ioctl_state: &'a IoctlState) -> Self {
Self {
@@ -471,22 +510,56 @@ impl<'a> Control<'a> {
/// # Note
/// Device events are currently implemented using a bounded queue.
/// To not miss any events, you should make sure to always await the stream.
- pub async fn scan(&mut self) -> Scanner<'_> {
+ pub async fn scan(&mut self, scan_opts: ScanOptions) -> Scanner<'_> {
+ const SCANTYPE_ACTIVE: u8 = 0;
const SCANTYPE_PASSIVE: u8 = 1;
+ let mut active_time = !0;
+ let mut passive_time = !0;
+
+ let scan_type = match scan_opts.scan_type {
+ ScanType::Active { dwell_time: None } => SCANTYPE_ACTIVE,
+ ScanType::Active {
+ dwell_time: Some(dwell_time),
+ } => {
+ active_time = dwell_time.as_millis() as u32;
+ if active_time == !0 {
+ active_time = !0 - 1;
+ }
+ SCANTYPE_ACTIVE
+ }
+ ScanType::Passive { dwell_time: None } => SCANTYPE_PASSIVE,
+ ScanType::Passive {
+ dwell_time: Some(dwell_time),
+ } => {
+ passive_time = dwell_time.as_millis() as u32;
+ if passive_time == !0 {
+ passive_time = !0 - 1;
+ }
+ SCANTYPE_PASSIVE
+ }
+ };
+
let scan_params = ScanParams {
version: 1,
action: 1,
sync_id: 1,
- ssid_len: 0,
- ssid: [0; 32],
- bssid: [0xff; 6],
+ ssid_len: scan_opts.ssid.as_ref().map(|e| e.as_bytes().len() as u32).unwrap_or(0),
+ ssid: scan_opts
+ .ssid
+ .map(|e| {
+ let mut ssid = [0; 32];
+ ssid[..e.as_bytes().len()].copy_from_slice(e.as_bytes());
+ ssid
+ })
+ .unwrap_or([0; 32]),
+ bssid: scan_opts.bssid.unwrap_or([0xff; 6]),
bss_type: 2,
- scan_type: SCANTYPE_PASSIVE,
- nprobes: !0,
- active_time: !0,
- passive_time: !0,
- home_time: !0,
+ scan_type,
+ nprobes: scan_opts.nprobes.unwrap_or(!0).into(),
+ active_time,
+ passive_time,
+ home_time: scan_opts.home_time.map(|e| e.as_millis() as u32).unwrap_or(!0),
channel_num: 0,
channel_list: [0; 1],
};
diff --git a/cyw43/src/events.rs b/cyw43/src/events.rs
index a94c49a0c..44bfa98e9 100644
--- a/cyw43/src/events.rs
+++ b/cyw43/src/events.rs
@@ -311,13 +311,13 @@ pub struct Status {
pub status: u32,
}
-#[derive(Clone, Copy)]
+#[derive(Copy, Clone)]
pub enum Payload {
None,
BssInfo(BssInfo),
}
-#[derive(Clone, Copy)]
+#[derive(Copy, Clone)]
pub struct Message {
pub header: Status,
diff --git a/examples/rp/src/bin/wifi_scan.rs b/examples/rp/src/bin/wifi_scan.rs
index 45bb5b76c..e678209dd 100644
--- a/examples/rp/src/bin/wifi_scan.rs
+++ b/examples/rp/src/bin/wifi_scan.rs
@@ -65,7 +65,7 @@ async fn main(spawner: Spawner) {
.set_power_management(cyw43::PowerManagementMode::PowerSave)
.await;
- let mut scanner = control.scan().await;
+ let mut scanner = control.scan(Default::default()).await;
while let Some(bss) = scanner.next().await {
if let Ok(ssid_str) = str::from_utf8(&bss.ssid) {
info!("scanned {} == {:x}", ssid_str, bss.bssid);
From 24968629ec810b844b819e8f84baab2a9349ed2f Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 20 Jan 2024 00:10:35 +0100
Subject: [PATCH 032/392] cyw43: Unify dwell time.
---
cyw43/Cargo.toml | 2 +-
cyw43/src/control.rs | 48 ++++++++++++++++++++------------------------
2 files changed, 23 insertions(+), 27 deletions(-)
diff --git a/cyw43/Cargo.toml b/cyw43/Cargo.toml
index 64c38ea7a..f279739e4 100644
--- a/cyw43/Cargo.toml
+++ b/cyw43/Cargo.toml
@@ -10,7 +10,7 @@ repository = "https://github.com/embassy-rs/embassy"
documentation = "https://docs.embassy.dev/cyw43"
[features]
-defmt = ["dep:defmt", "heapless/defmt-03"]
+defmt = ["dep:defmt", "heapless/defmt-03", "embassy-time/defmt"]
log = ["dep:log"]
# Fetch console logs from the WiFi firmware and forward them to `log` or `defmt`.
diff --git a/cyw43/src/control.rs b/cyw43/src/control.rs
index 26d50d311..135b8c245 100644
--- a/cyw43/src/control.rs
+++ b/cyw43/src/control.rs
@@ -38,14 +38,8 @@ pub struct Control<'a> {
#[derive(Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum ScanType {
- Active {
- /// Period of time to wait on each channel when active scanning.
- dwell_time: Option<Duration>,
- },
- Passive {
- /// Period of time to wait on each channel when passive scanning.
- dwell_time: Option<Duration>,
- },
+ Active,
+ Passive,
}
#[derive(Clone)]
@@ -59,7 +53,10 @@ pub struct ScanOptions {
pub nprobes: Option<u16>,
/// Time to spend waiting on the home channel.
pub home_time: Option<Duration>,
+ /// Scan type: active or passive.
pub scan_type: ScanType,
+ /// Period of time to wait on each channel when passive scanning.
+ pub dwell_time: Option<Duration>,
}
impl Default for ScanOptions {
@@ -69,7 +66,8 @@ impl Default for ScanOptions {
bssid: None,
nprobes: None,
home_time: None,
- scan_type: ScanType::Passive { dwell_time: None },
+ scan_type: ScanType::Passive,
+ dwell_time: None,
}
}
}
@@ -514,28 +512,26 @@ impl<'a> Control<'a> {
const SCANTYPE_ACTIVE: u8 = 0;
const SCANTYPE_PASSIVE: u8 = 1;
+ let dwell_time = match scan_opts.dwell_time {
+ None => !0,
+ Some(t) => {
+ let mut t = t.as_millis() as u32;
+ if t == !0 {
+ t = !0 - 1;
+ }
+ t
+ }
+ };
+
let mut active_time = !0;
let mut passive_time = !0;
-
let scan_type = match scan_opts.scan_type {
- ScanType::Active { dwell_time: None } => SCANTYPE_ACTIVE,
- ScanType::Active {
- dwell_time: Some(dwell_time),
- } => {
- active_time = dwell_time.as_millis() as u32;
- if active_time == !0 {
- active_time = !0 - 1;
- }
+ ScanType::Active => {
+ active_time = dwell_time;
SCANTYPE_ACTIVE
}
- ScanType::Passive { dwell_time: None } => SCANTYPE_PASSIVE,
- ScanType::Passive {
- dwell_time: Some(dwell_time),
- } => {
- passive_time = dwell_time.as_millis() as u32;
- if passive_time == !0 {
- passive_time = !0 - 1;
- }
+ ScanType::Passive => {
+ passive_time = dwell_time;
SCANTYPE_PASSIVE
}
};
From ec47e931acbc4a4b1a9f0781e9317f1e680427eb Mon Sep 17 00:00:00 2001
From: Andres Vahter <andres@vahter.me>
Date: Mon, 8 Jan 2024 17:33:11 +0200
Subject: [PATCH 033/392] stm32: fix buffered uart flush
usart_v4 uses internal FIFO and therefore actually all bytes are not yet sent out although state.tx_buf.is_empty()
---
embassy-stm32/src/usart/buffered.rs | 30 +++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index f8e0bfda5..e050f8e0f 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -1,5 +1,6 @@
use core::future::poll_fn;
use core::slice;
+use core::sync::atomic::{AtomicBool, Ordering};
use core::task::Poll;
use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
@@ -61,6 +62,18 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
state.rx_waker.wake();
}
+ // With `usart_v4` hardware FIFO is enabled, making `state.tx_buf`
+ // insufficient to determine if all bytes are sent out.
+ // Transmission complete (TC) interrupt here indicates that all bytes are pushed out from the FIFO.
+ #[cfg(usart_v4)]
+ if sr_val.tc() {
+ r.cr1().modify(|w| {
+ w.set_tcie(false);
+ });
+ state.tx_done.store(true, Ordering::Release);
+ state.rx_waker.wake();
+ }
+
// TX
if sr(r).read().txe() {
let mut tx_reader = state.tx_buf.reader();
@@ -69,6 +82,12 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
r.cr1().modify(|w| {
w.set_txeie(true);
});
+
+ #[cfg(usart_v4)]
+ r.cr1().modify(|w| {
+ w.set_tcie(true);
+ });
+
tdr(r).write_volatile(buf[0].into());
tx_reader.pop_done(1);
state.tx_waker.wake();
@@ -90,6 +109,7 @@ pub(crate) mod sealed {
pub(crate) rx_buf: RingBuffer,
pub(crate) tx_waker: AtomicWaker,
pub(crate) tx_buf: RingBuffer,
+ pub(crate) tx_done: AtomicBool,
}
impl State {
@@ -100,6 +120,7 @@ pub(crate) mod sealed {
tx_buf: RingBuffer::new(),
rx_waker: AtomicWaker::new(),
tx_waker: AtomicWaker::new(),
+ tx_done: AtomicBool::new(true),
}
}
}
@@ -366,6 +387,8 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
async fn write(&self, buf: &[u8]) -> Result<usize, Error> {
poll_fn(move |cx| {
let state = T::buffered_state();
+ state.tx_done.store(false, Ordering::Release);
+
let empty = state.tx_buf.is_empty();
let mut tx_writer = unsafe { state.tx_buf.writer() };
@@ -391,6 +414,13 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
async fn flush(&self) -> Result<(), Error> {
poll_fn(move |cx| {
let state = T::buffered_state();
+
+ #[cfg(usart_v4)]
+ if !state.tx_done.load(Ordering::Acquire) {
+ state.tx_waker.register(cx.waker());
+ return Poll::Pending;
+ }
+ #[cfg(not(usart_v4))]
if !state.tx_buf.is_empty() {
state.tx_waker.register(cx.waker());
return Poll::Pending;
From 17d6e4eefeb9bdc9d7c3776afb815298be5b468c Mon Sep 17 00:00:00 2001
From: Andres Vahter <andres@vahter.me>
Date: Tue, 9 Jan 2024 09:25:10 +0200
Subject: [PATCH 034/392] stm32 uart: do not wake after sending each byte
usart_v4 uses TC interrupt to see if all bytes are sent out from the FIFO and waker is called from this interrupt. This minimises unnecessary wakeups during sending.
---
embassy-stm32/src/usart/buffered.rs | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index e050f8e0f..211091c38 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -62,8 +62,8 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
state.rx_waker.wake();
}
- // With `usart_v4` hardware FIFO is enabled, making `state.tx_buf`
- // insufficient to determine if all bytes are sent out.
+ // With `usart_v4` hardware FIFO is enabled, making `state.tx_buf` insufficient
+ // to determine if all bytes are sent out.
// Transmission complete (TC) interrupt here indicates that all bytes are pushed out from the FIFO.
#[cfg(usart_v4)]
if sr_val.tc() {
@@ -90,9 +90,12 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
tdr(r).write_volatile(buf[0].into());
tx_reader.pop_done(1);
+
+ // Notice that in case of `usart_v4` waker is called when TC interrupt happens.
+ #[cfg(not(usart_v4))]
state.tx_waker.wake();
} else {
- // Disable interrupt until we have something to transmit again
+ // Disable interrupt until we have something to transmit again.
r.cr1().modify(|w| {
w.set_txeie(false);
});
From c936d66934225db8ddd283d7da2d7a158686df71 Mon Sep 17 00:00:00 2001
From: Andres Vahter <andres@vahter.me>
Date: Tue, 9 Jan 2024 14:47:30 +0200
Subject: [PATCH 035/392] stm32 uart: fix `flush` for non usart_v4 variants
Byte was written to TDR and right after that waker was called. This means `flush` would see that `tx_buf` is empty and can return Ready although actually hardware was still writing this last byte to the wire.
With this change non `usart_v4 ` variants would also use TC interrupt to check when last byte was sent out.
---
embassy-stm32/src/usart/buffered.rs | 27 +++++++++------------------
1 file changed, 9 insertions(+), 18 deletions(-)
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 211091c38..52740c13e 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -62,10 +62,9 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
state.rx_waker.wake();
}
- // With `usart_v4` hardware FIFO is enabled, making `state.tx_buf` insufficient
- // to determine if all bytes are sent out.
- // Transmission complete (TC) interrupt here indicates that all bytes are pushed out from the FIFO.
- #[cfg(usart_v4)]
+ // With `usart_v4` hardware FIFO is enabled and Transmission complete (TC)
+ // indicates that all bytes are pushed out from the FIFO.
+ // For other usart variants it shows that last byte from the buffer was just sent.
if sr_val.tc() {
r.cr1().modify(|w| {
w.set_tcie(false);
@@ -83,17 +82,15 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
w.set_txeie(true);
});
- #[cfg(usart_v4)]
- r.cr1().modify(|w| {
- w.set_tcie(true);
- });
+ // Enable transmission complete interrupt when last byte is going to be sent out.
+ if buf.len() == 1 {
+ r.cr1().modify(|w| {
+ w.set_tcie(true);
+ });
+ }
tdr(r).write_volatile(buf[0].into());
tx_reader.pop_done(1);
-
- // Notice that in case of `usart_v4` waker is called when TC interrupt happens.
- #[cfg(not(usart_v4))]
- state.tx_waker.wake();
} else {
// Disable interrupt until we have something to transmit again.
r.cr1().modify(|w| {
@@ -418,16 +415,10 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
poll_fn(move |cx| {
let state = T::buffered_state();
- #[cfg(usart_v4)]
if !state.tx_done.load(Ordering::Acquire) {
state.tx_waker.register(cx.waker());
return Poll::Pending;
}
- #[cfg(not(usart_v4))]
- if !state.tx_buf.is_empty() {
- state.tx_waker.register(cx.waker());
- return Poll::Pending;
- }
Poll::Ready(Ok(()))
})
From 534c53c901345f8af517b8991a4bcd99d290c11c Mon Sep 17 00:00:00 2001
From: Andres Vahter <andres@vahter.me>
Date: Fri, 19 Jan 2024 19:58:00 +0200
Subject: [PATCH 036/392] stm32 uart: remove unwrap
unwraps take more space because of panics
---
embassy-stm32/src/usart/buffered.rs | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 52740c13e..abc766bc7 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -47,8 +47,10 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
let mut rx_writer = state.rx_buf.writer();
let buf = rx_writer.push_slice();
if !buf.is_empty() {
- buf[0] = dr.unwrap();
- rx_writer.push_done(1);
+ if let Some(byte) = dr {
+ buf[0] = byte;
+ rx_writer.push_done(1);
+ }
} else {
// FIXME: Should we disable any further RX interrupts when the buffer becomes full.
}
From ec2e3de0f493cd0cc116f5f67a814ae7c457d9b1 Mon Sep 17 00:00:00 2001
From: Andres Vahter <andres@vahter.me>
Date: Fri, 19 Jan 2024 20:28:29 +0200
Subject: [PATCH 037/392] stm32 uart: fix buffered flush for usart_v1, usart_v2
There is one caveat. For some reason with first send using usart_v1/usart_v2 TC flag appears right after first byte from buffer is written to DR. Consecutive transfers work as expected - TC flag appears when last byte is fully transferred to wire.
---
embassy-stm32/src/usart/buffered.rs | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index abc766bc7..c78752883 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -68,11 +68,16 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
// indicates that all bytes are pushed out from the FIFO.
// For other usart variants it shows that last byte from the buffer was just sent.
if sr_val.tc() {
+ // For others it is cleared above with `clear_interrupt_flags`.
+ #[cfg(any(usart_v1, usart_v2))]
+ sr(r).modify(|w| w.set_tc(false));
+
r.cr1().modify(|w| {
w.set_tcie(false);
});
+
state.tx_done.store(true, Ordering::Release);
- state.rx_waker.wake();
+ state.tx_waker.wake();
}
// TX
From 7696b1c0b8f409fdcd9e171b7e8a51c29661a2da Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 20 Jan 2024 01:47:56 +0100
Subject: [PATCH 038/392] tests/stm32: fix h7 wrong smps config.
---
tests/stm32/src/common.rs | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 313380b35..fefe72c86 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -394,6 +394,10 @@ pub fn config() -> Config {
config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.voltage_scale = VoltageScale::Scale1;
config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+ #[cfg(any(feature = "stm32h755zi"))]
+ {
+ config.rcc.supply_config = SupplyConfig::DirectSMPS;
+ }
}
#[cfg(any(feature = "stm32h7a3zi"))]
From 69d4b428412fb0252d2a7eb807f3439e999bccfb Mon Sep 17 00:00:00 2001
From: Dennis Ranke <dennis.ranke@gmail.com>
Date: Sat, 20 Jan 2024 16:08:32 +0100
Subject: [PATCH 039/392] add pio_i2s example for RP2040
---
examples/rp/src/bin/pio_i2s.rs | 130 +++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
create mode 100644 examples/rp/src/bin/pio_i2s.rs
diff --git a/examples/rp/src/bin/pio_i2s.rs b/examples/rp/src/bin/pio_i2s.rs
new file mode 100644
index 000000000..66802c8b7
--- /dev/null
+++ b/examples/rp/src/bin/pio_i2s.rs
@@ -0,0 +1,130 @@
+//! This example shows generating audio and sending it to a connected i2s DAC using the PIO
+//! module of the RP2040.
+//!
+//! Connect the i2s DAC as follows:
+//! bclk : GPIO 18
+//! lrc : GPIO 19
+//! din : GPIO 20
+//! Then hold down the boot select button to trigger a rising triangle waveform.
+
+#![no_std]
+#![no_main]
+
+use core::mem;
+
+use defmt_rtt as _;
+use embassy_executor::Spawner;
+use embassy_rp::{
+ bind_interrupts,
+ peripherals::PIO0,
+ pio::{Config, FifoJoin, InterruptHandler, Pio, ShiftConfig, ShiftDirection},
+ Peripheral,
+};
+use fixed::traits::ToFixed;
+use panic_probe as _;
+use static_cell::StaticCell;
+
+bind_interrupts!(struct Irqs {
+ PIO0_IRQ_0 => InterruptHandler<PIO0>;
+});
+
+const SAMPLE_RATE: u32 = 48_000;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let mut p = embassy_rp::init(Default::default());
+
+ // Setup pio state machine for i2s output
+ let mut pio = Pio::new(p.PIO0, Irqs);
+
+ #[rustfmt::skip]
+ let pio_program = pio_proc::pio_asm!(
+ ".side_set 2",
+ " set x, 14 side 0b01", // side 0bWB - W = Word Clock, B = Bit Clock
+ "left_data:",
+ " out pins, 1 side 0b00",
+ " jmp x-- left_data side 0b01",
+ " out pins 1 side 0b10",
+ " set x, 14 side 0b11",
+ "right_data:",
+ " out pins 1 side 0b10",
+ " jmp x-- right_data side 0b11",
+ " out pins 1 side 0b00",
+ );
+
+ let bit_clock_pin = p.PIN_18;
+ let left_right_clock_pin = p.PIN_19;
+ let data_pin = p.PIN_20;
+
+ let data_pin = pio.common.make_pio_pin(data_pin);
+ let bit_clock_pin = pio.common.make_pio_pin(bit_clock_pin);
+ let left_right_clock_pin = pio.common.make_pio_pin(left_right_clock_pin);
+
+ let cfg = {
+ let mut cfg = Config::default();
+ cfg.use_program(
+ &pio.common.load_program(&pio_program.program),
+ &[&bit_clock_pin, &left_right_clock_pin],
+ );
+ cfg.set_out_pins(&[&data_pin]);
+ const BIT_DEPTH: u32 = 16;
+ const CHANNELS: u32 = 2;
+ let clock_frequency = SAMPLE_RATE * BIT_DEPTH * CHANNELS;
+ cfg.clock_divider = (125_000_000. / clock_frequency as f64 / 2.).to_fixed();
+ cfg.shift_out = ShiftConfig {
+ threshold: 32,
+ direction: ShiftDirection::Left,
+ auto_fill: true,
+ };
+ // join fifos to have twice the time to start the next dma transfer
+ cfg.fifo_join = FifoJoin::TxOnly;
+ cfg
+ };
+ pio.sm0.set_config(&cfg);
+ pio.sm0.set_pin_dirs(
+ embassy_rp::pio::Direction::Out,
+ &[&data_pin, &left_right_clock_pin, &bit_clock_pin],
+ );
+
+ // create two audio buffers (back and front) which will take turns being
+ // filled with new audio data and being sent to the pio fifo using dma
+ const BUFFER_SIZE: usize = 960;
+ static DMA_BUFFER: StaticCell<[u32; BUFFER_SIZE * 2]> = StaticCell::new();
+ let dma_buffer = DMA_BUFFER.init_with(|| [0u32; BUFFER_SIZE * 2]);
+ let (mut back_buffer, mut front_buffer) = dma_buffer.split_at_mut(BUFFER_SIZE);
+
+ // start pio state machine
+ pio.sm0.set_enable(true);
+ let tx = pio.sm0.tx();
+ let mut dma_ref = p.DMA_CH0.into_ref();
+
+ let mut fade_value: i32 = 0;
+ let mut phase: i32 = 0;
+
+ loop {
+ // trigger transfer of front buffer data to the pio fifo
+ // but don't await the returned future, yet
+ let dma_future = tx.dma_push(dma_ref.reborrow(), front_buffer);
+
+ // fade in audio when bootsel is pressed
+ let fade_target = if p.BOOTSEL.is_pressed() { i32::MAX } else { 0 };
+
+ // fill back buffer with fresh audio samples before awaiting the dma future
+ for s in back_buffer.iter_mut() {
+ // exponential approach of fade_value => fade_target
+ fade_value += (fade_target - fade_value) >> 14;
+ // generate triangle wave with amplitude and frequency based on fade value
+ phase = (phase + (fade_value >> 22)) & 0xffff;
+ let triangle_sample = (phase as i16 as i32).abs() - 16384;
+ let sample = (triangle_sample * (fade_value >> 15)) >> 16;
+ // duplicate mono sample into lower and upper half of dma word
+ *s = (sample as u16 as u32) * 0x10001;
+ }
+
+ // now await the dma future. once the dma finishes, the next buffer needs to be queued
+ // within DMA_DEPTH / SAMPLE_RATE = 8 / 48000 seconds = 166us
+ dma_future.await;
+ mem::swap(&mut back_buffer, &mut front_buffer);
+ }
+}
+
From 7931fcfb3d3211b9c7e46b43cebe48c433893b15 Mon Sep 17 00:00:00 2001
From: Dennis Ranke <dennis.ranke@gmail.com>
Date: Sat, 20 Jan 2024 16:35:09 +0100
Subject: [PATCH 040/392] fix wrong formatting due to not using nightly rustfmt
---
examples/rp/src/bin/pio_i2s.rs | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/examples/rp/src/bin/pio_i2s.rs b/examples/rp/src/bin/pio_i2s.rs
index 66802c8b7..cf60e5b30 100644
--- a/examples/rp/src/bin/pio_i2s.rs
+++ b/examples/rp/src/bin/pio_i2s.rs
@@ -12,17 +12,13 @@
use core::mem;
-use defmt_rtt as _;
use embassy_executor::Spawner;
-use embassy_rp::{
- bind_interrupts,
- peripherals::PIO0,
- pio::{Config, FifoJoin, InterruptHandler, Pio, ShiftConfig, ShiftDirection},
- Peripheral,
-};
+use embassy_rp::peripherals::PIO0;
+use embassy_rp::pio::{Config, FifoJoin, InterruptHandler, Pio, ShiftConfig, ShiftDirection};
+use embassy_rp::{bind_interrupts, Peripheral};
use fixed::traits::ToFixed;
-use panic_probe as _;
use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
PIO0_IRQ_0 => InterruptHandler<PIO0>;
@@ -115,7 +111,7 @@ async fn main(_spawner: Spawner) {
fade_value += (fade_target - fade_value) >> 14;
// generate triangle wave with amplitude and frequency based on fade value
phase = (phase + (fade_value >> 22)) & 0xffff;
- let triangle_sample = (phase as i16 as i32).abs() - 16384;
+ let triangle_sample = (phase as i16 as i32).abs() - 16384;
let sample = (triangle_sample * (fade_value >> 15)) >> 16;
// duplicate mono sample into lower and upper half of dma word
*s = (sample as u16 as u32) * 0x10001;
@@ -127,4 +123,3 @@ async fn main(_spawner: Spawner) {
mem::swap(&mut back_buffer, &mut front_buffer);
}
}
-
From 9f76dbb93b4ab5efc8a0d51b4507ab7eb144fcd9 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 22 Jan 2024 21:29:25 +0100
Subject: [PATCH 041/392] Remove nightly-only flags from cargo configs.
---
examples/boot/.cargo/config.toml | 4 ++--
examples/boot/application/rp/.cargo/config.toml | 4 ++--
examples/boot/bootloader/nrf/.cargo/config.toml | 6 +++---
tests/rp/.cargo/config.toml | 2 +-
tests/stm32/.cargo/config.toml | 8 ++++----
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/examples/boot/.cargo/config.toml b/examples/boot/.cargo/config.toml
index de3a814f7..be1b73e45 100644
--- a/examples/boot/.cargo/config.toml
+++ b/examples/boot/.cargo/config.toml
@@ -1,6 +1,6 @@
[unstable]
-build-std = ["core"]
-build-std-features = ["panic_immediate_abort"]
+#build-std = ["core"]
+#build-std-features = ["panic_immediate_abort"]
[build]
target = "thumbv7em-none-eabi"
diff --git a/examples/boot/application/rp/.cargo/config.toml b/examples/boot/application/rp/.cargo/config.toml
index cd8d1ef02..22ab3a5c1 100644
--- a/examples/boot/application/rp/.cargo/config.toml
+++ b/examples/boot/application/rp/.cargo/config.toml
@@ -1,6 +1,6 @@
[unstable]
-build-std = ["core"]
-build-std-features = ["panic_immediate_abort"]
+#build-std = ["core"]
+#build-std-features = ["panic_immediate_abort"]
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
runner = "probe-rs run --chip RP2040"
diff --git a/examples/boot/bootloader/nrf/.cargo/config.toml b/examples/boot/bootloader/nrf/.cargo/config.toml
index c292846aa..58acd1a49 100644
--- a/examples/boot/bootloader/nrf/.cargo/config.toml
+++ b/examples/boot/bootloader/nrf/.cargo/config.toml
@@ -1,6 +1,6 @@
[unstable]
-build-std = ["core"]
-build-std-features = ["panic_immediate_abort"]
+#build-std = ["core"]
+#build-std-features = ["panic_immediate_abort"]
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
#runner = "./fruitrunner"
@@ -8,7 +8,7 @@ runner = "probe-rs run --chip nrf52840_xxAA"
rustflags = [
# Code-size optimizations.
- "-Z", "trap-unreachable=no",
+ #"-Z", "trap-unreachable=no",
#"-C", "no-vectorize-loops",
"-C", "force-frame-pointers=yes",
]
diff --git a/tests/rp/.cargo/config.toml b/tests/rp/.cargo/config.toml
index 40b5d7000..de7bb0e56 100644
--- a/tests/rp/.cargo/config.toml
+++ b/tests/rp/.cargo/config.toml
@@ -10,7 +10,7 @@ runner = "teleprobe client run"
rustflags = [
# Code-size optimizations.
- "-Z", "trap-unreachable=no",
+ #"-Z", "trap-unreachable=no",
"-C", "inline-threshold=5",
"-C", "no-vectorize-loops",
]
diff --git a/tests/stm32/.cargo/config.toml b/tests/stm32/.cargo/config.toml
index 2e3f055d4..8e32b4cee 100644
--- a/tests/stm32/.cargo/config.toml
+++ b/tests/stm32/.cargo/config.toml
@@ -1,6 +1,6 @@
[unstable]
-build-std = ["core"]
-build-std-features = ["panic_immediate_abort"]
+#build-std = ["core"]
+#build-std-features = ["panic_immediate_abort"]
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
runner = "teleprobe client run"
@@ -8,7 +8,7 @@ runner = "teleprobe client run"
rustflags = [
# Code-size optimizations.
- "-Z", "trap-unreachable=no",
+ #"-Z", "trap-unreachable=no",
"-C", "inline-threshold=5",
"-C", "no-vectorize-loops",
]
@@ -20,4 +20,4 @@ target = "thumbv6m-none-eabi"
#target = "thumbv8m.main-none-eabihf"
[env]
-DEFMT_LOG = "trace,embassy_hal_internal=debug,embassy_net_esp_hosted=debug,smoltcp=info"
\ No newline at end of file
+DEFMT_LOG = "trace,embassy_hal_internal=debug,embassy_net_esp_hosted=debug,smoltcp=info"
From 3387ee7238f1c9c4eeccb732ba543cbe38ab7ccd Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 22 Jan 2024 20:12:36 +0100
Subject: [PATCH 042/392] stm32/gpio: remove generics.
---
.../layer-by-layer/blinky-async/src/main.rs | 4 +-
.../layer-by-layer/blinky-irq/src/main.rs | 13 +-
embassy-stm32/src/exti.rs | 45 +++---
embassy-stm32/src/gpio.rs | 141 ++++++------------
.../boot/application/stm32f3/src/bin/a.rs | 5 +-
.../boot/application/stm32f7/src/bin/a.rs | 5 +-
.../boot/application/stm32h7/src/bin/a.rs | 5 +-
.../boot/application/stm32l0/src/bin/a.rs | 5 +-
.../boot/application/stm32l1/src/bin/a.rs | 5 +-
.../boot/application/stm32l4/src/bin/a.rs | 5 +-
.../boot/application/stm32wl/src/bin/a.rs | 5 +-
examples/stm32c0/src/bin/button_exti.rs | 5 +-
.../src/bin/button_controlled_blink.rs | 5 +-
examples/stm32f0/src/bin/button_exti.rs | 5 +-
examples/stm32f3/src/bin/button_events.rs | 28 ++--
examples/stm32f3/src/bin/button_exti.rs | 5 +-
examples/stm32f4/src/bin/button_exti.rs | 5 +-
examples/stm32f7/src/bin/button_exti.rs | 5 +-
examples/stm32g0/src/bin/button_exti.rs | 5 +-
examples/stm32g4/src/bin/button_exti.rs | 5 +-
examples/stm32h5/src/bin/button_exti.rs | 5 +-
examples/stm32h7/src/bin/button_exti.rs | 5 +-
examples/stm32l0/src/bin/button_exti.rs | 5 +-
examples/stm32l4/src/bin/button_exti.rs | 5 +-
.../src/bin/spe_adin1110_http_server.rs | 13 +-
examples/stm32l5/src/bin/button_exti.rs | 5 +-
examples/stm32wb/src/bin/button_exti.rs | 5 +-
examples/stm32wba/src/bin/button_exti.rs | 5 +-
examples/stm32wl/src/bin/button_exti.rs | 5 +-
29 files changed, 144 insertions(+), 215 deletions(-)
diff --git a/docs/modules/ROOT/examples/layer-by-layer/blinky-async/src/main.rs b/docs/modules/ROOT/examples/layer-by-layer/blinky-async/src/main.rs
index e6753be28..004602816 100644
--- a/docs/modules/ROOT/examples/layer-by-layer/blinky-async/src/main.rs
+++ b/docs/modules/ROOT/examples/layer-by-layer/blinky-async/src/main.rs
@@ -3,14 +3,14 @@
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
let mut led = Output::new(p.PB14, Level::Low, Speed::VeryHigh);
- let mut button = ExtiInput::new(Input::new(p.PC13, Pull::Up), p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
loop {
button.wait_for_any_edge().await;
diff --git a/docs/modules/ROOT/examples/layer-by-layer/blinky-irq/src/main.rs b/docs/modules/ROOT/examples/layer-by-layer/blinky-irq/src/main.rs
index aecba0755..743c9d99b 100644
--- a/docs/modules/ROOT/examples/layer-by-layer/blinky-irq/src/main.rs
+++ b/docs/modules/ROOT/examples/layer-by-layer/blinky-irq/src/main.rs
@@ -6,13 +6,12 @@ use core::cell::RefCell;
use cortex_m::interrupt::Mutex;
use cortex_m::peripheral::NVIC;
use cortex_m_rt::entry;
-use embassy_stm32::gpio::{Input, Level, Output, Pin, Pull, Speed};
-use embassy_stm32::peripherals::{PB14, PC13};
+use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
use embassy_stm32::{interrupt, pac};
use {defmt_rtt as _, panic_probe as _};
-static BUTTON: Mutex<RefCell<Option<Input<'static, PC13>>>> = Mutex::new(RefCell::new(None));
-static LED: Mutex<RefCell<Option<Output<'static, PB14>>>> = Mutex::new(RefCell::new(None));
+static BUTTON: Mutex<RefCell<Option<Input<'static>>>> = Mutex::new(RefCell::new(None));
+static LED: Mutex<RefCell<Option<Output<'static>>>> = Mutex::new(RefCell::new(None));
#[entry]
fn main() -> ! {
@@ -62,14 +61,14 @@ fn EXTI15_10() {
const PORT: u8 = 2;
const PIN: usize = 13;
-fn check_interrupt<P: Pin>(_pin: &mut Input<'static, P>) -> bool {
+fn check_interrupt(_pin: &mut Input<'static>) -> bool {
let exti = pac::EXTI;
let pin = PIN;
let lines = exti.pr(0).read();
lines.line(pin)
}
-fn clear_interrupt<P: Pin>(_pin: &mut Input<'static, P>) {
+fn clear_interrupt(_pin: &mut Input<'static>) {
let exti = pac::EXTI;
let pin = PIN;
let mut lines = exti.pr(0).read();
@@ -77,7 +76,7 @@ fn clear_interrupt<P: Pin>(_pin: &mut Input<'static, P>) {
exti.pr(0).write_value(lines);
}
-fn enable_interrupt<P: Pin>(_pin: &mut Input<'static, P>) {
+fn enable_interrupt(_pin: &mut Input<'static>) {
cortex_m::interrupt::free(|_| {
let rcc = pac::RCC;
rcc.apb2enr().modify(|w| w.set_syscfgen(true));
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 2821435ef..bd10ba158 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -5,10 +5,10 @@ use core::marker::PhantomData;
use core::pin::Pin;
use core::task::{Context, Poll};
-use embassy_hal_internal::impl_peripheral;
+use embassy_hal_internal::{impl_peripheral, into_ref};
use embassy_sync::waitqueue::AtomicWaker;
-use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin};
+use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, Pull};
use crate::pac::exti::regs::Lines;
use crate::pac::EXTI;
use crate::{interrupt, pac, peripherals, Peripheral};
@@ -93,16 +93,27 @@ impl Iterator for BitIter {
/// EXTI channel, which is a limited resource.
///
/// Pins PA5, PB5, PC5... all use EXTI channel 5, so you can't use EXTI on, say, PA5 and PC5 at the same time.
-pub struct ExtiInput<'d, T: GpioPin> {
- pin: Input<'d, T>,
+pub struct ExtiInput<'d> {
+ pin: Input<'d>,
}
-impl<'d, T: GpioPin> Unpin for ExtiInput<'d, T> {}
+impl<'d> Unpin for ExtiInput<'d> {}
-impl<'d, T: GpioPin> ExtiInput<'d, T> {
+impl<'d> ExtiInput<'d> {
/// Create an EXTI input.
- pub fn new(pin: Input<'d, T>, _ch: impl Peripheral<P = T::ExtiChannel> + 'd) -> Self {
- Self { pin }
+ pub fn new<T: GpioPin>(
+ pin: impl Peripheral<P = T> + 'd,
+ ch: impl Peripheral<P = T::ExtiChannel> + 'd,
+ pull: Pull,
+ ) -> Self {
+ into_ref!(pin, ch);
+
+ // Needed if using AnyPin+AnyChannel.
+ assert_eq!(pin.pin(), ch.number());
+
+ Self {
+ pin: Input::new(pin, pull),
+ }
}
/// Get whether the pin is high.
@@ -162,7 +173,7 @@ impl<'d, T: GpioPin> ExtiInput<'d, T> {
}
}
-impl<'d, T: GpioPin> embedded_hal_02::digital::v2::InputPin for ExtiInput<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::InputPin for ExtiInput<'d> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
@@ -174,11 +185,11 @@ impl<'d, T: GpioPin> embedded_hal_02::digital::v2::InputPin for ExtiInput<'d, T>
}
}
-impl<'d, T: GpioPin> embedded_hal_1::digital::ErrorType for ExtiInput<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for ExtiInput<'d> {
type Error = Infallible;
}
-impl<'d, T: GpioPin> embedded_hal_1::digital::InputPin for ExtiInput<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for ExtiInput<'d> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
}
@@ -188,7 +199,7 @@ impl<'d, T: GpioPin> embedded_hal_1::digital::InputPin for ExtiInput<'d, T> {
}
}
-impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for ExtiInput<'d, T> {
+impl<'d> embedded_hal_async::digital::Wait for ExtiInput<'d> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
self.wait_for_high().await;
Ok(())
@@ -326,7 +337,7 @@ pub(crate) mod sealed {
/// EXTI channel trait.
pub trait Channel: sealed::Channel + Sized {
/// Get the EXTI channel number.
- fn number(&self) -> usize;
+ fn number(&self) -> u8;
/// Type-erase (degrade) this channel into an `AnyChannel`.
///
@@ -350,8 +361,8 @@ pub struct AnyChannel {
impl_peripheral!(AnyChannel);
impl sealed::Channel for AnyChannel {}
impl Channel for AnyChannel {
- fn number(&self) -> usize {
- self.number as usize
+ fn number(&self) -> u8 {
+ self.number
}
}
@@ -359,8 +370,8 @@ macro_rules! impl_exti {
($type:ident, $number:expr) => {
impl sealed::Channel for peripherals::$type {}
impl Channel for peripherals::$type {
- fn number(&self) -> usize {
- $number as usize
+ fn number(&self) -> u8 {
+ $number
}
}
};
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 7eb70496f..1051a13c8 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -6,6 +6,7 @@ use core::convert::Infallible;
use critical_section::CriticalSection;
use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
+use self::sealed::Pin as _;
use crate::pac::gpio::{self, vals};
use crate::{pac, peripherals, Peripheral};
@@ -14,41 +15,21 @@ use crate::{pac, peripherals, Peripheral};
/// This pin can either be a disconnected, input, or output pin, or both. The level register bit will remain
/// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
/// mode.
-pub struct Flex<'d, T: Pin> {
- pub(crate) pin: PeripheralRef<'d, T>,
+pub struct Flex<'d> {
+ pub(crate) pin: PeripheralRef<'d, AnyPin>,
}
-impl<'d, T: Pin> Flex<'d, T> {
+impl<'d> Flex<'d> {
/// Wrap the pin in a `Flex`.
///
/// The pin remains disconnected. The initial output level is unspecified, but can be changed
/// before the pin is put into output mode.
///
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd) -> Self {
into_ref!(pin);
// Pin will be in disconnected state.
- Self { pin }
- }
-
- /// Type-erase (degrade) this pin into an `AnyPin`.
- ///
- /// This converts pin singletons (`PA5`, `PB6`, ...), which
- /// are all different types, into the same type. It is useful for
- /// creating arrays of pins, or avoiding generics.
- #[inline]
- pub fn degrade(self) -> Flex<'d, AnyPin> {
- // Safety: We are about to drop the other copy of this pin, so
- // this clone is safe.
- let pin = unsafe { self.pin.clone_unchecked() };
-
- // We don't want to run the destructor here, because that would
- // deconfigure the pin.
- core::mem::forget(self);
-
- Flex {
- pin: pin.map_into::<AnyPin>(),
- }
+ Self { pin: pin.map_into() }
}
/// Put the pin into input mode.
@@ -218,7 +199,7 @@ impl<'d, T: Pin> Flex<'d, T> {
}
}
-impl<'d, T: Pin> Drop for Flex<'d, T> {
+impl<'d> Drop for Flex<'d> {
#[inline]
fn drop(&mut self) {
critical_section::with(|_| {
@@ -309,31 +290,19 @@ impl From<Speed> for vals::Ospeedr {
}
/// GPIO input driver.
-pub struct Input<'d, T: Pin> {
- pub(crate) pin: Flex<'d, T>,
+pub struct Input<'d> {
+ pub(crate) pin: Flex<'d>,
}
-impl<'d, T: Pin> Input<'d, T> {
+impl<'d> Input<'d> {
/// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, pull: Pull) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
pin.set_as_input(pull);
Self { pin }
}
- /// Type-erase (degrade) this pin into an `AnyPin`.
- ///
- /// This converts pin singletons (`PA5`, `PB6`, ...), which
- /// are all different types, into the same type. It is useful for
- /// creating arrays of pins, or avoiding generics.
- #[inline]
- pub fn degrade(self) -> Input<'d, AnyPin> {
- Input {
- pin: self.pin.degrade(),
- }
- }
-
/// Get whether the pin input level is high.
#[inline]
pub fn is_high(&self) -> bool {
@@ -386,14 +355,14 @@ impl From<Level> for bool {
/// Note that pins will **return to their floating state** when `Output` is dropped.
/// If pins should retain their state indefinitely, either keep ownership of the
/// `Output`, or pass it to [`core::mem::forget`].
-pub struct Output<'d, T: Pin> {
- pub(crate) pin: Flex<'d, T>,
+pub struct Output<'d> {
+ pub(crate) pin: Flex<'d>,
}
-impl<'d, T: Pin> Output<'d, T> {
+impl<'d> Output<'d> {
/// Create GPIO output driver for a [Pin] with the provided [Level] and [Speed] configuration.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level, speed: Speed) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed) -> Self {
let mut pin = Flex::new(pin);
match initial_output {
Level::High => pin.set_high(),
@@ -403,18 +372,6 @@ impl<'d, T: Pin> Output<'d, T> {
Self { pin }
}
- /// Type-erase (degrade) this pin into an `AnyPin`.
- ///
- /// This converts pin singletons (`PA5`, `PB6`, ...), which
- /// are all different types, into the same type. It is useful for
- /// creating arrays of pins, or avoiding generics.
- #[inline]
- pub fn degrade(self) -> Output<'d, AnyPin> {
- Output {
- pin: self.pin.degrade(),
- }
- }
-
/// Set the output as high.
#[inline]
pub fn set_high(&mut self) {
@@ -463,14 +420,14 @@ impl<'d, T: Pin> Output<'d, T> {
/// Note that pins will **return to their floating state** when `OutputOpenDrain` is dropped.
/// If pins should retain their state indefinitely, either keep ownership of the
/// `OutputOpenDrain`, or pass it to [`core::mem::forget`].
-pub struct OutputOpenDrain<'d, T: Pin> {
- pub(crate) pin: Flex<'d, T>,
+pub struct OutputOpenDrain<'d> {
+ pub(crate) pin: Flex<'d>,
}
-impl<'d, T: Pin> OutputOpenDrain<'d, T> {
+impl<'d> OutputOpenDrain<'d> {
/// Create a new GPIO open drain output driver for a [Pin] with the provided [Level] and [Speed], [Pull] configuration.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level, speed: Speed, pull: Pull) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
match initial_output {
@@ -482,18 +439,6 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
Self { pin }
}
- /// Type-erase (degrade) this pin into an `AnyPin`.
- ///
- /// This converts pin singletons (`PA5`, `PB6`, ...), which
- /// are all different types, into the same type. It is useful for
- /// creating arrays of pins, or avoiding generics.
- #[inline]
- pub fn degrade(self) -> Output<'d, AnyPin> {
- Output {
- pin: self.pin.degrade(),
- }
- }
-
/// Get whether the pin input level is high.
#[inline]
pub fn is_high(&self) -> bool {
@@ -836,7 +781,7 @@ pub(crate) unsafe fn init(_cs: CriticalSection) {
});
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Input<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::InputPin for Input<'d> {
type Error = Infallible;
#[inline]
@@ -850,7 +795,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Input<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Output<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::OutputPin for Output<'d> {
type Error = Infallible;
#[inline]
@@ -866,7 +811,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Output<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
@@ -879,7 +824,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d,
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -888,7 +833,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::OutputPin for OutputOpenDrain<'d> {
type Error = Infallible;
#[inline]
@@ -904,7 +849,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for OutputOpenDrain<'d,
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for OutputOpenDrain<'d> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
@@ -917,7 +862,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for OutputOpenD
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for OutputOpenDrain<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -926,7 +871,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for OutputOpe
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Flex<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::InputPin for Flex<'d> {
type Error = Infallible;
#[inline]
@@ -940,7 +885,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::OutputPin for Flex<'d> {
type Error = Infallible;
#[inline]
@@ -956,7 +901,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d> {
#[inline]
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
@@ -969,7 +914,7 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d, T>
}
}
-impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -978,11 +923,11 @@ impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d,
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Input<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Input<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for Input<'d> {
#[inline]
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
@@ -994,11 +939,11 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Output<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for Output<'d> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
@@ -1010,7 +955,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for Output<'d> {
#[inline]
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
@@ -1023,11 +968,11 @@ impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for OutputOpenDrain<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d> {
#[inline]
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
@@ -1039,7 +984,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
@@ -1051,7 +996,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<'d> {
#[inline]
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
@@ -1064,7 +1009,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for Flex<'d> {
#[inline]
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
@@ -1076,7 +1021,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for Flex<'d> {
#[inline]
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
@@ -1088,11 +1033,11 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Flex<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for Flex<'d> {
#[inline]
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
diff --git a/examples/boot/application/stm32f3/src/bin/a.rs b/examples/boot/application/stm32f3/src/bin/a.rs
index 96ae5c47b..3f9ebe5c8 100644
--- a/examples/boot/application/stm32f3/src/bin/a.rs
+++ b/examples/boot/application/stm32f3/src/bin/a.rs
@@ -8,7 +8,7 @@ use embassy_embedded_hal::adapter::BlockingAsync;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::flash::{Flash, WRITE_SIZE};
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::mutex::Mutex;
use panic_reset as _;
@@ -23,8 +23,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(BlockingAsync::new(flash));
- let button = Input::new(p.PC13, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
let mut led = Output::new(p.PA5, Level::Low, Speed::Low);
led.set_high();
diff --git a/examples/boot/application/stm32f7/src/bin/a.rs b/examples/boot/application/stm32f7/src/bin/a.rs
index a6107386a..c57c29263 100644
--- a/examples/boot/application/stm32f7/src/bin/a.rs
+++ b/examples/boot/application/stm32f7/src/bin/a.rs
@@ -9,7 +9,7 @@ use embassy_boot_stm32::{AlignedBuffer, BlockingFirmwareUpdater, FirmwareUpdater
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::flash::{Flash, WRITE_SIZE};
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::blocking_mutex::Mutex;
use embedded_storage::nor_flash::NorFlash;
use panic_reset as _;
@@ -25,8 +25,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(RefCell::new(flash));
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
let mut led = Output::new(p.PB7, Level::Low, Speed::Low);
led.set_high();
diff --git a/examples/boot/application/stm32h7/src/bin/a.rs b/examples/boot/application/stm32h7/src/bin/a.rs
index b73506cf3..a00d17408 100644
--- a/examples/boot/application/stm32h7/src/bin/a.rs
+++ b/examples/boot/application/stm32h7/src/bin/a.rs
@@ -9,7 +9,7 @@ use embassy_boot_stm32::{AlignedBuffer, BlockingFirmwareUpdater, FirmwareUpdater
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::flash::{Flash, WRITE_SIZE};
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::blocking_mutex::Mutex;
use embedded_storage::nor_flash::NorFlash;
use panic_reset as _;
@@ -25,8 +25,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(RefCell::new(flash));
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
let mut led = Output::new(p.PB14, Level::Low, Speed::Low);
led.set_high();
diff --git a/examples/boot/application/stm32l0/src/bin/a.rs b/examples/boot/application/stm32l0/src/bin/a.rs
index 02f74bdef..dbec49d44 100644
--- a/examples/boot/application/stm32l0/src/bin/a.rs
+++ b/examples/boot/application/stm32l0/src/bin/a.rs
@@ -8,7 +8,7 @@ use embassy_embedded_hal::adapter::BlockingAsync;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::flash::{Flash, WRITE_SIZE};
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::mutex::Mutex;
use embassy_time::Timer;
use panic_reset as _;
@@ -24,8 +24,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(BlockingAsync::new(flash));
- let button = Input::new(p.PB2, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI2);
+ let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up);
let mut led = Output::new(p.PB5, Level::Low, Speed::Low);
diff --git a/examples/boot/application/stm32l1/src/bin/a.rs b/examples/boot/application/stm32l1/src/bin/a.rs
index 02f74bdef..dbec49d44 100644
--- a/examples/boot/application/stm32l1/src/bin/a.rs
+++ b/examples/boot/application/stm32l1/src/bin/a.rs
@@ -8,7 +8,7 @@ use embassy_embedded_hal::adapter::BlockingAsync;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::flash::{Flash, WRITE_SIZE};
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::mutex::Mutex;
use embassy_time::Timer;
use panic_reset as _;
@@ -24,8 +24,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(BlockingAsync::new(flash));
- let button = Input::new(p.PB2, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI2);
+ let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up);
let mut led = Output::new(p.PB5, Level::Low, Speed::Low);
diff --git a/examples/boot/application/stm32l4/src/bin/a.rs b/examples/boot/application/stm32l4/src/bin/a.rs
index 892446968..e946c3cdf 100644
--- a/examples/boot/application/stm32l4/src/bin/a.rs
+++ b/examples/boot/application/stm32l4/src/bin/a.rs
@@ -8,7 +8,7 @@ use embassy_embedded_hal::adapter::BlockingAsync;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::flash::{Flash, WRITE_SIZE};
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::mutex::Mutex;
use panic_reset as _;
@@ -23,8 +23,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(BlockingAsync::new(flash));
- let button = Input::new(p.PC13, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
let mut led = Output::new(p.PB14, Level::Low, Speed::Low);
led.set_high();
diff --git a/examples/boot/application/stm32wl/src/bin/a.rs b/examples/boot/application/stm32wl/src/bin/a.rs
index d9665e6ee..b582d8b25 100644
--- a/examples/boot/application/stm32wl/src/bin/a.rs
+++ b/examples/boot/application/stm32wl/src/bin/a.rs
@@ -8,7 +8,7 @@ use embassy_embedded_hal::adapter::BlockingAsync;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::flash::{Flash, WRITE_SIZE};
-use embassy_stm32::gpio::{Input, Level, Output, Pull, Speed};
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::mutex::Mutex;
use panic_reset as _;
@@ -23,8 +23,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(BlockingAsync::new(flash));
- let button = Input::new(p.PA0, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI0);
+ let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up);
let mut led = Output::new(p.PB9, Level::Low, Speed::Low);
led.set_high();
diff --git a/examples/stm32c0/src/bin/button_exti.rs b/examples/stm32c0/src/bin/button_exti.rs
index 1e970fdd6..34a08bbc6 100644
--- a/examples/stm32c0/src/bin/button_exti.rs
+++ b/examples/stm32c0/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
info!("Press the USER button...");
diff --git a/examples/stm32f0/src/bin/button_controlled_blink.rs b/examples/stm32f0/src/bin/button_controlled_blink.rs
index 360d153c3..4465483d9 100644
--- a/examples/stm32f0/src/bin/button_controlled_blink.rs
+++ b/examples/stm32f0/src/bin/button_controlled_blink.rs
@@ -8,7 +8,7 @@ use core::sync::atomic::{AtomicU32, Ordering};
use defmt::info;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{AnyPin, Input, Level, Output, Pin, Pull, Speed};
+use embassy_stm32::gpio::{AnyPin, Level, Output, Pin, Pull, Speed};
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
@@ -36,8 +36,7 @@ async fn main(spawner: Spawner) {
// Configure the button pin and obtain handler.
// On the Nucleo F091RC there is a button connected to pin PC13.
- let button = Input::new(p.PC13, Pull::None);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::None);
// Create and initialize a delay variable to manage delay loop
let mut del_var = 2000;
diff --git a/examples/stm32f0/src/bin/button_exti.rs b/examples/stm32f0/src/bin/button_exti.rs
index ce17c1a48..fd615a215 100644
--- a/examples/stm32f0/src/bin/button_exti.rs
+++ b/examples/stm32f0/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -13,8 +13,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
// Configure the button pin and obtain handler.
// On the Nucleo F091RC there is a button connected to pin PC13.
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
info!("Press the USER button...");
loop {
diff --git a/examples/stm32f3/src/bin/button_events.rs b/examples/stm32f3/src/bin/button_events.rs
index 2f7da4ef5..f5ed5d2c9 100644
--- a/examples/stm32f3/src/bin/button_events.rs
+++ b/examples/stm32f3/src/bin/button_events.rs
@@ -12,21 +12,20 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{AnyPin, Input, Level, Output, Pin, Pull, Speed};
-use embassy_stm32::peripherals::PA0;
+use embassy_stm32::gpio::{Level, Output, Pull, Speed};
use embassy_sync::blocking_mutex::raw::ThreadModeRawMutex;
use embassy_sync::channel::Channel;
use embassy_time::{with_timeout, Duration, Timer};
use {defmt_rtt as _, panic_probe as _};
struct Leds<'a> {
- leds: [Output<'a, AnyPin>; 8],
+ leds: [Output<'a>; 8],
direction: i8,
current_led: usize,
}
impl<'a> Leds<'a> {
- fn new(pins: [Output<'a, AnyPin>; 8]) -> Self {
+ fn new(pins: [Output<'a>; 8]) -> Self {
Self {
leds: pins,
direction: 1,
@@ -100,18 +99,17 @@ static CHANNEL: Channel<ThreadModeRawMutex, ButtonEvent, 4> = Channel::new();
#[embassy_executor::main]
async fn main(spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
- let button = Input::new(p.PA0, Pull::Down);
- let button = ExtiInput::new(button, p.EXTI0);
+ let button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Down);
info!("Press the USER button...");
let leds = [
- Output::new(p.PE9.degrade(), Level::Low, Speed::Low),
- Output::new(p.PE10.degrade(), Level::Low, Speed::Low),
- Output::new(p.PE11.degrade(), Level::Low, Speed::Low),
- Output::new(p.PE12.degrade(), Level::Low, Speed::Low),
- Output::new(p.PE13.degrade(), Level::Low, Speed::Low),
- Output::new(p.PE14.degrade(), Level::Low, Speed::Low),
- Output::new(p.PE15.degrade(), Level::Low, Speed::Low),
- Output::new(p.PE8.degrade(), Level::Low, Speed::Low),
+ Output::new(p.PE9, Level::Low, Speed::Low),
+ Output::new(p.PE10, Level::Low, Speed::Low),
+ Output::new(p.PE11, Level::Low, Speed::Low),
+ Output::new(p.PE12, Level::Low, Speed::Low),
+ Output::new(p.PE13, Level::Low, Speed::Low),
+ Output::new(p.PE14, Level::Low, Speed::Low),
+ Output::new(p.PE15, Level::Low, Speed::Low),
+ Output::new(p.PE8, Level::Low, Speed::Low),
];
let leds = Leds::new(leds);
@@ -127,7 +125,7 @@ async fn led_blinker(mut leds: Leds<'static>) {
}
#[embassy_executor::task]
-async fn button_waiter(mut button: ExtiInput<'static, PA0>) {
+async fn button_waiter(mut button: ExtiInput<'static>) {
const DOUBLE_CLICK_DELAY: u64 = 250;
const HOLD_DELAY: u64 = 1000;
diff --git a/examples/stm32f3/src/bin/button_exti.rs b/examples/stm32f3/src/bin/button_exti.rs
index 86ff68492..a55530e0e 100644
--- a/examples/stm32f3/src/bin/button_exti.rs
+++ b/examples/stm32f3/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PA0, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI0);
+ let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Down);
info!("Press the USER button...");
diff --git a/examples/stm32f4/src/bin/button_exti.rs b/examples/stm32f4/src/bin/button_exti.rs
index 67751187d..2a546dac5 100644
--- a/examples/stm32f4/src/bin/button_exti.rs
+++ b/examples/stm32f4/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
info!("Press the USER button...");
diff --git a/examples/stm32f7/src/bin/button_exti.rs b/examples/stm32f7/src/bin/button_exti.rs
index 67751187d..2a546dac5 100644
--- a/examples/stm32f7/src/bin/button_exti.rs
+++ b/examples/stm32f7/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
info!("Press the USER button...");
diff --git a/examples/stm32g0/src/bin/button_exti.rs b/examples/stm32g0/src/bin/button_exti.rs
index 1e970fdd6..34a08bbc6 100644
--- a/examples/stm32g0/src/bin/button_exti.rs
+++ b/examples/stm32g0/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
info!("Press the USER button...");
diff --git a/examples/stm32g4/src/bin/button_exti.rs b/examples/stm32g4/src/bin/button_exti.rs
index 67751187d..2a546dac5 100644
--- a/examples/stm32g4/src/bin/button_exti.rs
+++ b/examples/stm32g4/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
info!("Press the USER button...");
diff --git a/examples/stm32h5/src/bin/button_exti.rs b/examples/stm32h5/src/bin/button_exti.rs
index 67751187d..2a546dac5 100644
--- a/examples/stm32h5/src/bin/button_exti.rs
+++ b/examples/stm32h5/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
info!("Press the USER button...");
diff --git a/examples/stm32h7/src/bin/button_exti.rs b/examples/stm32h7/src/bin/button_exti.rs
index 67751187d..2a546dac5 100644
--- a/examples/stm32h7/src/bin/button_exti.rs
+++ b/examples/stm32h7/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
info!("Press the USER button...");
diff --git a/examples/stm32l0/src/bin/button_exti.rs b/examples/stm32l0/src/bin/button_exti.rs
index f517fce04..4945da7ce 100644
--- a/examples/stm32l0/src/bin/button_exti.rs
+++ b/examples/stm32l0/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use embassy_stm32::Config;
use {defmt_rtt as _, panic_probe as _};
@@ -13,8 +13,7 @@ async fn main(_spawner: Spawner) {
let config = Config::default();
let p = embassy_stm32::init(config);
- let button = Input::new(p.PB2, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI2);
+ let mut button = ExtiInput::new(p.PB2, p.EXTI2, Pull::Up);
info!("Press the USER button...");
diff --git a/examples/stm32l4/src/bin/button_exti.rs b/examples/stm32l4/src/bin/button_exti.rs
index 1e970fdd6..34a08bbc6 100644
--- a/examples/stm32l4/src/bin/button_exti.rs
+++ b/examples/stm32l4/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
info!("Press the USER button...");
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 5b4cdfe5e..026a3a477 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -58,9 +58,9 @@ const IP_ADDRESS: Ipv4Cidr = Ipv4Cidr::new(Ipv4Address([192, 168, 1, 5]), 24);
const HTTP_LISTEN_PORT: u16 = 80;
pub type SpeSpi = Spi<'static, peripherals::SPI2, peripherals::DMA1_CH1, peripherals::DMA1_CH2>;
-pub type SpeSpiCs = ExclusiveDevice<SpeSpi, Output<'static, peripherals::PB12>, Delay>;
-pub type SpeInt = exti::ExtiInput<'static, peripherals::PB11>;
-pub type SpeRst = Output<'static, peripherals::PC7>;
+pub type SpeSpiCs = ExclusiveDevice<SpeSpi, Output<'static>, Delay>;
+pub type SpeInt = exti::ExtiInput<'static>;
+pub type SpeRst = Output<'static>;
pub type Adin1110T = ADIN1110<SpeSpiCs>;
pub type TempSensI2c = I2c<'static, peripherals::I2C3, peripherals::DMA1_CH6, peripherals::DMA1_CH7>;
@@ -134,8 +134,7 @@ async fn main(spawner: Spawner) {
let spe_cfg1 = Input::new(dp.PC9, Pull::None);
let _spe_ts_capt = Output::new(dp.PC6, Level::Low, Speed::Low);
- let spe_int = Input::new(dp.PB11, Pull::None);
- let spe_int = exti::ExtiInput::new(spe_int, dp.EXTI11);
+ let spe_int = exti::ExtiInput::new(dp.PB11, dp.EXTI11, Pull::None);
let spe_spi_cs_n = Output::new(dp.PB12, Level::High, Speed::High);
let spe_spi_sclk = dp.PB13;
@@ -298,7 +297,7 @@ async fn wait_for_config(stack: &'static Stack<Device<'static>>) -> embassy_net:
}
#[embassy_executor::task]
-async fn heartbeat_led(mut led: Output<'static, peripherals::PE6>) {
+async fn heartbeat_led(mut led: Output<'static>) {
let mut tmr = Ticker::every(Duration::from_hz(3));
loop {
led.toggle();
@@ -308,7 +307,7 @@ async fn heartbeat_led(mut led: Output<'static, peripherals::PE6>) {
// ADT7422
#[embassy_executor::task]
-async fn temp_task(temp_dev_i2c: TempSensI2c, mut led: Output<'static, peripherals::PG15>) -> ! {
+async fn temp_task(temp_dev_i2c: TempSensI2c, mut led: Output<'static>) -> ! {
let mut tmr = Ticker::every(Duration::from_hz(1));
let mut temp_sens = ADT7422::new(temp_dev_i2c, 0x48).unwrap();
diff --git a/examples/stm32l5/src/bin/button_exti.rs b/examples/stm32l5/src/bin/button_exti.rs
index 91d0ccc2e..e6639d22b 100644
--- a/examples/stm32l5/src/bin/button_exti.rs
+++ b/examples/stm32l5/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Down);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Down);
info!("Press the USER button...");
diff --git a/examples/stm32wb/src/bin/button_exti.rs b/examples/stm32wb/src/bin/button_exti.rs
index d34dde3e9..2871fd55f 100644
--- a/examples/stm32wb/src/bin/button_exti.rs
+++ b/examples/stm32wb/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC4, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI4);
+ let mut button = ExtiInput::new(p.PC4, p.EXTI4, Pull::Up);
info!("Press the USER button...");
diff --git a/examples/stm32wba/src/bin/button_exti.rs b/examples/stm32wba/src/bin/button_exti.rs
index 1e970fdd6..34a08bbc6 100644
--- a/examples/stm32wba/src/bin/button_exti.rs
+++ b/examples/stm32wba/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PC13, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI13);
+ let mut button = ExtiInput::new(p.PC13, p.EXTI13, Pull::Up);
info!("Press the USER button...");
diff --git a/examples/stm32wl/src/bin/button_exti.rs b/examples/stm32wl/src/bin/button_exti.rs
index e6ad4b80b..27d5330bd 100644
--- a/examples/stm32wl/src/bin/button_exti.rs
+++ b/examples/stm32wl/src/bin/button_exti.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
-use embassy_stm32::gpio::{Input, Pull};
+use embassy_stm32::gpio::Pull;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@@ -12,8 +12,7 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
- let button = Input::new(p.PA0, Pull::Up);
- let mut button = ExtiInput::new(button, p.EXTI0);
+ let mut button = ExtiInput::new(p.PA0, p.EXTI0, Pull::Up);
info!("Press the USER button...");
From 2bc5e9523d4373002487614ecfef1e3f0858fd66 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 22 Jan 2024 21:19:18 +0100
Subject: [PATCH 043/392] nrf/gpio: remove generics.
---
docs/modules/ROOT/examples/basic/src/main.rs | 3 +-
embassy-nrf/src/gpio.rs | 62 +++++++++----------
embassy-nrf/src/gpiote.rs | 53 +++++++++-------
.../nrf52840/src/bin/ethernet_enc28j60.rs | 12 +---
examples/nrf52840/src/bin/gpiote_port.rs | 12 ++--
examples/nrf52840/src/bin/usb_hid_keyboard.rs | 4 +-
examples/nrf52840/src/bin/wifi_esp_hosted.rs | 12 ++--
tests/nrf/src/bin/ethernet_enc28j60_perf.rs | 5 +-
tests/nrf/src/bin/wifi_esp_hosted_perf.rs | 12 ++--
9 files changed, 86 insertions(+), 89 deletions(-)
diff --git a/docs/modules/ROOT/examples/basic/src/main.rs b/docs/modules/ROOT/examples/basic/src/main.rs
index 2a4ee5968..4412712c8 100644
--- a/docs/modules/ROOT/examples/basic/src/main.rs
+++ b/docs/modules/ROOT/examples/basic/src/main.rs
@@ -4,12 +4,11 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_nrf::gpio::{Level, Output, OutputDrive};
-use embassy_nrf::peripherals::P0_13;
use embassy_time::{Duration, Timer};
use {defmt_rtt as _, panic_probe as _}; // global logger
#[embassy_executor::task]
-async fn blinker(mut led: Output<'static, P0_13>, interval: Duration) {
+async fn blinker(mut led: Output<'static>, interval: Duration) {
loop {
led.set_high();
Timer::after(interval).await;
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index eabf409dd..287811e61 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -36,14 +36,14 @@ pub enum Pull {
}
/// GPIO input driver.
-pub struct Input<'d, T: Pin> {
- pub(crate) pin: Flex<'d, T>,
+pub struct Input<'d> {
+ pub(crate) pin: Flex<'d>,
}
-impl<'d, T: Pin> Input<'d, T> {
+impl<'d> Input<'d> {
/// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, pull: Pull) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
pin.set_as_input(pull);
@@ -122,14 +122,14 @@ pub enum OutputDrive {
}
/// GPIO output driver.
-pub struct Output<'d, T: Pin> {
- pub(crate) pin: Flex<'d, T>,
+pub struct Output<'d> {
+ pub(crate) pin: Flex<'d>,
}
-impl<'d, T: Pin> Output<'d, T> {
+impl<'d> Output<'d> {
/// Create GPIO output driver for a [Pin] with the provided [Level] and [OutputDriver] configuration.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level, drive: OutputDrive) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, drive: OutputDrive) -> Self {
let mut pin = Flex::new(pin);
match initial_output {
Level::High => pin.set_high(),
@@ -209,20 +209,20 @@ fn convert_pull(pull: Pull) -> PULL_A {
/// This pin can either be a disconnected, input, or output pin, or both. The level register bit will remain
/// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
/// mode.
-pub struct Flex<'d, T: Pin> {
- pub(crate) pin: PeripheralRef<'d, T>,
+pub struct Flex<'d> {
+ pub(crate) pin: PeripheralRef<'d, AnyPin>,
}
-impl<'d, T: Pin> Flex<'d, T> {
+impl<'d> Flex<'d> {
/// Wrap the pin in a `Flex`.
///
/// The pin remains disconnected. The initial output level is unspecified, but can be changed
/// before the pin is put into output mode.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd) -> Self {
into_ref!(pin);
// Pin will be in disconnected state.
- Self { pin }
+ Self { pin: pin.map_into() }
}
/// Put the pin into input mode.
@@ -349,7 +349,7 @@ impl<'d, T: Pin> Flex<'d, T> {
}
}
-impl<'d, T: Pin> Drop for Flex<'d, T> {
+impl<'d> Drop for Flex<'d> {
fn drop(&mut self) {
self.pin.conf().reset();
}
@@ -510,7 +510,7 @@ macro_rules! impl_pin {
mod eh02 {
use super::*;
- impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Input<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::InputPin for Input<'d> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
@@ -522,7 +522,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Output<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::OutputPin for Output<'d> {
type Error = Infallible;
fn set_high(&mut self) -> Result<(), Self::Error> {
@@ -534,7 +534,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d> {
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
@@ -544,7 +544,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -556,7 +556,7 @@ mod eh02 {
/// Implement [`embedded_hal_02::digital::v2::InputPin`] for [`Flex`];
///
/// If the pin is not in input mode the result is unspecified.
- impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::InputPin for Flex<'d> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
@@ -568,7 +568,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::OutputPin for Flex<'d> {
type Error = Infallible;
fn set_high(&mut self) -> Result<(), Self::Error> {
@@ -580,7 +580,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d> {
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
@@ -590,7 +590,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -600,11 +600,11 @@ mod eh02 {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Input<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Input<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for Input<'d> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
}
@@ -614,11 +614,11 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Output<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for Output<'d> {
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
@@ -628,7 +628,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for Output<'d> {
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
}
@@ -638,14 +638,14 @@ impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Flex<'d> {
type Error = Infallible;
}
/// Implement [`InputPin`] for [`Flex`];
///
/// If the pin is not in input mode the result is unspecified.
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for Flex<'d> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
}
@@ -655,7 +655,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for Flex<'d> {
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
@@ -665,7 +665,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for Flex<'d> {
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
}
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index 8020b8dc2..a459446a2 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -156,12 +156,12 @@ impl Iterator for BitIter {
}
/// GPIOTE channel driver in input mode
-pub struct InputChannel<'d, C: Channel, T: GpioPin> {
- ch: PeripheralRef<'d, C>,
- pin: Input<'d, T>,
+pub struct InputChannel<'d> {
+ ch: PeripheralRef<'d, AnyChannel>,
+ pin: Input<'d>,
}
-impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
+impl<'d> Drop for InputChannel<'d> {
fn drop(&mut self) {
let g = regs();
let num = self.ch.number();
@@ -170,9 +170,9 @@ impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
}
}
-impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
+impl<'d> InputChannel<'d> {
/// Create a new GPIOTE input channel driver.
- pub fn new(ch: impl Peripheral<P = C> + 'd, pin: Input<'d, T>, polarity: InputChannelPolarity) -> Self {
+ pub fn new(ch: impl Peripheral<P = impl Channel> + 'd, pin: Input<'d>, polarity: InputChannelPolarity) -> Self {
into_ref!(ch);
let g = regs();
@@ -195,7 +195,7 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
g.events_in[num].reset();
- InputChannel { ch, pin }
+ InputChannel { ch: ch.map_into(), pin }
}
/// Asynchronously wait for an event in this channel.
@@ -227,12 +227,12 @@ impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
}
/// GPIOTE channel driver in output mode
-pub struct OutputChannel<'d, C: Channel, T: GpioPin> {
- ch: PeripheralRef<'d, C>,
- _pin: Output<'d, T>,
+pub struct OutputChannel<'d> {
+ ch: PeripheralRef<'d, AnyChannel>,
+ _pin: Output<'d>,
}
-impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
+impl<'d> Drop for OutputChannel<'d> {
fn drop(&mut self) {
let g = regs();
let num = self.ch.number();
@@ -241,9 +241,9 @@ impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
}
}
-impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
+impl<'d> OutputChannel<'d> {
/// Create a new GPIOTE output channel driver.
- pub fn new(ch: impl Peripheral<P = C> + 'd, pin: Output<'d, T>, polarity: OutputChannelPolarity) -> Self {
+ pub fn new(ch: impl Peripheral<P = impl Channel> + 'd, pin: Output<'d>, polarity: OutputChannelPolarity) -> Self {
into_ref!(ch);
let g = regs();
let num = ch.number();
@@ -267,7 +267,10 @@ impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
unsafe { w.psel().bits(pin.pin.pin.pin()) }
});
- OutputChannel { ch, _pin: pin }
+ OutputChannel {
+ ch: ch.map_into(),
+ _pin: pin,
+ }
}
/// Triggers the OUT task (does the action as configured with task_out_polarity, defaults to Toggle).
@@ -348,7 +351,7 @@ impl<'a> Future for PortInputFuture<'a> {
}
}
-impl<'d, T: GpioPin> Input<'d, T> {
+impl<'d> Input<'d> {
/// Wait until the pin is high. If it is already high, return immediately.
pub async fn wait_for_high(&mut self) {
self.pin.wait_for_high().await
@@ -375,7 +378,7 @@ impl<'d, T: GpioPin> Input<'d, T> {
}
}
-impl<'d, T: GpioPin> Flex<'d, T> {
+impl<'d> Flex<'d> {
/// Wait until the pin is high. If it is already high, return immediately.
pub async fn wait_for_high(&mut self) {
self.pin.conf().modify(|_, w| w.sense().high());
@@ -420,7 +423,7 @@ mod sealed {
/// GPIOTE channel trait.
///
/// Implemented by all GPIOTE channels.
-pub trait Channel: sealed::Channel + Sized {
+pub trait Channel: sealed::Channel + Into<AnyChannel> + Sized + 'static {
/// Get the channel number.
fn number(&self) -> usize;
@@ -460,6 +463,12 @@ macro_rules! impl_channel {
$number as usize
}
}
+
+ impl From<peripherals::$type> for AnyChannel {
+ fn from(val: peripherals::$type) -> Self {
+ Channel::degrade(val)
+ }
+ }
};
}
@@ -477,7 +486,7 @@ impl_channel!(GPIOTE_CH7, 7);
mod eh02 {
use super::*;
- impl<'d, C: Channel, T: GpioPin> embedded_hal_02::digital::v2::InputPin for InputChannel<'d, C, T> {
+ impl<'d> embedded_hal_02::digital::v2::InputPin for InputChannel<'d> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
@@ -490,11 +499,11 @@ mod eh02 {
}
}
-impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::ErrorType for InputChannel<'d, C, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for InputChannel<'d> {
type Error = Infallible;
}
-impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::InputPin for InputChannel<'d, C, T> {
+impl<'d> embedded_hal_1::digital::InputPin for InputChannel<'d> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok(self.pin.is_high())
}
@@ -504,7 +513,7 @@ impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::InputPin for InputChan
}
}
-impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Input<'d, T> {
+impl<'d> embedded_hal_async::digital::Wait for Input<'d> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
Ok(self.wait_for_high().await)
}
@@ -526,7 +535,7 @@ impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Input<'d, T> {
}
}
-impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Flex<'d, T> {
+impl<'d> embedded_hal_async::digital::Wait for Flex<'d> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
Ok(self.wait_for_high().await)
}
diff --git a/examples/nrf52840/src/bin/ethernet_enc28j60.rs b/examples/nrf52840/src/bin/ethernet_enc28j60.rs
index a8e64b38a..279f32edc 100644
--- a/examples/nrf52840/src/bin/ethernet_enc28j60.rs
+++ b/examples/nrf52840/src/bin/ethernet_enc28j60.rs
@@ -24,10 +24,7 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::task]
async fn net_task(
stack: &'static Stack<
- Enc28j60<
- ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static, peripherals::P0_15>, Delay>,
- Output<'static, peripherals::P0_13>,
- >,
+ Enc28j60<ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static>, Delay>, Output<'static>>,
>,
) -> ! {
stack.run().await
@@ -71,12 +68,7 @@ async fn main(spawner: Spawner) {
// Init network stack
static RESOURCES: StaticCell<StackResources<2>> = StaticCell::new();
static STACK: StaticCell<
- Stack<
- Enc28j60<
- ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static, peripherals::P0_15>, Delay>,
- Output<'static, peripherals::P0_13>,
- >,
- >,
+ Stack<Enc28j60<ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static>, Delay>, Output<'static>>>,
> = StaticCell::new();
let stack = STACK.init(Stack::new(
device,
diff --git a/examples/nrf52840/src/bin/gpiote_port.rs b/examples/nrf52840/src/bin/gpiote_port.rs
index c1afe2f20..0dddb1a97 100644
--- a/examples/nrf52840/src/bin/gpiote_port.rs
+++ b/examples/nrf52840/src/bin/gpiote_port.rs
@@ -3,11 +3,11 @@
use defmt::{info, unwrap};
use embassy_executor::Spawner;
-use embassy_nrf::gpio::{AnyPin, Input, Pin as _, Pull};
+use embassy_nrf::gpio::{Input, Pull};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::task(pool_size = 4)]
-async fn button_task(n: usize, mut pin: Input<'static, AnyPin>) {
+async fn button_task(n: usize, mut pin: Input<'static>) {
loop {
pin.wait_for_low().await;
info!("Button {:?} pressed!", n);
@@ -21,10 +21,10 @@ async fn main(spawner: Spawner) {
let p = embassy_nrf::init(Default::default());
info!("Starting!");
- let btn1 = Input::new(p.P0_11.degrade(), Pull::Up);
- let btn2 = Input::new(p.P0_12.degrade(), Pull::Up);
- let btn3 = Input::new(p.P0_24.degrade(), Pull::Up);
- let btn4 = Input::new(p.P0_25.degrade(), Pull::Up);
+ let btn1 = Input::new(p.P0_11, Pull::Up);
+ let btn2 = Input::new(p.P0_12, Pull::Up);
+ let btn3 = Input::new(p.P0_24, Pull::Up);
+ let btn4 = Input::new(p.P0_25, Pull::Up);
unwrap!(spawner.spawn(button_task(1, btn1)));
unwrap!(spawner.spawn(button_task(2, btn2)));
diff --git a/examples/nrf52840/src/bin/usb_hid_keyboard.rs b/examples/nrf52840/src/bin/usb_hid_keyboard.rs
index 45850b4a4..3e86590c4 100644
--- a/examples/nrf52840/src/bin/usb_hid_keyboard.rs
+++ b/examples/nrf52840/src/bin/usb_hid_keyboard.rs
@@ -8,7 +8,7 @@ use defmt::*;
use embassy_executor::Spawner;
use embassy_futures::join::join;
use embassy_futures::select::{select, Either};
-use embassy_nrf::gpio::{Input, Pin, Pull};
+use embassy_nrf::gpio::{Input, Pull};
use embassy_nrf::usb::vbus_detect::HardwareVbusDetect;
use embassy_nrf::usb::Driver;
use embassy_nrf::{bind_interrupts, pac, peripherals, usb};
@@ -97,7 +97,7 @@ async fn main(_spawner: Spawner) {
}
};
- let mut button = Input::new(p.P0_11.degrade(), Pull::Up);
+ let mut button = Input::new(p.P0_11, Pull::Up);
let (reader, mut writer) = hid.split();
diff --git a/examples/nrf52840/src/bin/wifi_esp_hosted.rs b/examples/nrf52840/src/bin/wifi_esp_hosted.rs
index fc2086f75..00bd50081 100644
--- a/examples/nrf52840/src/bin/wifi_esp_hosted.rs
+++ b/examples/nrf52840/src/bin/wifi_esp_hosted.rs
@@ -5,7 +5,7 @@ use defmt::{info, unwrap, warn};
use embassy_executor::Spawner;
use embassy_net::tcp::TcpSocket;
use embassy_net::{Stack, StackResources};
-use embassy_nrf::gpio::{AnyPin, Input, Level, Output, OutputDrive, Pin, Pull};
+use embassy_nrf::gpio::{Input, Level, Output, OutputDrive, Pull};
use embassy_nrf::rng::Rng;
use embassy_nrf::spim::{self, Spim};
use embassy_nrf::{bind_interrupts, peripherals};
@@ -27,9 +27,9 @@ bind_interrupts!(struct Irqs {
async fn wifi_task(
runner: hosted::Runner<
'static,
- ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static, peripherals::P0_31>, Delay>,
- Input<'static, AnyPin>,
- Output<'static, peripherals::P1_05>,
+ ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static>, Delay>,
+ Input<'static>,
+ Output<'static>,
>,
) -> ! {
runner.run().await
@@ -50,8 +50,8 @@ async fn main(spawner: Spawner) {
let sck = p.P0_29;
let mosi = p.P0_30;
let cs = Output::new(p.P0_31, Level::High, OutputDrive::HighDrive);
- let handshake = Input::new(p.P1_01.degrade(), Pull::Up);
- let ready = Input::new(p.P1_04.degrade(), Pull::None);
+ let handshake = Input::new(p.P1_01, Pull::Up);
+ let ready = Input::new(p.P1_04, Pull::None);
let reset = Output::new(p.P1_05, Level::Low, OutputDrive::Standard);
let mut config = spim::Config::default();
diff --git a/tests/nrf/src/bin/ethernet_enc28j60_perf.rs b/tests/nrf/src/bin/ethernet_enc28j60_perf.rs
index 7dc1941d7..33c2f4235 100644
--- a/tests/nrf/src/bin/ethernet_enc28j60_perf.rs
+++ b/tests/nrf/src/bin/ethernet_enc28j60_perf.rs
@@ -21,10 +21,7 @@ bind_interrupts!(struct Irqs {
RNG => embassy_nrf::rng::InterruptHandler<peripherals::RNG>;
});
-type MyDriver = Enc28j60<
- ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static, peripherals::P0_15>, Delay>,
- Output<'static, peripherals::P0_13>,
->;
+type MyDriver = Enc28j60<ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static>, Delay>, Output<'static>>;
#[embassy_executor::task]
async fn net_task(stack: &'static Stack<MyDriver>) -> ! {
diff --git a/tests/nrf/src/bin/wifi_esp_hosted_perf.rs b/tests/nrf/src/bin/wifi_esp_hosted_perf.rs
index c96064f84..b83edddc4 100644
--- a/tests/nrf/src/bin/wifi_esp_hosted_perf.rs
+++ b/tests/nrf/src/bin/wifi_esp_hosted_perf.rs
@@ -6,7 +6,7 @@ teleprobe_meta::timeout!(120);
use defmt::{info, unwrap};
use embassy_executor::Spawner;
use embassy_net::{Config, Stack, StackResources};
-use embassy_nrf::gpio::{AnyPin, Input, Level, Output, OutputDrive, Pin, Pull};
+use embassy_nrf::gpio::{Input, Level, Output, OutputDrive, Pull};
use embassy_nrf::rng::Rng;
use embassy_nrf::spim::{self, Spim};
use embassy_nrf::{bind_interrupts, peripherals};
@@ -28,9 +28,9 @@ const WIFI_PASSWORD: &str = "V8YxhKt5CdIAJFud";
async fn wifi_task(
runner: hosted::Runner<
'static,
- ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static, peripherals::P0_31>, Delay>,
- Input<'static, AnyPin>,
- Output<'static, peripherals::P1_05>,
+ ExclusiveDevice<Spim<'static, peripherals::SPI3>, Output<'static>, Delay>,
+ Input<'static>,
+ Output<'static>,
>,
) -> ! {
runner.run().await
@@ -53,8 +53,8 @@ async fn main(spawner: Spawner) {
let sck = p.P0_29;
let mosi = p.P0_30;
let cs = Output::new(p.P0_31, Level::High, OutputDrive::HighDrive);
- let handshake = Input::new(p.P1_01.degrade(), Pull::Up);
- let ready = Input::new(p.P1_04.degrade(), Pull::None);
+ let handshake = Input::new(p.P1_01, Pull::Up);
+ let ready = Input::new(p.P1_04, Pull::None);
let reset = Output::new(p.P1_05, Level::Low, OutputDrive::Standard);
let mut config = spim::Config::default();
From ee0ebe3121e5d51240e671d8c5cc19ad878b9db9 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 22 Jan 2024 21:30:29 +0100
Subject: [PATCH 044/392] rp/gpio: remove generics.
---
cyw43-pio/src/lib.rs | 14 +-
embassy-rp/src/gpio.rs | 125 +++++++++---------
examples/rp/src/bin/blinky_two_tasks.rs | 2 +-
.../rp/src/bin/ethernet_w5500_multisocket.rs | 8 +-
.../rp/src/bin/ethernet_w5500_tcp_client.rs | 8 +-
.../rp/src/bin/ethernet_w5500_tcp_server.rs | 8 +-
examples/rp/src/bin/ethernet_w5500_udp.rs | 8 +-
examples/rp/src/bin/multicore.rs | 3 +-
examples/rp/src/bin/wifi_ap_tcp_server.rs | 6 +-
examples/rp/src/bin/wifi_blinky.rs | 6 +-
examples/rp/src/bin/wifi_scan.rs | 6 +-
examples/rp/src/bin/wifi_tcp_server.rs | 6 +-
tests/rp/src/bin/cyw43-perf.rs | 6 +-
tests/rp/src/bin/ethernet_w5100s_perf.rs | 8 +-
tests/rp/src/bin/uart.rs | 6 +-
tests/rp/src/bin/uart_buffered.rs | 6 +-
tests/rp/src/bin/uart_dma.rs | 6 +-
17 files changed, 109 insertions(+), 123 deletions(-)
diff --git a/cyw43-pio/src/lib.rs b/cyw43-pio/src/lib.rs
index 5efab10e4..8c217b995 100644
--- a/cyw43-pio/src/lib.rs
+++ b/cyw43-pio/src/lib.rs
@@ -7,25 +7,24 @@ use core::slice;
use cyw43::SpiBusCyw43;
use embassy_rp::dma::Channel;
-use embassy_rp::gpio::{Drive, Level, Output, Pin, Pull, SlewRate};
+use embassy_rp::gpio::{Drive, Level, Output, Pull, SlewRate};
use embassy_rp::pio::{instr, Common, Config, Direction, Instance, Irq, PioPin, ShiftDirection, StateMachine};
use embassy_rp::{Peripheral, PeripheralRef};
use fixed::FixedU32;
use pio_proc::pio_asm;
/// SPI comms driven by PIO.
-pub struct PioSpi<'d, CS: Pin, PIO: Instance, const SM: usize, DMA> {
- cs: Output<'d, CS>,
+pub struct PioSpi<'d, PIO: Instance, const SM: usize, DMA> {
+ cs: Output<'d>,
sm: StateMachine<'d, PIO, SM>,
irq: Irq<'d, PIO, 0>,
dma: PeripheralRef<'d, DMA>,
wrap_target: u8,
}
-impl<'d, CS, PIO, const SM: usize, DMA> PioSpi<'d, CS, PIO, SM, DMA>
+impl<'d, PIO, const SM: usize, DMA> PioSpi<'d, PIO, SM, DMA>
where
DMA: Channel,
- CS: Pin,
PIO: Instance,
{
/// Create a new instance of PioSpi.
@@ -33,7 +32,7 @@ where
common: &mut Common<'d, PIO>,
mut sm: StateMachine<'d, PIO, SM>,
irq: Irq<'d, PIO, 0>,
- cs: Output<'d, CS>,
+ cs: Output<'d>,
dio: DIO,
clk: CLK,
dma: impl Peripheral<P = DMA> + 'd,
@@ -206,9 +205,8 @@ where
}
}
-impl<'d, CS, PIO, const SM: usize, DMA> SpiBusCyw43 for PioSpi<'d, CS, PIO, SM, DMA>
+impl<'d, PIO, const SM: usize, DMA> SpiBusCyw43 for PioSpi<'d, PIO, SM, DMA>
where
- CS: Pin,
PIO: Instance,
DMA: Channel,
{
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index 7eb57bbe6..93b29bbf9 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -8,6 +8,7 @@ use core::task::{Context, Poll};
use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
+use self::sealed::Pin as _;
use crate::interrupt::InterruptExt;
use crate::pac::common::{Reg, RW};
use crate::pac::SIO;
@@ -105,14 +106,14 @@ pub struct DormantWakeConfig {
}
/// GPIO input driver.
-pub struct Input<'d, T: Pin> {
- pin: Flex<'d, T>,
+pub struct Input<'d> {
+ pin: Flex<'d>,
}
-impl<'d, T: Pin> Input<'d, T> {
+impl<'d> Input<'d> {
/// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, pull: Pull) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
pin.set_as_input();
pin.set_pull(pull);
@@ -175,7 +176,7 @@ impl<'d, T: Pin> Input<'d, T> {
/// Configure dormant wake.
#[inline]
- pub fn dormant_wake(&mut self, cfg: DormantWakeConfig) -> DormantWake<T> {
+ pub fn dormant_wake(&mut self, cfg: DormantWakeConfig) -> DormantWake<'_> {
self.pin.dormant_wake(cfg)
}
}
@@ -255,14 +256,12 @@ fn IO_IRQ_QSPI() {
}
#[must_use = "futures do nothing unless you `.await` or poll them"]
-struct InputFuture<'a, T: Pin> {
- pin: PeripheralRef<'a, T>,
+struct InputFuture<'d> {
+ pin: PeripheralRef<'d, AnyPin>,
}
-impl<'d, T: Pin> InputFuture<'d, T> {
- /// Create a new future wiating for input trigger.
- pub fn new(pin: impl Peripheral<P = T> + 'd, level: InterruptTrigger) -> Self {
- into_ref!(pin);
+impl<'d> InputFuture<'d> {
+ fn new(pin: PeripheralRef<'d, AnyPin>, level: InterruptTrigger) -> Self {
let pin_group = (pin.pin() % 8) as usize;
// first, clear the INTR register bits. without this INTR will still
// contain reports of previous edges, causing the IRQ to fire early
@@ -305,7 +304,7 @@ impl<'d, T: Pin> InputFuture<'d, T> {
}
}
-impl<'d, T: Pin> Future for InputFuture<'d, T> {
+impl<'d> Future for InputFuture<'d> {
type Output = ();
fn poll(self: FuturePin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
@@ -344,14 +343,14 @@ impl<'d, T: Pin> Future for InputFuture<'d, T> {
}
/// GPIO output driver.
-pub struct Output<'d, T: Pin> {
- pin: Flex<'d, T>,
+pub struct Output<'d> {
+ pin: Flex<'d>,
}
-impl<'d, T: Pin> Output<'d, T> {
+impl<'d> Output<'d> {
/// Create GPIO output driver for a [Pin] with the provided [Level].
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level) -> Self {
let mut pin = Flex::new(pin);
match initial_output {
Level::High => pin.set_high(),
@@ -418,14 +417,14 @@ impl<'d, T: Pin> Output<'d, T> {
}
/// GPIO output open-drain.
-pub struct OutputOpenDrain<'d, T: Pin> {
- pin: Flex<'d, T>,
+pub struct OutputOpenDrain<'d> {
+ pin: Flex<'d>,
}
-impl<'d, T: Pin> OutputOpenDrain<'d, T> {
+impl<'d> OutputOpenDrain<'d> {
/// Create GPIO output driver for a [Pin] in open drain mode with the provided [Level].
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd, initial_output: Level) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level) -> Self {
let mut pin = Flex::new(pin);
pin.set_low();
match initial_output {
@@ -548,17 +547,17 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
/// This pin can be either an input or output pin. The output level register bit will remain
/// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
/// mode.
-pub struct Flex<'d, T: Pin> {
- pin: PeripheralRef<'d, T>,
+pub struct Flex<'d> {
+ pin: PeripheralRef<'d, AnyPin>,
}
-impl<'d, T: Pin> Flex<'d, T> {
+impl<'d> Flex<'d> {
/// Wrap the pin in a `Flex`.
///
/// The pin remains disconnected. The initial output level is unspecified, but can be changed
/// before the pin is put into output mode.
#[inline]
- pub fn new(pin: impl Peripheral<P = T> + 'd) -> Self {
+ pub fn new(pin: impl Peripheral<P = impl Pin> + 'd) -> Self {
into_ref!(pin);
pin.pad_ctrl().write(|w| {
@@ -569,7 +568,7 @@ impl<'d, T: Pin> Flex<'d, T> {
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0 as _);
});
- Self { pin }
+ Self { pin: pin.map_into() }
}
#[inline]
@@ -716,36 +715,36 @@ impl<'d, T: Pin> Flex<'d, T> {
/// Wait until the pin is high. If it is already high, return immediately.
#[inline]
pub async fn wait_for_high(&mut self) {
- InputFuture::new(&mut self.pin, InterruptTrigger::LevelHigh).await;
+ InputFuture::new(self.pin.reborrow(), InterruptTrigger::LevelHigh).await;
}
/// Wait until the pin is low. If it is already low, return immediately.
#[inline]
pub async fn wait_for_low(&mut self) {
- InputFuture::new(&mut self.pin, InterruptTrigger::LevelLow).await;
+ InputFuture::new(self.pin.reborrow(), InterruptTrigger::LevelLow).await;
}
/// Wait for the pin to undergo a transition from low to high.
#[inline]
pub async fn wait_for_rising_edge(&mut self) {
- InputFuture::new(&mut self.pin, InterruptTrigger::EdgeHigh).await;
+ InputFuture::new(self.pin.reborrow(), InterruptTrigger::EdgeHigh).await;
}
/// Wait for the pin to undergo a transition from high to low.
#[inline]
pub async fn wait_for_falling_edge(&mut self) {
- InputFuture::new(&mut self.pin, InterruptTrigger::EdgeLow).await;
+ InputFuture::new(self.pin.reborrow(), InterruptTrigger::EdgeLow).await;
}
/// Wait for the pin to undergo any transition, i.e low to high OR high to low.
#[inline]
pub async fn wait_for_any_edge(&mut self) {
- InputFuture::new(&mut self.pin, InterruptTrigger::AnyEdge).await;
+ InputFuture::new(self.pin.reborrow(), InterruptTrigger::AnyEdge).await;
}
/// Configure dormant wake.
#[inline]
- pub fn dormant_wake(&mut self, cfg: DormantWakeConfig) -> DormantWake<T> {
+ pub fn dormant_wake(&mut self, cfg: DormantWakeConfig) -> DormantWake<'_> {
let idx = self.pin._pin() as usize;
self.pin.io().intr(idx / 8).write(|w| {
w.set_edge_high(idx % 8, cfg.edge_high);
@@ -764,7 +763,7 @@ impl<'d, T: Pin> Flex<'d, T> {
}
}
-impl<'d, T: Pin> Drop for Flex<'d, T> {
+impl<'d> Drop for Flex<'d> {
#[inline]
fn drop(&mut self) {
let idx = self.pin._pin() as usize;
@@ -782,12 +781,12 @@ impl<'d, T: Pin> Drop for Flex<'d, T> {
}
/// Dormant wake driver.
-pub struct DormantWake<'w, T: Pin> {
- pin: PeripheralRef<'w, T>,
+pub struct DormantWake<'w> {
+ pin: PeripheralRef<'w, AnyPin>,
cfg: DormantWakeConfig,
}
-impl<'w, T: Pin> Drop for DormantWake<'w, T> {
+impl<'w> Drop for DormantWake<'w> {
fn drop(&mut self) {
let idx = self.pin._pin() as usize;
self.pin.io().intr(idx / 8).write(|w| {
@@ -970,7 +969,7 @@ mod eh02 {
use super::*;
- impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Input<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::InputPin for Input<'d> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
@@ -982,7 +981,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Output<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::OutputPin for Output<'d> {
type Error = Infallible;
fn set_high(&mut self) -> Result<(), Self::Error> {
@@ -994,7 +993,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for Output<'d> {
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
@@ -1004,7 +1003,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for Output<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -1012,7 +1011,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for OutputOpenDrain<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::InputPin for OutputOpenDrain<'d> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
@@ -1024,7 +1023,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for OutputOpenDrain<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::OutputPin for OutputOpenDrain<'d> {
type Error = Infallible;
#[inline]
@@ -1038,7 +1037,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for OutputOpenDrain<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for OutputOpenDrain<'d> {
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
@@ -1048,7 +1047,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for OutputOpenDrain<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for OutputOpenDrain<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -1056,7 +1055,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::InputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::InputPin for Flex<'d> {
type Error = Infallible;
fn is_high(&self) -> Result<bool, Self::Error> {
@@ -1068,7 +1067,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::OutputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::OutputPin for Flex<'d> {
type Error = Infallible;
fn set_high(&mut self) -> Result<(), Self::Error> {
@@ -1080,7 +1079,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::StatefulOutputPin for Flex<'d> {
fn is_set_high(&self) -> Result<bool, Self::Error> {
Ok(self.is_set_high())
}
@@ -1090,7 +1089,7 @@ mod eh02 {
}
}
- impl<'d, T: Pin> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d, T> {
+ impl<'d> embedded_hal_02::digital::v2::ToggleableOutputPin for Flex<'d> {
type Error = Infallible;
#[inline]
fn toggle(&mut self) -> Result<(), Self::Error> {
@@ -1099,11 +1098,11 @@ mod eh02 {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Input<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Input<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for Input<'d> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
}
@@ -1113,11 +1112,11 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Input<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Output<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for Output<'d> {
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
@@ -1127,7 +1126,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Output<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for Output<'d> {
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
}
@@ -1137,11 +1136,11 @@ impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Output<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for OutputOpenDrain<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d> {
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
@@ -1151,7 +1150,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for OutputOpenDrain<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<'d> {
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
}
@@ -1161,7 +1160,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for OutputOpenDrain<
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
}
@@ -1171,11 +1170,11 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for OutputOpenDrain<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::ErrorType for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::ErrorType for Flex<'d> {
type Error = Infallible;
}
-impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::InputPin for Flex<'d> {
fn is_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_high())
}
@@ -1185,7 +1184,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::InputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::OutputPin for Flex<'d> {
fn set_high(&mut self) -> Result<(), Self::Error> {
Ok(self.set_high())
}
@@ -1195,7 +1194,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::OutputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Flex<'d, T> {
+impl<'d> embedded_hal_1::digital::StatefulOutputPin for Flex<'d> {
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
Ok((*self).is_set_high())
}
@@ -1205,7 +1204,7 @@ impl<'d, T: Pin> embedded_hal_1::digital::StatefulOutputPin for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_async::digital::Wait for Flex<'d, T> {
+impl<'d> embedded_hal_async::digital::Wait for Flex<'d> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
self.wait_for_high().await;
Ok(())
@@ -1232,7 +1231,7 @@ impl<'d, T: Pin> embedded_hal_async::digital::Wait for Flex<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_async::digital::Wait for Input<'d, T> {
+impl<'d> embedded_hal_async::digital::Wait for Input<'d> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
self.wait_for_high().await;
Ok(())
@@ -1259,7 +1258,7 @@ impl<'d, T: Pin> embedded_hal_async::digital::Wait for Input<'d, T> {
}
}
-impl<'d, T: Pin> embedded_hal_async::digital::Wait for OutputOpenDrain<'d, T> {
+impl<'d> embedded_hal_async::digital::Wait for OutputOpenDrain<'d> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
self.wait_for_high().await;
Ok(())
diff --git a/examples/rp/src/bin/blinky_two_tasks.rs b/examples/rp/src/bin/blinky_two_tasks.rs
index a03f3a592..a57b513d6 100644
--- a/examples/rp/src/bin/blinky_two_tasks.rs
+++ b/examples/rp/src/bin/blinky_two_tasks.rs
@@ -14,7 +14,7 @@ use embassy_time::{Duration, Ticker};
use gpio::{AnyPin, Level, Output};
use {defmt_rtt as _, panic_probe as _};
-type LedType = Mutex<ThreadModeRawMutex, Option<Output<'static, AnyPin>>>;
+type LedType = Mutex<ThreadModeRawMutex, Option<Output<'static>>>;
static LED: LedType = Mutex::new(None);
#[embassy_executor::main]
diff --git a/examples/rp/src/bin/ethernet_w5500_multisocket.rs b/examples/rp/src/bin/ethernet_w5500_multisocket.rs
index a16ea0007..bd52cadca 100644
--- a/examples/rp/src/bin/ethernet_w5500_multisocket.rs
+++ b/examples/rp/src/bin/ethernet_w5500_multisocket.rs
@@ -13,7 +13,7 @@ use embassy_net_wiznet::chip::W5500;
use embassy_net_wiznet::*;
use embassy_rp::clocks::RoscRng;
use embassy_rp::gpio::{Input, Level, Output, Pull};
-use embassy_rp::peripherals::{PIN_17, PIN_20, PIN_21, SPI0};
+use embassy_rp::peripherals::SPI0;
use embassy_rp::spi::{Async, Config as SpiConfig, Spi};
use embassy_time::{Delay, Duration};
use embedded_hal_bus::spi::ExclusiveDevice;
@@ -27,9 +27,9 @@ async fn ethernet_task(
runner: Runner<
'static,
W5500,
- ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static, PIN_17>, Delay>,
- Input<'static, PIN_21>,
- Output<'static, PIN_20>,
+ ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static>, Delay>,
+ Input<'static>,
+ Output<'static>,
>,
) -> ! {
runner.run().await
diff --git a/examples/rp/src/bin/ethernet_w5500_tcp_client.rs b/examples/rp/src/bin/ethernet_w5500_tcp_client.rs
index 975b3d385..3e4fbd2e6 100644
--- a/examples/rp/src/bin/ethernet_w5500_tcp_client.rs
+++ b/examples/rp/src/bin/ethernet_w5500_tcp_client.rs
@@ -15,7 +15,7 @@ use embassy_net_wiznet::chip::W5500;
use embassy_net_wiznet::*;
use embassy_rp::clocks::RoscRng;
use embassy_rp::gpio::{Input, Level, Output, Pull};
-use embassy_rp::peripherals::{PIN_17, PIN_20, PIN_21, SPI0};
+use embassy_rp::peripherals::SPI0;
use embassy_rp::spi::{Async, Config as SpiConfig, Spi};
use embassy_time::{Delay, Duration, Timer};
use embedded_hal_bus::spi::ExclusiveDevice;
@@ -29,9 +29,9 @@ async fn ethernet_task(
runner: Runner<
'static,
W5500,
- ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static, PIN_17>, Delay>,
- Input<'static, PIN_21>,
- Output<'static, PIN_20>,
+ ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static>, Delay>,
+ Input<'static>,
+ Output<'static>,
>,
) -> ! {
runner.run().await
diff --git a/examples/rp/src/bin/ethernet_w5500_tcp_server.rs b/examples/rp/src/bin/ethernet_w5500_tcp_server.rs
index 489af2c76..5532851f3 100644
--- a/examples/rp/src/bin/ethernet_w5500_tcp_server.rs
+++ b/examples/rp/src/bin/ethernet_w5500_tcp_server.rs
@@ -14,7 +14,7 @@ use embassy_net_wiznet::chip::W5500;
use embassy_net_wiznet::*;
use embassy_rp::clocks::RoscRng;
use embassy_rp::gpio::{Input, Level, Output, Pull};
-use embassy_rp::peripherals::{PIN_17, PIN_20, PIN_21, SPI0};
+use embassy_rp::peripherals::SPI0;
use embassy_rp::spi::{Async, Config as SpiConfig, Spi};
use embassy_time::{Delay, Duration};
use embedded_hal_bus::spi::ExclusiveDevice;
@@ -28,9 +28,9 @@ async fn ethernet_task(
runner: Runner<
'static,
W5500,
- ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static, PIN_17>, Delay>,
- Input<'static, PIN_21>,
- Output<'static, PIN_20>,
+ ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static>, Delay>,
+ Input<'static>,
+ Output<'static>,
>,
) -> ! {
runner.run().await
diff --git a/examples/rp/src/bin/ethernet_w5500_udp.rs b/examples/rp/src/bin/ethernet_w5500_udp.rs
index 41bd7d077..adb1d8941 100644
--- a/examples/rp/src/bin/ethernet_w5500_udp.rs
+++ b/examples/rp/src/bin/ethernet_w5500_udp.rs
@@ -14,7 +14,7 @@ use embassy_net_wiznet::chip::W5500;
use embassy_net_wiznet::*;
use embassy_rp::clocks::RoscRng;
use embassy_rp::gpio::{Input, Level, Output, Pull};
-use embassy_rp::peripherals::{PIN_17, PIN_20, PIN_21, SPI0};
+use embassy_rp::peripherals::SPI0;
use embassy_rp::spi::{Async, Config as SpiConfig, Spi};
use embassy_time::Delay;
use embedded_hal_bus::spi::ExclusiveDevice;
@@ -27,9 +27,9 @@ async fn ethernet_task(
runner: Runner<
'static,
W5500,
- ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static, PIN_17>, Delay>,
- Input<'static, PIN_21>,
- Output<'static, PIN_20>,
+ ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static>, Delay>,
+ Input<'static>,
+ Output<'static>,
>,
) -> ! {
runner.run().await
diff --git a/examples/rp/src/bin/multicore.rs b/examples/rp/src/bin/multicore.rs
index a1678d99a..c7b087476 100644
--- a/examples/rp/src/bin/multicore.rs
+++ b/examples/rp/src/bin/multicore.rs
@@ -9,7 +9,6 @@ use defmt::*;
use embassy_executor::Executor;
use embassy_rp::gpio::{Level, Output};
use embassy_rp::multicore::{spawn_core1, Stack};
-use embassy_rp::peripherals::PIN_25;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::channel::Channel;
use embassy_time::Timer;
@@ -52,7 +51,7 @@ async fn core0_task() {
}
#[embassy_executor::task]
-async fn core1_task(mut led: Output<'static, PIN_25>) {
+async fn core1_task(mut led: Output<'static>) {
info!("Hello from core 1");
loop {
match CHANNEL.receive().await {
diff --git a/examples/rp/src/bin/wifi_ap_tcp_server.rs b/examples/rp/src/bin/wifi_ap_tcp_server.rs
index 1bd75607e..b60852359 100644
--- a/examples/rp/src/bin/wifi_ap_tcp_server.rs
+++ b/examples/rp/src/bin/wifi_ap_tcp_server.rs
@@ -14,7 +14,7 @@ use embassy_net::tcp::TcpSocket;
use embassy_net::{Config, Stack, StackResources};
use embassy_rp::bind_interrupts;
use embassy_rp::gpio::{Level, Output};
-use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_25, PIO0};
+use embassy_rp::peripherals::{DMA_CH0, PIO0};
use embassy_rp::pio::{InterruptHandler, Pio};
use embassy_time::Duration;
use embedded_io_async::Write;
@@ -26,9 +26,7 @@ bind_interrupts!(struct Irqs {
});
#[embassy_executor::task]
-async fn wifi_task(
- runner: cyw43::Runner<'static, Output<'static, PIN_23>, PioSpi<'static, PIN_25, PIO0, 0, DMA_CH0>>,
-) -> ! {
+async fn wifi_task(runner: cyw43::Runner<'static, Output<'static>, PioSpi<'static, PIO0, 0, DMA_CH0>>) -> ! {
runner.run().await
}
diff --git a/examples/rp/src/bin/wifi_blinky.rs b/examples/rp/src/bin/wifi_blinky.rs
index 1ed74993c..18eefe41f 100644
--- a/examples/rp/src/bin/wifi_blinky.rs
+++ b/examples/rp/src/bin/wifi_blinky.rs
@@ -10,7 +10,7 @@ use defmt::*;
use embassy_executor::Spawner;
use embassy_rp::bind_interrupts;
use embassy_rp::gpio::{Level, Output};
-use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_25, PIO0};
+use embassy_rp::peripherals::{DMA_CH0, PIO0};
use embassy_rp::pio::{InterruptHandler, Pio};
use embassy_time::{Duration, Timer};
use static_cell::StaticCell;
@@ -21,9 +21,7 @@ bind_interrupts!(struct Irqs {
});
#[embassy_executor::task]
-async fn wifi_task(
- runner: cyw43::Runner<'static, Output<'static, PIN_23>, PioSpi<'static, PIN_25, PIO0, 0, DMA_CH0>>,
-) -> ! {
+async fn wifi_task(runner: cyw43::Runner<'static, Output<'static>, PioSpi<'static, PIO0, 0, DMA_CH0>>) -> ! {
runner.run().await
}
diff --git a/examples/rp/src/bin/wifi_scan.rs b/examples/rp/src/bin/wifi_scan.rs
index e678209dd..e0f85a6b0 100644
--- a/examples/rp/src/bin/wifi_scan.rs
+++ b/examples/rp/src/bin/wifi_scan.rs
@@ -13,7 +13,7 @@ use embassy_executor::Spawner;
use embassy_net::Stack;
use embassy_rp::bind_interrupts;
use embassy_rp::gpio::{Level, Output};
-use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_25, PIO0};
+use embassy_rp::peripherals::{DMA_CH0, PIO0};
use embassy_rp::pio::{InterruptHandler, Pio};
use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
@@ -23,9 +23,7 @@ bind_interrupts!(struct Irqs {
});
#[embassy_executor::task]
-async fn wifi_task(
- runner: cyw43::Runner<'static, Output<'static, PIN_23>, PioSpi<'static, PIN_25, PIO0, 0, DMA_CH0>>,
-) -> ! {
+async fn wifi_task(runner: cyw43::Runner<'static, Output<'static>, PioSpi<'static, PIO0, 0, DMA_CH0>>) -> ! {
runner.run().await
}
diff --git a/examples/rp/src/bin/wifi_tcp_server.rs b/examples/rp/src/bin/wifi_tcp_server.rs
index c346f1ded..f1afc4a00 100644
--- a/examples/rp/src/bin/wifi_tcp_server.rs
+++ b/examples/rp/src/bin/wifi_tcp_server.rs
@@ -14,7 +14,7 @@ use embassy_net::tcp::TcpSocket;
use embassy_net::{Config, Stack, StackResources};
use embassy_rp::bind_interrupts;
use embassy_rp::gpio::{Level, Output};
-use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_25, PIO0};
+use embassy_rp::peripherals::{DMA_CH0, PIO0};
use embassy_rp::pio::{InterruptHandler, Pio};
use embassy_time::{Duration, Timer};
use embedded_io_async::Write;
@@ -29,9 +29,7 @@ const WIFI_NETWORK: &str = "EmbassyTest";
const WIFI_PASSWORD: &str = "V8YxhKt5CdIAJFud";
#[embassy_executor::task]
-async fn wifi_task(
- runner: cyw43::Runner<'static, Output<'static, PIN_23>, PioSpi<'static, PIN_25, PIO0, 0, DMA_CH0>>,
-) -> ! {
+async fn wifi_task(runner: cyw43::Runner<'static, Output<'static>, PioSpi<'static, PIO0, 0, DMA_CH0>>) -> ! {
runner.run().await
}
diff --git a/tests/rp/src/bin/cyw43-perf.rs b/tests/rp/src/bin/cyw43-perf.rs
index a1b2946e6..b46ae670a 100644
--- a/tests/rp/src/bin/cyw43-perf.rs
+++ b/tests/rp/src/bin/cyw43-perf.rs
@@ -7,7 +7,7 @@ use defmt::{panic, *};
use embassy_executor::Spawner;
use embassy_net::{Config, Stack, StackResources};
use embassy_rp::gpio::{Level, Output};
-use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_25, PIO0};
+use embassy_rp::peripherals::{DMA_CH0, PIO0};
use embassy_rp::pio::{InterruptHandler, Pio};
use embassy_rp::{bind_interrupts, rom_data};
use static_cell::StaticCell;
@@ -24,9 +24,7 @@ const WIFI_NETWORK: &str = "EmbassyTest";
const WIFI_PASSWORD: &str = "V8YxhKt5CdIAJFud";
#[embassy_executor::task]
-async fn wifi_task(
- runner: cyw43::Runner<'static, Output<'static, PIN_23>, PioSpi<'static, PIN_25, PIO0, 0, DMA_CH0>>,
-) -> ! {
+async fn wifi_task(runner: cyw43::Runner<'static, Output<'static>, PioSpi<'static, PIO0, 0, DMA_CH0>>) -> ! {
runner.run().await
}
diff --git a/tests/rp/src/bin/ethernet_w5100s_perf.rs b/tests/rp/src/bin/ethernet_w5100s_perf.rs
index 8c9089d0e..5d5547773 100644
--- a/tests/rp/src/bin/ethernet_w5100s_perf.rs
+++ b/tests/rp/src/bin/ethernet_w5100s_perf.rs
@@ -10,7 +10,7 @@ use embassy_net_wiznet::chip::W5100S;
use embassy_net_wiznet::*;
use embassy_rp::clocks::RoscRng;
use embassy_rp::gpio::{Input, Level, Output, Pull};
-use embassy_rp::peripherals::{PIN_17, PIN_20, PIN_21, SPI0};
+use embassy_rp::peripherals::SPI0;
use embassy_rp::spi::{Async, Config as SpiConfig, Spi};
use embassy_time::Delay;
use embedded_hal_bus::spi::ExclusiveDevice;
@@ -23,9 +23,9 @@ async fn ethernet_task(
runner: Runner<
'static,
W5100S,
- ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static, PIN_17>, Delay>,
- Input<'static, PIN_21>,
- Output<'static, PIN_20>,
+ ExclusiveDevice<Spi<'static, SPI0, Async>, Output<'static>, Delay>,
+ Input<'static>,
+ Output<'static>,
>,
) -> ! {
runner.run().await
diff --git a/tests/rp/src/bin/uart.rs b/tests/rp/src/bin/uart.rs
index f4d641175..6e6e5517b 100644
--- a/tests/rp/src/bin/uart.rs
+++ b/tests/rp/src/bin/uart.rs
@@ -21,7 +21,7 @@ fn read1<const N: usize>(uart: &mut UartRx<'_, impl Instance, Blocking>) -> Resu
Ok(buf)
}
-async fn send(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: Option<bool>) {
+async fn send(pin: &mut Output<'_>, v: u8, parity: Option<bool>) {
pin.set_low();
Timer::after_millis(1).await;
for i in 0..8 {
@@ -116,7 +116,7 @@ async fn main(_spawner: Spawner) {
config.parity = Parity::ParityEven;
let mut uart = UartRx::new_blocking(&mut uart, &mut rx, config);
- async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: u8) {
+ async fn chr(pin: &mut Output<'_>, v: u8, parity: u8) {
send(pin, v, Some(parity != 0)).await;
}
@@ -142,7 +142,7 @@ async fn main(_spawner: Spawner) {
config.baudrate = 1000;
let mut uart = UartRx::new_blocking(&mut uart, &mut rx, config);
- async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, good: bool) {
+ async fn chr(pin: &mut Output<'_>, v: u8, good: bool) {
if good {
send(pin, v, None).await;
} else {
diff --git a/tests/rp/src/bin/uart_buffered.rs b/tests/rp/src/bin/uart_buffered.rs
index 14647e44a..d68c23cbd 100644
--- a/tests/rp/src/bin/uart_buffered.rs
+++ b/tests/rp/src/bin/uart_buffered.rs
@@ -36,7 +36,7 @@ async fn read1<const N: usize>(uart: &mut BufferedUartRx<'_, impl Instance>) ->
}
}
-async fn send(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: Option<bool>) {
+async fn send(pin: &mut Output<'_>, v: u8, parity: Option<bool>) {
pin.set_low();
Timer::after_millis(1).await;
for i in 0..8 {
@@ -161,7 +161,7 @@ async fn main(_spawner: Spawner) {
let rx_buf = &mut [0u8; 16];
let mut uart = BufferedUartRx::new(&mut uart, Irqs, &mut rx, rx_buf, config);
- async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: u32) {
+ async fn chr(pin: &mut Output<'_>, v: u8, parity: u32) {
send(pin, v, Some(parity != 0)).await;
}
@@ -208,7 +208,7 @@ async fn main(_spawner: Spawner) {
let rx_buf = &mut [0u8; 16];
let mut uart = BufferedUartRx::new(&mut uart, Irqs, &mut rx, rx_buf, config);
- async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, good: bool) {
+ async fn chr(pin: &mut Output<'_>, v: u8, good: bool) {
if good {
send(pin, v, None).await;
} else {
diff --git a/tests/rp/src/bin/uart_dma.rs b/tests/rp/src/bin/uart_dma.rs
index 130d8599e..edc87175a 100644
--- a/tests/rp/src/bin/uart_dma.rs
+++ b/tests/rp/src/bin/uart_dma.rs
@@ -27,7 +27,7 @@ async fn read1<const N: usize>(uart: &mut UartRx<'_, impl Instance, Async>) -> R
Ok(buf)
}
-async fn send(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: Option<bool>) {
+async fn send(pin: &mut Output<'_>, v: u8, parity: Option<bool>) {
pin.set_low();
Timer::after_millis(1).await;
for i in 0..8 {
@@ -160,7 +160,7 @@ async fn main(_spawner: Spawner) {
config.parity = Parity::ParityEven;
let mut uart = UartRx::new(&mut uart, &mut rx, Irqs, &mut p.DMA_CH0, config);
- async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, parity: u32) {
+ async fn chr(pin: &mut Output<'_>, v: u8, parity: u32) {
send(pin, v, Some(parity != 0)).await;
}
@@ -205,7 +205,7 @@ async fn main(_spawner: Spawner) {
config.baudrate = 1000;
let mut uart = UartRx::new(&mut uart, &mut rx, Irqs, &mut p.DMA_CH0, config);
- async fn chr(pin: &mut Output<'_, impl embassy_rp::gpio::Pin>, v: u8, good: bool) {
+ async fn chr(pin: &mut Output<'_>, v: u8, good: bool) {
if good {
send(pin, v, None).await;
} else {
From 40e9fc36dc3af75a9625413504d4e90a0d5f35d9 Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Tue, 23 Jan 2024 12:06:28 +0100
Subject: [PATCH 045/392] Update faq.adoc
Don't suggest people disable debuginfo, and explain why
---
docs/modules/ROOT/pages/faq.adoc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/modules/ROOT/pages/faq.adoc b/docs/modules/ROOT/pages/faq.adoc
index 147f119b0..bf061d978 100644
--- a/docs/modules/ROOT/pages/faq.adoc
+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -44,11 +44,12 @@ The first step to managing your binary size is to set up your link:https://doc.r
[source,toml]
----
[profile.release]
-debug = false
lto = true
opt-level = "s"
incremental = false
codegen-units = 1
+# note: debug = true is okay - debuginfo isn't flashed to the device!
+debug = true
----
All of these flags are elaborated on in the Rust Book page linked above.
From 4410aacafb2141c1c0838598d11581e24aab3b0f Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 19 Jan 2024 23:13:46 +0100
Subject: [PATCH 046/392] feat: add basic support for nRF51 chips to
embassy-nrf
---
embassy-nrf/Cargo.toml | 8 ++
embassy-nrf/src/chips/nrf51.rs | 168 ++++++++++++++++++++++++++++++
embassy-nrf/src/gpio.rs | 12 +++
embassy-nrf/src/lib.rs | 19 +++-
embassy-nrf/src/ppi/ppi.rs | 1 +
embassy-nrf/src/rng.rs | 2 +-
embassy-nrf/src/time_driver.rs | 2 +-
embassy-nrf/src/timer.rs | 16 ++-
examples/nrf51/.cargo/config.toml | 9 ++
examples/nrf51/Cargo.toml | 20 ++++
examples/nrf51/build.rs | 35 +++++++
examples/nrf51/memory.x | 5 +
examples/nrf51/src/bin/blinky.rs | 21 ++++
13 files changed, 311 insertions(+), 7 deletions(-)
create mode 100644 embassy-nrf/src/chips/nrf51.rs
create mode 100644 examples/nrf51/.cargo/config.toml
create mode 100644 examples/nrf51/Cargo.toml
create mode 100644 examples/nrf51/build.rs
create mode 100644 examples/nrf51/memory.x
create mode 100644 examples/nrf51/src/bin/blinky.rs
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 10f268b51..529a56c46 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -15,6 +15,7 @@ src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-nrf/s
features = ["time", "defmt", "unstable-pac", "gpiote", "time-driver-rtc1"]
flavors = [
+ { regex_feature = "nrf51", target = "thumbv6m-none-eabi" },
{ regex_feature = "nrf52.*", target = "thumbv7em-none-eabihf" },
{ regex_feature = "nrf53.*", target = "thumbv8m.main-none-eabihf" },
{ regex_feature = "nrf91.*", target = "thumbv8m.main-none-eabihf" },
@@ -28,6 +29,7 @@ rustdoc-args = ["--cfg", "docsrs"]
default = ["rt"]
## Cortex-M runtime (enabled by default)
rt = [
+ "nrf51-pac?/rt",
"nrf52805-pac?/rt",
"nrf52810-pac?/rt",
"nrf52811-pac?/rt",
@@ -71,6 +73,8 @@ reset-pin-as-gpio = []
qspi-multiwrite-flash = []
#! ### Chip selection features
+## nRF51
+nrf51 = ["nrf51-pac", "_nrf51", "portable-atomic/unsafe-assume-single-core"]
## nRF52805
nrf52805 = ["nrf52805-pac", "_nrf52"]
## nRF52810
@@ -104,6 +108,7 @@ _nrf5340-net = ["_nrf5340", "nrf5340-net-pac"]
_nrf5340 = ["_gpio-p1", "_dppi"]
_nrf9160 = ["nrf9160-pac", "_dppi"]
_nrf52 = ["_ppi"]
+_nrf51 = ["_ppi"]
_time-driver = ["dep:embassy-time-driver", "embassy-time-driver?/tick-hz-32_768"]
@@ -132,6 +137,8 @@ embedded-hal-async = { version = "1.0" }
embedded-io = { version = "0.6.0" }
embedded-io-async = { version = "0.6.1" }
+portable-atomic = { version = "1", default-features = false, features = ["require-cas"] }
+
defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
cortex-m-rt = ">=0.6.15,<0.8"
@@ -144,6 +151,7 @@ embedded-storage-async = "0.4.0"
cfg-if = "1.0.0"
document-features = "0.2.7"
+nrf51-pac = { version = "0.12.0", optional = true }
nrf52805-pac = { version = "0.12.0", optional = true }
nrf52810-pac = { version = "0.12.0", optional = true }
nrf52811-pac = { version = "0.12.0", optional = true }
diff --git a/embassy-nrf/src/chips/nrf51.rs b/embassy-nrf/src/chips/nrf51.rs
new file mode 100644
index 000000000..f5db4b847
--- /dev/null
+++ b/embassy-nrf/src/chips/nrf51.rs
@@ -0,0 +1,168 @@
+pub use nrf51_pac as pac;
+
+/// The maximum buffer size that the EasyDMA can send/recv in one operation.
+pub const EASY_DMA_SIZE: usize = (1 << 14) - 1;
+pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
+
+pub const FLASH_SIZE: usize = 128 * 1024;
+
+embassy_hal_internal::peripherals! {
+ // RTC
+ RTC0,
+ RTC1,
+
+ // WDT
+ WDT,
+
+ // NVMC
+ NVMC,
+
+ // RNG
+ RNG,
+
+ // UARTE
+ UART0,
+
+ // SPI/TWI
+ TWI0,
+ SPI0,
+
+ // ADC
+ ADC,
+
+ // TIMER
+ TIMER0,
+ TIMER1,
+ TIMER2,
+
+ // GPIOTE
+ GPIOTE_CH0,
+ GPIOTE_CH1,
+ GPIOTE_CH2,
+ GPIOTE_CH3,
+
+ // PPI
+ PPI_CH0,
+ PPI_CH1,
+ PPI_CH2,
+ PPI_CH3,
+ PPI_CH4,
+ PPI_CH5,
+ PPI_CH6,
+ PPI_CH7,
+ PPI_CH8,
+ PPI_CH9,
+ PPI_CH10,
+ PPI_CH11,
+ PPI_CH12,
+ PPI_CH13,
+ PPI_CH14,
+ PPI_CH15,
+
+ PPI_GROUP0,
+ PPI_GROUP1,
+ PPI_GROUP2,
+ PPI_GROUP3,
+
+ // GPIO port 0
+ P0_00,
+ P0_01,
+ P0_02,
+ P0_03,
+ P0_04,
+ P0_05,
+ P0_06,
+ P0_07,
+ P0_08,
+ P0_09,
+ P0_10,
+ P0_11,
+ P0_12,
+ P0_13,
+ P0_14,
+ P0_15,
+ P0_16,
+ P0_17,
+ P0_18,
+ P0_19,
+ P0_20,
+ P0_21,
+ P0_22,
+ P0_23,
+ P0_24,
+ P0_25,
+ P0_26,
+ P0_27,
+ P0_28,
+ P0_29,
+ P0_30,
+ P0_31,
+
+ // TEMP
+ TEMP,
+}
+
+// impl_timer!(TIMER0, TIMER0, TIMER0);
+// impl_timer!(TIMER1, TIMER1, TIMER1);
+// impl_timer!(TIMER2, TIMER2, TIMER2);
+
+impl_pin!(P0_00, 0, 0);
+impl_pin!(P0_01, 0, 1);
+impl_pin!(P0_02, 0, 2);
+impl_pin!(P0_03, 0, 3);
+impl_pin!(P0_04, 0, 4);
+impl_pin!(P0_05, 0, 5);
+impl_pin!(P0_06, 0, 6);
+impl_pin!(P0_07, 0, 7);
+impl_pin!(P0_08, 0, 8);
+impl_pin!(P0_09, 0, 9);
+impl_pin!(P0_10, 0, 10);
+impl_pin!(P0_11, 0, 11);
+impl_pin!(P0_12, 0, 12);
+impl_pin!(P0_13, 0, 13);
+impl_pin!(P0_14, 0, 14);
+impl_pin!(P0_15, 0, 15);
+impl_pin!(P0_16, 0, 16);
+impl_pin!(P0_17, 0, 17);
+impl_pin!(P0_18, 0, 18);
+impl_pin!(P0_19, 0, 19);
+impl_pin!(P0_20, 0, 20);
+impl_pin!(P0_21, 0, 21);
+impl_pin!(P0_22, 0, 22);
+impl_pin!(P0_23, 0, 23);
+impl_pin!(P0_24, 0, 24);
+impl_pin!(P0_25, 0, 25);
+impl_pin!(P0_26, 0, 26);
+impl_pin!(P0_27, 0, 27);
+impl_pin!(P0_28, 0, 28);
+impl_pin!(P0_29, 0, 29);
+impl_pin!(P0_30, 0, 30);
+impl_pin!(P0_31, 0, 31);
+
+embassy_hal_internal::interrupt_mod!(
+ POWER_CLOCK,
+ RADIO,
+ UART0,
+ SPI0_TWI0,
+ SPI1_TWI1,
+ GPIOTE,
+ ADC,
+ TIMER0,
+ TIMER1,
+ TIMER2,
+ RTC0,
+ TEMP,
+ RNG,
+ ECB,
+ CCM_AAR,
+ WDT,
+ RTC1,
+ QDEC,
+ LPCOMP,
+ SWI0,
+ SWI1,
+ SWI2,
+ SWI3,
+ SWI4,
+ SWI5,
+);
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index 287811e61..164363460 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -8,8 +8,17 @@ use cfg_if::cfg_if;
use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
use self::sealed::Pin as _;
+
+#[cfg(not(feature = "nrf51"))]
use crate::pac::p0 as gpio;
+#[cfg(not(feature = "nrf51"))]
use crate::pac::p0::pin_cnf::{DRIVE_A, PULL_A};
+
+#[cfg(feature = "nrf51")]
+use crate::pac::gpio;
+#[cfg(feature = "nrf51")]
+use crate::pac::gpio::pin_cnf::{DRIVE_A, PULL_A};
+
use crate::{pac, Peripheral};
/// A GPIO port with up to 32 pins.
@@ -376,6 +385,9 @@ pub(crate) mod sealed {
fn block(&self) -> &gpio::RegisterBlock {
unsafe {
match self.pin_port() / 32 {
+ #[cfg(feature = "nrf51")]
+ 0 => &*pac::GPIO::ptr(),
+ #[cfg(not(feature = "nrf51"))]
0 => &*pac::P0::ptr(),
#[cfg(feature = "_gpio-p1")]
1 => &*pac::P1::ptr(),
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index d9c92a76d..923e48ec2 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -40,6 +40,7 @@ pub(crate) mod util;
#[cfg(feature = "_time-driver")]
mod time_driver;
+#[cfg(not(feature = "nrf51"))]
pub mod buffered_uarte;
pub mod gpio;
#[cfg(feature = "gpiote")]
@@ -58,7 +59,12 @@ pub mod nvmc;
))]
pub mod pdm;
pub mod ppi;
-#[cfg(not(any(feature = "nrf52805", feature = "nrf52820", feature = "_nrf5340-net")))]
+#[cfg(not(any(
+ feature = "nrf51",
+ feature = "nrf52805",
+ feature = "nrf52820",
+ feature = "_nrf5340-net"
+)))]
pub mod pwm;
#[cfg(not(any(feature = "nrf51", feature = "_nrf9160", feature = "_nrf5340-net")))]
pub mod qdec;
@@ -66,15 +72,20 @@ pub mod qdec;
pub mod qspi;
#[cfg(not(any(feature = "_nrf5340-app", feature = "_nrf9160")))]
pub mod rng;
-#[cfg(not(any(feature = "nrf52820", feature = "_nrf5340-net")))]
+#[cfg(not(any(feature = "nrf51", feature = "nrf52820", feature = "_nrf5340-net")))]
pub mod saadc;
+#[cfg(not(feature = "nrf51"))]
pub mod spim;
+#[cfg(not(feature = "nrf51"))]
pub mod spis;
#[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
pub mod temp;
pub mod timer;
+#[cfg(not(feature = "nrf51"))]
pub mod twim;
+#[cfg(not(feature = "nrf51"))]
pub mod twis;
+#[cfg(not(feature = "nrf51"))]
pub mod uarte;
#[cfg(any(
feature = "_nrf5340-app",
@@ -87,6 +98,7 @@ pub mod usb;
pub mod wdt;
// This mod MUST go last, so that it sees all the `impl_foo!` macros
+#[cfg_attr(feature = "nrf51", path = "chips/nrf51.rs")]
#[cfg_attr(feature = "nrf52805", path = "chips/nrf52805.rs")]
#[cfg_attr(feature = "nrf52810", path = "chips/nrf52810.rs")]
#[cfg_attr(feature = "nrf52811", path = "chips/nrf52811.rs")]
@@ -374,6 +386,7 @@ pub fn init(config: config::Config) -> Peripherals {
let mut needs_reset = false;
// Setup debug protection.
+ #[cfg(not(feature = "nrf51"))]
match config.debug {
config::Debug::Allowed => {
#[cfg(feature = "_nrf52")]
@@ -489,7 +502,7 @@ pub fn init(config: config::Config) -> Peripherals {
}
// Configure LFCLK.
- #[cfg(not(any(feature = "_nrf5340", feature = "_nrf9160")))]
+ #[cfg(not(any(feature = "nrf51", feature = "_nrf5340", feature = "_nrf9160")))]
match config.lfclk_source {
config::LfclkSource::InternalRC => r.lfclksrc.write(|w| w.src().rc()),
config::LfclkSource::Synthesized => r.lfclksrc.write(|w| w.src().synth()),
diff --git a/embassy-nrf/src/ppi/ppi.rs b/embassy-nrf/src/ppi/ppi.rs
index 3e9e9fc81..4a12764ad 100644
--- a/embassy-nrf/src/ppi/ppi.rs
+++ b/embassy-nrf/src/ppi/ppi.rs
@@ -84,6 +84,7 @@ impl<'d, C: Channel, const EVENT_COUNT: usize, const TASK_COUNT: usize> Drop for
let n = self.ch.number();
r.ch[n].eep.write(|w| unsafe { w.bits(0) });
r.ch[n].tep.write(|w| unsafe { w.bits(0) });
+ #[cfg(not(feature = "nrf51"))]
r.fork[n].tep.write(|w| unsafe { w.bits(0) });
}
}
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index e2803f0d3..7f2e76a55 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -5,7 +5,7 @@
use core::future::poll_fn;
use core::marker::PhantomData;
use core::ptr;
-use core::sync::atomic::{AtomicPtr, Ordering};
+use portable_atomic::{AtomicPtr, Ordering};
use core::task::Poll;
use embassy_hal_internal::drop::OnDrop;
diff --git a/embassy-nrf/src/time_driver.rs b/embassy-nrf/src/time_driver.rs
index 042f7c5f7..855d133df 100644
--- a/embassy-nrf/src/time_driver.rs
+++ b/embassy-nrf/src/time_driver.rs
@@ -1,6 +1,6 @@
use core::cell::Cell;
-use core::sync::atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use core::{mem, ptr};
+use portable_atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use critical_section::CriticalSection;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
diff --git a/embassy-nrf/src/timer.rs b/embassy-nrf/src/timer.rs
index 3dbfdac42..272fffc0a 100644
--- a/embassy-nrf/src/timer.rs
+++ b/embassy-nrf/src/timer.rs
@@ -122,12 +122,16 @@ impl<'d, T: Instance> Timer<'d, T> {
// since changing BITMODE while running can cause 'unpredictable behaviour' according to the specification.
this.stop();
+ #[cfg(not(feature = "nrf51"))]
if is_counter {
regs.mode.write(|w| w.mode().low_power_counter());
} else {
regs.mode.write(|w| w.mode().timer());
}
+ #[cfg(feature = "nrf51")]
+ regs.mode.write(|w| w.mode().timer());
+
// Make the counter's max value as high as possible.
// TODO: is there a reason someone would want to set this lower?
regs.bitmode.write(|w| w.bitmode()._32bit());
@@ -238,7 +242,11 @@ pub struct Cc<'d, T: Instance> {
impl<'d, T: Instance> Cc<'d, T> {
/// Get the current value stored in the register.
pub fn read(&self) -> u32 {
- T::regs().cc[self.n].read().cc().bits()
+ #[cfg(not(feature = "nrf51"))]
+ return T::regs().cc[self.n].read().cc().bits();
+
+ #[cfg(feature = "nrf51")]
+ return T::regs().cc[self.n].read().bits();
}
/// Set the value stored in the register.
@@ -246,7 +254,11 @@ impl<'d, T: Instance> Cc<'d, T> {
/// `event_compare` will fire when the timer's counter reaches this value.
pub fn write(&self, value: u32) {
// SAFETY: there are no invalid values for the CC register.
- T::regs().cc[self.n].write(|w| unsafe { w.cc().bits(value) })
+ #[cfg(not(feature = "nrf51"))]
+ T::regs().cc[self.n].write(|w| unsafe { w.cc().bits(value) });
+
+ #[cfg(feature = "nrf51")]
+ T::regs().cc[self.n].write(|w| unsafe { w.bits(value) });
}
/// Capture the current value of the timer's counter in this register, and return it.
diff --git a/examples/nrf51/.cargo/config.toml b/examples/nrf51/.cargo/config.toml
new file mode 100644
index 000000000..84f0e1572
--- /dev/null
+++ b/examples/nrf51/.cargo/config.toml
@@ -0,0 +1,9 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# replace nRF82840_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF51822_xxAA"
+
+[build]
+target = "thumbv6m-none-eabi"
+
+[env]
+DEFMT_LOG = "trace"
diff --git a/examples/nrf51/Cargo.toml b/examples/nrf51/Cargo.toml
new file mode 100644
index 000000000..8507c415c
--- /dev/null
+++ b/examples/nrf51/Cargo.toml
@@ -0,0 +1,20 @@
+[package]
+edition = "2021"
+name = "embassy-nrf51-examples"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+
+[dependencies]
+embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-8192", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
+embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
+
+defmt = "0.3"
+defmt-rtt = "0.4"
+
+cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
+cortex-m-rt = "0.7"
+panic-probe = { version = "0.3", features = ["print-defmt"] }
+
+[profile.release]
+debug = 2
diff --git a/examples/nrf51/build.rs b/examples/nrf51/build.rs
new file mode 100644
index 000000000..30691aa97
--- /dev/null
+++ b/examples/nrf51/build.rs
@@ -0,0 +1,35 @@
+//! This build script copies the `memory.x` file from the crate root into
+//! a directory where the linker can always find it at build time.
+//! For many projects this is optional, as the linker always searches the
+//! project root directory -- wherever `Cargo.toml` is. However, if you
+//! are using a workspace or have a more complicated build setup, this
+//! build script becomes required. Additionally, by requesting that
+//! Cargo re-run the build script whenever `memory.x` is changed,
+//! updating `memory.x` ensures a rebuild of the application with the
+//! new memory settings.
+
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+ // Put `memory.x` in our output directory and ensure it's
+ // on the linker search path.
+ let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+ File::create(out.join("memory.x"))
+ .unwrap()
+ .write_all(include_bytes!("memory.x"))
+ .unwrap();
+ println!("cargo:rustc-link-search={}", out.display());
+
+ // By default, Cargo will re-run a build script whenever
+ // any file in the project changes. By specifying `memory.x`
+ // here, we ensure the build script is only re-run when
+ // `memory.x` is changed.
+ println!("cargo:rerun-if-changed=memory.x");
+
+ println!("cargo:rustc-link-arg-bins=--nmagic");
+ println!("cargo:rustc-link-arg-bins=-Tlink.x");
+ println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+}
diff --git a/examples/nrf51/memory.x b/examples/nrf51/memory.x
new file mode 100644
index 000000000..ad5f80292
--- /dev/null
+++ b/examples/nrf51/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+ FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+ RAM : ORIGIN = 0x20000000, LENGTH = 32K
+}
diff --git a/examples/nrf51/src/bin/blinky.rs b/examples/nrf51/src/bin/blinky.rs
new file mode 100644
index 000000000..ff686c6ae
--- /dev/null
+++ b/examples/nrf51/src/bin/blinky.rs
@@ -0,0 +1,21 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_nrf::gpio::{Level, Output, OutputDrive};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+
+ let p = embassy_nrf::init(Default::default());
+ let mut led = Output::new(p.P0_21, Level::Low, OutputDrive::Standard);
+
+ loop {
+ led.set_high();
+ Timer::after_millis(300).await;
+ led.set_low();
+ Timer::after_millis(300).await;
+ }
+}
From 2a810a1a6ad5351ef2248133855dc01ba4b7a76b Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Sat, 20 Jan 2024 16:23:12 +0100
Subject: [PATCH 047/392] rustfmt
---
embassy-nrf/src/rng.rs | 2 +-
examples/nrf51/src/bin/blinky.rs | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index 7f2e76a55..79088b25d 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -5,8 +5,8 @@
use core::future::poll_fn;
use core::marker::PhantomData;
use core::ptr;
-use portable_atomic::{AtomicPtr, Ordering};
use core::task::Poll;
+use portable_atomic::{AtomicPtr, Ordering};
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
diff --git a/examples/nrf51/src/bin/blinky.rs b/examples/nrf51/src/bin/blinky.rs
index ff686c6ae..7c12ffcbc 100644
--- a/examples/nrf51/src/bin/blinky.rs
+++ b/examples/nrf51/src/bin/blinky.rs
@@ -8,7 +8,6 @@ use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
-
let p = embassy_nrf::init(Default::default());
let mut led = Output::new(p.P0_21, Level::Low, OutputDrive::Standard);
From 53ea850d289384ea1810419b980ad73bcd556a04 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Sat, 20 Jan 2024 16:24:02 +0100
Subject: [PATCH 048/392] rustfmt again
---
embassy-nrf/src/gpio.rs | 11 ++++-------
embassy-nrf/src/rng.rs | 2 +-
embassy-nrf/src/time_driver.rs | 2 +-
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index 164363460..b1eb8ae87 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -8,17 +8,14 @@ use cfg_if::cfg_if;
use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
use self::sealed::Pin as _;
-
-#[cfg(not(feature = "nrf51"))]
-use crate::pac::p0 as gpio;
-#[cfg(not(feature = "nrf51"))]
-use crate::pac::p0::pin_cnf::{DRIVE_A, PULL_A};
-
#[cfg(feature = "nrf51")]
use crate::pac::gpio;
#[cfg(feature = "nrf51")]
use crate::pac::gpio::pin_cnf::{DRIVE_A, PULL_A};
-
+#[cfg(not(feature = "nrf51"))]
+use crate::pac::p0 as gpio;
+#[cfg(not(feature = "nrf51"))]
+use crate::pac::p0::pin_cnf::{DRIVE_A, PULL_A};
use crate::{pac, Peripheral};
/// A GPIO port with up to 32 pins.
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index 79088b25d..966097578 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -6,11 +6,11 @@ use core::future::poll_fn;
use core::marker::PhantomData;
use core::ptr;
use core::task::Poll;
-use portable_atomic::{AtomicPtr, Ordering};
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
+use portable_atomic::{AtomicPtr, Ordering};
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, Peripheral};
diff --git a/embassy-nrf/src/time_driver.rs b/embassy-nrf/src/time_driver.rs
index 855d133df..0f31c5c9c 100644
--- a/embassy-nrf/src/time_driver.rs
+++ b/embassy-nrf/src/time_driver.rs
@@ -1,11 +1,11 @@
use core::cell::Cell;
use core::{mem, ptr};
-use portable_atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use critical_section::CriticalSection;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
use embassy_time_driver::{AlarmHandle, Driver};
+use portable_atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use crate::interrupt::InterruptExt;
use crate::{interrupt, pac};
From 25f82538aed809c17264bab8cddad30004fb60cf Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Sat, 20 Jan 2024 20:56:24 +0100
Subject: [PATCH 049/392] fix doc comment
---
examples/nrf51/.cargo/config.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/nrf51/.cargo/config.toml b/examples/nrf51/.cargo/config.toml
index 84f0e1572..29d35a9b4 100644
--- a/examples/nrf51/.cargo/config.toml
+++ b/examples/nrf51/.cargo/config.toml
@@ -1,5 +1,5 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace nRF82840_xxAA with your chip as listed in `probe-rs chip list`
+# replace nRF51822_xxAA with your chip as listed in `probe-rs chip list`
runner = "probe-rs run --chip nRF51822_xxAA"
[build]
From 6126183db852fbf4187d4a5516cc8bd6d3697443 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Tue, 23 Jan 2024 23:16:06 +0100
Subject: [PATCH 050/392] fix: remove portable-atomic from rng
---
embassy-nrf/src/rng.rs | 127 ++++++++++++++++++++++-------------------
1 file changed, 67 insertions(+), 60 deletions(-)
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index 966097578..6145dd14f 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -9,8 +9,6 @@ use core::task::Poll;
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
-use embassy_sync::waitqueue::AtomicWaker;
-use portable_atomic::{AtomicPtr, Ordering};
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, Peripheral};
@@ -22,7 +20,6 @@ pub struct InterruptHandler<T: Instance> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
- let s = T::state();
let r = T::regs();
// Clear the event.
@@ -30,46 +27,26 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
// Mutate the slice within a critical section,
// so that the future isn't dropped in between us loading the pointer and actually dereferencing it.
- let (ptr, end) = critical_section::with(|_| {
- let ptr = s.ptr.load(Ordering::Relaxed);
+ critical_section::with(|cs| {
+ let mut state = T::state().borrow_mut(cs);
// We need to make sure we haven't already filled the whole slice,
// in case the interrupt fired again before the executor got back to the future.
- let end = s.end.load(Ordering::Relaxed);
- if !ptr.is_null() && ptr != end {
+ if !state.ptr.is_null() && state.ptr != state.end {
// If the future was dropped, the pointer would have been set to null,
// so we're still good to mutate the slice.
// The safety contract of `Rng::new` means that the future can't have been dropped
// without calling its destructor.
unsafe {
- *ptr = r.value.read().value().bits();
+ *state.ptr = r.value.read().value().bits();
+ state.ptr = state.ptr.add(1);
}
+
+ if state.ptr == state.end {
+ state.waker.wake();
+ }
+
}
- (ptr, end)
});
-
- if ptr.is_null() || ptr == end {
- // If the future was dropped, there's nothing to do.
- // If `ptr == end`, we were called by mistake, so return.
- return;
- }
-
- let new_ptr = unsafe { ptr.add(1) };
- match s
- .ptr
- .compare_exchange(ptr, new_ptr, Ordering::Relaxed, Ordering::Relaxed)
- {
- Ok(_) => {
- let end = s.end.load(Ordering::Relaxed);
- // It doesn't matter if `end` was changed under our feet, because then this will just be false.
- if new_ptr == end {
- s.waker.wake();
- }
- }
- Err(_) => {
- // If the future was dropped or finished, there's no point trying to wake it.
- // It will have already stopped the RNG, so there's no need to do that either.
- }
- }
}
}
@@ -136,13 +113,15 @@ impl<'d, T: Instance> Rng<'d, T> {
return; // Nothing to fill
}
- let s = T::state();
let range = dest.as_mut_ptr_range();
// Even if we've preempted the interrupt, it can't preempt us again,
// so we don't need to worry about the order we write these in.
- s.ptr.store(range.start, Ordering::Relaxed);
- s.end.store(range.end, Ordering::Relaxed);
+ critical_section::with(|cs| {
+ let mut state = T::state().borrow_mut(cs);
+ state.ptr = range.start;
+ state.end = range.end;
+ });
self.enable_irq();
self.start();
@@ -151,24 +130,24 @@ impl<'d, T: Instance> Rng<'d, T> {
self.stop();
self.disable_irq();
- // The interrupt is now disabled and can't preempt us anymore, so the order doesn't matter here.
- s.ptr.store(ptr::null_mut(), Ordering::Relaxed);
- s.end.store(ptr::null_mut(), Ordering::Relaxed);
+ critical_section::with(|cs| {
+ let mut state = T::state().borrow_mut(cs);
+ state.ptr = ptr::null_mut();
+ state.end = ptr::null_mut();
+ });
});
poll_fn(|cx| {
- s.waker.register(cx.waker());
-
- // The interrupt will never modify `end`, so load it first and then get the most up-to-date `ptr`.
- let end = s.end.load(Ordering::Relaxed);
- let ptr = s.ptr.load(Ordering::Relaxed);
-
- if ptr == end {
- // We're done.
- Poll::Ready(())
- } else {
- Poll::Pending
- }
+ critical_section::with(|cs| {
+ let mut s = T::state().borrow_mut(cs);
+ s.waker.register(cx.waker());
+ if s.ptr == s.end {
+ // We're done.
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
})
.await;
@@ -194,9 +173,11 @@ impl<'d, T: Instance> Rng<'d, T> {
impl<'d, T: Instance> Drop for Rng<'d, T> {
fn drop(&mut self) {
self.stop();
- let s = T::state();
- s.ptr.store(ptr::null_mut(), Ordering::Relaxed);
- s.end.store(ptr::null_mut(), Ordering::Relaxed);
+ critical_section::with(|cs| {
+ let mut state = T::state().borrow_mut(cs);
+ state.ptr = ptr::null_mut();
+ state.end = ptr::null_mut();
+ });
}
}
@@ -227,21 +208,47 @@ impl<'d, T: Instance> rand_core::RngCore for Rng<'d, T> {
impl<'d, T: Instance> rand_core::CryptoRng for Rng<'d, T> {}
pub(crate) mod sealed {
+ use core::cell::{Ref, RefMut, RefCell};
+
+ use critical_section::Mutex;
+ use critical_section::CriticalSection;
+ use embassy_sync::waitqueue::WakerRegistration;
+
use super::*;
/// Peripheral static state
pub struct State {
- pub ptr: AtomicPtr<u8>,
- pub end: AtomicPtr<u8>,
- pub waker: AtomicWaker,
+ inner: Mutex<RefCell<InnerState>>,
+ }
+
+ pub struct InnerState {
+ pub ptr: *mut u8,
+ pub end: *mut u8,
+ pub waker: WakerRegistration,
}
impl State {
pub const fn new() -> Self {
Self {
- ptr: AtomicPtr::new(ptr::null_mut()),
- end: AtomicPtr::new(ptr::null_mut()),
- waker: AtomicWaker::new(),
+ inner: Mutex::new(RefCell::new(InnerState::new())),
+ }
+ }
+
+ pub fn borrow<'cs>(&'cs self, cs: CriticalSection<'cs>) -> Ref<'cs, InnerState> {
+ self.inner.borrow(cs).borrow()
+ }
+
+ pub fn borrow_mut<'cs>(&'cs self, cs: CriticalSection<'cs>) -> RefMut<'cs, InnerState> {
+ self.inner.borrow(cs).borrow_mut()
+ }
+ }
+
+ impl InnerState {
+ pub const fn new() -> Self {
+ Self {
+ ptr: ptr::null_mut(),
+ end: ptr::null_mut(),
+ waker: WakerRegistration::new(),
}
}
}
From 00d66cce1db71511b1a872a837c2d5dd0c22a598 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Wed, 24 Jan 2024 19:27:55 +0100
Subject: [PATCH 051/392] modify time driver to not require portable-atomic
---
embassy-nrf/src/time_driver.rs | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/embassy-nrf/src/time_driver.rs b/embassy-nrf/src/time_driver.rs
index 0f31c5c9c..b41169c01 100644
--- a/embassy-nrf/src/time_driver.rs
+++ b/embassy-nrf/src/time_driver.rs
@@ -1,11 +1,11 @@
use core::cell::Cell;
use core::{mem, ptr};
+use core::sync::atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use critical_section::CriticalSection;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
use embassy_time_driver::{AlarmHandle, Driver};
-use portable_atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use crate::interrupt::InterruptExt;
use crate::{interrupt, pac};
@@ -171,7 +171,8 @@ impl RtcDriver {
fn next_period(&self) {
critical_section::with(|cs| {
let r = rtc();
- let period = self.period.fetch_add(1, Ordering::Relaxed) + 1;
+ let period = self.period.load(Ordering::Relaxed) + 1;
+ self.period.store(period, Ordering::Relaxed);
let t = (period as u64) << 23;
for n in 0..ALARM_COUNT {
@@ -219,18 +220,15 @@ impl Driver for RtcDriver {
}
unsafe fn allocate_alarm(&self) -> Option<AlarmHandle> {
- let id = self.alarm_count.fetch_update(Ordering::AcqRel, Ordering::Acquire, |x| {
- if x < ALARM_COUNT as u8 {
- Some(x + 1)
+ critical_section::with(|_| {
+ let id = self.alarm_count.load(Ordering::Relaxed);
+ if id < ALARM_COUNT as u8 {
+ self.alarm_count.store(id + 1, Ordering::Relaxed);
+ Some(AlarmHandle::new(id))
} else {
None
}
- });
-
- match id {
- Ok(id) => Some(AlarmHandle::new(id)),
- Err(_) => None,
- }
+ })
}
fn set_alarm_callback(&self, alarm: AlarmHandle, callback: fn(*mut ()), ctx: *mut ()) {
From 3ac52b2c4857048d56d943ed24c6d72847e60f0a Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Wed, 24 Jan 2024 19:28:05 +0100
Subject: [PATCH 052/392] remove portable-atomic dependency
---
embassy-nrf/Cargo.toml | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 529a56c46..a682e1227 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -74,7 +74,7 @@ qspi-multiwrite-flash = []
#! ### Chip selection features
## nRF51
-nrf51 = ["nrf51-pac", "_nrf51", "portable-atomic/unsafe-assume-single-core"]
+nrf51 = ["nrf51-pac", "_nrf51"]
## nRF52805
nrf52805 = ["nrf52805-pac", "_nrf52"]
## nRF52810
@@ -137,8 +137,6 @@ embedded-hal-async = { version = "1.0" }
embedded-io = { version = "0.6.0" }
embedded-io-async = { version = "0.6.1" }
-portable-atomic = { version = "1", default-features = false, features = ["require-cas"] }
-
defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
cortex-m-rt = ">=0.6.15,<0.8"
From 7d961a7f447a56a458a556b747710ec3375950d7 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Wed, 24 Jan 2024 19:28:28 +0100
Subject: [PATCH 053/392] cargo fmt
---
embassy-nrf/src/rng.rs | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index 6145dd14f..a65ad5518 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -44,7 +44,6 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
if state.ptr == state.end {
state.waker.wake();
}
-
}
});
}
@@ -113,7 +112,6 @@ impl<'d, T: Instance> Rng<'d, T> {
return; // Nothing to fill
}
-
let range = dest.as_mut_ptr_range();
// Even if we've preempted the interrupt, it can't preempt us again,
// so we don't need to worry about the order we write these in.
@@ -208,10 +206,10 @@ impl<'d, T: Instance> rand_core::RngCore for Rng<'d, T> {
impl<'d, T: Instance> rand_core::CryptoRng for Rng<'d, T> {}
pub(crate) mod sealed {
- use core::cell::{Ref, RefMut, RefCell};
+ use core::cell::{Ref, RefCell, RefMut};
- use critical_section::Mutex;
use critical_section::CriticalSection;
+ use critical_section::Mutex;
use embassy_sync::waitqueue::WakerRegistration;
use super::*;
From 85d7779668ce14abbde4cd8fb1ea9395df529206 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Wed, 24 Jan 2024 19:30:46 +0100
Subject: [PATCH 054/392] rename nrf52 HIL test
---
ci.sh | 2 +-
tests/{nrf => nrf52840}/.cargo/config.toml | 0
tests/{nrf => nrf52840}/Cargo.toml | 0
tests/{nrf => nrf52840}/build.rs | 0
tests/{nrf => nrf52840}/memory.x | 0
tests/{nrf => nrf52840}/src/bin/buffered_uart.rs | 0
tests/{nrf => nrf52840}/src/bin/buffered_uart_full.rs | 0
tests/{nrf => nrf52840}/src/bin/buffered_uart_spam.rs | 0
tests/{nrf => nrf52840}/src/bin/ethernet_enc28j60_perf.rs | 0
tests/{nrf => nrf52840}/src/bin/timer.rs | 0
tests/{nrf => nrf52840}/src/bin/wifi_esp_hosted_perf.rs | 0
11 files changed, 1 insertion(+), 1 deletion(-)
rename tests/{nrf => nrf52840}/.cargo/config.toml (100%)
rename tests/{nrf => nrf52840}/Cargo.toml (100%)
rename tests/{nrf => nrf52840}/build.rs (100%)
rename tests/{nrf => nrf52840}/memory.x (100%)
rename tests/{nrf => nrf52840}/src/bin/buffered_uart.rs (100%)
rename tests/{nrf => nrf52840}/src/bin/buffered_uart_full.rs (100%)
rename tests/{nrf => nrf52840}/src/bin/buffered_uart_spam.rs (100%)
rename tests/{nrf => nrf52840}/src/bin/ethernet_enc28j60_perf.rs (100%)
rename tests/{nrf => nrf52840}/src/bin/timer.rs (100%)
rename tests/{nrf => nrf52840}/src/bin/wifi_esp_hosted_perf.rs (100%)
diff --git a/ci.sh b/ci.sh
index 3322c60d1..cf12f95fd 100755
--- a/ci.sh
+++ b/ci.sh
@@ -211,7 +211,7 @@ cargo batch \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l496zg --out-dir out/tests/stm32l496zg \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc --out-dir out/tests/stm32wl55jc \
--- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
- --- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
+ --- build --release --manifest-path tests/nrf52840/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
--- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
$BUILD_EXTRA
diff --git a/tests/nrf/.cargo/config.toml b/tests/nrf52840/.cargo/config.toml
similarity index 100%
rename from tests/nrf/.cargo/config.toml
rename to tests/nrf52840/.cargo/config.toml
diff --git a/tests/nrf/Cargo.toml b/tests/nrf52840/Cargo.toml
similarity index 100%
rename from tests/nrf/Cargo.toml
rename to tests/nrf52840/Cargo.toml
diff --git a/tests/nrf/build.rs b/tests/nrf52840/build.rs
similarity index 100%
rename from tests/nrf/build.rs
rename to tests/nrf52840/build.rs
diff --git a/tests/nrf/memory.x b/tests/nrf52840/memory.x
similarity index 100%
rename from tests/nrf/memory.x
rename to tests/nrf52840/memory.x
diff --git a/tests/nrf/src/bin/buffered_uart.rs b/tests/nrf52840/src/bin/buffered_uart.rs
similarity index 100%
rename from tests/nrf/src/bin/buffered_uart.rs
rename to tests/nrf52840/src/bin/buffered_uart.rs
diff --git a/tests/nrf/src/bin/buffered_uart_full.rs b/tests/nrf52840/src/bin/buffered_uart_full.rs
similarity index 100%
rename from tests/nrf/src/bin/buffered_uart_full.rs
rename to tests/nrf52840/src/bin/buffered_uart_full.rs
diff --git a/tests/nrf/src/bin/buffered_uart_spam.rs b/tests/nrf52840/src/bin/buffered_uart_spam.rs
similarity index 100%
rename from tests/nrf/src/bin/buffered_uart_spam.rs
rename to tests/nrf52840/src/bin/buffered_uart_spam.rs
diff --git a/tests/nrf/src/bin/ethernet_enc28j60_perf.rs b/tests/nrf52840/src/bin/ethernet_enc28j60_perf.rs
similarity index 100%
rename from tests/nrf/src/bin/ethernet_enc28j60_perf.rs
rename to tests/nrf52840/src/bin/ethernet_enc28j60_perf.rs
diff --git a/tests/nrf/src/bin/timer.rs b/tests/nrf52840/src/bin/timer.rs
similarity index 100%
rename from tests/nrf/src/bin/timer.rs
rename to tests/nrf52840/src/bin/timer.rs
diff --git a/tests/nrf/src/bin/wifi_esp_hosted_perf.rs b/tests/nrf52840/src/bin/wifi_esp_hosted_perf.rs
similarity index 100%
rename from tests/nrf/src/bin/wifi_esp_hosted_perf.rs
rename to tests/nrf52840/src/bin/wifi_esp_hosted_perf.rs
From db0f4a0b91cc89aef58a6345743fb51ffe1be3a4 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Wed, 24 Jan 2024 20:19:34 +0100
Subject: [PATCH 055/392] cleanup
---
embassy-nrf/src/chips/nrf51.rs | 8 +++++---
embassy-nrf/src/ppi/mod.rs | 1 +
embassy-nrf/src/ppi/ppi.rs | 4 ++--
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/embassy-nrf/src/chips/nrf51.rs b/embassy-nrf/src/chips/nrf51.rs
index f5db4b847..e7147ac93 100644
--- a/embassy-nrf/src/chips/nrf51.rs
+++ b/embassy-nrf/src/chips/nrf51.rs
@@ -102,9 +102,11 @@ embassy_hal_internal::peripherals! {
TEMP,
}
-// impl_timer!(TIMER0, TIMER0, TIMER0);
-// impl_timer!(TIMER1, TIMER1, TIMER1);
-// impl_timer!(TIMER2, TIMER2, TIMER2);
+impl_timer!(TIMER0, TIMER0, TIMER0);
+impl_timer!(TIMER1, TIMER1, TIMER1);
+impl_timer!(TIMER2, TIMER2, TIMER2);
+
+impl_rng!(RNG, RNG, RNG);
impl_pin!(P0_00, 0, 0);
impl_pin!(P0_01, 0, 1);
diff --git a/embassy-nrf/src/ppi/mod.rs b/embassy-nrf/src/ppi/mod.rs
index 5b4a64388..f5764b8b7 100644
--- a/embassy-nrf/src/ppi/mod.rs
+++ b/embassy-nrf/src/ppi/mod.rs
@@ -284,6 +284,7 @@ impl ConfigurableChannel for AnyConfigurableChannel {
}
}
+#[cfg(not(feature = "nrf51"))]
macro_rules! impl_ppi_channel {
($type:ident, $number:expr) => {
impl crate::ppi::sealed::Channel for peripherals::$type {}
diff --git a/embassy-nrf/src/ppi/ppi.rs b/embassy-nrf/src/ppi/ppi.rs
index 4a12764ad..8ff52ece3 100644
--- a/embassy-nrf/src/ppi/ppi.rs
+++ b/embassy-nrf/src/ppi/ppi.rs
@@ -1,6 +1,6 @@
use embassy_hal_internal::into_ref;
-use super::{Channel, ConfigurableChannel, Event, Ppi, StaticChannel, Task};
+use super::{Channel, ConfigurableChannel, Event, Ppi, Task};
use crate::{pac, Peripheral};
impl<'d> Task<'d> {
@@ -19,7 +19,7 @@ pub(crate) fn regs() -> &'static pac::ppi::RegisterBlock {
}
#[cfg(not(feature = "nrf51"))] // Not for nrf51 because of the fork task
-impl<'d, C: StaticChannel> Ppi<'d, C, 0, 1> {
+impl<'d, C: super::StaticChannel> Ppi<'d, C, 0, 1> {
/// Configure PPI channel to trigger `task`.
pub fn new_zero_to_one(ch: impl Peripheral<P = C> + 'd, task: Task) -> Self {
into_ref!(ch);
From 1989c229f99b1177133af51d514ba44a5b02fe6f Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 08:38:01 +0100
Subject: [PATCH 056/392] fix: make inner state send as it's protected critical
section
---
embassy-nrf/src/rng.rs | 2 ++
1 file changed, 2 insertions(+)
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index a65ad5518..667637bfa 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -225,6 +225,8 @@ pub(crate) mod sealed {
pub waker: WakerRegistration,
}
+ unsafe impl Send for InnerState {}
+
impl State {
pub const fn new() -> Self {
Self {
From 3739cc069914861d891a21734b3da9418bd01e9f Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 08:38:28 +0100
Subject: [PATCH 057/392] fix warnings
---
embassy-nrf/src/chips/nrf51.rs | 1 -
embassy-nrf/src/gpio.rs | 1 +
embassy-nrf/src/lib.rs | 4 ++++
embassy-nrf/src/timer.rs | 4 ++--
embassy-nrf/src/util.rs | 1 +
5 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/embassy-nrf/src/chips/nrf51.rs b/embassy-nrf/src/chips/nrf51.rs
index e7147ac93..016352fb8 100644
--- a/embassy-nrf/src/chips/nrf51.rs
+++ b/embassy-nrf/src/chips/nrf51.rs
@@ -2,7 +2,6 @@ pub use nrf51_pac as pac;
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
pub const EASY_DMA_SIZE: usize = (1 << 14) - 1;
-pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
pub const FLASH_SIZE: usize = 128 * 1024;
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index b1eb8ae87..b2f987109 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -487,6 +487,7 @@ impl<'a, P: Pin> PselBits for Option<PeripheralRef<'a, P>> {
}
}
+#[allow(dead_code)]
pub(crate) fn deconfigure_pin(psel_bits: u32) {
if psel_bits & 0x8000_0000 != 0 {
return;
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 923e48ec2..358a7cc27 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -336,6 +336,7 @@ mod consts {
pub const APPROTECT_DISABLED: u32 = 0x0000_005a;
}
+#[cfg(not(feature = "nrf51"))]
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
enum WriteResult {
@@ -347,10 +348,12 @@ enum WriteResult {
Failed,
}
+#[cfg(not(feature = "nrf51"))]
unsafe fn uicr_write(address: *mut u32, value: u32) -> WriteResult {
uicr_write_masked(address, value, 0xFFFF_FFFF)
}
+#[cfg(not(feature = "nrf51"))]
unsafe fn uicr_write_masked(address: *mut u32, value: u32, mask: u32) -> WriteResult {
let curr_val = address.read_volatile();
if curr_val & mask == value & mask {
@@ -383,6 +386,7 @@ pub fn init(config: config::Config) -> Peripherals {
// before doing anything important.
let peripherals = Peripherals::take();
+ #[allow(unused_mut)]
let mut needs_reset = false;
// Setup debug protection.
diff --git a/embassy-nrf/src/timer.rs b/embassy-nrf/src/timer.rs
index 272fffc0a..3c35baee5 100644
--- a/embassy-nrf/src/timer.rs
+++ b/embassy-nrf/src/timer.rs
@@ -111,7 +111,7 @@ impl<'d, T: Instance> Timer<'d, T> {
Self::new_inner(timer, true)
}
- fn new_inner(timer: impl Peripheral<P = T> + 'd, is_counter: bool) -> Self {
+ fn new_inner(timer: impl Peripheral<P = T> + 'd, _is_counter: bool) -> Self {
into_ref!(timer);
let regs = T::regs();
@@ -123,7 +123,7 @@ impl<'d, T: Instance> Timer<'d, T> {
this.stop();
#[cfg(not(feature = "nrf51"))]
- if is_counter {
+ if _is_counter {
regs.mode.write(|w| w.mode().low_power_counter());
} else {
regs.mode.write(|w| w.mode().timer());
diff --git a/embassy-nrf/src/util.rs b/embassy-nrf/src/util.rs
index cd0f59490..b408c517b 100644
--- a/embassy-nrf/src/util.rs
+++ b/embassy-nrf/src/util.rs
@@ -1,3 +1,4 @@
+#![allow(dead_code)]
use core::mem;
const SRAM_LOWER: usize = 0x2000_0000;
From 1263d28595d7f92e348c866764e6e6275b08967f Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 08:39:25 +0100
Subject: [PATCH 058/392] nightly fmt
---
embassy-nrf/src/rng.rs | 3 +--
embassy-nrf/src/time_driver.rs | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index 667637bfa..40b73231b 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -208,8 +208,7 @@ impl<'d, T: Instance> rand_core::CryptoRng for Rng<'d, T> {}
pub(crate) mod sealed {
use core::cell::{Ref, RefCell, RefMut};
- use critical_section::CriticalSection;
- use critical_section::Mutex;
+ use critical_section::{CriticalSection, Mutex};
use embassy_sync::waitqueue::WakerRegistration;
use super::*;
diff --git a/embassy-nrf/src/time_driver.rs b/embassy-nrf/src/time_driver.rs
index b41169c01..3407c9504 100644
--- a/embassy-nrf/src/time_driver.rs
+++ b/embassy-nrf/src/time_driver.rs
@@ -1,7 +1,7 @@
use core::cell::Cell;
+use core::sync::atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use core::{mem, ptr};
-use core::sync::atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
use critical_section::CriticalSection;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
From 9418f0f9e53ceddfcaefe90a7fd3ad308f440758 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 14:05:45 +0100
Subject: [PATCH 059/392] add HIL test to CI
---
ci.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/ci.sh b/ci.sh
index cf12f95fd..1299dc2c9 100755
--- a/ci.sh
+++ b/ci.sh
@@ -212,6 +212,7 @@ cargo batch \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc --out-dir out/tests/stm32wl55jc \
--- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
--- build --release --manifest-path tests/nrf52840/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
+ --- build --release --manifest-path tests/nrf51822/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/nrf51-dk \
--- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
$BUILD_EXTRA
From 7e6bc64331ad2fad71791ac4e0eb76667212f475 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 14:23:57 +0100
Subject: [PATCH 060/392] fix: add missing hil test project
---
tests/nrf51822/.cargo/config.toml | 9 +++++++++
tests/nrf51822/Cargo.toml | 22 ++++++++++++++++++++++
tests/nrf51822/build.rs | 17 +++++++++++++++++
tests/nrf51822/memory.x | 5 +++++
tests/nrf51822/src/bin/gpio.rs | 28 ++++++++++++++++++++++++++++
tests/nrf51822/src/bin/timer.rs | 25 +++++++++++++++++++++++++
6 files changed, 106 insertions(+)
create mode 100644 tests/nrf51822/.cargo/config.toml
create mode 100644 tests/nrf51822/Cargo.toml
create mode 100644 tests/nrf51822/build.rs
create mode 100644 tests/nrf51822/memory.x
create mode 100644 tests/nrf51822/src/bin/gpio.rs
create mode 100644 tests/nrf51822/src/bin/timer.rs
diff --git a/tests/nrf51822/.cargo/config.toml b/tests/nrf51822/.cargo/config.toml
new file mode 100644
index 000000000..3d0c71092
--- /dev/null
+++ b/tests/nrf51822/.cargo/config.toml
@@ -0,0 +1,9 @@
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+#runner = "teleprobe local run --chip nRF51822_xxAA --elf"
+runner = "teleprobe client run"
+
+[build]
+target = "thumbv6m-none-eabi"
+
+[env]
+DEFMT_LOG = "trace,embassy_hal_internal=debug"
diff --git a/tests/nrf51822/Cargo.toml b/tests/nrf51822/Cargo.toml
new file mode 100644
index 000000000..468fa03fa
--- /dev/null
+++ b/tests/nrf51822/Cargo.toml
@@ -0,0 +1,22 @@
+[package]
+edition = "2021"
+name = "embassy-nrf51822-tests"
+version = "0.1.0"
+license = "MIT OR Apache-2.0"
+
+[dependencies]
+teleprobe-meta = "1"
+
+embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt", ] }
+embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "task-arena-size-8192", "integrated-timers"] }
+embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
+embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac"] }
+embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
+embedded-hal-async = { version = "1.0" }
+
+defmt = "0.3"
+defmt-rtt = "0.4"
+
+cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
+cortex-m-rt = "0.7.0"
+panic-probe = { version = "0.3", features = ["print-defmt"] }
diff --git a/tests/nrf51822/build.rs b/tests/nrf51822/build.rs
new file mode 100644
index 000000000..71c82a70f
--- /dev/null
+++ b/tests/nrf51822/build.rs
@@ -0,0 +1,17 @@
+use std::error::Error;
+use std::path::PathBuf;
+use std::{env, fs};
+
+fn main() -> Result<(), Box<dyn Error>> {
+ let out = PathBuf::from(env::var("OUT_DIR").unwrap());
+ fs::write(out.join("link_ram.x"), include_bytes!("../link_ram_cortex_m.x")).unwrap();
+ println!("cargo:rustc-link-search={}", out.display());
+ println!("cargo:rerun-if-changed=link_ram.x");
+
+ println!("cargo:rustc-link-arg-bins=--nmagic");
+ println!("cargo:rustc-link-arg-bins=-Tlink_ram.x");
+ println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+ println!("cargo:rustc-link-arg-bins=-Tteleprobe.x");
+
+ Ok(())
+}
diff --git a/tests/nrf51822/memory.x b/tests/nrf51822/memory.x
new file mode 100644
index 000000000..c140005ce
--- /dev/null
+++ b/tests/nrf51822/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+ FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+ RAM : ORIGIN = 0x20000000, LENGTH = 32K
+}
diff --git a/tests/nrf51822/src/bin/gpio.rs b/tests/nrf51822/src/bin/gpio.rs
new file mode 100644
index 000000000..6c6bc0839
--- /dev/null
+++ b/tests/nrf51822/src/bin/gpio.rs
@@ -0,0 +1,28 @@
+#![no_std]
+#![no_main]
+teleprobe_meta::target!(b"nrf51-dk");
+
+use defmt::{assert, info};
+use embassy_executor::Spawner;
+use embassy_nrf::gpio::{Input, Level, Output, OutputDrive, Pull};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p = embassy_nrf::init(Default::default());
+
+ let input = Input::new(p.P0_13, Pull::None);
+ let mut output = Output::new(p.P0_14, Level::Low, OutputDrive::Standard);
+
+ output.set_low();
+ Timer::after_millis(1).await;
+ assert!(input.is_low());
+
+ output.set_high();
+ Timer::after_millis(1).await;
+ assert!(input.is_high());
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
diff --git a/tests/nrf51822/src/bin/timer.rs b/tests/nrf51822/src/bin/timer.rs
new file mode 100644
index 000000000..2a147e7ba
--- /dev/null
+++ b/tests/nrf51822/src/bin/timer.rs
@@ -0,0 +1,25 @@
+#![no_std]
+#![no_main]
+teleprobe_meta::target!(b"nrf52840-dk");
+
+use defmt::{assert, info};
+use embassy_executor::Spawner;
+use embassy_time::{Instant, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let _p = embassy_nrf::init(Default::default());
+ info!("Hello World!");
+
+ let start = Instant::now();
+ Timer::after_millis(100).await;
+ let end = Instant::now();
+ let ms = (end - start).as_millis();
+ info!("slept for {} ms", ms);
+ assert!(ms >= 99);
+ assert!(ms < 110);
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
From d19c67023d45ac7482bc05f1cea994abd97d0a2d Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 14:36:51 +0100
Subject: [PATCH 061/392] fix: teleprobe target
---
tests/nrf51822/src/bin/timer.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/nrf51822/src/bin/timer.rs b/tests/nrf51822/src/bin/timer.rs
index 2a147e7ba..93f4c2b1c 100644
--- a/tests/nrf51822/src/bin/timer.rs
+++ b/tests/nrf51822/src/bin/timer.rs
@@ -1,6 +1,6 @@
#![no_std]
#![no_main]
-teleprobe_meta::target!(b"nrf52840-dk");
+teleprobe_meta::target!(b"nrf51-dk");
use defmt::{assert, info};
use embassy_executor::Spawner;
From 309dda057d05cd0c197ffe2befa271e9cad314b7 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 14:39:09 +0100
Subject: [PATCH 062/392] add nrf51 builds to ci
---
ci.sh | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/ci.sh b/ci.sh
index 1299dc2c9..d29a686af 100755
--- a/ci.sh
+++ b/ci.sh
@@ -67,6 +67,9 @@ cargo batch \
--- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,defmt,time \
--- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,defmt,time-driver-rtc1 \
--- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,gpiote,defmt,time,time-driver-rtc1 \
+ --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,defmt,time,time-driver-rtc1 \
+ --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,defmt,time \
+ --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,time \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features time-driver,defmt \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features time-driver,log \
--- build --release --manifest-path embassy-rp/Cargo.toml --target thumbv6m-none-eabi --features time-driver,intrinsics \
@@ -148,6 +151,7 @@ cargo batch \
--- build --release --manifest-path examples/nrf52840/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/nrf52840 \
--- build --release --manifest-path examples/nrf5340/Cargo.toml --target thumbv8m.main-none-eabihf --out-dir out/examples/nrf5340 \
--- build --release --manifest-path examples/nrf9160/Cargo.toml --target thumbv8m.main-none-eabihf --out-dir out/examples/nrf9160 \
+ --- build --release --manifest-path examples/nrf51/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/nrf51 \
--- build --release --manifest-path examples/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/rp \
--- build --release --manifest-path examples/stm32f0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32f0 \
--- build --release --manifest-path examples/stm32f1/Cargo.toml --target thumbv7m-none-eabi --out-dir out/examples/stm32f1 \
From f117213b6ee80c224e781d7bf4e750df49c345a6 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 21:47:49 +0100
Subject: [PATCH 063/392] fix: use nrf51-dk chip variant
---
ci.sh | 2 +-
examples/nrf51/.cargo/config.toml | 4 ++--
tests/{nrf51822 => nrf51422}/.cargo/config.toml | 2 +-
tests/{nrf51822 => nrf51422}/Cargo.toml | 2 +-
tests/{nrf51822 => nrf51422}/build.rs | 0
tests/{nrf51822 => nrf51422}/memory.x | 0
tests/{nrf51822 => nrf51422}/src/bin/gpio.rs | 0
tests/{nrf51822 => nrf51422}/src/bin/timer.rs | 0
8 files changed, 5 insertions(+), 5 deletions(-)
rename tests/{nrf51822 => nrf51422}/.cargo/config.toml (75%)
rename tests/{nrf51822 => nrf51422}/Cargo.toml (96%)
rename tests/{nrf51822 => nrf51422}/build.rs (100%)
rename tests/{nrf51822 => nrf51422}/memory.x (100%)
rename tests/{nrf51822 => nrf51422}/src/bin/gpio.rs (100%)
rename tests/{nrf51822 => nrf51422}/src/bin/timer.rs (100%)
diff --git a/ci.sh b/ci.sh
index d29a686af..6a5e6e3f5 100755
--- a/ci.sh
+++ b/ci.sh
@@ -216,7 +216,7 @@ cargo batch \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc --out-dir out/tests/stm32wl55jc \
--- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
--- build --release --manifest-path tests/nrf52840/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
- --- build --release --manifest-path tests/nrf51822/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/nrf51-dk \
+ --- build --release --manifest-path tests/nrf51422/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/nrf51-dk \
--- build --release --manifest-path tests/riscv32/Cargo.toml --target riscv32imac-unknown-none-elf \
$BUILD_EXTRA
diff --git a/examples/nrf51/.cargo/config.toml b/examples/nrf51/.cargo/config.toml
index 29d35a9b4..1671f5db1 100644
--- a/examples/nrf51/.cargo/config.toml
+++ b/examples/nrf51/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-# replace nRF51822_xxAA with your chip as listed in `probe-rs chip list`
-runner = "probe-rs run --chip nRF51822_xxAA"
+# replace nRF51422_xxAA with your chip as listed in `probe-rs chip list`
+runner = "probe-rs run --chip nRF51422_xxAA"
[build]
target = "thumbv6m-none-eabi"
diff --git a/tests/nrf51822/.cargo/config.toml b/tests/nrf51422/.cargo/config.toml
similarity index 75%
rename from tests/nrf51822/.cargo/config.toml
rename to tests/nrf51422/.cargo/config.toml
index 3d0c71092..634805633 100644
--- a/tests/nrf51822/.cargo/config.toml
+++ b/tests/nrf51422/.cargo/config.toml
@@ -1,5 +1,5 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
-#runner = "teleprobe local run --chip nRF51822_xxAA --elf"
+#runner = "teleprobe local run --chip nRF51422_xxAA --elf"
runner = "teleprobe client run"
[build]
diff --git a/tests/nrf51822/Cargo.toml b/tests/nrf51422/Cargo.toml
similarity index 96%
rename from tests/nrf51822/Cargo.toml
rename to tests/nrf51422/Cargo.toml
index 468fa03fa..d95f122b0 100644
--- a/tests/nrf51822/Cargo.toml
+++ b/tests/nrf51422/Cargo.toml
@@ -1,6 +1,6 @@
[package]
edition = "2021"
-name = "embassy-nrf51822-tests"
+name = "embassy-nrf51-tests"
version = "0.1.0"
license = "MIT OR Apache-2.0"
diff --git a/tests/nrf51822/build.rs b/tests/nrf51422/build.rs
similarity index 100%
rename from tests/nrf51822/build.rs
rename to tests/nrf51422/build.rs
diff --git a/tests/nrf51822/memory.x b/tests/nrf51422/memory.x
similarity index 100%
rename from tests/nrf51822/memory.x
rename to tests/nrf51422/memory.x
diff --git a/tests/nrf51822/src/bin/gpio.rs b/tests/nrf51422/src/bin/gpio.rs
similarity index 100%
rename from tests/nrf51822/src/bin/gpio.rs
rename to tests/nrf51422/src/bin/gpio.rs
diff --git a/tests/nrf51822/src/bin/timer.rs b/tests/nrf51422/src/bin/timer.rs
similarity index 100%
rename from tests/nrf51822/src/bin/timer.rs
rename to tests/nrf51422/src/bin/timer.rs
From b16eca3f21f947dcd4b3fe279bd4f577679428bc Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 21:50:03 +0100
Subject: [PATCH 064/392] adjust memory settings for lower end variant
---
examples/nrf51/memory.x | 4 ++--
tests/nrf51422/memory.x | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/examples/nrf51/memory.x b/examples/nrf51/memory.x
index ad5f80292..98b3c792f 100644
--- a/examples/nrf51/memory.x
+++ b/examples/nrf51/memory.x
@@ -1,5 +1,5 @@
MEMORY
{
- FLASH : ORIGIN = 0x00000000, LENGTH = 256K
- RAM : ORIGIN = 0x20000000, LENGTH = 32K
+ FLASH : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM : ORIGIN = 0x20000000, LENGTH = 16K
}
diff --git a/tests/nrf51422/memory.x b/tests/nrf51422/memory.x
index c140005ce..a5881e66f 100644
--- a/tests/nrf51422/memory.x
+++ b/tests/nrf51422/memory.x
@@ -1,5 +1,5 @@
MEMORY
{
- FLASH : ORIGIN = 0x00000000, LENGTH = 256K
- RAM : ORIGIN = 0x20000000, LENGTH = 32K
+ FLASH : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM : ORIGIN = 0x20000000, LENGTH = 16K
}
From 43553381cda95b75d9de1460d5ea6add6e739134 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Thu, 25 Jan 2024 21:51:23 +0100
Subject: [PATCH 065/392] lower arena for nrf51
---
examples/nrf51/Cargo.toml | 2 +-
tests/nrf51422/Cargo.toml | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/examples/nrf51/Cargo.toml b/examples/nrf51/Cargo.toml
index 8507c415c..d1e919a33 100644
--- a/examples/nrf51/Cargo.toml
+++ b/examples/nrf51/Cargo.toml
@@ -5,7 +5,7 @@ version = "0.1.0"
license = "MIT OR Apache-2.0"
[dependencies]
-embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-8192", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-4096", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
diff --git a/tests/nrf51422/Cargo.toml b/tests/nrf51422/Cargo.toml
index d95f122b0..246b71117 100644
--- a/tests/nrf51422/Cargo.toml
+++ b/tests/nrf51422/Cargo.toml
@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
teleprobe-meta = "1"
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt", ] }
-embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "task-arena-size-8192", "integrated-timers"] }
+embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "task-arena-size-4096", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac"] }
embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
From 3c159205a78cb2cc72e3dfeec1eff80d7b95846d Mon Sep 17 00:00:00 2001
From: Shane Snover <ssnover95@gmail.com>
Date: Thu, 25 Jan 2024 22:30:42 -0700
Subject: [PATCH 066/392] Fix the backticks on the getting started page
---
docs/modules/ROOT/pages/getting_started.adoc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/modules/ROOT/pages/getting_started.adoc b/docs/modules/ROOT/pages/getting_started.adoc
index ab819ac2a..24bde1c1f 100644
--- a/docs/modules/ROOT/pages/getting_started.adoc
+++ b/docs/modules/ROOT/pages/getting_started.adoc
@@ -88,7 +88,7 @@ NOTE: How does the `cargo run` command know how to connect to our board and prog
If you hare having issues when running `cargo run --release`, please check the following:
-* You are specifying the correct `--chip on the command line``, OR
+* You are specifying the correct `--chip` on the command line, OR
* You have set `.cargo/config.toml`'s run line to the correct chip, AND
* You have changed `examples/Cargo.toml`'s HAL (e.g. embassy-stm32) dependency's feature to use the correct chip (replace the existing stm32xxxx feature)
From 2f347ece9149551bd9db1068179f74500641a33e Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 26 Jan 2024 08:00:50 +0100
Subject: [PATCH 067/392] add simplest test
---
tests/nrf51422/src/bin/test.rs | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 tests/nrf51422/src/bin/test.rs
diff --git a/tests/nrf51422/src/bin/test.rs b/tests/nrf51422/src/bin/test.rs
new file mode 100644
index 000000000..591bfbccc
--- /dev/null
+++ b/tests/nrf51422/src/bin/test.rs
@@ -0,0 +1,15 @@
+#![no_std]
+#![no_main]
+teleprobe_meta::target!(b"nrf51-dk");
+
+use defmt::{assert, info};
+use embassy_executor::Spawner;
+use embassy_time::{Instant, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let _p = embassy_nrf::init(Default::default());
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
From 7c21178e378c888963150b879fc9d51684872f9e Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 26 Jan 2024 08:14:11 +0100
Subject: [PATCH 068/392] fix warnings
---
tests/nrf51422/src/bin/test.rs | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/nrf51422/src/bin/test.rs b/tests/nrf51422/src/bin/test.rs
index 591bfbccc..d3ffe26e3 100644
--- a/tests/nrf51422/src/bin/test.rs
+++ b/tests/nrf51422/src/bin/test.rs
@@ -2,9 +2,8 @@
#![no_main]
teleprobe_meta::target!(b"nrf51-dk");
-use defmt::{assert, info};
+use defmt::info;
use embassy_executor::Spawner;
-use embassy_time::{Instant, Timer};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
From 4d8043cade887ecdc8a42e0b9bd9d3b5bcee1dbb Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 26 Jan 2024 08:39:50 +0100
Subject: [PATCH 069/392] assert only at least time slept
Cannot deterministically guarantee the upper bound
---
tests/nrf51422/src/bin/timer.rs | 1 -
tests/nrf52840/src/bin/timer.rs | 1 -
2 files changed, 2 deletions(-)
diff --git a/tests/nrf51422/src/bin/timer.rs b/tests/nrf51422/src/bin/timer.rs
index 93f4c2b1c..cf9ea41a8 100644
--- a/tests/nrf51422/src/bin/timer.rs
+++ b/tests/nrf51422/src/bin/timer.rs
@@ -18,7 +18,6 @@ async fn main(_spawner: Spawner) {
let ms = (end - start).as_millis();
info!("slept for {} ms", ms);
assert!(ms >= 99);
- assert!(ms < 110);
info!("Test OK");
cortex_m::asm::bkpt();
diff --git a/tests/nrf52840/src/bin/timer.rs b/tests/nrf52840/src/bin/timer.rs
index 2a147e7ba..117947a94 100644
--- a/tests/nrf52840/src/bin/timer.rs
+++ b/tests/nrf52840/src/bin/timer.rs
@@ -18,7 +18,6 @@ async fn main(_spawner: Spawner) {
let ms = (end - start).as_millis();
info!("slept for {} ms", ms);
assert!(ms >= 99);
- assert!(ms < 110);
info!("Test OK");
cortex_m::asm::bkpt();
From ee90ee185c150085ee59c873e016b6f88f646b56 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 26 Jan 2024 08:58:23 +0100
Subject: [PATCH 070/392] fix: link nrf51 tests from flash for now
---
tests/nrf51422/Cargo.toml | 4 ++--
tests/nrf51422/build.rs | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/nrf51422/Cargo.toml b/tests/nrf51422/Cargo.toml
index 246b71117..2cab20ac0 100644
--- a/tests/nrf51422/Cargo.toml
+++ b/tests/nrf51422/Cargo.toml
@@ -8,9 +8,9 @@ license = "MIT OR Apache-2.0"
teleprobe-meta = "1"
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt", ] }
-embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "task-arena-size-4096", "integrated-timers"] }
+embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "task-arena-size-128", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac"] }
+embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac", "time"] }
embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
embedded-hal-async = { version = "1.0" }
diff --git a/tests/nrf51422/build.rs b/tests/nrf51422/build.rs
index 71c82a70f..13ebbe4ee 100644
--- a/tests/nrf51422/build.rs
+++ b/tests/nrf51422/build.rs
@@ -4,12 +4,12 @@ use std::{env, fs};
fn main() -> Result<(), Box<dyn Error>> {
let out = PathBuf::from(env::var("OUT_DIR").unwrap());
- fs::write(out.join("link_ram.x"), include_bytes!("../link_ram_cortex_m.x")).unwrap();
+ fs::write(out.join("memory.x"), include_bytes!("memory.x")).unwrap();
println!("cargo:rustc-link-search={}", out.display());
- println!("cargo:rerun-if-changed=link_ram.x");
+ println!("cargo:rerun-if-changed=memory.x");
println!("cargo:rustc-link-arg-bins=--nmagic");
- println!("cargo:rustc-link-arg-bins=-Tlink_ram.x");
+ println!("cargo:rustc-link-arg-bins=-Tlink.x");
println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
println!("cargo:rustc-link-arg-bins=-Tteleprobe.x");
From 0bd9a2f09434c5c67088bce79597c581a900adeb Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 26 Jan 2024 09:03:08 +0100
Subject: [PATCH 071/392] fix gpio test and remove dummy
---
tests/nrf51422/src/bin/gpio.rs | 4 ++--
tests/nrf51422/src/bin/test.rs | 14 --------------
2 files changed, 2 insertions(+), 16 deletions(-)
delete mode 100644 tests/nrf51422/src/bin/test.rs
diff --git a/tests/nrf51422/src/bin/gpio.rs b/tests/nrf51422/src/bin/gpio.rs
index 6c6bc0839..0e5712273 100644
--- a/tests/nrf51422/src/bin/gpio.rs
+++ b/tests/nrf51422/src/bin/gpio.rs
@@ -16,11 +16,11 @@ async fn main(_spawner: Spawner) {
let mut output = Output::new(p.P0_14, Level::Low, OutputDrive::Standard);
output.set_low();
- Timer::after_millis(1).await;
+ Timer::after_millis(10).await;
assert!(input.is_low());
output.set_high();
- Timer::after_millis(1).await;
+ Timer::after_millis(10).await;
assert!(input.is_high());
info!("Test OK");
diff --git a/tests/nrf51422/src/bin/test.rs b/tests/nrf51422/src/bin/test.rs
deleted file mode 100644
index d3ffe26e3..000000000
--- a/tests/nrf51422/src/bin/test.rs
+++ /dev/null
@@ -1,14 +0,0 @@
-#![no_std]
-#![no_main]
-teleprobe_meta::target!(b"nrf51-dk");
-
-use defmt::info;
-use embassy_executor::Spawner;
-use {defmt_rtt as _, panic_probe as _};
-
-#[embassy_executor::main]
-async fn main(_spawner: Spawner) {
- let _p = embassy_nrf::init(Default::default());
- info!("Test OK");
- cortex_m::asm::bkpt();
-}
From bea3c5495a37481c85bcfce8d55f94049e4b89fd Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 26 Jan 2024 09:05:58 +0100
Subject: [PATCH 072/392] use pull-up to ensure we assert the correct change
---
tests/nrf51422/src/bin/gpio.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/nrf51422/src/bin/gpio.rs b/tests/nrf51422/src/bin/gpio.rs
index 0e5712273..6d5a87d0a 100644
--- a/tests/nrf51422/src/bin/gpio.rs
+++ b/tests/nrf51422/src/bin/gpio.rs
@@ -12,7 +12,7 @@ use {defmt_rtt as _, panic_probe as _};
async fn main(_spawner: Spawner) {
let p = embassy_nrf::init(Default::default());
- let input = Input::new(p.P0_13, Pull::None);
+ let input = Input::new(p.P0_13, Pull::Up);
let mut output = Output::new(p.P0_14, Level::Low, OutputDrive::Standard);
output.set_low();
From 531645e5d4650c87df5c0a3e2603a43ee9049f7b Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 26 Jan 2024 09:11:17 +0100
Subject: [PATCH 073/392] docs: mention nrf51
---
embassy-nrf/README.md | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/embassy-nrf/README.md b/embassy-nrf/README.md
index 50662749d..3df5f1fa5 100644
--- a/embassy-nrf/README.md
+++ b/embassy-nrf/README.md
@@ -14,11 +14,12 @@ For a complete list of available peripherals and features, see the [embassy-nrf
The `embassy-nrf` HAL supports most variants of the nRF family:
+* nRF51 ([examples](https://github.com/embassy-rs/embassy/tree/main/examples/nrf51))
* nRF52 ([examples](https://github.com/embassy-rs/embassy/tree/main/examples/nrf52840))
* nRF53 ([examples](https://github.com/embassy-rs/embassy/tree/main/examples/nrf5340))
* nRF91 ([examples](https://github.com/embassy-rs/embassy/tree/main/examples/nrf9160))
-Most peripherals are supported. To check what's available, make sure to pick the MCU you're targeting in the top menu in the [documentation](https://docs.embassy.dev/embassy-nrf).
+Most peripherals are supported, but can vary between chip families. To check what's available, make sure to pick the MCU you're targeting in the top menu in the [documentation](https://docs.embassy.dev/embassy-nrf).
For MCUs with TrustZone support, both Secure (S) and Non-Secure (NS) modes are supported. Running in Secure mode
allows running Rust code without a SPM or TF-M binary, saving flash space and simplifying development.
From d4542f443688d37a204096f68d84710e5c52d3f5 Mon Sep 17 00:00:00 2001
From: Lachezar Lechev <elpiel93@gmail.com>
Date: Fri, 26 Jan 2024 12:36:28 +0200
Subject: [PATCH 074/392] docs(ci): add embassy-usb-dfu to the docs build
---
.github/ci/doc.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/.github/ci/doc.sh b/.github/ci/doc.sh
index 70833f934..d0aff1e43 100755
--- a/.github/ci/doc.sh
+++ b/.github/ci/doc.sh
@@ -35,6 +35,7 @@ docserver-builder -i ./embassy-time-driver -o webroot/crates/embassy-time-driver
docserver-builder -i ./embassy-time-queue-driver -o webroot/crates/embassy-time-queue-driver/git.zup
docserver-builder -i ./embassy-usb -o webroot/crates/embassy-usb/git.zup
+docserver-builder -i ./embassy-usb-dfu -o webroot/crates/embassy-usb-dfu/git.zup
docserver-builder -i ./embassy-usb-driver -o webroot/crates/embassy-usb-driver/git.zup
docserver-builder -i ./embassy-usb-logger -o webroot/crates/embassy-usb-logger/git.zup
From adb024bdbe49ba77b3f30af016c0c2ee184f456b Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Fri, 26 Jan 2024 14:23:51 +0100
Subject: [PATCH 075/392] usb-dfu: add docs metadata.
---
.github/ci/doc.sh | 2 +-
embassy-usb-dfu/Cargo.toml | 14 ++++++++++++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/.github/ci/doc.sh b/.github/ci/doc.sh
index d0aff1e43..7112d8aaa 100755
--- a/.github/ci/doc.sh
+++ b/.github/ci/doc.sh
@@ -1,7 +1,7 @@
#!/bin/bash
## on push branch=main
-set -euo pipefail
+set -euxo pipefail
export RUSTUP_HOME=/ci/cache/rustup
export CARGO_HOME=/ci/cache/cargo
diff --git a/embassy-usb-dfu/Cargo.toml b/embassy-usb-dfu/Cargo.toml
index 1ca5fea42..4d6ffeb5f 100644
--- a/embassy-usb-dfu/Cargo.toml
+++ b/embassy-usb-dfu/Cargo.toml
@@ -12,14 +12,24 @@ categories = [
"asynchronous"
]
-# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+[package.metadata.embassy_docs]
+src_base = "https://github.com/embassy-rs/embassy/blob/embassy-usb-v$VERSION/embassy-usb-dfu/src/"
+src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-usb-dfu/src/"
+features = ["defmt", "cortex-m"]
+target = "thumbv7em-none-eabi"
+flavors = [
+ { name = "dfu", features = [ "dfu" ] },
+ { name = "application", features = [ "application" ] },
+]
+
+[package.metadata.docs.rs]
+features = ["defmt", "cortex-m", "dfu"]
[dependencies]
bitflags = "2.4.1"
cortex-m = { version = "0.7.7", features = ["inline-asm"], optional = true }
defmt = { version = "0.3.5", optional = true }
embassy-boot = { version = "0.2.0", path = "../embassy-boot" }
-# embassy-embedded-hal = { version = "0.1.0", path = "../embassy-embedded-hal" }
embassy-futures = { version = "0.1.1", path = "../embassy-futures" }
embassy-sync = { version = "0.5.0", path = "../embassy-sync" }
embassy-time = { version = "0.3.0", path = "../embassy-time" }
From 31fa0aebd8825fa2faf8ec988f0eda2e62ad4dad Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Fri, 26 Jan 2024 14:26:19 +0100
Subject: [PATCH 076/392] executor: update remove portable-atomic comment.
Fixes #2481
---
embassy-executor/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index d6fe8ee8b..409df0d75 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -41,7 +41,7 @@ critical-section = "1.1"
document-features = "0.2.7"
# needed for riscv and avr
-# remove when https://github.com/rust-lang/rust/pull/114499 is merged
+# remove when https://github.com/rust-lang/rust/pull/114499 lands on stable (on 1.76)
portable-atomic = { version = "1.5", optional = true }
# arch-cortex-m dependencies
From dd2577fcf06cd2805097769b4fcad4e0feea5639 Mon Sep 17 00:00:00 2001
From: Martin Marmsoler <martin.marmsoler@gmail.com>
Date: Fri, 26 Jan 2024 20:55:53 +0100
Subject: [PATCH 077/392] use constant for the pwm clock
Description: So it can be used outside of the crate to calculate max duty
---
embassy-nrf/src/pwm.rs | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index 2f0397632..197ba640c 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -47,6 +47,7 @@ pub enum Error {
}
const MAX_SEQUENCE_LEN: usize = 32767;
+pub const PWM_CLK_HZ: u32 = 16_000_000;
impl<'d, T: Instance> SequencePwm<'d, T> {
/// Create a new 1-channel PWM
@@ -788,7 +789,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
/// Sets the PWM output frequency.
#[inline(always)]
pub fn set_period(&self, freq: u32) {
- let clk = 16_000_000u32 >> (self.prescaler() as u8);
+ let clk = PWM_CLK_HZ >> (self.prescaler() as u8);
let duty = clk / freq;
self.set_max_duty(duty.min(32767) as u16);
}
@@ -796,7 +797,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
/// Returns the PWM output frequency.
#[inline(always)]
pub fn period(&self) -> u32 {
- let clk = 16_000_000u32 >> (self.prescaler() as u8);
+ let clk = PWM_CLK_HZ >> (self.prescaler() as u8);
let max_duty = self.max_duty() as u32;
clk / max_duty
}
From c26e62e4f4a17e4c7165b7e2b9fc7c7b0f670960 Mon Sep 17 00:00:00 2001
From: Martin Marmsoler <martin.marmsoler@gmail.com>
Date: Fri, 26 Jan 2024 21:24:14 +0100
Subject: [PATCH 078/392] add documentation
---
embassy-nrf/src/pwm.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index 197ba640c..03354abf8 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -47,6 +47,7 @@ pub enum Error {
}
const MAX_SEQUENCE_LEN: usize = 32767;
+/// The used pwm clock frequency
pub const PWM_CLK_HZ: u32 = 16_000_000;
impl<'d, T: Instance> SequencePwm<'d, T> {
From 2809d3bd45c9d469ae398d55f8d2c4bfda33c9dd Mon Sep 17 00:00:00 2001
From: Martin Marmsoler <martin.marmsoler@gmail.com>
Date: Fri, 26 Jan 2024 22:09:49 +0100
Subject: [PATCH 079/392] add is_enabled() function
---
embassy-nrf/src/pwm.rs | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index 03354abf8..856e12024 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -715,6 +715,13 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
pwm
}
+ /// Returns the enable state of the pwm counter
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ let r = T::regs();
+ r.enable.read().enable().bit_is_set()
+ }
+
/// Enables the PWM generator.
#[inline(always)]
pub fn enable(&self) {
From 6efb5fd28425876ad72faa8bbc34facd7f3e3f81 Mon Sep 17 00:00:00 2001
From: Matthew Tran <0e4ef622@gmail.com>
Date: Fri, 26 Jan 2024 22:38:03 -0600
Subject: [PATCH 080/392] nrf/spi: add bit order config
---
embassy-nrf/src/spim.rs | 13 +++++++++----
embassy-nrf/src/spis.rs | 13 +++++++++----
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index b0723d495..6b6f79188 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -10,6 +10,7 @@ use core::task::Poll;
use embassy_embedded_hal::SetConfig;
use embassy_hal_internal::{into_ref, PeripheralRef};
pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+pub use pac::spim0::config::ORDER_A as BitOrder;
pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
use crate::chip::FORCE_COPY_BUFFER_SIZE;
@@ -41,6 +42,9 @@ pub struct Config {
/// SPI mode
pub mode: Mode,
+ /// Bit order
+ pub bit_order: BitOrder,
+
/// Overread character.
///
/// When doing bidirectional transfers, if the TX buffer is shorter than the RX buffer,
@@ -53,6 +57,7 @@ impl Default for Config {
Self {
frequency: Frequency::M1,
mode: MODE_0,
+ bit_order: BitOrder::MSB_FIRST,
orc: 0x00,
}
}
@@ -580,22 +585,22 @@ impl<'d, T: Instance> SetConfig for Spim<'d, T> {
r.config.write(|w| {
match mode {
MODE_0 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_high();
w.cpha().leading();
}
MODE_1 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_high();
w.cpha().trailing();
}
MODE_2 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_low();
w.cpha().leading();
}
MODE_3 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_low();
w.cpha().trailing();
}
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 3aad25298..60f4c9865 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -9,6 +9,7 @@ use core::task::Poll;
use embassy_embedded_hal::SetConfig;
use embassy_hal_internal::{into_ref, PeripheralRef};
pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+pub use pac::spis0::config::ORDER_A as BitOrder;
use crate::chip::FORCE_COPY_BUFFER_SIZE;
use crate::gpio::sealed::Pin as _;
@@ -36,6 +37,9 @@ pub struct Config {
/// SPI mode
pub mode: Mode,
+ /// Bit order
+ pub bit_order: BitOrder,
+
/// Overread character.
///
/// If the master keeps clocking the bus after all the bytes in the TX buffer have
@@ -56,6 +60,7 @@ impl Default for Config {
fn default() -> Self {
Self {
mode: MODE_0,
+ bit_order: BitOrder::MSB_FIRST,
orc: 0x00,
def: 0x00,
auto_acquire: true,
@@ -503,22 +508,22 @@ impl<'d, T: Instance> SetConfig for Spis<'d, T> {
r.config.write(|w| {
match mode {
MODE_0 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_high();
w.cpha().leading();
}
MODE_1 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_high();
w.cpha().trailing();
}
MODE_2 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_low();
w.cpha().leading();
}
MODE_3 => {
- w.order().msb_first();
+ w.order().variant(config.bit_order);
w.cpol().active_low();
w.cpha().trailing();
}
From b08a0955c3d6e66c0163508e86f9dc7e40e142d3 Mon Sep 17 00:00:00 2001
From: Martin Marmsoler <martin.marmsoler@gmail.com>
Date: Sat, 27 Jan 2024 18:19:56 +0100
Subject: [PATCH 081/392] implement retriving duty.
Description: When disabling the pwm and enabling again, it is required to restart the sequence. If the previous duty is not known, it is not possible to turn on the pwm again
---
embassy-nrf/src/pwm.rs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index 856e12024..90aeb09c0 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -736,6 +736,11 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
r.enable.write(|w| w.enable().disabled());
}
+ /// Returns the current duty of the channel
+ pub fn duty(&self, channel: usize) -> u16 {
+ self.duty[channel]
+ }
+
/// Sets duty cycle (15 bit) for a PWM channel.
pub fn set_duty(&mut self, channel: usize, duty: u16) {
let r = T::regs();
From 319b0fe3d78c60aa123a8cbdfac850d61f1478b0 Mon Sep 17 00:00:00 2001
From: Martin Marmsoler <martin.marmsoler@gmail.com>
Date: Sat, 27 Jan 2024 18:20:53 +0100
Subject: [PATCH 082/392] Do not wait when the pwm is disabled
Reason: because in this case no seqend event is raised and therefore an infinity loop occurs
---
embassy-nrf/src/pwm.rs | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index 90aeb09c0..e0583b770 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -760,7 +760,9 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
// defensive wait until waveform is loaded after seqstart so set_duty
// can't be called again while dma is still reading
- while r.events_seqend[0].read().bits() == 0 {}
+ if self.is_enabled() {
+ while r.events_seqend[0].read().bits() == 0 {}
+ }
}
/// Sets the PWM clock prescaler.
From 283debfda4b84a15e3f6de551256b9a65c729715 Mon Sep 17 00:00:00 2001
From: Valentin Trophime <60969974+ValouBambou@users.noreply.github.com>
Date: Mon, 29 Jan 2024 11:36:03 +0100
Subject: [PATCH 083/392] fix: typo in netcat command for std example
The previous given command `nc -l 8000` doesn't let me see anything and lead to a "WARN connect error: ConnectionReset". By explicitly changing the `local-port` of `nc` with the `-p` I can now see the `Hello` message printed, and the warning log disappeared.
---
examples/std/README.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/examples/std/README.md b/examples/std/README.md
index adc795928..e3a59d6ea 100644
--- a/examples/std/README.md
+++ b/examples/std/README.md
@@ -13,11 +13,11 @@ sudo ip -6 route add fe80::/64 dev tap0
sudo ip -6 route add fdaa::/64 dev tap0
```
-Second, have something listening there. For example `nc -l 8000`
+Second, have something listening there. For example `nc -lp 8000`
Then run the example located in the `examples` folder:
```sh
cd $EMBASSY_ROOT/examples/std/
cargo run --bin net -- --static-ip
-```
\ No newline at end of file
+```
From 0708ce1410404ebf66c94fadc71cb7b0128161d3 Mon Sep 17 00:00:00 2001
From: "Jomer.Dev" <Jomer.Dev@posteo.de>
Date: Mon, 29 Jan 2024 17:14:23 +0100
Subject: [PATCH 084/392] Use saturating_sub to make sure we don't overflow
---
embassy-rp/src/uart/mod.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-rp/src/uart/mod.rs b/embassy-rp/src/uart/mod.rs
index 9f5ba4e8a..f372cb640 100644
--- a/embassy-rp/src/uart/mod.rs
+++ b/embassy-rp/src/uart/mod.rs
@@ -604,8 +604,8 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
return match (all_full, last_was_break) {
(true, true) | (false, _) => {
// We got less than the full amount + a break, or the full amount
- // and the last byte was a break. Subtract the break off.
- Ok((next_addr - 1) - sval)
+ // and the last byte was a break. Subtract the break off by adding one to sval.
+ Ok(next_addr.saturating_sub(1 + sval))
}
(true, false) => {
// We finished the whole DMA, and the last DMA'd byte was NOT a break
From 5b2293e2b147736b9d324b1b561ae4227e057a04 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Tue, 30 Jan 2024 02:34:12 +0100
Subject: [PATCH 085/392] update stm32-metapac.
---
embassy-stm32/Cargo.toml | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 865970dfb..70d4daf09 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -67,8 +67,8 @@ futures = { version = "0.3.17", default-features = false, features = ["async-awa
rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
-stm32-metapac = { version = "15" }
-#stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-656ecf6714fa34fdfb3b3e2f2cd034bffed3f303" }
+#stm32-metapac = { version = "15" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab2bc2a739324793656ca1640e1caee2d88df72d" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -86,8 +86,8 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
-stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-#stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-656ecf6714fa34fdfb3b3e2f2cd034bffed3f303", default-features = false, features = ["metadata"]}
+#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab2bc2a739324793656ca1640e1caee2d88df72d", default-features = false, features = ["metadata"]}
[features]
From f38807433882374fe4ccf3510070abb42639c1cb Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Tue, 30 Jan 2024 10:34:09 +0100
Subject: [PATCH 086/392] Add some comments from chat
---
docs/modules/ROOT/pages/faq.adoc | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/docs/modules/ROOT/pages/faq.adoc b/docs/modules/ROOT/pages/faq.adoc
index bf061d978..254c0aa97 100644
--- a/docs/modules/ROOT/pages/faq.adoc
+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -181,3 +181,21 @@ Check out link:https://docs.embassy.dev/embassy-executor/git/cortex-m/index.html
== Can I use manual ISRs alongside Embassy?
Yes! This can be useful if you need to respond to an event as fast as possible, and the latency caused by the usual “ISR, wake, return from ISR, context switch to woken task” flow is too much for your application. Simply define a `#[interrupt] fn INTERRUPT_NAME() {}` handler as you would link:https://docs.rust-embedded.org/book/start/interrupts.html[in any other embedded rust project].
+
+== How can I measure resource usage (CPU, RAM, etc.)?
+
+=== For CPU Usage:
+
+There are a couple techniques that have been documented, generally you want to measure how long you are spending in the idle or low priority loop.
+
+We need to document specifically how to do this in embassy, but link:https://blog.japaric.io/cpu-monitor/[this older post] describes the general process.
+
+If you end up doing this, please update this section with more specific examples!
+
+=== For Static Memory Usage
+
+Tools like `cargo size` and `cargo nm` can tell you the size of any globals or other static usage. Specifically you will want to see the size of the `.data` and `.bss` sections, which together make up the total global/static memory usage.
+
+=== For Max Stack Usage
+
+Check out link:https://github.com/Dirbaio/cargo-call-stack/[`cargo-call-stack`] for statically calculating worst-case stack usage. There are some caveats and inaccuracies possible with this, but this is a good way to get the general idea.
From 5e7876c80047718457923bcd8f1e9859e6483b57 Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Tue, 30 Jan 2024 12:41:46 +0100
Subject: [PATCH 087/392] Update docs/modules/ROOT/pages/faq.adoc
---
docs/modules/ROOT/pages/faq.adoc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/modules/ROOT/pages/faq.adoc b/docs/modules/ROOT/pages/faq.adoc
index 254c0aa97..05ff7c598 100644
--- a/docs/modules/ROOT/pages/faq.adoc
+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -198,4 +198,4 @@ Tools like `cargo size` and `cargo nm` can tell you the size of any globals or o
=== For Max Stack Usage
-Check out link:https://github.com/Dirbaio/cargo-call-stack/[`cargo-call-stack`] for statically calculating worst-case stack usage. There are some caveats and inaccuracies possible with this, but this is a good way to get the general idea.
+Check out link:https://github.com/Dirbaio/cargo-call-stack/[`cargo-call-stack`] for statically calculating worst-case stack usage. There are some caveats and inaccuracies possible with this, but this is a good way to get the general idea. See link:https://github.com/dirbaio/cargo-call-stack#known-limitations[the README] for more details.
From a91a7a8557ae8998de7b08d753e7a55172fb43c8 Mon Sep 17 00:00:00 2001
From: Tomasz bla Fortuna <bla@reactor.local>
Date: Sun, 14 Jan 2024 09:44:37 +0100
Subject: [PATCH 088/392] Add FDCAN dependency in correct flavor based on
selected chip.
Author: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Change from review.
---
embassy-stm32/Cargo.toml | 896 ++++++++++++++++++------------------
examples/stm32g4/Cargo.toml | 2 +-
2 files changed, 450 insertions(+), 448 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 70d4daf09..6c7591f57 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -80,6 +80,8 @@ chrono = { version = "^0.4", default-features = false, optional = true}
bit_field = "0.10.2"
document-features = "0.2.7"
+fdcan = { version = "0.2.0", optional = true }
+
[dev-dependencies]
critical-section = { version = "1.1", features = ["std"] }
@@ -693,373 +695,373 @@ stm32f779ai = [ "stm32-metapac/stm32f779ai" ]
stm32f779bi = [ "stm32-metapac/stm32f779bi" ]
stm32f779ii = [ "stm32-metapac/stm32f779ii" ]
stm32f779ni = [ "stm32-metapac/stm32f779ni" ]
-stm32g030c6 = [ "stm32-metapac/stm32g030c6" ]
-stm32g030c8 = [ "stm32-metapac/stm32g030c8" ]
-stm32g030f6 = [ "stm32-metapac/stm32g030f6" ]
-stm32g030j6 = [ "stm32-metapac/stm32g030j6" ]
-stm32g030k6 = [ "stm32-metapac/stm32g030k6" ]
-stm32g030k8 = [ "stm32-metapac/stm32g030k8" ]
-stm32g031c4 = [ "stm32-metapac/stm32g031c4" ]
-stm32g031c6 = [ "stm32-metapac/stm32g031c6" ]
-stm32g031c8 = [ "stm32-metapac/stm32g031c8" ]
-stm32g031f4 = [ "stm32-metapac/stm32g031f4" ]
-stm32g031f6 = [ "stm32-metapac/stm32g031f6" ]
-stm32g031f8 = [ "stm32-metapac/stm32g031f8" ]
-stm32g031g4 = [ "stm32-metapac/stm32g031g4" ]
-stm32g031g6 = [ "stm32-metapac/stm32g031g6" ]
-stm32g031g8 = [ "stm32-metapac/stm32g031g8" ]
-stm32g031j4 = [ "stm32-metapac/stm32g031j4" ]
-stm32g031j6 = [ "stm32-metapac/stm32g031j6" ]
-stm32g031k4 = [ "stm32-metapac/stm32g031k4" ]
-stm32g031k6 = [ "stm32-metapac/stm32g031k6" ]
-stm32g031k8 = [ "stm32-metapac/stm32g031k8" ]
-stm32g031y8 = [ "stm32-metapac/stm32g031y8" ]
-stm32g041c6 = [ "stm32-metapac/stm32g041c6" ]
-stm32g041c8 = [ "stm32-metapac/stm32g041c8" ]
-stm32g041f6 = [ "stm32-metapac/stm32g041f6" ]
-stm32g041f8 = [ "stm32-metapac/stm32g041f8" ]
-stm32g041g6 = [ "stm32-metapac/stm32g041g6" ]
-stm32g041g8 = [ "stm32-metapac/stm32g041g8" ]
-stm32g041j6 = [ "stm32-metapac/stm32g041j6" ]
-stm32g041k6 = [ "stm32-metapac/stm32g041k6" ]
-stm32g041k8 = [ "stm32-metapac/stm32g041k8" ]
-stm32g041y8 = [ "stm32-metapac/stm32g041y8" ]
-stm32g050c6 = [ "stm32-metapac/stm32g050c6" ]
-stm32g050c8 = [ "stm32-metapac/stm32g050c8" ]
-stm32g050f6 = [ "stm32-metapac/stm32g050f6" ]
-stm32g050k6 = [ "stm32-metapac/stm32g050k6" ]
-stm32g050k8 = [ "stm32-metapac/stm32g050k8" ]
-stm32g051c6 = [ "stm32-metapac/stm32g051c6" ]
-stm32g051c8 = [ "stm32-metapac/stm32g051c8" ]
-stm32g051f6 = [ "stm32-metapac/stm32g051f6" ]
-stm32g051f8 = [ "stm32-metapac/stm32g051f8" ]
-stm32g051g6 = [ "stm32-metapac/stm32g051g6" ]
-stm32g051g8 = [ "stm32-metapac/stm32g051g8" ]
-stm32g051k6 = [ "stm32-metapac/stm32g051k6" ]
-stm32g051k8 = [ "stm32-metapac/stm32g051k8" ]
-stm32g061c6 = [ "stm32-metapac/stm32g061c6" ]
-stm32g061c8 = [ "stm32-metapac/stm32g061c8" ]
-stm32g061f6 = [ "stm32-metapac/stm32g061f6" ]
-stm32g061f8 = [ "stm32-metapac/stm32g061f8" ]
-stm32g061g6 = [ "stm32-metapac/stm32g061g6" ]
-stm32g061g8 = [ "stm32-metapac/stm32g061g8" ]
-stm32g061k6 = [ "stm32-metapac/stm32g061k6" ]
-stm32g061k8 = [ "stm32-metapac/stm32g061k8" ]
-stm32g070cb = [ "stm32-metapac/stm32g070cb" ]
-stm32g070kb = [ "stm32-metapac/stm32g070kb" ]
-stm32g070rb = [ "stm32-metapac/stm32g070rb" ]
-stm32g071c6 = [ "stm32-metapac/stm32g071c6" ]
-stm32g071c8 = [ "stm32-metapac/stm32g071c8" ]
-stm32g071cb = [ "stm32-metapac/stm32g071cb" ]
-stm32g071eb = [ "stm32-metapac/stm32g071eb" ]
-stm32g071g6 = [ "stm32-metapac/stm32g071g6" ]
-stm32g071g8 = [ "stm32-metapac/stm32g071g8" ]
-stm32g071gb = [ "stm32-metapac/stm32g071gb" ]
-stm32g071k6 = [ "stm32-metapac/stm32g071k6" ]
-stm32g071k8 = [ "stm32-metapac/stm32g071k8" ]
-stm32g071kb = [ "stm32-metapac/stm32g071kb" ]
-stm32g071r6 = [ "stm32-metapac/stm32g071r6" ]
-stm32g071r8 = [ "stm32-metapac/stm32g071r8" ]
-stm32g071rb = [ "stm32-metapac/stm32g071rb" ]
-stm32g081cb = [ "stm32-metapac/stm32g081cb" ]
-stm32g081eb = [ "stm32-metapac/stm32g081eb" ]
-stm32g081gb = [ "stm32-metapac/stm32g081gb" ]
-stm32g081kb = [ "stm32-metapac/stm32g081kb" ]
-stm32g081rb = [ "stm32-metapac/stm32g081rb" ]
-stm32g0b0ce = [ "stm32-metapac/stm32g0b0ce" ]
-stm32g0b0ke = [ "stm32-metapac/stm32g0b0ke" ]
-stm32g0b0re = [ "stm32-metapac/stm32g0b0re" ]
-stm32g0b0ve = [ "stm32-metapac/stm32g0b0ve" ]
-stm32g0b1cb = [ "stm32-metapac/stm32g0b1cb" ]
-stm32g0b1cc = [ "stm32-metapac/stm32g0b1cc" ]
-stm32g0b1ce = [ "stm32-metapac/stm32g0b1ce" ]
-stm32g0b1kb = [ "stm32-metapac/stm32g0b1kb" ]
-stm32g0b1kc = [ "stm32-metapac/stm32g0b1kc" ]
-stm32g0b1ke = [ "stm32-metapac/stm32g0b1ke" ]
-stm32g0b1mb = [ "stm32-metapac/stm32g0b1mb" ]
-stm32g0b1mc = [ "stm32-metapac/stm32g0b1mc" ]
-stm32g0b1me = [ "stm32-metapac/stm32g0b1me" ]
-stm32g0b1ne = [ "stm32-metapac/stm32g0b1ne" ]
-stm32g0b1rb = [ "stm32-metapac/stm32g0b1rb" ]
-stm32g0b1rc = [ "stm32-metapac/stm32g0b1rc" ]
-stm32g0b1re = [ "stm32-metapac/stm32g0b1re" ]
-stm32g0b1vb = [ "stm32-metapac/stm32g0b1vb" ]
-stm32g0b1vc = [ "stm32-metapac/stm32g0b1vc" ]
-stm32g0b1ve = [ "stm32-metapac/stm32g0b1ve" ]
-stm32g0c1cc = [ "stm32-metapac/stm32g0c1cc" ]
-stm32g0c1ce = [ "stm32-metapac/stm32g0c1ce" ]
-stm32g0c1kc = [ "stm32-metapac/stm32g0c1kc" ]
-stm32g0c1ke = [ "stm32-metapac/stm32g0c1ke" ]
-stm32g0c1mc = [ "stm32-metapac/stm32g0c1mc" ]
-stm32g0c1me = [ "stm32-metapac/stm32g0c1me" ]
-stm32g0c1ne = [ "stm32-metapac/stm32g0c1ne" ]
-stm32g0c1rc = [ "stm32-metapac/stm32g0c1rc" ]
-stm32g0c1re = [ "stm32-metapac/stm32g0c1re" ]
-stm32g0c1vc = [ "stm32-metapac/stm32g0c1vc" ]
-stm32g0c1ve = [ "stm32-metapac/stm32g0c1ve" ]
-stm32g431c6 = [ "stm32-metapac/stm32g431c6" ]
-stm32g431c8 = [ "stm32-metapac/stm32g431c8" ]
-stm32g431cb = [ "stm32-metapac/stm32g431cb" ]
-stm32g431k6 = [ "stm32-metapac/stm32g431k6" ]
-stm32g431k8 = [ "stm32-metapac/stm32g431k8" ]
-stm32g431kb = [ "stm32-metapac/stm32g431kb" ]
-stm32g431m6 = [ "stm32-metapac/stm32g431m6" ]
-stm32g431m8 = [ "stm32-metapac/stm32g431m8" ]
-stm32g431mb = [ "stm32-metapac/stm32g431mb" ]
-stm32g431r6 = [ "stm32-metapac/stm32g431r6" ]
-stm32g431r8 = [ "stm32-metapac/stm32g431r8" ]
-stm32g431rb = [ "stm32-metapac/stm32g431rb" ]
-stm32g431v6 = [ "stm32-metapac/stm32g431v6" ]
-stm32g431v8 = [ "stm32-metapac/stm32g431v8" ]
-stm32g431vb = [ "stm32-metapac/stm32g431vb" ]
-stm32g441cb = [ "stm32-metapac/stm32g441cb" ]
-stm32g441kb = [ "stm32-metapac/stm32g441kb" ]
-stm32g441mb = [ "stm32-metapac/stm32g441mb" ]
-stm32g441rb = [ "stm32-metapac/stm32g441rb" ]
-stm32g441vb = [ "stm32-metapac/stm32g441vb" ]
-stm32g471cc = [ "stm32-metapac/stm32g471cc" ]
-stm32g471ce = [ "stm32-metapac/stm32g471ce" ]
-stm32g471mc = [ "stm32-metapac/stm32g471mc" ]
-stm32g471me = [ "stm32-metapac/stm32g471me" ]
-stm32g471qc = [ "stm32-metapac/stm32g471qc" ]
-stm32g471qe = [ "stm32-metapac/stm32g471qe" ]
-stm32g471rc = [ "stm32-metapac/stm32g471rc" ]
-stm32g471re = [ "stm32-metapac/stm32g471re" ]
-stm32g471vc = [ "stm32-metapac/stm32g471vc" ]
-stm32g471ve = [ "stm32-metapac/stm32g471ve" ]
-stm32g473cb = [ "stm32-metapac/stm32g473cb" ]
-stm32g473cc = [ "stm32-metapac/stm32g473cc" ]
-stm32g473ce = [ "stm32-metapac/stm32g473ce" ]
-stm32g473mb = [ "stm32-metapac/stm32g473mb" ]
-stm32g473mc = [ "stm32-metapac/stm32g473mc" ]
-stm32g473me = [ "stm32-metapac/stm32g473me" ]
-stm32g473pb = [ "stm32-metapac/stm32g473pb" ]
-stm32g473pc = [ "stm32-metapac/stm32g473pc" ]
-stm32g473pe = [ "stm32-metapac/stm32g473pe" ]
-stm32g473qb = [ "stm32-metapac/stm32g473qb" ]
-stm32g473qc = [ "stm32-metapac/stm32g473qc" ]
-stm32g473qe = [ "stm32-metapac/stm32g473qe" ]
-stm32g473rb = [ "stm32-metapac/stm32g473rb" ]
-stm32g473rc = [ "stm32-metapac/stm32g473rc" ]
-stm32g473re = [ "stm32-metapac/stm32g473re" ]
-stm32g473vb = [ "stm32-metapac/stm32g473vb" ]
-stm32g473vc = [ "stm32-metapac/stm32g473vc" ]
-stm32g473ve = [ "stm32-metapac/stm32g473ve" ]
-stm32g474cb = [ "stm32-metapac/stm32g474cb" ]
-stm32g474cc = [ "stm32-metapac/stm32g474cc" ]
-stm32g474ce = [ "stm32-metapac/stm32g474ce" ]
-stm32g474mb = [ "stm32-metapac/stm32g474mb" ]
-stm32g474mc = [ "stm32-metapac/stm32g474mc" ]
-stm32g474me = [ "stm32-metapac/stm32g474me" ]
-stm32g474pb = [ "stm32-metapac/stm32g474pb" ]
-stm32g474pc = [ "stm32-metapac/stm32g474pc" ]
-stm32g474pe = [ "stm32-metapac/stm32g474pe" ]
-stm32g474qb = [ "stm32-metapac/stm32g474qb" ]
-stm32g474qc = [ "stm32-metapac/stm32g474qc" ]
-stm32g474qe = [ "stm32-metapac/stm32g474qe" ]
-stm32g474rb = [ "stm32-metapac/stm32g474rb" ]
-stm32g474rc = [ "stm32-metapac/stm32g474rc" ]
-stm32g474re = [ "stm32-metapac/stm32g474re" ]
-stm32g474vb = [ "stm32-metapac/stm32g474vb" ]
-stm32g474vc = [ "stm32-metapac/stm32g474vc" ]
-stm32g474ve = [ "stm32-metapac/stm32g474ve" ]
-stm32g483ce = [ "stm32-metapac/stm32g483ce" ]
-stm32g483me = [ "stm32-metapac/stm32g483me" ]
-stm32g483pe = [ "stm32-metapac/stm32g483pe" ]
-stm32g483qe = [ "stm32-metapac/stm32g483qe" ]
-stm32g483re = [ "stm32-metapac/stm32g483re" ]
-stm32g483ve = [ "stm32-metapac/stm32g483ve" ]
-stm32g484ce = [ "stm32-metapac/stm32g484ce" ]
-stm32g484me = [ "stm32-metapac/stm32g484me" ]
-stm32g484pe = [ "stm32-metapac/stm32g484pe" ]
-stm32g484qe = [ "stm32-metapac/stm32g484qe" ]
-stm32g484re = [ "stm32-metapac/stm32g484re" ]
-stm32g484ve = [ "stm32-metapac/stm32g484ve" ]
-stm32g491cc = [ "stm32-metapac/stm32g491cc" ]
-stm32g491ce = [ "stm32-metapac/stm32g491ce" ]
-stm32g491kc = [ "stm32-metapac/stm32g491kc" ]
-stm32g491ke = [ "stm32-metapac/stm32g491ke" ]
-stm32g491mc = [ "stm32-metapac/stm32g491mc" ]
-stm32g491me = [ "stm32-metapac/stm32g491me" ]
-stm32g491rc = [ "stm32-metapac/stm32g491rc" ]
-stm32g491re = [ "stm32-metapac/stm32g491re" ]
-stm32g491vc = [ "stm32-metapac/stm32g491vc" ]
-stm32g491ve = [ "stm32-metapac/stm32g491ve" ]
-stm32g4a1ce = [ "stm32-metapac/stm32g4a1ce" ]
-stm32g4a1ke = [ "stm32-metapac/stm32g4a1ke" ]
-stm32g4a1me = [ "stm32-metapac/stm32g4a1me" ]
-stm32g4a1re = [ "stm32-metapac/stm32g4a1re" ]
-stm32g4a1ve = [ "stm32-metapac/stm32g4a1ve" ]
-stm32h503cb = [ "stm32-metapac/stm32h503cb" ]
-stm32h503eb = [ "stm32-metapac/stm32h503eb" ]
-stm32h503kb = [ "stm32-metapac/stm32h503kb" ]
-stm32h503rb = [ "stm32-metapac/stm32h503rb" ]
-stm32h562ag = [ "stm32-metapac/stm32h562ag" ]
-stm32h562ai = [ "stm32-metapac/stm32h562ai" ]
-stm32h562ig = [ "stm32-metapac/stm32h562ig" ]
-stm32h562ii = [ "stm32-metapac/stm32h562ii" ]
-stm32h562rg = [ "stm32-metapac/stm32h562rg" ]
-stm32h562ri = [ "stm32-metapac/stm32h562ri" ]
-stm32h562vg = [ "stm32-metapac/stm32h562vg" ]
-stm32h562vi = [ "stm32-metapac/stm32h562vi" ]
-stm32h562zg = [ "stm32-metapac/stm32h562zg" ]
-stm32h562zi = [ "stm32-metapac/stm32h562zi" ]
-stm32h563ag = [ "stm32-metapac/stm32h563ag" ]
-stm32h563ai = [ "stm32-metapac/stm32h563ai" ]
-stm32h563ig = [ "stm32-metapac/stm32h563ig" ]
-stm32h563ii = [ "stm32-metapac/stm32h563ii" ]
-stm32h563mi = [ "stm32-metapac/stm32h563mi" ]
-stm32h563rg = [ "stm32-metapac/stm32h563rg" ]
-stm32h563ri = [ "stm32-metapac/stm32h563ri" ]
-stm32h563vg = [ "stm32-metapac/stm32h563vg" ]
-stm32h563vi = [ "stm32-metapac/stm32h563vi" ]
-stm32h563zg = [ "stm32-metapac/stm32h563zg" ]
-stm32h563zi = [ "stm32-metapac/stm32h563zi" ]
-stm32h573ai = [ "stm32-metapac/stm32h573ai" ]
-stm32h573ii = [ "stm32-metapac/stm32h573ii" ]
-stm32h573mi = [ "stm32-metapac/stm32h573mi" ]
-stm32h573ri = [ "stm32-metapac/stm32h573ri" ]
-stm32h573vi = [ "stm32-metapac/stm32h573vi" ]
-stm32h573zi = [ "stm32-metapac/stm32h573zi" ]
-stm32h723ve = [ "stm32-metapac/stm32h723ve" ]
-stm32h723vg = [ "stm32-metapac/stm32h723vg" ]
-stm32h723ze = [ "stm32-metapac/stm32h723ze" ]
-stm32h723zg = [ "stm32-metapac/stm32h723zg" ]
-stm32h725ae = [ "stm32-metapac/stm32h725ae" ]
-stm32h725ag = [ "stm32-metapac/stm32h725ag" ]
-stm32h725ie = [ "stm32-metapac/stm32h725ie" ]
-stm32h725ig = [ "stm32-metapac/stm32h725ig" ]
-stm32h725re = [ "stm32-metapac/stm32h725re" ]
-stm32h725rg = [ "stm32-metapac/stm32h725rg" ]
-stm32h725ve = [ "stm32-metapac/stm32h725ve" ]
-stm32h725vg = [ "stm32-metapac/stm32h725vg" ]
-stm32h725ze = [ "stm32-metapac/stm32h725ze" ]
-stm32h725zg = [ "stm32-metapac/stm32h725zg" ]
-stm32h730ab = [ "stm32-metapac/stm32h730ab" ]
-stm32h730ib = [ "stm32-metapac/stm32h730ib" ]
-stm32h730vb = [ "stm32-metapac/stm32h730vb" ]
-stm32h730zb = [ "stm32-metapac/stm32h730zb" ]
-stm32h733vg = [ "stm32-metapac/stm32h733vg" ]
-stm32h733zg = [ "stm32-metapac/stm32h733zg" ]
-stm32h735ag = [ "stm32-metapac/stm32h735ag" ]
-stm32h735ig = [ "stm32-metapac/stm32h735ig" ]
-stm32h735rg = [ "stm32-metapac/stm32h735rg" ]
-stm32h735vg = [ "stm32-metapac/stm32h735vg" ]
-stm32h735zg = [ "stm32-metapac/stm32h735zg" ]
-stm32h742ag = [ "stm32-metapac/stm32h742ag" ]
-stm32h742ai = [ "stm32-metapac/stm32h742ai" ]
-stm32h742bg = [ "stm32-metapac/stm32h742bg" ]
-stm32h742bi = [ "stm32-metapac/stm32h742bi" ]
-stm32h742ig = [ "stm32-metapac/stm32h742ig" ]
-stm32h742ii = [ "stm32-metapac/stm32h742ii" ]
-stm32h742vg = [ "stm32-metapac/stm32h742vg" ]
-stm32h742vi = [ "stm32-metapac/stm32h742vi" ]
-stm32h742xg = [ "stm32-metapac/stm32h742xg" ]
-stm32h742xi = [ "stm32-metapac/stm32h742xi" ]
-stm32h742zg = [ "stm32-metapac/stm32h742zg" ]
-stm32h742zi = [ "stm32-metapac/stm32h742zi" ]
-stm32h743ag = [ "stm32-metapac/stm32h743ag" ]
-stm32h743ai = [ "stm32-metapac/stm32h743ai" ]
-stm32h743bg = [ "stm32-metapac/stm32h743bg" ]
-stm32h743bi = [ "stm32-metapac/stm32h743bi" ]
-stm32h743ig = [ "stm32-metapac/stm32h743ig" ]
-stm32h743ii = [ "stm32-metapac/stm32h743ii" ]
-stm32h743vg = [ "stm32-metapac/stm32h743vg" ]
-stm32h743vi = [ "stm32-metapac/stm32h743vi" ]
-stm32h743xg = [ "stm32-metapac/stm32h743xg" ]
-stm32h743xi = [ "stm32-metapac/stm32h743xi" ]
-stm32h743zg = [ "stm32-metapac/stm32h743zg" ]
-stm32h743zi = [ "stm32-metapac/stm32h743zi" ]
-stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7" ]
-stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4" ]
-stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7" ]
-stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4" ]
-stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7" ]
-stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4" ]
-stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7" ]
-stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4" ]
-stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7" ]
-stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4" ]
-stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7" ]
-stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4" ]
-stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7" ]
-stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4" ]
-stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7" ]
-stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4" ]
-stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7" ]
-stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4" ]
-stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7" ]
-stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4" ]
-stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7" ]
-stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4" ]
-stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7" ]
-stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4" ]
-stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7" ]
-stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4" ]
-stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7" ]
-stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4" ]
-stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7" ]
-stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4" ]
-stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7" ]
-stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4" ]
-stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7" ]
-stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4" ]
-stm32h750ib = [ "stm32-metapac/stm32h750ib" ]
-stm32h750vb = [ "stm32-metapac/stm32h750vb" ]
-stm32h750xb = [ "stm32-metapac/stm32h750xb" ]
-stm32h750zb = [ "stm32-metapac/stm32h750zb" ]
-stm32h753ai = [ "stm32-metapac/stm32h753ai" ]
-stm32h753bi = [ "stm32-metapac/stm32h753bi" ]
-stm32h753ii = [ "stm32-metapac/stm32h753ii" ]
-stm32h753vi = [ "stm32-metapac/stm32h753vi" ]
-stm32h753xi = [ "stm32-metapac/stm32h753xi" ]
-stm32h753zi = [ "stm32-metapac/stm32h753zi" ]
-stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7" ]
-stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4" ]
-stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7" ]
-stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4" ]
-stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7" ]
-stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4" ]
-stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7" ]
-stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4" ]
-stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7" ]
-stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4" ]
-stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7" ]
-stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4" ]
-stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7" ]
-stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4" ]
-stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7" ]
-stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4" ]
-stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7" ]
-stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4" ]
-stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag" ]
-stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai" ]
-stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig" ]
-stm32h7a3ii = [ "stm32-metapac/stm32h7a3ii" ]
-stm32h7a3lg = [ "stm32-metapac/stm32h7a3lg" ]
-stm32h7a3li = [ "stm32-metapac/stm32h7a3li" ]
-stm32h7a3ng = [ "stm32-metapac/stm32h7a3ng" ]
-stm32h7a3ni = [ "stm32-metapac/stm32h7a3ni" ]
-stm32h7a3qi = [ "stm32-metapac/stm32h7a3qi" ]
-stm32h7a3rg = [ "stm32-metapac/stm32h7a3rg" ]
-stm32h7a3ri = [ "stm32-metapac/stm32h7a3ri" ]
-stm32h7a3vg = [ "stm32-metapac/stm32h7a3vg" ]
-stm32h7a3vi = [ "stm32-metapac/stm32h7a3vi" ]
-stm32h7a3zg = [ "stm32-metapac/stm32h7a3zg" ]
-stm32h7a3zi = [ "stm32-metapac/stm32h7a3zi" ]
-stm32h7b0ab = [ "stm32-metapac/stm32h7b0ab" ]
-stm32h7b0ib = [ "stm32-metapac/stm32h7b0ib" ]
-stm32h7b0rb = [ "stm32-metapac/stm32h7b0rb" ]
-stm32h7b0vb = [ "stm32-metapac/stm32h7b0vb" ]
-stm32h7b0zb = [ "stm32-metapac/stm32h7b0zb" ]
-stm32h7b3ai = [ "stm32-metapac/stm32h7b3ai" ]
-stm32h7b3ii = [ "stm32-metapac/stm32h7b3ii" ]
-stm32h7b3li = [ "stm32-metapac/stm32h7b3li" ]
-stm32h7b3ni = [ "stm32-metapac/stm32h7b3ni" ]
-stm32h7b3qi = [ "stm32-metapac/stm32h7b3qi" ]
-stm32h7b3ri = [ "stm32-metapac/stm32h7b3ri" ]
-stm32h7b3vi = [ "stm32-metapac/stm32h7b3vi" ]
-stm32h7b3zi = [ "stm32-metapac/stm32h7b3zi" ]
+stm32g030c6 = [ "stm32-metapac/stm32g030c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g030c8 = [ "stm32-metapac/stm32g030c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g030f6 = [ "stm32-metapac/stm32g030f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g030j6 = [ "stm32-metapac/stm32g030j6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g030k6 = [ "stm32-metapac/stm32g030k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g030k8 = [ "stm32-metapac/stm32g030k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031c4 = [ "stm32-metapac/stm32g031c4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031c6 = [ "stm32-metapac/stm32g031c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031c8 = [ "stm32-metapac/stm32g031c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031f4 = [ "stm32-metapac/stm32g031f4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031f6 = [ "stm32-metapac/stm32g031f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031f8 = [ "stm32-metapac/stm32g031f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031g4 = [ "stm32-metapac/stm32g031g4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031g6 = [ "stm32-metapac/stm32g031g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031g8 = [ "stm32-metapac/stm32g031g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031j4 = [ "stm32-metapac/stm32g031j4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031j6 = [ "stm32-metapac/stm32g031j6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031k4 = [ "stm32-metapac/stm32g031k4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031k6 = [ "stm32-metapac/stm32g031k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031k8 = [ "stm32-metapac/stm32g031k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g031y8 = [ "stm32-metapac/stm32g031y8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041c6 = [ "stm32-metapac/stm32g041c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041c8 = [ "stm32-metapac/stm32g041c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041f6 = [ "stm32-metapac/stm32g041f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041f8 = [ "stm32-metapac/stm32g041f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041g6 = [ "stm32-metapac/stm32g041g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041g8 = [ "stm32-metapac/stm32g041g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041j6 = [ "stm32-metapac/stm32g041j6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041k6 = [ "stm32-metapac/stm32g041k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041k8 = [ "stm32-metapac/stm32g041k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g041y8 = [ "stm32-metapac/stm32g041y8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g050c6 = [ "stm32-metapac/stm32g050c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g050c8 = [ "stm32-metapac/stm32g050c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g050f6 = [ "stm32-metapac/stm32g050f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g050k6 = [ "stm32-metapac/stm32g050k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g050k8 = [ "stm32-metapac/stm32g050k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051c6 = [ "stm32-metapac/stm32g051c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051c8 = [ "stm32-metapac/stm32g051c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051f6 = [ "stm32-metapac/stm32g051f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051f8 = [ "stm32-metapac/stm32g051f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051g6 = [ "stm32-metapac/stm32g051g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051g8 = [ "stm32-metapac/stm32g051g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051k6 = [ "stm32-metapac/stm32g051k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g051k8 = [ "stm32-metapac/stm32g051k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061c6 = [ "stm32-metapac/stm32g061c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061c8 = [ "stm32-metapac/stm32g061c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061f6 = [ "stm32-metapac/stm32g061f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061f8 = [ "stm32-metapac/stm32g061f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061g6 = [ "stm32-metapac/stm32g061g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061g8 = [ "stm32-metapac/stm32g061g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061k6 = [ "stm32-metapac/stm32g061k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g061k8 = [ "stm32-metapac/stm32g061k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g070cb = [ "stm32-metapac/stm32g070cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g070kb = [ "stm32-metapac/stm32g070kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g070rb = [ "stm32-metapac/stm32g070rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071c6 = [ "stm32-metapac/stm32g071c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071c8 = [ "stm32-metapac/stm32g071c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071cb = [ "stm32-metapac/stm32g071cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071eb = [ "stm32-metapac/stm32g071eb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071g6 = [ "stm32-metapac/stm32g071g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071g8 = [ "stm32-metapac/stm32g071g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071gb = [ "stm32-metapac/stm32g071gb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071k6 = [ "stm32-metapac/stm32g071k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071k8 = [ "stm32-metapac/stm32g071k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071kb = [ "stm32-metapac/stm32g071kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071r6 = [ "stm32-metapac/stm32g071r6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071r8 = [ "stm32-metapac/stm32g071r8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g071rb = [ "stm32-metapac/stm32g071rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g081cb = [ "stm32-metapac/stm32g081cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g081eb = [ "stm32-metapac/stm32g081eb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g081gb = [ "stm32-metapac/stm32g081gb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g081kb = [ "stm32-metapac/stm32g081kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g081rb = [ "stm32-metapac/stm32g081rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b0ce = [ "stm32-metapac/stm32g0b0ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b0ke = [ "stm32-metapac/stm32g0b0ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b0re = [ "stm32-metapac/stm32g0b0re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b0ve = [ "stm32-metapac/stm32g0b0ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1cb = [ "stm32-metapac/stm32g0b1cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1cc = [ "stm32-metapac/stm32g0b1cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1ce = [ "stm32-metapac/stm32g0b1ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1kb = [ "stm32-metapac/stm32g0b1kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1kc = [ "stm32-metapac/stm32g0b1kc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1ke = [ "stm32-metapac/stm32g0b1ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1mb = [ "stm32-metapac/stm32g0b1mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1mc = [ "stm32-metapac/stm32g0b1mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1me = [ "stm32-metapac/stm32g0b1me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1ne = [ "stm32-metapac/stm32g0b1ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1rb = [ "stm32-metapac/stm32g0b1rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1rc = [ "stm32-metapac/stm32g0b1rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1re = [ "stm32-metapac/stm32g0b1re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1vb = [ "stm32-metapac/stm32g0b1vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1vc = [ "stm32-metapac/stm32g0b1vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0b1ve = [ "stm32-metapac/stm32g0b1ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1cc = [ "stm32-metapac/stm32g0c1cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1ce = [ "stm32-metapac/stm32g0c1ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1kc = [ "stm32-metapac/stm32g0c1kc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1ke = [ "stm32-metapac/stm32g0c1ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1mc = [ "stm32-metapac/stm32g0c1mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1me = [ "stm32-metapac/stm32g0c1me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1ne = [ "stm32-metapac/stm32g0c1ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1rc = [ "stm32-metapac/stm32g0c1rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1re = [ "stm32-metapac/stm32g0c1re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1vc = [ "stm32-metapac/stm32g0c1vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g0c1ve = [ "stm32-metapac/stm32g0c1ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431c6 = [ "stm32-metapac/stm32g431c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431c8 = [ "stm32-metapac/stm32g431c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431cb = [ "stm32-metapac/stm32g431cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431k6 = [ "stm32-metapac/stm32g431k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431k8 = [ "stm32-metapac/stm32g431k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431kb = [ "stm32-metapac/stm32g431kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431m6 = [ "stm32-metapac/stm32g431m6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431m8 = [ "stm32-metapac/stm32g431m8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431mb = [ "stm32-metapac/stm32g431mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431r6 = [ "stm32-metapac/stm32g431r6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431r8 = [ "stm32-metapac/stm32g431r8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431rb = [ "stm32-metapac/stm32g431rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431v6 = [ "stm32-metapac/stm32g431v6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431v8 = [ "stm32-metapac/stm32g431v8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g431vb = [ "stm32-metapac/stm32g431vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g441cb = [ "stm32-metapac/stm32g441cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g441kb = [ "stm32-metapac/stm32g441kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g441mb = [ "stm32-metapac/stm32g441mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g441rb = [ "stm32-metapac/stm32g441rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g441vb = [ "stm32-metapac/stm32g441vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471cc = [ "stm32-metapac/stm32g471cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471ce = [ "stm32-metapac/stm32g471ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471mc = [ "stm32-metapac/stm32g471mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471me = [ "stm32-metapac/stm32g471me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471qc = [ "stm32-metapac/stm32g471qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471qe = [ "stm32-metapac/stm32g471qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471rc = [ "stm32-metapac/stm32g471rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471re = [ "stm32-metapac/stm32g471re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471vc = [ "stm32-metapac/stm32g471vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g471ve = [ "stm32-metapac/stm32g471ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473cb = [ "stm32-metapac/stm32g473cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473cc = [ "stm32-metapac/stm32g473cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473ce = [ "stm32-metapac/stm32g473ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473mb = [ "stm32-metapac/stm32g473mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473mc = [ "stm32-metapac/stm32g473mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473me = [ "stm32-metapac/stm32g473me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473pb = [ "stm32-metapac/stm32g473pb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473pc = [ "stm32-metapac/stm32g473pc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473pe = [ "stm32-metapac/stm32g473pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473qb = [ "stm32-metapac/stm32g473qb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473qc = [ "stm32-metapac/stm32g473qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473qe = [ "stm32-metapac/stm32g473qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473rb = [ "stm32-metapac/stm32g473rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473rc = [ "stm32-metapac/stm32g473rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473re = [ "stm32-metapac/stm32g473re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473vb = [ "stm32-metapac/stm32g473vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473vc = [ "stm32-metapac/stm32g473vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g473ve = [ "stm32-metapac/stm32g473ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474cb = [ "stm32-metapac/stm32g474cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474cc = [ "stm32-metapac/stm32g474cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474ce = [ "stm32-metapac/stm32g474ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474mb = [ "stm32-metapac/stm32g474mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474mc = [ "stm32-metapac/stm32g474mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474me = [ "stm32-metapac/stm32g474me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474pb = [ "stm32-metapac/stm32g474pb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474pc = [ "stm32-metapac/stm32g474pc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474pe = [ "stm32-metapac/stm32g474pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474qb = [ "stm32-metapac/stm32g474qb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474qc = [ "stm32-metapac/stm32g474qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474qe = [ "stm32-metapac/stm32g474qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474rb = [ "stm32-metapac/stm32g474rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474rc = [ "stm32-metapac/stm32g474rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474re = [ "stm32-metapac/stm32g474re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474vb = [ "stm32-metapac/stm32g474vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474vc = [ "stm32-metapac/stm32g474vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g474ve = [ "stm32-metapac/stm32g474ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g483ce = [ "stm32-metapac/stm32g483ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g483me = [ "stm32-metapac/stm32g483me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g483pe = [ "stm32-metapac/stm32g483pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g483qe = [ "stm32-metapac/stm32g483qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g483re = [ "stm32-metapac/stm32g483re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g483ve = [ "stm32-metapac/stm32g483ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g484ce = [ "stm32-metapac/stm32g484ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g484me = [ "stm32-metapac/stm32g484me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g484pe = [ "stm32-metapac/stm32g484pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g484qe = [ "stm32-metapac/stm32g484qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g484re = [ "stm32-metapac/stm32g484re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g484ve = [ "stm32-metapac/stm32g484ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491cc = [ "stm32-metapac/stm32g491cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491ce = [ "stm32-metapac/stm32g491ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491kc = [ "stm32-metapac/stm32g491kc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491ke = [ "stm32-metapac/stm32g491ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491mc = [ "stm32-metapac/stm32g491mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491me = [ "stm32-metapac/stm32g491me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491rc = [ "stm32-metapac/stm32g491rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491re = [ "stm32-metapac/stm32g491re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491vc = [ "stm32-metapac/stm32g491vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g491ve = [ "stm32-metapac/stm32g491ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g4a1ce = [ "stm32-metapac/stm32g4a1ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g4a1ke = [ "stm32-metapac/stm32g4a1ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g4a1me = [ "stm32-metapac/stm32g4a1me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g4a1re = [ "stm32-metapac/stm32g4a1re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32g4a1ve = [ "stm32-metapac/stm32g4a1ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h503cb = [ "stm32-metapac/stm32h503cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h503eb = [ "stm32-metapac/stm32h503eb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h503kb = [ "stm32-metapac/stm32h503kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h503rb = [ "stm32-metapac/stm32h503rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562ag = [ "stm32-metapac/stm32h562ag", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562ai = [ "stm32-metapac/stm32h562ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562ig = [ "stm32-metapac/stm32h562ig", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562ii = [ "stm32-metapac/stm32h562ii", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562rg = [ "stm32-metapac/stm32h562rg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562ri = [ "stm32-metapac/stm32h562ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562vg = [ "stm32-metapac/stm32h562vg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562vi = [ "stm32-metapac/stm32h562vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562zg = [ "stm32-metapac/stm32h562zg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h562zi = [ "stm32-metapac/stm32h562zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563ag = [ "stm32-metapac/stm32h563ag", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563ai = [ "stm32-metapac/stm32h563ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563ig = [ "stm32-metapac/stm32h563ig", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563ii = [ "stm32-metapac/stm32h563ii", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563mi = [ "stm32-metapac/stm32h563mi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563rg = [ "stm32-metapac/stm32h563rg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563ri = [ "stm32-metapac/stm32h563ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563vg = [ "stm32-metapac/stm32h563vg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563vi = [ "stm32-metapac/stm32h563vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563zg = [ "stm32-metapac/stm32h563zg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h563zi = [ "stm32-metapac/stm32h563zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h573ai = [ "stm32-metapac/stm32h573ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h573ii = [ "stm32-metapac/stm32h573ii", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h573mi = [ "stm32-metapac/stm32h573mi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h573ri = [ "stm32-metapac/stm32h573ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h573vi = [ "stm32-metapac/stm32h573vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h573zi = [ "stm32-metapac/stm32h573zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32h723ve = [ "stm32-metapac/stm32h723ve", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h723vg = [ "stm32-metapac/stm32h723vg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h723ze = [ "stm32-metapac/stm32h723ze", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h723zg = [ "stm32-metapac/stm32h723zg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725ae = [ "stm32-metapac/stm32h725ae", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725ag = [ "stm32-metapac/stm32h725ag", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725ie = [ "stm32-metapac/stm32h725ie", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725ig = [ "stm32-metapac/stm32h725ig", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725re = [ "stm32-metapac/stm32h725re", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725rg = [ "stm32-metapac/stm32h725rg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725ve = [ "stm32-metapac/stm32h725ve", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725vg = [ "stm32-metapac/stm32h725vg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725ze = [ "stm32-metapac/stm32h725ze", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h725zg = [ "stm32-metapac/stm32h725zg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h730ab = [ "stm32-metapac/stm32h730ab", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h730ib = [ "stm32-metapac/stm32h730ib", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h730vb = [ "stm32-metapac/stm32h730vb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h730zb = [ "stm32-metapac/stm32h730zb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h733vg = [ "stm32-metapac/stm32h733vg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h733zg = [ "stm32-metapac/stm32h733zg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h735ag = [ "stm32-metapac/stm32h735ag", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h735ig = [ "stm32-metapac/stm32h735ig", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h735rg = [ "stm32-metapac/stm32h735rg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h735vg = [ "stm32-metapac/stm32h735vg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h735zg = [ "stm32-metapac/stm32h735zg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742ag = [ "stm32-metapac/stm32h742ag", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742ai = [ "stm32-metapac/stm32h742ai", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742bg = [ "stm32-metapac/stm32h742bg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742bi = [ "stm32-metapac/stm32h742bi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742ig = [ "stm32-metapac/stm32h742ig", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742ii = [ "stm32-metapac/stm32h742ii", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742vg = [ "stm32-metapac/stm32h742vg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742vi = [ "stm32-metapac/stm32h742vi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742xg = [ "stm32-metapac/stm32h742xg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742xi = [ "stm32-metapac/stm32h742xi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742zg = [ "stm32-metapac/stm32h742zg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h742zi = [ "stm32-metapac/stm32h742zi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743ag = [ "stm32-metapac/stm32h743ag", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743ai = [ "stm32-metapac/stm32h743ai", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743bg = [ "stm32-metapac/stm32h743bg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743bi = [ "stm32-metapac/stm32h743bi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743ig = [ "stm32-metapac/stm32h743ig", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743ii = [ "stm32-metapac/stm32h743ii", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743vg = [ "stm32-metapac/stm32h743vg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743vi = [ "stm32-metapac/stm32h743vi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743xg = [ "stm32-metapac/stm32h743xg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743xi = [ "stm32-metapac/stm32h743xi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743zg = [ "stm32-metapac/stm32h743zg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h743zi = [ "stm32-metapac/stm32h743zi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h750ib = [ "stm32-metapac/stm32h750ib", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h750vb = [ "stm32-metapac/stm32h750vb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h750xb = [ "stm32-metapac/stm32h750xb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h750zb = [ "stm32-metapac/stm32h750zb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h753ai = [ "stm32-metapac/stm32h753ai", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h753bi = [ "stm32-metapac/stm32h753bi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h753ii = [ "stm32-metapac/stm32h753ii", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h753vi = [ "stm32-metapac/stm32h753vi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h753xi = [ "stm32-metapac/stm32h753xi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h753zi = [ "stm32-metapac/stm32h753zi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3ii = [ "stm32-metapac/stm32h7a3ii", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3lg = [ "stm32-metapac/stm32h7a3lg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3li = [ "stm32-metapac/stm32h7a3li", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3ng = [ "stm32-metapac/stm32h7a3ng", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3ni = [ "stm32-metapac/stm32h7a3ni", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3qi = [ "stm32-metapac/stm32h7a3qi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3rg = [ "stm32-metapac/stm32h7a3rg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3ri = [ "stm32-metapac/stm32h7a3ri", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3vg = [ "stm32-metapac/stm32h7a3vg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3vi = [ "stm32-metapac/stm32h7a3vi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3zg = [ "stm32-metapac/stm32h7a3zg", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7a3zi = [ "stm32-metapac/stm32h7a3zi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b0ab = [ "stm32-metapac/stm32h7b0ab", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b0ib = [ "stm32-metapac/stm32h7b0ib", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b0rb = [ "stm32-metapac/stm32h7b0rb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b0vb = [ "stm32-metapac/stm32h7b0vb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b0zb = [ "stm32-metapac/stm32h7b0zb", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3ai = [ "stm32-metapac/stm32h7b3ai", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3ii = [ "stm32-metapac/stm32h7b3ii", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3li = [ "stm32-metapac/stm32h7b3li", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3ni = [ "stm32-metapac/stm32h7b3ni", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3qi = [ "stm32-metapac/stm32h7b3qi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3ri = [ "stm32-metapac/stm32h7b3ri", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3vi = [ "stm32-metapac/stm32h7b3vi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32h7b3zi = [ "stm32-metapac/stm32h7b3zi", "dep:fdcan", "fdcan/fdcan_h7" ]
stm32l010c6 = [ "stm32-metapac/stm32l010c6" ]
stm32l010f4 = [ "stm32-metapac/stm32l010f4" ]
stm32l010k4 = [ "stm32-metapac/stm32l010k4" ]
@@ -1386,86 +1388,86 @@ stm32l4s7zi = [ "stm32-metapac/stm32l4s7zi" ]
stm32l4s9ai = [ "stm32-metapac/stm32l4s9ai" ]
stm32l4s9vi = [ "stm32-metapac/stm32l4s9vi" ]
stm32l4s9zi = [ "stm32-metapac/stm32l4s9zi" ]
-stm32l552cc = [ "stm32-metapac/stm32l552cc" ]
-stm32l552ce = [ "stm32-metapac/stm32l552ce" ]
-stm32l552me = [ "stm32-metapac/stm32l552me" ]
-stm32l552qc = [ "stm32-metapac/stm32l552qc" ]
-stm32l552qe = [ "stm32-metapac/stm32l552qe" ]
-stm32l552rc = [ "stm32-metapac/stm32l552rc" ]
-stm32l552re = [ "stm32-metapac/stm32l552re" ]
-stm32l552vc = [ "stm32-metapac/stm32l552vc" ]
-stm32l552ve = [ "stm32-metapac/stm32l552ve" ]
-stm32l552zc = [ "stm32-metapac/stm32l552zc" ]
-stm32l552ze = [ "stm32-metapac/stm32l552ze" ]
-stm32l562ce = [ "stm32-metapac/stm32l562ce" ]
-stm32l562me = [ "stm32-metapac/stm32l562me" ]
-stm32l562qe = [ "stm32-metapac/stm32l562qe" ]
-stm32l562re = [ "stm32-metapac/stm32l562re" ]
-stm32l562ve = [ "stm32-metapac/stm32l562ve" ]
-stm32l562ze = [ "stm32-metapac/stm32l562ze" ]
-stm32u535cb = [ "stm32-metapac/stm32u535cb" ]
-stm32u535cc = [ "stm32-metapac/stm32u535cc" ]
-stm32u535ce = [ "stm32-metapac/stm32u535ce" ]
-stm32u535je = [ "stm32-metapac/stm32u535je" ]
-stm32u535nc = [ "stm32-metapac/stm32u535nc" ]
-stm32u535ne = [ "stm32-metapac/stm32u535ne" ]
-stm32u535rb = [ "stm32-metapac/stm32u535rb" ]
-stm32u535rc = [ "stm32-metapac/stm32u535rc" ]
-stm32u535re = [ "stm32-metapac/stm32u535re" ]
-stm32u535vc = [ "stm32-metapac/stm32u535vc" ]
-stm32u535ve = [ "stm32-metapac/stm32u535ve" ]
-stm32u545ce = [ "stm32-metapac/stm32u545ce" ]
-stm32u545je = [ "stm32-metapac/stm32u545je" ]
-stm32u545ne = [ "stm32-metapac/stm32u545ne" ]
-stm32u545re = [ "stm32-metapac/stm32u545re" ]
-stm32u545ve = [ "stm32-metapac/stm32u545ve" ]
-stm32u575ag = [ "stm32-metapac/stm32u575ag" ]
-stm32u575ai = [ "stm32-metapac/stm32u575ai" ]
-stm32u575cg = [ "stm32-metapac/stm32u575cg" ]
-stm32u575ci = [ "stm32-metapac/stm32u575ci" ]
-stm32u575og = [ "stm32-metapac/stm32u575og" ]
-stm32u575oi = [ "stm32-metapac/stm32u575oi" ]
-stm32u575qg = [ "stm32-metapac/stm32u575qg" ]
-stm32u575qi = [ "stm32-metapac/stm32u575qi" ]
-stm32u575rg = [ "stm32-metapac/stm32u575rg" ]
-stm32u575ri = [ "stm32-metapac/stm32u575ri" ]
-stm32u575vg = [ "stm32-metapac/stm32u575vg" ]
-stm32u575vi = [ "stm32-metapac/stm32u575vi" ]
-stm32u575zg = [ "stm32-metapac/stm32u575zg" ]
-stm32u575zi = [ "stm32-metapac/stm32u575zi" ]
-stm32u585ai = [ "stm32-metapac/stm32u585ai" ]
-stm32u585ci = [ "stm32-metapac/stm32u585ci" ]
-stm32u585oi = [ "stm32-metapac/stm32u585oi" ]
-stm32u585qi = [ "stm32-metapac/stm32u585qi" ]
-stm32u585ri = [ "stm32-metapac/stm32u585ri" ]
-stm32u585vi = [ "stm32-metapac/stm32u585vi" ]
-stm32u585zi = [ "stm32-metapac/stm32u585zi" ]
-stm32u595ai = [ "stm32-metapac/stm32u595ai" ]
-stm32u595aj = [ "stm32-metapac/stm32u595aj" ]
-stm32u595qi = [ "stm32-metapac/stm32u595qi" ]
-stm32u595qj = [ "stm32-metapac/stm32u595qj" ]
-stm32u595ri = [ "stm32-metapac/stm32u595ri" ]
-stm32u595rj = [ "stm32-metapac/stm32u595rj" ]
-stm32u595vi = [ "stm32-metapac/stm32u595vi" ]
-stm32u595vj = [ "stm32-metapac/stm32u595vj" ]
-stm32u595zi = [ "stm32-metapac/stm32u595zi" ]
-stm32u595zj = [ "stm32-metapac/stm32u595zj" ]
-stm32u599bj = [ "stm32-metapac/stm32u599bj" ]
-stm32u599ni = [ "stm32-metapac/stm32u599ni" ]
-stm32u599nj = [ "stm32-metapac/stm32u599nj" ]
-stm32u599vi = [ "stm32-metapac/stm32u599vi" ]
-stm32u599vj = [ "stm32-metapac/stm32u599vj" ]
-stm32u599zi = [ "stm32-metapac/stm32u599zi" ]
-stm32u599zj = [ "stm32-metapac/stm32u599zj" ]
-stm32u5a5aj = [ "stm32-metapac/stm32u5a5aj" ]
-stm32u5a5qj = [ "stm32-metapac/stm32u5a5qj" ]
-stm32u5a5rj = [ "stm32-metapac/stm32u5a5rj" ]
-stm32u5a5vj = [ "stm32-metapac/stm32u5a5vj" ]
-stm32u5a5zj = [ "stm32-metapac/stm32u5a5zj" ]
-stm32u5a9bj = [ "stm32-metapac/stm32u5a9bj" ]
-stm32u5a9nj = [ "stm32-metapac/stm32u5a9nj" ]
-stm32u5a9vj = [ "stm32-metapac/stm32u5a9vj" ]
-stm32u5a9zj = [ "stm32-metapac/stm32u5a9zj" ]
+stm32l552cc = [ "stm32-metapac/stm32l552cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552ce = [ "stm32-metapac/stm32l552ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552me = [ "stm32-metapac/stm32l552me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552qc = [ "stm32-metapac/stm32l552qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552qe = [ "stm32-metapac/stm32l552qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552rc = [ "stm32-metapac/stm32l552rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552re = [ "stm32-metapac/stm32l552re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552vc = [ "stm32-metapac/stm32l552vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552ve = [ "stm32-metapac/stm32l552ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552zc = [ "stm32-metapac/stm32l552zc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552ze = [ "stm32-metapac/stm32l552ze", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l562ce = [ "stm32-metapac/stm32l562ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l562me = [ "stm32-metapac/stm32l562me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l562qe = [ "stm32-metapac/stm32l562qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l562re = [ "stm32-metapac/stm32l562re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l562ve = [ "stm32-metapac/stm32l562ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l562ze = [ "stm32-metapac/stm32l562ze", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535cb = [ "stm32-metapac/stm32u535cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535cc = [ "stm32-metapac/stm32u535cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535ce = [ "stm32-metapac/stm32u535ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535je = [ "stm32-metapac/stm32u535je", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535nc = [ "stm32-metapac/stm32u535nc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535ne = [ "stm32-metapac/stm32u535ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535rb = [ "stm32-metapac/stm32u535rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535rc = [ "stm32-metapac/stm32u535rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535re = [ "stm32-metapac/stm32u535re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535vc = [ "stm32-metapac/stm32u535vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u535ve = [ "stm32-metapac/stm32u535ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u545ce = [ "stm32-metapac/stm32u545ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u545je = [ "stm32-metapac/stm32u545je", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u545ne = [ "stm32-metapac/stm32u545ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u545re = [ "stm32-metapac/stm32u545re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u545ve = [ "stm32-metapac/stm32u545ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575ag = [ "stm32-metapac/stm32u575ag", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575ai = [ "stm32-metapac/stm32u575ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575cg = [ "stm32-metapac/stm32u575cg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575ci = [ "stm32-metapac/stm32u575ci", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575og = [ "stm32-metapac/stm32u575og", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575oi = [ "stm32-metapac/stm32u575oi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575qg = [ "stm32-metapac/stm32u575qg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575qi = [ "stm32-metapac/stm32u575qi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575rg = [ "stm32-metapac/stm32u575rg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575ri = [ "stm32-metapac/stm32u575ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575vg = [ "stm32-metapac/stm32u575vg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575vi = [ "stm32-metapac/stm32u575vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575zg = [ "stm32-metapac/stm32u575zg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u575zi = [ "stm32-metapac/stm32u575zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u585ai = [ "stm32-metapac/stm32u585ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u585ci = [ "stm32-metapac/stm32u585ci", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u585oi = [ "stm32-metapac/stm32u585oi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u585qi = [ "stm32-metapac/stm32u585qi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u585ri = [ "stm32-metapac/stm32u585ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u585vi = [ "stm32-metapac/stm32u585vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u585zi = [ "stm32-metapac/stm32u585zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595ai = [ "stm32-metapac/stm32u595ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595aj = [ "stm32-metapac/stm32u595aj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595qi = [ "stm32-metapac/stm32u595qi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595qj = [ "stm32-metapac/stm32u595qj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595ri = [ "stm32-metapac/stm32u595ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595rj = [ "stm32-metapac/stm32u595rj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595vi = [ "stm32-metapac/stm32u595vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595vj = [ "stm32-metapac/stm32u595vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595zi = [ "stm32-metapac/stm32u595zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u595zj = [ "stm32-metapac/stm32u595zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u599bj = [ "stm32-metapac/stm32u599bj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u599ni = [ "stm32-metapac/stm32u599ni", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u599nj = [ "stm32-metapac/stm32u599nj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u599vi = [ "stm32-metapac/stm32u599vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u599vj = [ "stm32-metapac/stm32u599vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u599zi = [ "stm32-metapac/stm32u599zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u599zj = [ "stm32-metapac/stm32u599zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a5aj = [ "stm32-metapac/stm32u5a5aj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a5qj = [ "stm32-metapac/stm32u5a5qj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a5rj = [ "stm32-metapac/stm32u5a5rj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a5vj = [ "stm32-metapac/stm32u5a5vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a5zj = [ "stm32-metapac/stm32u5a5zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a9bj = [ "stm32-metapac/stm32u5a9bj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a9nj = [ "stm32-metapac/stm32u5a9nj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a9vj = [ "stm32-metapac/stm32u5a9vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32u5a9zj = [ "stm32-metapac/stm32u5a9zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
stm32wb10cc = [ "stm32-metapac/stm32wb10cc" ]
stm32wb15cc = [ "stm32-metapac/stm32wb15cc" ]
stm32wb30ce = [ "stm32-metapac/stm32wb30ce" ]
diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index 895ad3e7c..b87f461b4 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
[dependencies]
# Change stm32g491re to your chip name, if necessary.
-embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g491re", "memory-x", "unstable-pac", "exti"] }
+embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g473re", "memory-x", "unstable-pac", "exti", "fdcan"] }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
From 03ba45065e529284d41ebca5a8e716633107fc48 Mon Sep 17 00:00:00 2001
From: Tomasz bla Fortuna <bla@reactor.local>
Date: Sun, 14 Jan 2024 09:47:26 +0100
Subject: [PATCH 089/392] Add FDCAN clock registers to G4 RCC.
Author: Adam Morgan <adam@luci.com>
Break definitions out of bxcan that can be used innm fdcan.
Typo
---
embassy-stm32/build.rs | 2 +-
embassy-stm32/src/can/bxcan.rs | 124 ++++-----------------------------
embassy-stm32/src/can/enums.rs | 30 ++++++++
embassy-stm32/src/can/util.rs | 117 +++++++++++++++++++++++++++++++
embassy-stm32/src/rcc/g4.rs | 7 +-
embassy-stm32/src/rcc/h.rs | 8 ++-
6 files changed, 173 insertions(+), 115 deletions(-)
create mode 100644 embassy-stm32/src/can/enums.rs
create mode 100644 embassy-stm32/src/can/util.rs
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 948ce3aff..414723573 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -449,7 +449,7 @@ fn main() {
// ========
// Generate RccPeripheral impls
- let refcounted_peripherals = HashSet::from(["usart", "adc"]);
+ let refcounted_peripherals = HashSet::from(["usart", "adc", "can"]);
let mut refcount_statics = BTreeSet::new();
for p in METADATA.peripherals {
diff --git a/embassy-stm32/src/can/bxcan.rs b/embassy-stm32/src/can/bxcan.rs
index cc87b2565..7e00eca6f 100644
--- a/embassy-stm32/src/can/bxcan.rs
+++ b/embassy-stm32/src/can/bxcan.rs
@@ -13,9 +13,12 @@ use crate::gpio::sealed::AFType;
use crate::interrupt::typelevel::Interrupt;
use crate::pac::can::vals::{Ide, Lec};
use crate::rcc::RccPeripheral;
-use crate::time::Hertz;
use crate::{interrupt, peripherals, Peripheral};
+pub mod enums;
+use enums::*;
+pub mod util;
+
/// Contains CAN frame and additional metadata.
///
/// Timestamp is available if `time` feature is enabled.
@@ -93,23 +96,6 @@ pub struct Can<'d, T: Instance> {
can: bxcan::Can<BxcanInstance<'d, T>>,
}
-/// CAN bus error
-#[allow(missing_docs)]
-#[derive(Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum BusError {
- Stuff,
- Form,
- Acknowledge,
- BitRecessive,
- BitDominant,
- Crc,
- Software,
- BusOff,
- BusPassive,
- BusWarning,
-}
-
/// Error returned by `try_read`
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -186,8 +172,15 @@ impl<'d, T: Instance> Can<'d, T> {
/// Set CAN bit rate.
pub fn set_bitrate(&mut self, bitrate: u32) {
- let bit_timing = Self::calc_bxcan_timings(T::frequency(), bitrate).unwrap();
- self.can.modify_config().set_bit_timing(bit_timing).leave_disabled();
+ let bit_timing = util::calc_can_timings(T::frequency(), bitrate).unwrap();
+ let sjw = u8::from(bit_timing.sync_jump_width) as u32;
+ let seg1 = u8::from(bit_timing.seg1) as u32;
+ let seg2 = u8::from(bit_timing.seg2) as u32;
+ let prescaler = u16::from(bit_timing.prescaler) as u32;
+ self.can
+ .modify_config()
+ .set_bit_timing((sjw - 1) << 24 | (seg1 - 1) << 16 | (seg2 - 1) << 20 | (prescaler - 1))
+ .leave_disabled();
}
/// Enables the peripheral and synchronizes with the bus.
@@ -302,97 +295,6 @@ impl<'d, T: Instance> Can<'d, T> {
}
}
- const fn calc_bxcan_timings(periph_clock: Hertz, can_bitrate: u32) -> Option<u32> {
- const BS1_MAX: u8 = 16;
- const BS2_MAX: u8 = 8;
- const MAX_SAMPLE_POINT_PERMILL: u16 = 900;
-
- let periph_clock = periph_clock.0;
-
- if can_bitrate < 1000 {
- return None;
- }
-
- // Ref. "Automatic Baudrate Detection in CANopen Networks", U. Koppe, MicroControl GmbH & Co. KG
- // CAN in Automation, 2003
- //
- // According to the source, optimal quanta per bit are:
- // Bitrate Optimal Maximum
- // 1000 kbps 8 10
- // 500 kbps 16 17
- // 250 kbps 16 17
- // 125 kbps 16 17
- let max_quanta_per_bit: u8 = if can_bitrate >= 1_000_000 { 10 } else { 17 };
-
- // Computing (prescaler * BS):
- // BITRATE = 1 / (PRESCALER * (1 / PCLK) * (1 + BS1 + BS2)) -- See the Reference Manual
- // BITRATE = PCLK / (PRESCALER * (1 + BS1 + BS2)) -- Simplified
- // let:
- // BS = 1 + BS1 + BS2 -- Number of time quanta per bit
- // PRESCALER_BS = PRESCALER * BS
- // ==>
- // PRESCALER_BS = PCLK / BITRATE
- let prescaler_bs = periph_clock / can_bitrate;
-
- // Searching for such prescaler value so that the number of quanta per bit is highest.
- let mut bs1_bs2_sum = max_quanta_per_bit - 1;
- while (prescaler_bs % (1 + bs1_bs2_sum) as u32) != 0 {
- if bs1_bs2_sum <= 2 {
- return None; // No solution
- }
- bs1_bs2_sum -= 1;
- }
-
- let prescaler = prescaler_bs / (1 + bs1_bs2_sum) as u32;
- if (prescaler < 1) || (prescaler > 1024) {
- return None; // No solution
- }
-
- // Now we have a constraint: (BS1 + BS2) == bs1_bs2_sum.
- // We need to find such values so that the sample point is as close as possible to the optimal value,
- // which is 87.5%, which is 7/8.
- //
- // Solve[(1 + bs1)/(1 + bs1 + bs2) == 7/8, bs2] (* Where 7/8 is 0.875, the recommended sample point location *)
- // {{bs2 -> (1 + bs1)/7}}
- //
- // Hence:
- // bs2 = (1 + bs1) / 7
- // bs1 = (7 * bs1_bs2_sum - 1) / 8
- //
- // Sample point location can be computed as follows:
- // Sample point location = (1 + bs1) / (1 + bs1 + bs2)
- //
- // Since the optimal solution is so close to the maximum, we prepare two solutions, and then pick the best one:
- // - With rounding to nearest
- // - With rounding to zero
- let mut bs1 = ((7 * bs1_bs2_sum - 1) + 4) / 8; // Trying rounding to nearest first
- let mut bs2 = bs1_bs2_sum - bs1;
- core::assert!(bs1_bs2_sum > bs1);
-
- let sample_point_permill = 1000 * ((1 + bs1) / (1 + bs1 + bs2)) as u16;
- if sample_point_permill > MAX_SAMPLE_POINT_PERMILL {
- // Nope, too far; now rounding to zero
- bs1 = (7 * bs1_bs2_sum - 1) / 8;
- bs2 = bs1_bs2_sum - bs1;
- }
-
- // Check is BS1 and BS2 are in range
- if (bs1 < 1) || (bs1 > BS1_MAX) || (bs2 < 1) || (bs2 > BS2_MAX) {
- return None;
- }
-
- // Check if final bitrate matches the requested
- if can_bitrate != (periph_clock / (prescaler * (1 + bs1 + bs2) as u32)) {
- return None;
- }
-
- // One is recommended by DS-015, CANOpen, and DeviceNet
- let sjw = 1;
-
- // Pack into BTR register values
- Some((sjw - 1) << 24 | (bs1 as u32 - 1) << 16 | (bs2 as u32 - 1) << 20 | (prescaler - 1))
- }
-
/// Split the CAN driver into transmit and receive halves.
///
/// Useful for doing separate transmit/receive tasks.
diff --git a/embassy-stm32/src/can/enums.rs b/embassy-stm32/src/can/enums.rs
new file mode 100644
index 000000000..36139a45c
--- /dev/null
+++ b/embassy-stm32/src/can/enums.rs
@@ -0,0 +1,30 @@
+//! Enums shared between CAN controller types.
+
+/// Bus error
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum BusError {
+ /// Bit stuffing error - more than 5 equal bits
+ Stuff,
+ /// Form error - A fixed format part of a received message has wrong format
+ Form,
+ /// The message transmitted by the FDCAN was not acknowledged by another node.
+ Acknowledge,
+ /// Bit0Error: During the transmission of a message the device wanted to send a dominant level
+ /// but the monitored bus value was recessive.
+ BitRecessive,
+ /// Bit1Error: During the transmission of a message the device wanted to send a recessive level
+ /// but the monitored bus value was dominant.
+ BitDominant,
+ /// The CRC check sum of a received message was incorrect. The CRC of an
+ /// incoming message does not match with the CRC calculated from the received data.
+ Crc,
+ /// A software error occured
+ Software,
+ /// The FDCAN is in Bus_Off state.
+ BusOff,
+ /// The FDCAN is in the Error_Passive state.
+ BusPassive,
+ /// At least one of error counter has reached the Error_Warning limit of 96.
+ BusWarning,
+}
diff --git a/embassy-stm32/src/can/util.rs b/embassy-stm32/src/can/util.rs
new file mode 100644
index 000000000..fcdbbad62
--- /dev/null
+++ b/embassy-stm32/src/can/util.rs
@@ -0,0 +1,117 @@
+//! Utility functions shared between CAN controller types.
+
+use core::num::{NonZeroU16, NonZeroU8};
+
+/// Shared struct to represent bit timings used by calc_can_timings.
+#[derive(Clone, Copy, Debug)]
+pub struct NominalBitTiming {
+ /// Value by which the oscillator frequency is divided for generating the bit time quanta. The bit
+ /// time is built up from a multiple of this quanta. Valid values are 1 to 512.
+ pub prescaler: NonZeroU16,
+ /// Valid values are 1 to 128.
+ pub seg1: NonZeroU8,
+ /// Valid values are 1 to 255.
+ pub seg2: NonZeroU8,
+ /// Valid values are 1 to 128.
+ pub sync_jump_width: NonZeroU8,
+}
+
+/// Calculate nominal CAN bit timing based on CAN bitrate and periphial clock frequency
+pub fn calc_can_timings(periph_clock: crate::time::Hertz, can_bitrate: u32) -> Option<NominalBitTiming> {
+ const BS1_MAX: u8 = 16;
+ const BS2_MAX: u8 = 8;
+ const MAX_SAMPLE_POINT_PERMILL: u16 = 900;
+
+ let periph_clock = periph_clock.0;
+
+ if can_bitrate < 1000 {
+ return None;
+ }
+
+ // Ref. "Automatic Baudrate Detection in CANopen Networks", U. Koppe, MicroControl GmbH & Co. KG
+ // CAN in Automation, 2003
+ //
+ // According to the source, optimal quanta per bit are:
+ // Bitrate Optimal Maximum
+ // 1000 kbps 8 10
+ // 500 kbps 16 17
+ // 250 kbps 16 17
+ // 125 kbps 16 17
+ let max_quanta_per_bit: u8 = if can_bitrate >= 1_000_000 { 10 } else { 17 };
+
+ // Computing (prescaler * BS):
+ // BITRATE = 1 / (PRESCALER * (1 / PCLK) * (1 + BS1 + BS2)) -- See the Reference Manual
+ // BITRATE = PCLK / (PRESCALER * (1 + BS1 + BS2)) -- Simplified
+ // let:
+ // BS = 1 + BS1 + BS2 -- Number of time quanta per bit
+ // PRESCALER_BS = PRESCALER * BS
+ // ==>
+ // PRESCALER_BS = PCLK / BITRATE
+ let prescaler_bs = periph_clock / can_bitrate;
+
+ // Searching for such prescaler value so that the number of quanta per bit is highest.
+ let mut bs1_bs2_sum = max_quanta_per_bit - 1;
+ while (prescaler_bs % (1 + bs1_bs2_sum) as u32) != 0 {
+ if bs1_bs2_sum <= 2 {
+ return None; // No solution
+ }
+ bs1_bs2_sum -= 1;
+ }
+
+ let prescaler = prescaler_bs / (1 + bs1_bs2_sum) as u32;
+ if (prescaler < 1) || (prescaler > 1024) {
+ return None; // No solution
+ }
+
+ // Now we have a constraint: (BS1 + BS2) == bs1_bs2_sum.
+ // We need to find such values so that the sample point is as close as possible to the optimal value,
+ // which is 87.5%, which is 7/8.
+ //
+ // Solve[(1 + bs1)/(1 + bs1 + bs2) == 7/8, bs2] (* Where 7/8 is 0.875, the recommended sample point location *)
+ // {{bs2 -> (1 + bs1)/7}}
+ //
+ // Hence:
+ // bs2 = (1 + bs1) / 7
+ // bs1 = (7 * bs1_bs2_sum - 1) / 8
+ //
+ // Sample point location can be computed as follows:
+ // Sample point location = (1 + bs1) / (1 + bs1 + bs2)
+ //
+ // Since the optimal solution is so close to the maximum, we prepare two solutions, and then pick the best one:
+ // - With rounding to nearest
+ // - With rounding to zero
+ let mut bs1 = ((7 * bs1_bs2_sum - 1) + 4) / 8; // Trying rounding to nearest first
+ let mut bs2 = bs1_bs2_sum - bs1;
+ core::assert!(bs1_bs2_sum > bs1);
+
+ let sample_point_permill = 1000 * ((1 + bs1) / (1 + bs1 + bs2)) as u16;
+ if sample_point_permill > MAX_SAMPLE_POINT_PERMILL {
+ // Nope, too far; now rounding to zero
+ bs1 = (7 * bs1_bs2_sum - 1) / 8;
+ bs2 = bs1_bs2_sum - bs1;
+ }
+
+ // Check is BS1 and BS2 are in range
+ if (bs1 < 1) || (bs1 > BS1_MAX) || (bs2 < 1) || (bs2 > BS2_MAX) {
+ return None;
+ }
+
+ // Check if final bitrate matches the requested
+ if can_bitrate != (periph_clock / (prescaler * (1 + bs1 + bs2) as u32)) {
+ return None;
+ }
+
+ // One is recommended by DS-015, CANOpen, and DeviceNet
+ let sync_jump_width = core::num::NonZeroU8::new(1)?;
+
+ let seg1 = core::num::NonZeroU8::new(bs1)?;
+ let seg2 = core::num::NonZeroU8::new(bs2)?;
+ let nz_prescaler = core::num::NonZeroU16::new(prescaler as u16)?;
+
+ Some(NominalBitTiming {
+ sync_jump_width,
+ prescaler: nz_prescaler,
+ seg1,
+ seg2,
+ })
+}
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index fca364c21..891f0490b 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -3,8 +3,8 @@ use stm32_metapac::rcc::vals::{Adcsel, Pllsrc, Sw};
use stm32_metapac::FLASH;
pub use crate::pac::rcc::vals::{
- Adcsel as AdcClockSource, Hpre as AHBPrescaler, Pllm as PllM, Plln as PllN, Pllp as PllP, Pllq as PllQ,
- Pllr as PllR, Ppre as APBPrescaler,
+ Adcsel as AdcClockSource, Fdcansel as FdCanClockSource, Hpre as AHBPrescaler, Pllm as PllM, Plln as PllN,
+ Pllp as PllP, Pllq as PllQ, Pllr as PllR, Ppre as APBPrescaler,
};
use crate::pac::{PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
@@ -87,6 +87,7 @@ pub struct Config {
pub clock_48mhz_src: Option<Clock48MhzSrc>,
pub adc12_clock_source: AdcClockSource,
pub adc345_clock_source: AdcClockSource,
+ pub fdcan_clock_source: FdCanClockSource,
pub ls: super::LsConfig,
}
@@ -104,6 +105,7 @@ impl Default for Config {
clock_48mhz_src: Some(Clock48MhzSrc::Hsi48(Default::default())),
adc12_clock_source: Adcsel::DISABLE,
adc345_clock_source: Adcsel::DISABLE,
+ fdcan_clock_source: FdCanClockSource::PCLK1,
ls: Default::default(),
}
}
@@ -282,6 +284,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr().modify(|w| w.set_adc12sel(config.adc12_clock_source));
RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
+ RCC.ccipr().modify(|w| w.set_fdcansel(config.fdcan_clock_source));
let adc12_ck = match config.adc12_clock_source {
AdcClockSource::DISABLE => None,
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 15b51a398..85e12637e 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -6,6 +6,7 @@ use crate::pac::pwr::vals::Vos;
pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
#[cfg(stm32h7)]
pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
+pub use crate::pac::rcc::vals::Fdcansel as FdCanClockSource;
pub use crate::pac::rcc::vals::{
Ckpersel as PerClockSource, Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
Pllsrc as PllSource, Sw as Sysclk,
@@ -212,6 +213,8 @@ pub struct Config {
pub per_clock_source: PerClockSource,
pub adc_clock_source: AdcClockSource,
+ pub fdcan_clock_source: FdCanClockSource,
+
pub timer_prescaler: TimerPrescaler,
pub voltage_scale: VoltageScale,
pub ls: super::LsConfig,
@@ -248,6 +251,8 @@ impl Default for Config {
#[cfg(stm32h7)]
adc_clock_source: AdcClockSource::PER,
+ fdcan_clock_source: FdCanClockSource::from_bits(0), // HSE
+
timer_prescaler: TimerPrescaler::DefaultX2,
voltage_scale: VoltageScale::Scale0,
ls: Default::default(),
@@ -585,7 +590,8 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr5().modify(|w| {
w.set_ckpersel(config.per_clock_source);
- w.set_adcdacsel(config.adc_clock_source)
+ w.set_adcdacsel(config.adc_clock_source);
+ w.set_fdcan1sel(config.fdcan_clock_source)
});
}
From 1de78d049017b7d21946a2e64d94c990f1bf4e7e Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sun, 14 Jan 2024 10:12:49 +0100
Subject: [PATCH 090/392] Initial FDCAN driver implementation.
Original author:
Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Cleanup and documentaion by:
Tomasz bla Fortuna <bla@reactor.local>
Corey Schuhen <cschuhen@gmail.com>
Use new PAC method now that the names are common.
Use broken out definitions that can be shared with bxcan
Populate Rx struct with an embassy timestamp.
Remove use of RefCell.
As per review comment. - THis will probably get squashed down.
Fix
---
embassy-stm32/src/can/fdcan.rs | 714 ++++++++++++++++++++++++++++++++-
embassy-stm32/src/rcc/h.rs | 7 +-
2 files changed, 706 insertions(+), 15 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 0cc2559cf..faf4af73f 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -1,14 +1,577 @@
-use crate::peripherals;
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::ops::{Deref, DerefMut};
+use core::task::Poll;
+
+use cfg_if::cfg_if;
+use embassy_hal_internal::{into_ref, PeripheralRef};
+pub use fdcan::frame::{FrameFormat, RxFrameInfo, TxFrameHeader};
+pub use fdcan::id::{ExtendedId, Id, StandardId};
+use fdcan::message_ram::RegisterBlock;
+use fdcan::{self, LastErrorCode};
+pub use fdcan::{config, filter};
+
+use crate::gpio::sealed::AFType;
+use crate::interrupt::typelevel::Interrupt;
+use crate::rcc::RccPeripheral;
+use crate::{interrupt, peripherals, Peripheral};
+
+pub mod enums;
+use enums::*;
+pub mod util;
+
+/// CAN Frame returned by read
+pub struct RxFrame {
+ /// CAN Header info: frame ID, data length and other meta
+ pub header: RxFrameInfo,
+ /// CAN(0-8 bytes) or FDCAN(0-64 bytes) Frame data
+ pub data: Data,
+ /// Reception time.
+ #[cfg(feature = "time")]
+ pub timestamp: embassy_time::Instant,
+}
+
+/// CAN frame used for write
+pub struct TxFrame {
+ /// CAN Header info: frame ID, data length and other meta
+ pub header: TxFrameHeader,
+ /// CAN(0-8 bytes) or FDCAN(0-64 bytes) Frame data
+ pub data: Data,
+}
+
+impl TxFrame {
+ /// Create new TX frame from header and data
+ pub fn new(header: TxFrameHeader, data: &[u8]) -> Option<Self> {
+ if data.len() < header.len as usize {
+ return None;
+ }
+
+ let Some(data) = Data::new(data) else { return None };
+
+ Some(TxFrame { header, data })
+ }
+
+ fn from_preserved(header: TxFrameHeader, data32: &[u32]) -> Option<Self> {
+ let mut data = [0u8; 64];
+
+ for i in 0..data32.len() {
+ data[4 * i..][..4].copy_from_slice(&data32[i].to_le_bytes());
+ }
+
+ let Some(data) = Data::new(&data) else { return None };
+
+ Some(TxFrame { header, data })
+ }
+
+ /// Access frame data. Slice length will match header.
+ pub fn data(&self) -> &[u8] {
+ &self.data.bytes[..(self.header.len as usize)]
+ }
+}
+
+impl RxFrame {
+ pub(crate) fn new(
+ header: RxFrameInfo,
+ data: &[u8],
+ #[cfg(feature = "time")] timestamp: embassy_time::Instant,
+ ) -> Self {
+ let data = Data::new(&data).unwrap_or_else(|| Data::empty());
+
+ RxFrame {
+ header,
+ data,
+ #[cfg(feature = "time")]
+ timestamp,
+ }
+ }
+
+ /// Access frame data. Slice length will match header.
+ pub fn data(&self) -> &[u8] {
+ &self.data.bytes[..(self.header.len as usize)]
+ }
+}
+
+/// Payload of a (FD)CAN data frame.
+///
+/// Contains 0 to 64 Bytes of data.
+#[derive(Debug, Copy, Clone)]
+pub struct Data {
+ pub(crate) bytes: [u8; 64],
+}
+
+impl Data {
+ /// Creates a data payload from a raw byte slice.
+ ///
+ /// Returns `None` if `data` is more than 64 bytes (which is the maximum) or
+ /// cannot be represented with an FDCAN DLC.
+ pub fn new(data: &[u8]) -> Option<Self> {
+ if !Data::is_valid_len(data.len()) {
+ return None;
+ }
+
+ let mut bytes = [0; 64];
+ bytes[..data.len()].copy_from_slice(data);
+
+ Some(Self { bytes })
+ }
+
+ /// Raw read access to data.
+ pub fn raw(&self) -> &[u8] {
+ &self.bytes
+ }
+
+ /// Checks if the length can be encoded in FDCAN DLC field.
+ pub const fn is_valid_len(len: usize) -> bool {
+ match len {
+ 0..=8 => true,
+ 12 => true,
+ 16 => true,
+ 20 => true,
+ 24 => true,
+ 32 => true,
+ 48 => true,
+ 64 => true,
+ _ => false,
+ }
+ }
+
+ /// Creates an empty data payload containing 0 bytes.
+ #[inline]
+ pub const fn empty() -> Self {
+ Self { bytes: [0; 64] }
+ }
+}
+
+/// Interrupt handler channel 0.
+pub struct IT0InterruptHandler<T: Instance> {
+ _phantom: PhantomData<T>,
+}
+
+// We use IT0 for everything currently
+impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0InterruptHandler<T> {
+ unsafe fn on_interrupt() {
+ let regs = T::regs();
+
+ let ir = regs.ir().read();
+
+ if ir.tc() {
+ regs.ir().write(|w| w.set_tc(true));
+ T::state().tx_waker.wake();
+ }
+
+ if ir.tefn() {
+ regs.ir().write(|w| w.set_tefn(true));
+ T::state().tx_waker.wake();
+ }
+
+ if ir.ped() || ir.pea() {
+ regs.ir().write(|w| {
+ w.set_ped(true);
+ w.set_pea(true);
+ });
+ }
+
+ if ir.rfn(0) {
+ regs.ir().write(|w| w.set_rfn(0, true));
+ T::state().rx_waker.wake();
+ }
+
+ if ir.rfn(1) {
+ regs.ir().write(|w| w.set_rfn(1, true));
+ T::state().rx_waker.wake();
+ }
+ }
+}
+
+/// Interrupt handler channel 1.
+pub struct IT1InterruptHandler<T: Instance> {
+ _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::IT1Interrupt> for IT1InterruptHandler<T> {
+ unsafe fn on_interrupt() {}
+}
+
+impl BusError {
+ fn try_from(lec: LastErrorCode) -> Option<BusError> {
+ match lec {
+ LastErrorCode::AckError => Some(BusError::Acknowledge),
+ // `0` data bit encodes a dominant state. `1` data bit is recessive.
+ // Bit0Error: During transmit, the node wanted to send a 0 but monitored a 1
+ LastErrorCode::Bit0Error => Some(BusError::BitRecessive),
+ LastErrorCode::Bit1Error => Some(BusError::BitDominant),
+ LastErrorCode::CRCError => Some(BusError::Crc),
+ LastErrorCode::FormError => Some(BusError::Form),
+ LastErrorCode::StuffError => Some(BusError::Stuff),
+ _ => None,
+ }
+ }
+}
+
+/// Operating modes trait
+pub trait FdcanOperatingMode {}
+impl FdcanOperatingMode for fdcan::PoweredDownMode {}
+impl FdcanOperatingMode for fdcan::ConfigMode {}
+impl FdcanOperatingMode for fdcan::InternalLoopbackMode {}
+impl FdcanOperatingMode for fdcan::ExternalLoopbackMode {}
+impl FdcanOperatingMode for fdcan::NormalOperationMode {}
+impl FdcanOperatingMode for fdcan::RestrictedOperationMode {}
+impl FdcanOperatingMode for fdcan::BusMonitoringMode {}
+impl FdcanOperatingMode for fdcan::TestMode {}
+
+/// FDCAN Instance
+pub struct Fdcan<'d, T: Instance, M: FdcanOperatingMode> {
+ /// Reference to internals.
+ pub can: fdcan::FdCan<FdcanInstance<'d, T>, M>,
+ ns_per_timer_tick: u64, // For FDCAN internal timer
+}
+
+fn calc_ns_per_timer_tick<T: Instance>(mode: config::FrameTransmissionConfig) -> u64 {
+ match mode {
+ // Use timestamp from Rx FIFO to adjust timestamp reported to user
+ config::FrameTransmissionConfig::ClassicCanOnly => {
+ let freq = T::frequency();
+ let prescale: u64 =
+ ({ T::regs().nbtp().read().nbrp() } + 1) as u64 * ({ T::regs().tscc().read().tcp() } + 1) as u64;
+ 1_000_000_000 as u64 / (freq.0 as u64 * prescale)
+ }
+ // For VBR this is too hard because the FDCAN timer switches clock rate you need to configure to use
+ // timer3 instead which is too hard to do from this module.
+ _ => 0,
+ }
+}
+
+#[cfg(feature = "time")]
+fn calc_timestamp<T: Instance>(ns_per_timer_tick: u64, ts_val: u16) -> embassy_time::Instant {
+ let now_embassy = embassy_time::Instant::now();
+ if ns_per_timer_tick == 0 {
+ return now_embassy;
+ }
+ let now_can = { T::regs().tscv().read().tsc() };
+ let delta = now_can.overflowing_sub(ts_val).0 as u64;
+ let ns = ns_per_timer_tick * delta as u64;
+ now_embassy - embassy_time::Duration::from_nanos(ns)
+}
+
+fn curr_error<T: Instance>() -> Option<BusError> {
+ let err = { T::regs().psr().read() };
+ if err.bo() {
+ return Some(BusError::BusOff);
+ } else if err.ep() {
+ return Some(BusError::BusPassive);
+ } else if err.ew() {
+ return Some(BusError::BusWarning);
+ } else {
+ cfg_if! {
+ if #[cfg(stm32h7)] {
+ let lec = err.lec();
+ } else {
+ let lec = err.lec().to_bits();
+ }
+ }
+ if let Ok(err) = LastErrorCode::try_from(lec) {
+ return BusError::try_from(err);
+ }
+ }
+ None
+}
+
+impl<'d, T: Instance> Fdcan<'d, T, fdcan::ConfigMode> {
+ /// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
+ /// You must call [Fdcan::enable_non_blocking] to use the peripheral.
+ pub fn new(
+ peri: impl Peripheral<P = T> + 'd,
+ rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+ tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+ _irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
+ + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
+ + 'd,
+ ) -> Fdcan<'d, T, fdcan::ConfigMode> {
+ into_ref!(peri, rx, tx);
+
+ rx.set_as_af(rx.af_num(), AFType::Input);
+ tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
+
+ T::enable_and_reset();
+
+ rx.set_as_af(rx.af_num(), AFType::Input);
+ tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
+
+ let mut can = fdcan::FdCan::new(FdcanInstance(peri)).into_config_mode();
+
+ T::configure_msg_ram();
+ unsafe {
+ // Enable timestamping
+ #[cfg(not(stm32h7))]
+ T::regs()
+ .tscc()
+ .write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
+ #[cfg(stm32h7)]
+ T::regs().tscc().write(|w| w.set_tss(0x01));
+
+ T::IT0Interrupt::unpend(); // Not unsafe
+ T::IT0Interrupt::enable();
+
+ T::IT1Interrupt::unpend(); // Not unsafe
+ T::IT1Interrupt::enable();
+
+ // this isn't really documented in the reference manual
+ // but corresponding txbtie bit has to be set for the TC (TxComplete) interrupt to fire
+ T::regs().txbtie().write(|w| w.0 = 0xffff_ffff);
+ }
+
+ can.enable_interrupt(fdcan::interrupt::Interrupt::RxFifo0NewMsg);
+ can.enable_interrupt(fdcan::interrupt::Interrupt::RxFifo1NewMsg);
+ can.enable_interrupt(fdcan::interrupt::Interrupt::TxComplete);
+ can.enable_interrupt_line(fdcan::interrupt::InterruptLine::_0, true);
+ can.enable_interrupt_line(fdcan::interrupt::InterruptLine::_1, true);
+
+ let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(can.get_config().frame_transmit);
+ Self { can, ns_per_timer_tick }
+ }
+
+ /// Configures the bit timings calculated from supplied bitrate.
+ pub fn set_bitrate(&mut self, bitrate: u32) {
+ let bit_timing = util::calc_can_timings(T::frequency(), bitrate).unwrap();
+ self.can.set_nominal_bit_timing(config::NominalBitTiming {
+ sync_jump_width: bit_timing.sync_jump_width,
+ prescaler: bit_timing.prescaler,
+ seg1: bit_timing.seg1,
+ seg2: bit_timing.seg2,
+ });
+ }
+}
+
+macro_rules! impl_transition {
+ ($from_mode:ident, $to_mode:ident, $name:ident, $func: ident) => {
+ impl<'d, T: Instance> Fdcan<'d, T, fdcan::$from_mode> {
+ /// Transition from $from_mode:ident mode to $to_mode:ident mode
+ pub fn $name(self) -> Fdcan<'d, T, fdcan::$to_mode> {
+ let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(self.can.get_config().frame_transmit);
+ Fdcan {
+ can: self.can.$func(),
+ ns_per_timer_tick,
+ }
+ }
+ }
+ };
+}
+
+impl_transition!(PoweredDownMode, ConfigMode, into_config_mode, into_config_mode);
+impl_transition!(InternalLoopbackMode, ConfigMode, into_config_mode, into_config_mode);
+
+impl_transition!(ConfigMode, NormalOperationMode, into_normal_mode, into_normal);
+impl_transition!(
+ ConfigMode,
+ ExternalLoopbackMode,
+ into_external_loopback_mode,
+ into_external_loopback
+);
+impl_transition!(
+ ConfigMode,
+ InternalLoopbackMode,
+ into_internal_loopback_mode,
+ into_internal_loopback
+);
+
+impl<'d, T: Instance, M: FdcanOperatingMode> Fdcan<'d, T, M>
+where
+ M: fdcan::Transmit,
+ M: fdcan::Receive,
+{
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write(&mut self, frame: &TxFrame) -> Option<TxFrame> {
+ poll_fn(|cx| {
+ T::state().tx_waker.register(cx.waker());
+ if let Ok(dropped) = self
+ .can
+ .transmit_preserve(frame.header, &frame.data.bytes, &mut |_, hdr, data32| {
+ TxFrame::from_preserved(hdr, data32)
+ })
+ {
+ return Poll::Ready(dropped.flatten());
+ }
+
+ // Couldn't replace any lower priority frames. Need to wait for some mailboxes
+ // to clear.
+ Poll::Pending
+ })
+ .await
+ }
+
+ /// Flush one of the TX mailboxes.
+ pub async fn flush(&self, mb: fdcan::Mailbox) {
+ poll_fn(|cx| {
+ T::state().tx_waker.register(cx.waker());
+
+ let idx: u8 = mb.into();
+ let idx = 1 << idx;
+ if !T::regs().txbrp().read().trp(idx) {
+ return Poll::Ready(());
+ }
+
+ Poll::Pending
+ })
+ .await;
+ }
+
+ /// Returns the next received message frame
+ pub async fn read(&mut self) -> Result<RxFrame, BusError> {
+ poll_fn(|cx| {
+ T::state().err_waker.register(cx.waker());
+ T::state().rx_waker.register(cx.waker());
+
+ let mut buffer: [u8; 64] = [0; 64];
+ if let Ok(rx) = self.can.receive0(&mut buffer) {
+ // rx: fdcan::ReceiveOverrun<RxFrameInfo>
+ // TODO: report overrun?
+ // for now we just drop it
+
+ let frame: RxFrame = RxFrame::new(
+ rx.unwrap(),
+ &buffer,
+ #[cfg(feature = "time")]
+ calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
+ );
+ return Poll::Ready(Ok(frame));
+ } else if let Ok(rx) = self.can.receive1(&mut buffer) {
+ // rx: fdcan::ReceiveOverrun<RxFrameInfo>
+ // TODO: report overrun?
+ // for now we just drop it
+
+ let frame: RxFrame = RxFrame::new(
+ rx.unwrap(),
+ &buffer,
+ #[cfg(feature = "time")]
+ calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
+ );
+ return Poll::Ready(Ok(frame));
+ } else if let Some(err) = curr_error::<T>() {
+ // TODO: this is probably wrong
+ return Poll::Ready(Err(err));
+ }
+ Poll::Pending
+ })
+ .await
+ }
+
+ /// Split instance into separate Tx(write) and Rx(read) portions
+ pub fn split<'c>(&'c mut self) -> (FdcanTx<'c, 'd, T, M>, FdcanRx<'c, 'd, T, M>) {
+ let (mut _control, tx, rx0, rx1) = self.can.split_by_ref();
+ (
+ FdcanTx { _control, tx },
+ FdcanRx {
+ rx0,
+ rx1,
+ ns_per_timer_tick: self.ns_per_timer_tick,
+ },
+ )
+ }
+}
+
+/// FDCAN Tx only Instance
+pub struct FdcanTx<'c, 'd, T: Instance, M: fdcan::Transmit> {
+ _control: &'c mut fdcan::FdCanControl<FdcanInstance<'d, T>, M>,
+ tx: &'c mut fdcan::Tx<FdcanInstance<'d, T>, M>,
+}
+
+impl<'c, 'd, T: Instance, M: fdcan::Transmit> FdcanTx<'c, 'd, T, M> {
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write(&mut self, frame: &TxFrame) -> Option<TxFrame> {
+ poll_fn(|cx| {
+ T::state().tx_waker.register(cx.waker());
+ if let Ok(dropped) = self
+ .tx
+ .transmit_preserve(frame.header, &frame.data.bytes, &mut |_, hdr, data32| {
+ TxFrame::from_preserved(hdr, data32)
+ })
+ {
+ return Poll::Ready(dropped.flatten());
+ }
+
+ // Couldn't replace any lower priority frames. Need to wait for some mailboxes
+ // to clear.
+ Poll::Pending
+ })
+ .await
+ }
+}
+
+/// FDCAN Rx only Instance
+#[allow(dead_code)]
+pub struct FdcanRx<'c, 'd, T: Instance, M: fdcan::Receive> {
+ rx0: &'c mut fdcan::Rx<FdcanInstance<'d, T>, M, fdcan::Fifo0>,
+ rx1: &'c mut fdcan::Rx<FdcanInstance<'d, T>, M, fdcan::Fifo1>,
+ ns_per_timer_tick: u64, // For FDCAN internal timer
+}
+
+impl<'c, 'd, T: Instance, M: fdcan::Receive> FdcanRx<'c, 'd, T, M> {
+ /// Returns the next received message frame
+ pub async fn read(&mut self) -> Result<RxFrame, BusError> {
+ poll_fn(|cx| {
+ T::state().err_waker.register(cx.waker());
+ T::state().rx_waker.register(cx.waker());
+
+ let mut buffer: [u8; 64] = [0; 64];
+ if let Ok(rx) = self.rx0.receive(&mut buffer) {
+ // rx: fdcan::ReceiveOverrun<RxFrameInfo>
+ // TODO: report overrun?
+ // for now we just drop it
+ let frame: RxFrame = RxFrame::new(
+ rx.unwrap(),
+ &buffer,
+ #[cfg(feature = "time")]
+ calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
+ );
+ return Poll::Ready(Ok(frame));
+ } else if let Ok(rx) = self.rx1.receive(&mut buffer) {
+ // rx: fdcan::ReceiveOverrun<RxFrameInfo>
+ // TODO: report overrun?
+ // for now we just drop it
+ let frame: RxFrame = RxFrame::new(
+ rx.unwrap(),
+ &buffer,
+ #[cfg(feature = "time")]
+ calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
+ );
+ return Poll::Ready(Ok(frame));
+ } else if let Some(err) = curr_error::<T>() {
+ // TODO: this is probably wrong
+ return Poll::Ready(Err(err));
+ }
+
+ Poll::Pending
+ })
+ .await
+ }
+}
+impl<'d, T: Instance, M: FdcanOperatingMode> Deref for Fdcan<'d, T, M> {
+ type Target = fdcan::FdCan<FdcanInstance<'d, T>, M>;
+
+ fn deref(&self) -> &Self::Target {
+ &self.can
+ }
+}
+
+impl<'d, T: Instance, M: FdcanOperatingMode> DerefMut for Fdcan<'d, T, M> {
+ fn deref_mut(&mut self) -> &mut Self::Target {
+ &mut self.can
+ }
+}
pub(crate) mod sealed {
- use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
- use embassy_sync::channel::Channel;
use embassy_sync::waitqueue::AtomicWaker;
pub struct State {
pub tx_waker: AtomicWaker,
pub err_waker: AtomicWaker,
- pub rx_queue: Channel<CriticalSectionRawMutex, (u16, bxcan::Frame), 32>,
+ pub rx_waker: AtomicWaker,
}
impl State {
@@ -16,25 +579,122 @@ pub(crate) mod sealed {
Self {
tx_waker: AtomicWaker::new(),
err_waker: AtomicWaker::new(),
- rx_queue: Channel::new(),
+ rx_waker: AtomicWaker::new(),
}
}
}
pub trait Instance {
+ const REGISTERS: *mut fdcan::RegisterBlock;
+ const MSG_RAM: *mut fdcan::message_ram::RegisterBlock;
+ const MSG_RAM_OFFSET: usize;
+
fn regs() -> &'static crate::pac::can::Fdcan;
fn state() -> &'static State;
+
+ #[cfg(not(stm32h7))]
+ fn configure_msg_ram() {}
+
+ #[cfg(stm32h7)]
+ fn configure_msg_ram() {
+ let r = Self::regs();
+
+ use fdcan::message_ram::*;
+ let mut offset_words = Self::MSG_RAM_OFFSET as u16;
+
+ // 11-bit filter
+ r.sidfc().modify(|w| w.set_flssa(offset_words));
+ offset_words += STANDARD_FILTER_MAX as u16;
+
+ // 29-bit filter
+ r.xidfc().modify(|w| w.set_flesa(offset_words));
+ offset_words += 2 * EXTENDED_FILTER_MAX as u16;
+
+ // Rx FIFO 0 and 1
+ for i in 0..=1 {
+ r.rxfc(i).modify(|w| {
+ w.set_fsa(offset_words);
+ w.set_fs(RX_FIFO_MAX);
+ w.set_fwm(RX_FIFO_MAX);
+ });
+ offset_words += 18 * RX_FIFO_MAX as u16;
+ }
+
+ // Rx buffer - see below
+ // Tx event FIFO
+ r.txefc().modify(|w| {
+ w.set_efsa(offset_words);
+ w.set_efs(TX_EVENT_MAX);
+ w.set_efwm(TX_EVENT_MAX);
+ });
+ offset_words += 2 * TX_EVENT_MAX as u16;
+
+ // Tx buffers
+ r.txbc().modify(|w| {
+ w.set_tbsa(offset_words);
+ w.set_tfqs(TX_FIFO_MAX);
+ });
+ offset_words += 18 * TX_FIFO_MAX as u16;
+
+ // Rx Buffer - not used
+ r.rxbc().modify(|w| {
+ w.set_rbsa(offset_words);
+ });
+
+ // TX event FIFO?
+ // Trigger memory?
+
+ // Set the element sizes to 16 bytes
+ r.rxesc().modify(|w| {
+ w.set_rbds(0b111);
+ for i in 0..=1 {
+ w.set_fds(i, 0b111);
+ }
+ });
+ r.txesc().modify(|w| {
+ w.set_tbds(0b111);
+ })
+ }
}
}
-/// Interruptable FDCAN instance.
-pub trait InterruptableInstance {}
-/// FDCAN instance.
-pub trait Instance: sealed::Instance + InterruptableInstance + 'static {}
+/// Trait for FDCAN interrupt channel 0
+pub trait IT0Instance {
+ /// Type for FDCAN interrupt channel 0
+ type IT0Interrupt: crate::interrupt::typelevel::Interrupt;
+}
-foreach_peripheral!(
- (can, $inst:ident) => {
+/// Trait for FDCAN interrupt channel 1
+pub trait IT1Instance {
+ /// Type for FDCAN interrupt channel 1
+ type IT1Interrupt: crate::interrupt::typelevel::Interrupt;
+}
+
+/// InterruptableInstance trait
+pub trait InterruptableInstance: IT0Instance + IT1Instance {}
+/// Instance trait
+pub trait Instance: sealed::Instance + RccPeripheral + InterruptableInstance + 'static {}
+/// Fdcan Instance struct
+pub struct FdcanInstance<'a, T>(PeripheralRef<'a, T>);
+
+unsafe impl<'d, T: Instance> fdcan::message_ram::Instance for FdcanInstance<'d, T> {
+ const MSG_RAM: *mut RegisterBlock = T::MSG_RAM;
+}
+
+unsafe impl<'d, T: Instance> fdcan::Instance for FdcanInstance<'d, T>
+where
+ FdcanInstance<'d, T>: fdcan::message_ram::Instance,
+{
+ const REGISTERS: *mut fdcan::RegisterBlock = T::REGISTERS;
+}
+
+macro_rules! impl_fdcan {
+ ($inst:ident, $msg_ram_inst:ident, $msg_ram_offset:literal) => {
impl sealed::Instance for peripherals::$inst {
+ const REGISTERS: *mut fdcan::RegisterBlock = crate::pac::$inst.as_ptr() as *mut _;
+ const MSG_RAM: *mut fdcan::message_ram::RegisterBlock = crate::pac::$msg_ram_inst.as_ptr() as *mut _;
+ const MSG_RAM_OFFSET: usize = $msg_ram_offset;
+
fn regs() -> &'static crate::pac::can::Fdcan {
&crate::pac::$inst
}
@@ -47,8 +707,40 @@ foreach_peripheral!(
impl Instance for peripherals::$inst {}
+ foreach_interrupt!(
+ ($inst,can,FDCAN,IT0,$irq:ident) => {
+ impl IT0Instance for peripherals::$inst {
+ type IT0Interrupt = crate::interrupt::typelevel::$irq;
+ }
+ };
+ ($inst,can,FDCAN,IT1,$irq:ident) => {
+ impl IT1Instance for peripherals::$inst {
+ type IT1Interrupt = crate::interrupt::typelevel::$irq;
+ }
+ };
+ );
+
impl InterruptableInstance for peripherals::$inst {}
};
+
+ ($inst:ident, $msg_ram_inst:ident) => {
+ impl_fdcan!($inst, $msg_ram_inst, 0);
+ };
+}
+
+#[cfg(not(stm32h7))]
+foreach_peripheral!(
+ (can, FDCAN) => { impl_fdcan!(FDCAN, FDCANRAM); };
+ (can, FDCAN1) => { impl_fdcan!(FDCAN1, FDCANRAM1); };
+ (can, FDCAN2) => { impl_fdcan!(FDCAN2, FDCANRAM2); };
+ (can, FDCAN3) => { impl_fdcan!(FDCAN3, FDCANRAM3); };
+);
+
+#[cfg(stm32h7)]
+foreach_peripheral!(
+ (can, FDCAN1) => { impl_fdcan!(FDCAN1, FDCANRAM, 0x0000); };
+ (can, FDCAN2) => { impl_fdcan!(FDCAN2, FDCANRAM, 0x0C00); };
+ (can, FDCAN3) => { impl_fdcan!(FDCAN3, FDCANRAM, 0x1800); };
);
pin_trait!(RxPin, Instance);
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 85e12637e..dcaf2dced 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -6,10 +6,9 @@ use crate::pac::pwr::vals::Vos;
pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
#[cfg(stm32h7)]
pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
-pub use crate::pac::rcc::vals::Fdcansel as FdCanClockSource;
pub use crate::pac::rcc::vals::{
- Ckpersel as PerClockSource, Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
- Pllsrc as PllSource, Sw as Sysclk,
+ Ckpersel as PerClockSource, Fdcansel as FdCanClockSource, Hsidiv as HSIPrescaler, Plldiv as PllDiv,
+ Pllm as PllPreDiv, Plln as PllMul, Pllsrc as PllSource, Sw as Sysclk,
};
use crate::pac::rcc::vals::{Ckpersel, Pllrge, Pllvcosel, Timpre};
use crate::pac::{FLASH, PWR, RCC};
@@ -591,7 +590,7 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr5().modify(|w| {
w.set_ckpersel(config.per_clock_source);
w.set_adcdacsel(config.adc_clock_source);
- w.set_fdcan1sel(config.fdcan_clock_source)
+ w.set_fdcan12sel(config.fdcan_clock_source)
});
}
From 1698f4dbc3b5f4e561c3edd20246af63c22da507 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Thu, 25 Jan 2024 17:10:25 +1000
Subject: [PATCH 091/392] Add FDCAN examples for STM32G4, STM32H5 and STM32H7
Fix examples
Fix examples
Fix examples.
---
examples/stm32g4/Cargo.toml | 2 +-
examples/stm32g4/src/bin/can.rs | 56 +++++++++++++++++++++++++
examples/stm32h5/src/bin/can.rs | 74 +++++++++++++++++++++++++++++++++
examples/stm32h7/src/bin/can.rs | 74 +++++++++++++++++++++++++++++++++
4 files changed, 205 insertions(+), 1 deletion(-)
create mode 100644 examples/stm32g4/src/bin/can.rs
create mode 100644 examples/stm32h5/src/bin/can.rs
create mode 100644 examples/stm32h7/src/bin/can.rs
diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index b87f461b4..895ad3e7c 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
[dependencies]
# Change stm32g491re to your chip name, if necessary.
-embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g473re", "memory-x", "unstable-pac", "exti", "fdcan"] }
+embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = [ "defmt", "time-driver-any", "stm32g491re", "memory-x", "unstable-pac", "exti"] }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
new file mode 100644
index 000000000..727921fba
--- /dev/null
+++ b/examples/stm32g4/src/bin/can.rs
@@ -0,0 +1,56 @@
+#![no_std]
+#![no_main]
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::peripherals::*;
+use embassy_stm32::{bind_interrupts, can, Config};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ FDCAN1_IT0 => can::IT0InterruptHandler<FDCAN1>;
+ FDCAN1_IT1 => can::IT1InterruptHandler<FDCAN1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let config = Config::default();
+
+ let peripherals = embassy_stm32::init(config);
+
+ let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
+
+ // 250k bps
+ can.set_bitrate(250_000);
+
+ info!("Configured");
+
+ //let mut can = can.into_external_loopback_mode();
+ let mut can = can.into_normal_mode();
+
+ let mut i = 0;
+ loop {
+ let frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::StandardId::new(0x123).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+ info!("Writing frame");
+ _ = can.write(&frame).await;
+
+ match can.read().await {
+ Ok(rx_frame) => info!("Rx: {}", rx_frame.data()[0]),
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ }
+}
diff --git a/examples/stm32h5/src/bin/can.rs b/examples/stm32h5/src/bin/can.rs
new file mode 100644
index 000000000..2906d1576
--- /dev/null
+++ b/examples/stm32h5/src/bin/can.rs
@@ -0,0 +1,74 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::peripherals::*;
+use embassy_stm32::{bind_interrupts, can, rcc, Config};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ FDCAN1_IT0 => can::IT0InterruptHandler<FDCAN1>;
+ FDCAN1_IT1 => can::IT1InterruptHandler<FDCAN1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let mut config = Config::default();
+
+ // configure FDCAN to use PLL1_Q at 64 MHz
+ config.rcc.pll1 = Some(rcc::Pll {
+ source: rcc::PllSource::HSI,
+ prediv: rcc::PllPreDiv::DIV4,
+ mul: rcc::PllMul::MUL8,
+ divp: None,
+ divq: Some(rcc::PllDiv::DIV2),
+ divr: None,
+ });
+ config.rcc.fdcan_clock_source = rcc::FdCanClockSource::PLL1_Q;
+
+ let peripherals = embassy_stm32::init(config);
+
+ let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
+
+ can.can.apply_config(
+ can::config::FdCanConfig::default().set_nominal_bit_timing(can::config::NominalBitTiming {
+ sync_jump_width: 1.try_into().unwrap(),
+ prescaler: 8.try_into().unwrap(),
+ seg1: 13.try_into().unwrap(),
+ seg2: 2.try_into().unwrap(),
+ }),
+ );
+
+ info!("Configured");
+
+ let mut can = can.into_external_loopback_mode();
+ //let mut can = can.into_normal_mode();
+
+ let mut i = 0;
+ loop {
+ let frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::StandardId::new(0x123).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+ info!("Writing frame");
+ _ = can.write(&frame).await;
+
+ match can.read().await {
+ Ok(rx_frame) => info!("Rx: {}", rx_frame.data()[0]),
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ }
+}
diff --git a/examples/stm32h7/src/bin/can.rs b/examples/stm32h7/src/bin/can.rs
new file mode 100644
index 000000000..2906d1576
--- /dev/null
+++ b/examples/stm32h7/src/bin/can.rs
@@ -0,0 +1,74 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::peripherals::*;
+use embassy_stm32::{bind_interrupts, can, rcc, Config};
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ FDCAN1_IT0 => can::IT0InterruptHandler<FDCAN1>;
+ FDCAN1_IT1 => can::IT1InterruptHandler<FDCAN1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let mut config = Config::default();
+
+ // configure FDCAN to use PLL1_Q at 64 MHz
+ config.rcc.pll1 = Some(rcc::Pll {
+ source: rcc::PllSource::HSI,
+ prediv: rcc::PllPreDiv::DIV4,
+ mul: rcc::PllMul::MUL8,
+ divp: None,
+ divq: Some(rcc::PllDiv::DIV2),
+ divr: None,
+ });
+ config.rcc.fdcan_clock_source = rcc::FdCanClockSource::PLL1_Q;
+
+ let peripherals = embassy_stm32::init(config);
+
+ let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
+
+ can.can.apply_config(
+ can::config::FdCanConfig::default().set_nominal_bit_timing(can::config::NominalBitTiming {
+ sync_jump_width: 1.try_into().unwrap(),
+ prescaler: 8.try_into().unwrap(),
+ seg1: 13.try_into().unwrap(),
+ seg2: 2.try_into().unwrap(),
+ }),
+ );
+
+ info!("Configured");
+
+ let mut can = can.into_external_loopback_mode();
+ //let mut can = can.into_normal_mode();
+
+ let mut i = 0;
+ loop {
+ let frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::StandardId::new(0x123).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+ info!("Writing frame");
+ _ = can.write(&frame).await;
+
+ match can.read().await {
+ Ok(rx_frame) => info!("Rx: {}", rx_frame.data()[0]),
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ }
+}
From 6e1047395d56dbbd1aa1a0352bdd3147e3994c5b Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Wed, 17 Jan 2024 21:13:24 +1000
Subject: [PATCH 092/392] HIL test for STM32 FDCAN support.
Internal loopback.
fdcan: use common.rs for HIL test.
Fix tests.
Fix tests.
Fix tests
Add HIL tests for H7 even though they are a bit crippled.
CI fixes
Bah
Test
bah
---
tests/stm32/Cargo.toml | 16 ++-
tests/stm32/src/bin/fdcan.rs | 243 +++++++++++++++++++++++++++++++++++
2 files changed, 254 insertions(+), 5 deletions(-)
create mode 100644 tests/stm32/src/bin/fdcan.rs
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index bf85f05d2..b8b52c076 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -14,11 +14,11 @@ stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not
stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma", "dac", "sdmmc"]
stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
-stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng"]
-stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
-stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng"]
-stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng"]
-stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng"]
+stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng", "fdcan"]
+stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "fdcan"]
+stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan"]
+stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan"]
+stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
@@ -37,6 +37,7 @@ sdmmc = []
stop = ["embassy-stm32/low-power", "embassy-stm32/low-power-debug-with-sleep"]
chrono = ["embassy-stm32/chrono", "dep:chrono"]
can = []
+fdcan = []
ble = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/ble"]
mac = ["dep:embassy-stm32-wpan", "embassy-stm32-wpan/mac"]
embassy-stm32-wpan = []
@@ -96,6 +97,11 @@ name = "eth"
path = "src/bin/eth.rs"
required-features = [ "eth",]
+[[bin]]
+name = "fdcan"
+path = "src/bin/fdcan.rs"
+required-features = [ "fdcan",]
+
[[bin]]
name = "gpio"
path = "src/bin/gpio.rs"
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
new file mode 100644
index 000000000..7363eaa16
--- /dev/null
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -0,0 +1,243 @@
+#![no_std]
+#![no_main]
+
+// required-features: fdcan
+
+#[path = "../common.rs"]
+mod common;
+use common::*;
+use defmt::assert;
+use embassy_executor::Spawner;
+use embassy_stm32::peripherals::*;
+use embassy_stm32::{bind_interrupts, can, Config};
+use embassy_time::{Duration, Instant};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ FDCAN1_IT0 => can::IT0InterruptHandler<FDCAN1>;
+ FDCAN1_IT1 => can::IT1InterruptHandler<FDCAN1>;
+});
+
+struct TestOptions {
+ config: Config,
+ max_latency: Duration,
+ second_fifo_working: bool,
+}
+
+#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi", feature = "stm32h563zi"))]
+fn options() -> TestOptions {
+ use embassy_stm32::rcc;
+ info!("H75 config");
+ let mut c = config();
+ c.rcc.hse = Some(rcc::Hse {
+ freq: embassy_stm32::time::Hertz(25_000_000),
+ mode: rcc::HseMode::Oscillator,
+ });
+ c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
+ TestOptions {
+ config: c,
+ max_latency: Duration::from_micros(3800),
+ second_fifo_working: false,
+ }
+}
+
+#[cfg(any(feature = "stm32h7a3zi"))]
+fn options() -> TestOptions {
+ use embassy_stm32::rcc;
+ info!("H7a config");
+ let mut c = config();
+ c.rcc.hse = Some(rcc::Hse {
+ freq: embassy_stm32::time::Hertz(25_000_000),
+ mode: rcc::HseMode::Oscillator,
+ });
+ c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
+ TestOptions {
+ config: c,
+ max_latency: Duration::from_micros(5500),
+ second_fifo_working: false,
+ }
+}
+
+#[cfg(any(feature = "stm32g491re"))]
+fn options() -> TestOptions {
+ info!("G4 config");
+ TestOptions {
+ config: config(),
+ max_latency: Duration::from_micros(500),
+ second_fifo_working: true,
+ }
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ //let peripherals = embassy_stm32::init(config());
+
+ let options = options();
+ let peripherals = embassy_stm32::init(options.config);
+
+ let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
+
+ // 250k bps
+ can.set_bitrate(250_000);
+
+ can.can.set_extended_filter(
+ can::filter::ExtendedFilterSlot::_0,
+ can::filter::ExtendedFilter::accept_all_into_fifo1(),
+ );
+
+ let mut can = can.into_internal_loopback_mode();
+
+ info!("CAN Configured");
+
+ let mut i: u8 = 0;
+ loop {
+ let tx_frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::StandardId::new(0x123).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+
+ info!("Transmitting frame...");
+ let tx_ts = Instant::now();
+ can.write(&tx_frame).await;
+
+ let envelope = can.read().await.unwrap();
+ info!("Frame received!");
+
+ // Check data.
+ assert!(i == envelope.data()[0], "{} == {}", i, envelope.data()[0]);
+
+ info!("loopback time {}", envelope.header.time_stamp);
+ info!("loopback frame {=u8}", envelope.data()[0]);
+ let latency = envelope.timestamp.saturating_duration_since(tx_ts);
+ info!("loopback latency {} us", latency.as_micros());
+
+ // Theoretical minimum latency is 55us, actual is usually ~80us
+ const MIN_LATENCY: Duration = Duration::from_micros(50);
+ // Was failing at 150 but we are not getting a real time stamp. I'm not
+ // sure if there are other delays
+ assert!(
+ MIN_LATENCY <= latency && latency <= options.max_latency,
+ "{} <= {} <= {}",
+ MIN_LATENCY,
+ latency,
+ options.max_latency
+ );
+
+ i += 1;
+ if i > 10 {
+ break;
+ }
+ }
+
+ let max_buffered = if options.second_fifo_working { 6 } else { 3 };
+
+ // Below here, check that we can receive from both FIFO0 and FIFO0
+ // Above we configured FIFO1 for extended ID packets. There are only 3 slots
+ // in each FIFO so make sure we write enough to fill them both up before reading.
+ for i in 0..3 {
+ // Try filling up the RX FIFO0 buffers with standard packets
+ let tx_frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::StandardId::new(0x123).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+ info!("Transmitting frame {}", i);
+ can.write(&tx_frame).await;
+ }
+ for i in 3..max_buffered {
+ // Try filling up the RX FIFO0 buffers with extended packets
+ let tx_frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::ExtendedId::new(0x1232344).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+
+ info!("Transmitting frame {}", i);
+ can.write(&tx_frame).await;
+ }
+
+ // Try and receive all 6 packets
+ for i in 0..max_buffered {
+ let envelope = can.read().await.unwrap();
+ match envelope.header.id {
+ can::Id::Extended(id) => {
+ info!("Extended received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ }
+ can::Id::Standard(id) => {
+ info!("Standard received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ }
+ }
+ }
+
+ // Test again with a split
+ let (mut tx, mut rx) = can.split();
+ for i in 0..3 {
+ // Try filling up the RX FIFO0 buffers with standard packets
+ let tx_frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::StandardId::new(0x123).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+
+ info!("Transmitting frame {}", i);
+ tx.write(&tx_frame).await;
+ }
+ for i in 3..max_buffered {
+ // Try filling up the RX FIFO0 buffers with extended packets
+ let tx_frame = can::TxFrame::new(
+ can::TxFrameHeader {
+ len: 1,
+ frame_format: can::FrameFormat::Standard,
+ id: can::ExtendedId::new(0x1232344).unwrap().into(),
+ bit_rate_switching: false,
+ marker: None,
+ },
+ &[i],
+ )
+ .unwrap();
+
+ info!("Transmitting frame {}", i);
+ tx.write(&tx_frame).await;
+ }
+
+ // Try and receive all 6 packets
+ for i in 0..max_buffered {
+ let envelope = rx.read().await.unwrap();
+ match envelope.header.id {
+ can::Id::Extended(id) => {
+ info!("Extended received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ }
+ can::Id::Standard(id) => {
+ info!("Standard received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ }
+ }
+ }
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
From a14dc8413abacc78002a972cd55b1fbf19bac6df Mon Sep 17 00:00:00 2001
From: Corey Schuhen <corey@schuhen.net>
Date: Wed, 31 Jan 2024 05:43:37 +1000
Subject: [PATCH 093/392] Disable h563 test.
---
tests/stm32/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index b8b52c076..cb1bd9a50 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -15,7 +15,7 @@ stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma"
stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng", "fdcan"]
-stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "fdcan"]
+stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan"]
stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan"]
stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
From 7ff21e8b8ba3bd03b4317abbc40f0e6a0b02289f Mon Sep 17 00:00:00 2001
From: Justin Beaurivage <justin@wearableavionics.com>
Date: Tue, 30 Jan 2024 17:06:57 -0500
Subject: [PATCH 094/392] Handle Uarte RX errors
---
embassy-nrf/Cargo.toml | 1 +
embassy-nrf/src/uarte.rs | 95 +++++++++++++++++++++++++++++++++++-----
2 files changed, 85 insertions(+), 11 deletions(-)
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 10f268b51..580f0e3e6 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -133,6 +133,7 @@ embedded-io = { version = "0.6.0" }
embedded-io-async = { version = "0.6.1" }
defmt = { version = "0.3", optional = true }
+bitflags = "2.4.2"
log = { version = "0.4.14", optional = true }
cortex-m-rt = ">=0.6.15,<0.8"
cortex-m = "0.7.6"
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 95434e7a7..90d851139 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -52,6 +52,39 @@ impl Default for Config {
}
}
+bitflags::bitflags! {
+ /// Error source flags
+ pub struct ErrorSource: u32 {
+ /// Buffer overrun
+ const OVERRUN = 0x01;
+ /// Parity error
+ const PARITY = 0x02;
+ /// Framing error
+ const FRAMING = 0x04;
+ /// Break condition
+ const BREAK = 0x08;
+ }
+}
+
+impl TryFrom<ErrorSource> for () {
+ type Error = Error;
+
+ #[inline]
+ fn try_from(errors: ErrorSource) -> Result<Self, Self::Error> {
+ if errors.contains(ErrorSource::OVERRUN) {
+ Err(Error::Overrun)
+ } else if errors.contains(ErrorSource::PARITY) {
+ Err(Error::Parity)
+ } else if errors.contains(ErrorSource::FRAMING) {
+ Err(Error::Framing)
+ } else if errors.contains(ErrorSource::BREAK) {
+ Err(Error::Break)
+ } else {
+ Ok(())
+ }
+ }
+}
+
/// UART error.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -61,6 +94,14 @@ pub enum Error {
BufferTooLong,
/// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
BufferNotInRAM,
+ /// Framing Error
+ Framing,
+ /// Parity Error
+ Parity,
+ /// Buffer Overrun
+ Overrun,
+ /// Break condition
+ Break,
}
/// Interrupt handler.
@@ -73,9 +114,16 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
let r = T::regs();
let s = T::state();
- if r.events_endrx.read().bits() != 0 {
+ let endrx = r.events_endrx.read().bits();
+ let error = r.events_error.read().bits();
+ if endrx != 0 || error != 0 {
s.endrx_waker.wake();
- r.intenclr.write(|w| w.endrx().clear());
+ if endrx != 0 {
+ r.intenclr.write(|w| w.endrx().clear());
+ }
+ if error != 0 {
+ r.intenclr.write(|w| w.error().clear());
+ }
}
if r.events_endtx.read().bits() != 0 {
s.endtx_waker.wake();
@@ -486,6 +534,13 @@ impl<'d, T: Instance> UarteRx<'d, T> {
Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config)
}
+ fn read_and_clear_errors(&mut self) -> Result<(), Error> {
+ let r = T::regs();
+ let err_bits = r.errorsrc.read().bits();
+ r.errorsrc.write(|w| unsafe { w.bits(err_bits) });
+ ErrorSource::from_bits_truncate(err_bits).try_into()
+ }
+
fn new_inner(
uarte: impl Peripheral<P = T> + 'd,
rxd: PeripheralRef<'d, AnyPin>,
@@ -572,7 +627,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
/// Read bytes until the buffer is filled.
pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
- if buffer.len() == 0 {
+ if buffer.is_empty() {
return Ok(());
}
if buffer.len() > EASY_DMA_SIZE {
@@ -588,8 +643,13 @@ impl<'d, T: Instance> UarteRx<'d, T> {
let drop = OnDrop::new(move || {
trace!("read drop: stopping");
- r.intenclr.write(|w| w.endrx().clear());
+ r.intenclr.write(|w| {
+ w.endrx().clear();
+ w.error().clear()
+ });
r.events_rxto.reset();
+ r.events_error.reset();
+ r.errorsrc.reset();
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
while r.events_endrx.read().bits() == 0 {}
@@ -601,17 +661,26 @@ impl<'d, T: Instance> UarteRx<'d, T> {
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
r.events_endrx.reset();
- r.intenset.write(|w| w.endrx().set());
+ r.events_error.reset();
+ r.intenset.write(|w| {
+ w.endrx().set();
+ w.error().set()
+ });
compiler_fence(Ordering::SeqCst);
trace!("startrx");
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
- poll_fn(|cx| {
+ let result = poll_fn(|cx| {
s.endrx_waker.register(cx.waker());
+
+ let maybe_err = self.read_and_clear_errors();
+ if let Err(e) = maybe_err {
+ return Poll::Ready(Err(e));
+ }
if r.events_endrx.read().bits() != 0 {
- return Poll::Ready(());
+ return Poll::Ready(Ok(()));
}
Poll::Pending
})
@@ -621,7 +690,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
r.events_rxstarted.reset();
drop.defuse();
- Ok(())
+ result
}
/// Read bytes until the buffer is filled.
@@ -642,19 +711,23 @@ impl<'d, T: Instance> UarteRx<'d, T> {
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
r.events_endrx.reset();
- r.intenclr.write(|w| w.endrx().clear());
+ r.events_error.reset();
+ r.intenclr.write(|w| {
+ w.endrx().clear();
+ w.error().clear()
+ });
compiler_fence(Ordering::SeqCst);
trace!("startrx");
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
- while r.events_endrx.read().bits() == 0 {}
+ while r.events_endrx.read().bits() == 0 && r.events_error.read().bits() == 0 {}
compiler_fence(Ordering::SeqCst);
r.events_rxstarted.reset();
- Ok(())
+ self.read_and_clear_errors()
}
}
From 1e698af05bc6e7e520d3f35ef661f34ea6ea359e Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Wed, 31 Jan 2024 14:04:48 -0500
Subject: [PATCH 095/392] Add timeout_at convenience function and example.
---
embassy-time/src/lib.rs | 2 +-
embassy-time/src/timer.rs | 15 ++++++-
examples/rp/src/bin/debounce.rs | 80 +++++++++++++++++++++++++++++++++
3 files changed, 95 insertions(+), 2 deletions(-)
create mode 100644 examples/rp/src/bin/debounce.rs
diff --git a/embassy-time/src/lib.rs b/embassy-time/src/lib.rs
index d27eb92f6..e7efce49c 100644
--- a/embassy-time/src/lib.rs
+++ b/embassy-time/src/lib.rs
@@ -32,7 +32,7 @@ pub use delay::{block_for, Delay};
pub use duration::Duration;
pub use embassy_time_driver::TICK_HZ;
pub use instant::Instant;
-pub use timer::{with_timeout, Ticker, TimeoutError, Timer};
+pub use timer::{timeout_at, with_timeout, Ticker, TimeoutError, Timer};
const fn gcd(a: u64, b: u64) -> u64 {
if b == 0 {
diff --git a/embassy-time/src/timer.rs b/embassy-time/src/timer.rs
index 565a65cb8..dbce9297c 100644
--- a/embassy-time/src/timer.rs
+++ b/embassy-time/src/timer.rs
@@ -8,7 +8,7 @@ use futures_util::{pin_mut, Stream};
use crate::{Duration, Instant};
-/// Error returned by [`with_timeout`] on timeout.
+/// Error returned by [`with_timeout`] and [`timeout_at`] on timeout.
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct TimeoutError;
@@ -26,6 +26,19 @@ pub async fn with_timeout<F: Future>(timeout: Duration, fut: F) -> Result<F::Out
}
}
+/// Runs a given future with a deadline time.
+///
+/// If the future completes before the deadline, its output is returned. Otherwise, on timeout,
+/// work on the future is stopped (`poll` is no longer called), the future is dropped and `Err(TimeoutError)` is returned.
+pub async fn timeout_at<F: Future>(at: Instant, fut: F) -> Result<F::Output, TimeoutError> {
+ let timeout_fut = Timer::at(at);
+ pin_mut!(fut);
+ match select(fut, timeout_fut).await {
+ Either::Left((r, _)) => Ok(r),
+ Either::Right(_) => Err(TimeoutError),
+ }
+}
+
/// A future that completes at a specified [Instant](struct.Instant.html).
#[must_use = "futures do nothing unless you `.await` or poll them"]
pub struct Timer {
diff --git a/examples/rp/src/bin/debounce.rs b/examples/rp/src/bin/debounce.rs
new file mode 100644
index 000000000..bf1579091
--- /dev/null
+++ b/examples/rp/src/bin/debounce.rs
@@ -0,0 +1,80 @@
+//! This example shows the ease of debouncing a button with async rust.
+//! Hook up a button or switch between pin 9 and ground.
+
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_rp::gpio::{Input, Level, Pull};
+use embassy_time::{timeout_at, Duration, Instant, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+pub struct Debouncer<'a> {
+ input: Input<'a>,
+ debounce: Duration,
+}
+
+impl<'a> Debouncer<'a> {
+ pub fn new(input: Input<'a>, debounce: Duration) -> Self {
+ Self { input, debounce }
+ }
+
+ pub async fn debounce(&mut self) -> Level {
+ loop {
+ let l1 = self.input.get_level();
+
+ self.input.wait_for_any_edge().await;
+
+ Timer::after(self.debounce).await;
+
+ let l2 = self.input.get_level();
+ if l1 != l2 {
+ break l2;
+ }
+ }
+ }
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p = embassy_rp::init(Default::default());
+ let mut btn = Debouncer::new(Input::new(p.PIN_9, Pull::Up), Duration::from_millis(20));
+
+ info!("Debounce Demo");
+
+ loop {
+ // button pressed
+ btn.debounce().await;
+ let start = Instant::now();
+ info!("Button Press");
+
+ match timeout_at(start + Duration::from_secs(1), btn.debounce()).await {
+ // Button Released < 1s
+ Ok(_) => {
+ info!("Button pressed for: {}ms", start.elapsed().as_millis());
+ continue;
+ }
+ // button held for > 1s
+ Err(_) => {
+ info!("Button Held");
+ }
+ }
+
+ match timeout_at(start + Duration::from_secs(5), btn.debounce()).await {
+ // Button released <5s
+ Ok(_) => {
+ info!("Button pressed for: {}ms", start.elapsed().as_millis());
+ continue;
+ }
+ // button held for > >5s
+ Err(_) => {
+ info!("Button Long Held");
+ }
+ }
+
+ // wait for button release before handling another press
+ btn.debounce().await;
+ info!("Button pressed for: {}ms", start.elapsed().as_millis());
+ }
+}
From d364447a34377c708fe6a7ea87aabda3ea1231ba Mon Sep 17 00:00:00 2001
From: Justin Beaurivage <justin@wearableavionics.com>
Date: Wed, 31 Jan 2024 14:16:58 -0500
Subject: [PATCH 096/392] Add error handling to UarteRxWithIdle
---
embassy-nrf/src/uarte.rs | 37 ++++++++++++++++++++++++-------------
1 file changed, 24 insertions(+), 13 deletions(-)
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 90d851139..97c887ab2 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -534,7 +534,8 @@ impl<'d, T: Instance> UarteRx<'d, T> {
Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config)
}
- fn read_and_clear_errors(&mut self) -> Result<(), Error> {
+ /// Check for errors and clear the error register if an error occured.
+ fn check_and_clear_errors(&mut self) -> Result<(), Error> {
let r = T::regs();
let err_bits = r.errorsrc.read().bits();
r.errorsrc.write(|w| unsafe { w.bits(err_bits) });
@@ -675,8 +676,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
let result = poll_fn(|cx| {
s.endrx_waker.register(cx.waker());
- let maybe_err = self.read_and_clear_errors();
- if let Err(e) = maybe_err {
+ if let Err(e) = self.check_and_clear_errors() {
return Poll::Ready(Err(e));
}
if r.events_endrx.read().bits() != 0 {
@@ -727,7 +727,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
compiler_fence(Ordering::SeqCst);
r.events_rxstarted.reset();
- self.read_and_clear_errors()
+ self.check_and_clear_errors()
}
}
@@ -794,8 +794,12 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
let drop = OnDrop::new(|| {
self.timer.stop();
- r.intenclr.write(|w| w.endrx().clear());
+ r.intenclr.write(|w| {
+ w.endrx().clear();
+ w.error().clear()
+ });
r.events_rxto.reset();
+ r.events_error.reset();
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
while r.events_endrx.read().bits() == 0 {}
@@ -805,17 +809,23 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
r.events_endrx.reset();
- r.intenset.write(|w| w.endrx().set());
+ r.events_error.reset();
+ r.intenset.write(|w| {w.endrx().set(); w.error().set()});
compiler_fence(Ordering::SeqCst);
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
- poll_fn(|cx| {
+ let result = poll_fn(|cx| {
s.endrx_waker.register(cx.waker());
- if r.events_endrx.read().bits() != 0 {
- return Poll::Ready(());
+
+ if let Err(e) = self.rx.check_and_clear_errors() {
+ return Poll::Ready(Err(e));
}
+ if r.events_endrx.read().bits() != 0 {
+ return Poll::Ready(Ok(()));
+ }
+
Poll::Pending
})
.await;
@@ -828,7 +838,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
drop.defuse();
- Ok(n)
+ result.map(|_| n)
}
/// Read bytes until the buffer is filled, or the line becomes idle.
@@ -853,13 +863,14 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
r.events_endrx.reset();
- r.intenclr.write(|w| w.endrx().clear());
+ r.events_error.reset();
+ r.intenclr.write(|w| {w.endrx().clear(); w.error().clear()});
compiler_fence(Ordering::SeqCst);
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
- while r.events_endrx.read().bits() == 0 {}
+ while r.events_endrx.read().bits() == 0 && r.events_error.read().bits() == 0 {}
compiler_fence(Ordering::SeqCst);
let n = r.rxd.amount.read().amount().bits() as usize;
@@ -867,7 +878,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
self.timer.stop();
r.events_rxstarted.reset();
- Ok(n)
+ self.rx.check_and_clear_errors().map(|_| n)
}
}
From cc12eb9680513f380e9a04e76322ae4355c2b6b2 Mon Sep 17 00:00:00 2001
From: Justin Beaurivage <justin@wearableavionics.com>
Date: Wed, 31 Jan 2024 14:20:06 -0500
Subject: [PATCH 097/392] Rustfmt
---
embassy-nrf/src/uarte.rs | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 97c887ab2..f29b5061b 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -676,7 +676,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
let result = poll_fn(|cx| {
s.endrx_waker.register(cx.waker());
- if let Err(e) = self.check_and_clear_errors() {
+ if let Err(e) = self.check_and_clear_errors() {
return Poll::Ready(Err(e));
}
if r.events_endrx.read().bits() != 0 {
@@ -810,7 +810,10 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
r.events_endrx.reset();
r.events_error.reset();
- r.intenset.write(|w| {w.endrx().set(); w.error().set()});
+ r.intenset.write(|w| {
+ w.endrx().set();
+ w.error().set()
+ });
compiler_fence(Ordering::SeqCst);
@@ -864,7 +867,10 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
r.events_endrx.reset();
r.events_error.reset();
- r.intenclr.write(|w| {w.endrx().clear(); w.error().clear()});
+ r.intenclr.write(|w| {
+ w.endrx().clear();
+ w.error().clear()
+ });
compiler_fence(Ordering::SeqCst);
From 8b7d85619537fc20ad7ad533433d84ba4975ddc4 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Wed, 31 Jan 2024 16:26:11 -0500
Subject: [PATCH 098/392] Rename timeout_at to with_deadline
---
embassy-time/src/lib.rs | 2 +-
embassy-time/src/timer.rs | 2 +-
examples/rp/src/bin/debounce.rs | 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/embassy-time/src/lib.rs b/embassy-time/src/lib.rs
index e7efce49c..3c8575ee9 100644
--- a/embassy-time/src/lib.rs
+++ b/embassy-time/src/lib.rs
@@ -32,7 +32,7 @@ pub use delay::{block_for, Delay};
pub use duration::Duration;
pub use embassy_time_driver::TICK_HZ;
pub use instant::Instant;
-pub use timer::{timeout_at, with_timeout, Ticker, TimeoutError, Timer};
+pub use timer::{with_deadline, with_timeout, Ticker, TimeoutError, Timer};
const fn gcd(a: u64, b: u64) -> u64 {
if b == 0 {
diff --git a/embassy-time/src/timer.rs b/embassy-time/src/timer.rs
index dbce9297c..bcd6bf4f7 100644
--- a/embassy-time/src/timer.rs
+++ b/embassy-time/src/timer.rs
@@ -30,7 +30,7 @@ pub async fn with_timeout<F: Future>(timeout: Duration, fut: F) -> Result<F::Out
///
/// If the future completes before the deadline, its output is returned. Otherwise, on timeout,
/// work on the future is stopped (`poll` is no longer called), the future is dropped and `Err(TimeoutError)` is returned.
-pub async fn timeout_at<F: Future>(at: Instant, fut: F) -> Result<F::Output, TimeoutError> {
+pub async fn with_deadline<F: Future>(at: Instant, fut: F) -> Result<F::Output, TimeoutError> {
let timeout_fut = Timer::at(at);
pin_mut!(fut);
match select(fut, timeout_fut).await {
diff --git a/examples/rp/src/bin/debounce.rs b/examples/rp/src/bin/debounce.rs
index bf1579091..0077f19fc 100644
--- a/examples/rp/src/bin/debounce.rs
+++ b/examples/rp/src/bin/debounce.rs
@@ -7,7 +7,7 @@
use defmt::info;
use embassy_executor::Spawner;
use embassy_rp::gpio::{Input, Level, Pull};
-use embassy_time::{timeout_at, Duration, Instant, Timer};
+use embassy_time::{with_deadline, Duration, Instant, Timer};
use {defmt_rtt as _, panic_probe as _};
pub struct Debouncer<'a> {
@@ -49,7 +49,7 @@ async fn main(_spawner: Spawner) {
let start = Instant::now();
info!("Button Press");
- match timeout_at(start + Duration::from_secs(1), btn.debounce()).await {
+ match with_deadline(start + Duration::from_secs(1), btn.debounce()).await {
// Button Released < 1s
Ok(_) => {
info!("Button pressed for: {}ms", start.elapsed().as_millis());
@@ -61,7 +61,7 @@ async fn main(_spawner: Spawner) {
}
}
- match timeout_at(start + Duration::from_secs(5), btn.debounce()).await {
+ match with_deadline(start + Duration::from_secs(5), btn.debounce()).await {
// Button released <5s
Ok(_) => {
info!("Button pressed for: {}ms", start.elapsed().as_millis());
From 0ab0b5590a0b07756ceaed9b26c78a6a821b34d5 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Wed, 31 Jan 2024 16:28:06 -0500
Subject: [PATCH 099/392] Fixup docs
---
embassy-time/src/timer.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-time/src/timer.rs b/embassy-time/src/timer.rs
index bcd6bf4f7..daa4c1699 100644
--- a/embassy-time/src/timer.rs
+++ b/embassy-time/src/timer.rs
@@ -8,7 +8,7 @@ use futures_util::{pin_mut, Stream};
use crate::{Duration, Instant};
-/// Error returned by [`with_timeout`] and [`timeout_at`] on timeout.
+/// Error returned by [`with_timeout`] and [`with_deadline`] on timeout.
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct TimeoutError;
From 42d8f3930a861dcc4540198bf2038151eb4e3e27 Mon Sep 17 00:00:00 2001
From: "Simon B. Gasse" <sgasse@users.noreply.github.com>
Date: Fri, 19 Jan 2024 21:10:03 +0100
Subject: [PATCH 100/392] Implement MII interface
- Extend the eth/v2 module to support MII besides RMII.
- Replace `Ethernet::new` with `Ethernet::new_mii` and
`Ethernet::new_rmii`.
- Update ethernet examples.
- Add example for MII ethernet.
---
embassy-stm32/build.rs | 7 +
embassy-stm32/src/eth/mod.rs | 7 +
embassy-stm32/src/eth/v2/mod.rs | 136 ++++++++++++++++----
examples/stm32f4/src/bin/eth.rs | 2 +-
examples/stm32f7/src/bin/eth.rs | 2 +-
examples/stm32h5/src/bin/eth.rs | 2 +-
examples/stm32h7/src/bin/eth.rs | 2 +-
examples/stm32h7/src/bin/eth_client.rs | 2 +-
examples/stm32h7/src/bin/eth_client_mii.rs | 142 +++++++++++++++++++++
tests/stm32/src/bin/eth.rs | 21 +++
10 files changed, 295 insertions(+), 28 deletions(-)
create mode 100644 examples/stm32h7/src/bin/eth_client_mii.rs
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 414723573..bd4195619 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -735,13 +735,20 @@ fn main() {
(("can", "TX"), quote!(crate::can::TxPin)),
(("can", "RX"), quote!(crate::can::RxPin)),
(("eth", "REF_CLK"), quote!(crate::eth::RefClkPin)),
+ (("eth", "RX_CLK"), quote!(crate::eth::RXClkPin)),
+ (("eth", "TX_CLK"), quote!(crate::eth::TXClkPin)),
(("eth", "MDIO"), quote!(crate::eth::MDIOPin)),
(("eth", "MDC"), quote!(crate::eth::MDCPin)),
(("eth", "CRS_DV"), quote!(crate::eth::CRSPin)),
+ (("eth", "RX_DV"), quote!(crate::eth::RXDVPin)),
(("eth", "RXD0"), quote!(crate::eth::RXD0Pin)),
(("eth", "RXD1"), quote!(crate::eth::RXD1Pin)),
+ (("eth", "RXD2"), quote!(crate::eth::RXD2Pin)),
+ (("eth", "RXD3"), quote!(crate::eth::RXD3Pin)),
(("eth", "TXD0"), quote!(crate::eth::TXD0Pin)),
(("eth", "TXD1"), quote!(crate::eth::TXD1Pin)),
+ (("eth", "TXD2"), quote!(crate::eth::TXD2Pin)),
+ (("eth", "TXD3"), quote!(crate::eth::TXD3Pin)),
(("eth", "TX_EN"), quote!(crate::eth::TXEnPin)),
(("fmc", "A0"), quote!(crate::fmc::A0Pin)),
(("fmc", "A1"), quote!(crate::fmc::A1Pin)),
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index 448405507..fbcdd7fae 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -192,12 +192,19 @@ impl sealed::Instance for crate::peripherals::ETH {
}
impl Instance for crate::peripherals::ETH {}
+pin_trait!(RXClkPin, Instance);
+pin_trait!(TXClkPin, Instance);
pin_trait!(RefClkPin, Instance);
pin_trait!(MDIOPin, Instance);
pin_trait!(MDCPin, Instance);
+pin_trait!(RXDVPin, Instance);
pin_trait!(CRSPin, Instance);
pin_trait!(RXD0Pin, Instance);
pin_trait!(RXD1Pin, Instance);
+pin_trait!(RXD2Pin, Instance);
+pin_trait!(RXD3Pin, Instance);
pin_trait!(TXD0Pin, Instance);
pin_trait!(TXD1Pin, Instance);
+pin_trait!(TXD2Pin, Instance);
+pin_trait!(TXD3Pin, Instance);
pin_trait!(TXEnPin, Instance);
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 59745cba0..a176b01e5 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -39,12 +39,18 @@ pub struct Ethernet<'d, T: Instance, P: PHY> {
_peri: PeripheralRef<'d, T>,
pub(crate) tx: TDesRing<'d>,
pub(crate) rx: RDesRing<'d>,
- pins: [PeripheralRef<'d, AnyPin>; 9],
+ pins: Pins<'d>,
pub(crate) phy: P,
pub(crate) station_management: EthernetStationManagement<T>,
pub(crate) mac_addr: [u8; 6],
}
+/// Pins of ethernet driver.
+enum Pins<'d> {
+ Rmii([PeripheralRef<'d, AnyPin>; 9]),
+ Mii([PeripheralRef<'d, AnyPin>; 14]),
+}
+
macro_rules! config_pins {
($($pin:ident),*) => {
critical_section::with(|_| {
@@ -57,11 +63,11 @@ macro_rules! config_pins {
}
impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
- /// Create a new Ethernet driver.
- pub fn new<const TX: usize, const RX: usize>(
+ /// Create a new RMII ethernet driver using 9 pins.
+ pub fn new_rmii<const TX: usize, const RX: usize>(
queue: &'d mut PacketQueue<TX, RX>,
peri: impl Peripheral<P = T> + 'd,
- _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+ irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
@@ -74,8 +80,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
phy: P,
mac_addr: [u8; 6],
) -> Self {
- into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
-
// Enable the necessary Clocks
#[cfg(not(rcc_h5))]
critical_section::with(|_| {
@@ -85,7 +89,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
w.set_eth1rxen(true);
});
- // RMII
crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
});
@@ -99,14 +102,110 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
w.set_ethrxen(true);
});
- // RMII
crate::pac::SYSCFG
.pmcr()
.modify(|w| w.set_eth_sel_phy(crate::pac::syscfg::vals::EthSelPhy::B_0X4));
});
+ into_ref!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
+ let pins = Pins::Rmii([
+ ref_clk.map_into(),
+ mdio.map_into(),
+ mdc.map_into(),
+ crs.map_into(),
+ rx_d0.map_into(),
+ rx_d1.map_into(),
+ tx_d0.map_into(),
+ tx_d1.map_into(),
+ tx_en.map_into(),
+ ]);
+
+ Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+ }
+
+ /// Create a new MII ethernet driver using 14 pins.
+ pub fn new_mii<const TX: usize, const RX: usize>(
+ queue: &'d mut PacketQueue<TX, RX>,
+ peri: impl Peripheral<P = T> + 'd,
+ irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+ rx_clk: impl Peripheral<P = impl RXClkPin<T>> + 'd,
+ tx_clk: impl Peripheral<P = impl TXClkPin<T>> + 'd,
+ mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
+ mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
+ rxdv: impl Peripheral<P = impl RXDVPin<T>> + 'd,
+ rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
+ rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
+ rx_d2: impl Peripheral<P = impl RXD2Pin<T>> + 'd,
+ rx_d3: impl Peripheral<P = impl RXD3Pin<T>> + 'd,
+ tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
+ tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
+ tx_d2: impl Peripheral<P = impl TXD2Pin<T>> + 'd,
+ tx_d3: impl Peripheral<P = impl TXD3Pin<T>> + 'd,
+ tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
+ phy: P,
+ mac_addr: [u8; 6],
+ ) -> Self {
+ // Enable necessary clocks.
+ #[cfg(not(rcc_h5))]
+ critical_section::with(|_| {
+ crate::pac::RCC.ahb1enr().modify(|w| {
+ w.set_eth1macen(true);
+ w.set_eth1txen(true);
+ w.set_eth1rxen(true);
+ });
+
+ crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b000));
+ });
+
+ #[cfg(rcc_h5)]
+ critical_section::with(|_| {
+ crate::pac::RCC.apb3enr().modify(|w| w.set_sbsen(true));
+
+ crate::pac::RCC.ahb1enr().modify(|w| {
+ w.set_ethen(true);
+ w.set_ethtxen(true);
+ w.set_ethrxen(true);
+ });
+
+ // TODO: This is for RMII - what would MII need here?
+ crate::pac::SYSCFG
+ .pmcr()
+ .modify(|w| w.set_eth_sel_phy(crate::pac::syscfg::vals::EthSelPhy::B_0X4));
+ });
+
+ into_ref!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+ config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+
+ let pins = Pins::Mii([
+ rx_clk.map_into(),
+ tx_clk.map_into(),
+ mdio.map_into(),
+ mdc.map_into(),
+ rxdv.map_into(),
+ rx_d0.map_into(),
+ rx_d1.map_into(),
+ rx_d2.map_into(),
+ rx_d3.map_into(),
+ tx_d0.map_into(),
+ tx_d1.map_into(),
+ tx_d2.map_into(),
+ tx_d3.map_into(),
+ tx_en.map_into(),
+ ]);
+
+ Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+ }
+
+ fn new_inner<const TX: usize, const RX: usize>(
+ queue: &'d mut PacketQueue<TX, RX>,
+ peri: impl Peripheral<P = T> + 'd,
+ _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+ pins: Pins<'d>,
+ phy: P,
+ mac_addr: [u8; 6],
+ ) -> Self {
let dma = ETH.ethernet_dma();
let mac = ETH.ethernet_mac();
let mtl = ETH.ethernet_mtl();
@@ -182,24 +281,12 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
}
};
- let pins = [
- ref_clk.map_into(),
- mdio.map_into(),
- mdc.map_into(),
- crs.map_into(),
- rx_d0.map_into(),
- rx_d1.map_into(),
- tx_d0.map_into(),
- tx_d1.map_into(),
- tx_en.map_into(),
- ];
-
let mut this = Self {
- _peri: peri,
+ _peri: peri.into_ref(),
tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
pins,
- phy: phy,
+ phy,
station_management: EthernetStationManagement {
peri: PhantomData,
clock_range: clock_range,
@@ -302,7 +389,10 @@ impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
dma.dmacrx_cr().modify(|w| w.set_sr(false));
critical_section::with(|_| {
- for pin in self.pins.iter_mut() {
+ for pin in match self.pins {
+ Pins::Rmii(ref mut pins) => pins.iter_mut(),
+ Pins::Mii(ref mut pins) => pins.iter_mut(),
+ } {
pin.set_as_disconnected();
}
})
diff --git a/examples/stm32f4/src/bin/eth.rs b/examples/stm32f4/src/bin/eth.rs
index 7f5c8fdb1..2933cfe3c 100644
--- a/examples/stm32f4/src/bin/eth.rs
+++ b/examples/stm32f4/src/bin/eth.rs
@@ -63,7 +63,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<16, 16>> = StaticCell::new();
- let device = Ethernet::new(
+ let device = Ethernet::new_rmii(
PACKETS.init(PacketQueue::<16, 16>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32f7/src/bin/eth.rs b/examples/stm32f7/src/bin/eth.rs
index 5bff48197..85b5bd3e0 100644
--- a/examples/stm32f7/src/bin/eth.rs
+++ b/examples/stm32f7/src/bin/eth.rs
@@ -64,7 +64,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<16, 16>> = StaticCell::new();
- let device = Ethernet::new(
+ let device = Ethernet::new_rmii(
PACKETS.init(PacketQueue::<16, 16>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index 2370656e6..79288877f 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -67,7 +67,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<4, 4>> = StaticCell::new();
- let device = Ethernet::new(
+ let device = Ethernet::new_rmii(
PACKETS.init(PacketQueue::<4, 4>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs
index cd9a27fcd..9abdcf3c0 100644
--- a/examples/stm32h7/src/bin/eth.rs
+++ b/examples/stm32h7/src/bin/eth.rs
@@ -64,7 +64,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<4, 4>> = StaticCell::new();
- let device = Ethernet::new(
+ let device = Ethernet::new_rmii(
PACKETS.init(PacketQueue::<4, 4>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index dcc6e36e2..c4da5776f 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -65,7 +65,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<16, 16>> = StaticCell::new();
- let device = Ethernet::new(
+ let device = Ethernet::new_rmii(
PACKETS.init(PacketQueue::<16, 16>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32h7/src/bin/eth_client_mii.rs b/examples/stm32h7/src/bin/eth_client_mii.rs
new file mode 100644
index 000000000..de6ea522a
--- /dev/null
+++ b/examples/stm32h7/src/bin/eth_client_mii.rs
@@ -0,0 +1,142 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_net::tcp::client::{TcpClient, TcpClientState};
+use embassy_net::{Stack, StackResources};
+use embassy_stm32::eth::generic_smi::GenericSMI;
+use embassy_stm32::eth::{Ethernet, PacketQueue};
+use embassy_stm32::peripherals::ETH;
+use embassy_stm32::rng::Rng;
+use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
+use embassy_time::Timer;
+use embedded_io_async::Write;
+use embedded_nal_async::{Ipv4Addr, SocketAddr, SocketAddrV4, TcpConnect};
+use rand_core::RngCore;
+use static_cell::StaticCell;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ ETH => eth::InterruptHandler;
+ RNG => rng::InterruptHandler<peripherals::RNG>;
+});
+
+type Device = Ethernet<'static, ETH, GenericSMI>;
+
+#[embassy_executor::task]
+async fn net_task(stack: &'static Stack<Device>) -> ! {
+ stack.run().await
+}
+
+#[embassy_executor::main]
+async fn main(spawner: Spawner) -> ! {
+ let mut config = Config::default();
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hsi = Some(HSIPrescaler::DIV1);
+ config.rcc.csi = true;
+ config.rcc.hsi48 = Some(Default::default()); // needed for RNG
+ config.rcc.pll1 = Some(Pll {
+ source: PllSource::HSI,
+ prediv: PllPreDiv::DIV4,
+ mul: PllMul::MUL50,
+ divp: Some(PllDiv::DIV2),
+ divq: None,
+ divr: None,
+ });
+ config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
+ config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
+ config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
+ config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
+ config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
+ config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
+ config.rcc.voltage_scale = VoltageScale::Scale1;
+ }
+ let p = embassy_stm32::init(config);
+ info!("Hello World!");
+
+ // Generate random seed.
+ let mut rng = Rng::new(p.RNG, Irqs);
+ let mut seed = [0; 8];
+ rng.fill_bytes(&mut seed);
+ let seed = u64::from_le_bytes(seed);
+
+ let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
+
+ static PACKETS: StaticCell<PacketQueue<16, 16>> = StaticCell::new();
+
+ let device = Ethernet::new_mii(
+ PACKETS.init(PacketQueue::<16, 16>::new()),
+ p.ETH,
+ Irqs,
+ p.PA1,
+ p.PC3,
+ p.PA2,
+ p.PC1,
+ p.PA7,
+ p.PC4,
+ p.PC5,
+ p.PB0,
+ p.PB1,
+ p.PG13,
+ p.PG12,
+ p.PC2,
+ p.PE2,
+ p.PG11,
+ GenericSMI::new(1),
+ mac_addr,
+ );
+ info!("Device created");
+
+ let config = embassy_net::Config::dhcpv4(Default::default());
+ //let config = embassy_net::Config::ipv4_static(embassy_net::StaticConfigV4 {
+ // address: Ipv4Cidr::new(Ipv4Address::new(10, 42, 0, 61), 24),
+ // dns_servers: Vec::new(),
+ // gateway: Some(Ipv4Address::new(10, 42, 0, 1)),
+ //});
+
+ // Init network stack
+ static STACK: StaticCell<Stack<Device>> = StaticCell::new();
+ static RESOURCES: StaticCell<StackResources<3>> = StaticCell::new();
+ let stack = &*STACK.init(Stack::new(
+ device,
+ config,
+ RESOURCES.init(StackResources::<3>::new()),
+ seed,
+ ));
+
+ // Launch network task
+ unwrap!(spawner.spawn(net_task(stack)));
+
+ // Ensure DHCP configuration is up before trying connect
+ stack.wait_config_up().await;
+
+ info!("Network task initialized");
+
+ let state: TcpClientState<1, 1024, 1024> = TcpClientState::new();
+ let client = TcpClient::new(&stack, &state);
+
+ loop {
+ // You need to start a server on the host machine, for example: `nc -l 8000`
+ let addr = SocketAddr::V4(SocketAddrV4::new(Ipv4Addr::new(192, 168, 100, 1), 8000));
+
+ info!("connecting...");
+ let r = client.connect(addr).await;
+ if let Err(e) = r {
+ info!("connect error: {:?}", e);
+ Timer::after_secs(1).await;
+ continue;
+ }
+ let mut connection = r.unwrap();
+ info!("connected!");
+ loop {
+ let r = connection.write_all(b"Hello\n").await;
+ if let Err(e) = r {
+ info!("write error: {:?}", e);
+ break;
+ }
+ Timer::after_secs(1).await;
+ }
+ }
+}
diff --git a/tests/stm32/src/bin/eth.rs b/tests/stm32/src/bin/eth.rs
index 7c02f0354..b244874e7 100644
--- a/tests/stm32/src/bin/eth.rs
+++ b/tests/stm32/src/bin/eth.rs
@@ -71,6 +71,7 @@ async fn main(spawner: Spawner) {
const PACKET_QUEUE_SIZE: usize = 4;
static PACKETS: StaticCell<PacketQueue<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>> = StaticCell::new();
+ #[cfg(not(eth_v2))]
let device = Ethernet::new(
PACKETS.init(PacketQueue::<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>::new()),
p.ETH,
@@ -90,6 +91,26 @@ async fn main(spawner: Spawner) {
GenericSMI::new(0),
mac_addr,
);
+ #[cfg(eth_v2)]
+ let device = Ethernet::new_rmii(
+ PACKETS.init(PacketQueue::<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>::new()),
+ p.ETH,
+ Irqs,
+ p.PA1,
+ p.PA2,
+ p.PC1,
+ p.PA7,
+ p.PC4,
+ p.PC5,
+ p.PG13,
+ #[cfg(not(feature = "stm32h563zi"))]
+ p.PB13,
+ #[cfg(feature = "stm32h563zi")]
+ p.PB15,
+ p.PG11,
+ GenericSMI::new(0),
+ mac_addr,
+ );
let config = embassy_net::Config::dhcpv4(Default::default());
//let config = embassy_net::Config::ipv4_static(embassy_net::StaticConfigV4 {
From e613324e1603741df150730fd26652458d0d0c50 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Thu, 1 Feb 2024 01:39:52 +0100
Subject: [PATCH 101/392] stm32/eth: rename new_rmii to new, update metapac to
fix issues with PC2_C.
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/eth/v2/mod.rs | 2 +-
examples/stm32f4/src/bin/eth.rs | 2 +-
examples/stm32f7/src/bin/eth.rs | 2 +-
examples/stm32h5/src/bin/eth.rs | 2 +-
examples/stm32h7/src/bin/eth.rs | 2 +-
examples/stm32h7/src/bin/eth_client.rs | 3 ++-
tests/stm32/src/bin/eth.rs | 21 ---------------------
8 files changed, 9 insertions(+), 29 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 6c7591f57..698febf71 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab2bc2a739324793656ca1640e1caee2d88df72d" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab2bc2a739324793656ca1640e1caee2d88df72d", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index a176b01e5..4b22d1d21 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -64,7 +64,7 @@ macro_rules! config_pins {
impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
/// Create a new RMII ethernet driver using 9 pins.
- pub fn new_rmii<const TX: usize, const RX: usize>(
+ pub fn new<const TX: usize, const RX: usize>(
queue: &'d mut PacketQueue<TX, RX>,
peri: impl Peripheral<P = T> + 'd,
irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
diff --git a/examples/stm32f4/src/bin/eth.rs b/examples/stm32f4/src/bin/eth.rs
index 2933cfe3c..7f5c8fdb1 100644
--- a/examples/stm32f4/src/bin/eth.rs
+++ b/examples/stm32f4/src/bin/eth.rs
@@ -63,7 +63,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<16, 16>> = StaticCell::new();
- let device = Ethernet::new_rmii(
+ let device = Ethernet::new(
PACKETS.init(PacketQueue::<16, 16>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32f7/src/bin/eth.rs b/examples/stm32f7/src/bin/eth.rs
index 85b5bd3e0..5bff48197 100644
--- a/examples/stm32f7/src/bin/eth.rs
+++ b/examples/stm32f7/src/bin/eth.rs
@@ -64,7 +64,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<16, 16>> = StaticCell::new();
- let device = Ethernet::new_rmii(
+ let device = Ethernet::new(
PACKETS.init(PacketQueue::<16, 16>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index 79288877f..2370656e6 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -67,7 +67,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<4, 4>> = StaticCell::new();
- let device = Ethernet::new_rmii(
+ let device = Ethernet::new(
PACKETS.init(PacketQueue::<4, 4>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs
index 9abdcf3c0..cd9a27fcd 100644
--- a/examples/stm32h7/src/bin/eth.rs
+++ b/examples/stm32h7/src/bin/eth.rs
@@ -64,7 +64,7 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<4, 4>> = StaticCell::new();
- let device = Ethernet::new_rmii(
+ let device = Ethernet::new(
PACKETS.init(PacketQueue::<4, 4>::new()),
p.ETH,
Irqs,
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index c4da5776f..aeb169e19 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -65,7 +65,8 @@ async fn main(spawner: Spawner) -> ! {
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
static PACKETS: StaticCell<PacketQueue<16, 16>> = StaticCell::new();
- let device = Ethernet::new_rmii(
+
+ let device = Ethernet::new(
PACKETS.init(PacketQueue::<16, 16>::new()),
p.ETH,
Irqs,
diff --git a/tests/stm32/src/bin/eth.rs b/tests/stm32/src/bin/eth.rs
index b244874e7..7c02f0354 100644
--- a/tests/stm32/src/bin/eth.rs
+++ b/tests/stm32/src/bin/eth.rs
@@ -71,7 +71,6 @@ async fn main(spawner: Spawner) {
const PACKET_QUEUE_SIZE: usize = 4;
static PACKETS: StaticCell<PacketQueue<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>> = StaticCell::new();
- #[cfg(not(eth_v2))]
let device = Ethernet::new(
PACKETS.init(PacketQueue::<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>::new()),
p.ETH,
@@ -91,26 +90,6 @@ async fn main(spawner: Spawner) {
GenericSMI::new(0),
mac_addr,
);
- #[cfg(eth_v2)]
- let device = Ethernet::new_rmii(
- PACKETS.init(PacketQueue::<PACKET_QUEUE_SIZE, PACKET_QUEUE_SIZE>::new()),
- p.ETH,
- Irqs,
- p.PA1,
- p.PA2,
- p.PC1,
- p.PA7,
- p.PC4,
- p.PC5,
- p.PG13,
- #[cfg(not(feature = "stm32h563zi"))]
- p.PB13,
- #[cfg(feature = "stm32h563zi")]
- p.PB15,
- p.PG11,
- GenericSMI::new(0),
- mac_addr,
- );
let config = embassy_net::Config::dhcpv4(Default::default());
//let config = embassy_net::Config::ipv4_static(embassy_net::StaticConfigV4 {
From 6e9ddd46267fd0fce2333af4f15bfd86f6f17f4d Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Wed, 31 Jan 2024 21:21:36 -0500
Subject: [PATCH 102/392] Added hash module with blocking implementation.
Included SHA256 example.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/hash/mod.rs | 260 +++++++++++++++++++++++++++++++
embassy-stm32/src/lib.rs | 2 +
examples/stm32f7/Cargo.toml | 5 +-
examples/stm32f7/src/bin/hash.rs | 49 ++++++
5 files changed, 316 insertions(+), 4 deletions(-)
create mode 100644 embassy-stm32/src/hash/mod.rs
create mode 100644 examples/stm32f7/src/bin/hash.rs
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 70d4daf09..d8a4c65fa 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab2bc2a739324793656ca1640e1caee2d88df72d" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -87,7 +87,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ab2bc2a739324793656ca1640e1caee2d88df72d", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
new file mode 100644
index 000000000..e3d2d7b16
--- /dev/null
+++ b/embassy-stm32/src/hash/mod.rs
@@ -0,0 +1,260 @@
+//! Hash generator (HASH)
+use core::cmp::min;
+
+use embassy_hal_internal::{into_ref, PeripheralRef};
+use stm32_metapac::hash::regs::*;
+
+use crate::pac::HASH as PAC_HASH;
+use crate::peripherals::HASH;
+use crate::rcc::sealed::RccPeripheral;
+use crate::Peripheral;
+
+const NUM_CONTEXT_REGS: usize = 54;
+const HASH_BUFFER_LEN: usize = 68;
+const DIGEST_BLOCK_SIZE: usize = 64;
+
+///Hash algorithm selection
+#[derive(PartialEq)]
+pub enum Algorithm {
+ /// SHA-1 Algorithm
+ SHA1 = 0,
+ /// MD5 Algorithm
+ MD5 = 1,
+ /// SHA-224 Algorithm
+ SHA224 = 2,
+ /// SHA-256 Algorithm
+ SHA256 = 3,
+}
+
+/// Input data width selection
+#[repr(u8)]
+#[derive(Clone, Copy)]
+pub enum DataType {
+ ///32-bit data, no data is swapped.
+ Width32 = 0,
+ ///16-bit data, each half-word is swapped.
+ Width16 = 1,
+ ///8-bit data, all bytes are swapped.
+ Width8 = 2,
+ ///1-bit data, all bits are swapped.
+ Width1 = 3,
+}
+
+/// Stores the state of the HASH peripheral for suspending/resuming
+/// digest calculation.
+pub struct Context {
+ first_word_sent: bool,
+ buffer: [u8; HASH_BUFFER_LEN],
+ buflen: usize,
+ algo: Algorithm,
+ format: DataType,
+ imr: u32,
+ str: u32,
+ cr: u32,
+ csr: [u32; NUM_CONTEXT_REGS],
+}
+
+/// HASH driver.
+pub struct Hash<'d> {
+ _peripheral: PeripheralRef<'d, HASH>,
+}
+
+impl<'d> Hash<'d> {
+ /// Instantiates, resets, and enables the HASH peripheral.
+ pub fn new(peripheral: impl Peripheral<P = HASH> + 'd) -> Self {
+ HASH::enable_and_reset();
+ into_ref!(peripheral);
+ let instance = Self {
+ _peripheral: peripheral,
+ };
+ instance
+ }
+
+ /// Starts computation of a new hash and returns the saved peripheral state.
+ pub fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
+ // Define a context for this new computation.
+ let mut ctx = Context {
+ first_word_sent: false,
+ buffer: [0; 68],
+ buflen: 0,
+ algo: algorithm,
+ format: format,
+ imr: 0,
+ str: 0,
+ cr: 0,
+ csr: [0; NUM_CONTEXT_REGS],
+ };
+
+ // Set the data type in the peripheral.
+ PAC_HASH.cr().modify(|w| w.set_datatype(ctx.format as u8));
+
+ // Select the algorithm.
+ let mut algo0 = false;
+ let mut algo1 = false;
+ if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
+ algo0 = true;
+ }
+ if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
+ algo1 = true;
+ }
+ PAC_HASH.cr().modify(|w| w.set_algo0(algo0));
+ PAC_HASH.cr().modify(|w| w.set_algo1(algo1));
+ PAC_HASH.cr().modify(|w| w.set_init(true));
+
+ // Store and return the state of the peripheral.
+ self.store_context(&mut ctx);
+ ctx
+ }
+
+ /// Restores the peripheral state using the given context,
+ /// then updates the state with the provided data.
+ pub fn update(&mut self, ctx: &mut Context, input: &[u8]) {
+ let mut data_waiting = input.len() + ctx.buflen;
+ if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
+ // There isn't enough data to digest a block, so append it to the buffer.
+ ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
+ ctx.buflen += input.len();
+ return;
+ }
+
+ //Restore the peripheral state.
+ self.load_context(&ctx);
+
+ let mut ilen_remaining = input.len();
+ let mut input_start = 0;
+
+ // Handle first block.
+ if !ctx.first_word_sent {
+ let empty_len = ctx.buffer.len() - ctx.buflen;
+ let copy_len = min(empty_len, ilen_remaining);
+ // Fill the buffer.
+ if copy_len > 0 {
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[0..copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ assert_eq!(ctx.buflen, HASH_BUFFER_LEN);
+ self.accumulate(ctx.buffer.as_slice());
+ data_waiting -= ctx.buflen;
+ ctx.buflen = 0;
+ ctx.first_word_sent = true;
+ }
+
+ if data_waiting < 64 {
+ // There isn't enough data remaining to process another block, so store it.
+ assert_eq!(ctx.buflen, 0);
+ ctx.buffer[0..ilen_remaining].copy_from_slice(&input[input_start..input_start + ilen_remaining]);
+ ctx.buflen += ilen_remaining;
+ } else {
+ let mut total_data_sent = 0;
+ // First ingest the data in the buffer.
+ let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
+ if empty_len > 0 {
+ let copy_len = min(empty_len, ilen_remaining);
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len]
+ .copy_from_slice(&input[input_start..input_start + copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ assert_eq!(ctx.buflen % 64, 0);
+ self.accumulate(&ctx.buffer[0..64]);
+ total_data_sent += ctx.buflen;
+ ctx.buflen = 0;
+
+ // Move any extra data to the now-empty buffer.
+ let leftovers = ilen_remaining % 64;
+ if leftovers > 0 {
+ assert!(ilen_remaining >= leftovers);
+ ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
+ ctx.buflen += leftovers;
+ ilen_remaining -= leftovers;
+ }
+ assert_eq!(ilen_remaining % 64, 0);
+
+ // Hash the remaining data.
+ self.accumulate(&input[input_start..input_start + ilen_remaining]);
+
+ total_data_sent += ilen_remaining;
+ assert_eq!(total_data_sent % 64, 0);
+ assert!(total_data_sent >= 64);
+ }
+
+ // Save the peripheral context.
+ self.store_context(ctx);
+ }
+
+ /// Computes a digest for the given context. A slice of the provided digest buffer is returned.
+ /// The length of the returned slice is dependent on the digest length of the selected algorithm.
+ pub fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; 32]) -> &'a [u8] {
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+ // Hash the leftover bytes, if any.
+ self.accumulate(&ctx.buffer[0..ctx.buflen]);
+ ctx.buflen = 0;
+
+ //Start the digest calculation.
+ PAC_HASH.str().write(|w| w.set_dcal(true));
+
+ //Wait for completion.
+ while !PAC_HASH.sr().read().dcis() {}
+
+ //Return the digest.
+ let digest_words = match ctx.algo {
+ Algorithm::SHA1 => 5,
+ Algorithm::MD5 => 4,
+ Algorithm::SHA224 => 7,
+ Algorithm::SHA256 => 8,
+ };
+ let mut i = 0;
+ while i < digest_words {
+ let word = PAC_HASH.hr(i).read();
+ digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
+ i += 1;
+ }
+ &digest[0..digest_words * 4]
+ }
+
+ fn accumulate(&mut self, input: &[u8]) {
+ //Set the number of valid bits.
+ let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
+ PAC_HASH.str().modify(|w| w.set_nblw(num_valid_bits));
+
+ let mut i = 0;
+ while i < input.len() {
+ let mut word: [u8; 4] = [0; 4];
+ let copy_idx = min(i + 4, input.len());
+ word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
+ PAC_HASH.din().write_value(u32::from_ne_bytes(word));
+ i += 4;
+ }
+ }
+
+ /// Save the peripheral state to a context.
+ fn store_context(&mut self, ctx: &mut Context) {
+ while !PAC_HASH.sr().read().dinis() {}
+ ctx.imr = PAC_HASH.imr().read().0;
+ ctx.str = PAC_HASH.str().read().0;
+ ctx.cr = PAC_HASH.cr().read().0;
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ ctx.csr[i] = PAC_HASH.csr(i).read();
+ i += 1;
+ }
+ }
+
+ /// Restore the peripheral state from a context.
+ fn load_context(&mut self, ctx: &Context) {
+ // Restore the peripheral state from the context.
+ PAC_HASH.imr().write_value(Imr { 0: ctx.imr });
+ PAC_HASH.str().write_value(Str { 0: ctx.str });
+ PAC_HASH.cr().write_value(Cr { 0: ctx.cr });
+ PAC_HASH.cr().modify(|w| w.set_init(true));
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ PAC_HASH.csr(i).write_value(ctx.csr[i]);
+ i += 1;
+ }
+ }
+}
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index a465fccd8..cd1ede0fa 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -45,6 +45,8 @@ pub mod exti;
pub mod flash;
#[cfg(fmc)]
pub mod fmc;
+#[cfg(hash)]
+pub mod hash;
#[cfg(hrtim)]
pub mod hrtim;
#[cfg(i2c)]
diff --git a/examples/stm32f7/Cargo.toml b/examples/stm32f7/Cargo.toml
index 941ba38cd..a612c2554 100644
--- a/examples/stm32f7/Cargo.toml
+++ b/examples/stm32f7/Cargo.toml
@@ -5,8 +5,8 @@ version = "0.1.0"
license = "MIT OR Apache-2.0"
[dependencies]
-# Change stm32f767zi to your chip name, if necessary.
-embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f767zi", "memory-x", "unstable-pac", "time-driver-any", "exti"] }
+# Change stm32f777zi to your chip name, if necessary.
+embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f777zi", "memory-x", "unstable-pac", "time-driver-any", "exti"] }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
@@ -28,6 +28,7 @@ rand_core = "0.6.3"
critical-section = "1.1"
embedded-storage = "0.3.1"
static_cell = "2"
+sha2 = { version = "0.10.8", default-features = false }
[profile.release]
debug = 2
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
new file mode 100644
index 000000000..1fd0e87eb
--- /dev/null
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -0,0 +1,49 @@
+#![no_std]
+#![no_main]
+
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_stm32::Config;
+use embassy_time::{Duration, Instant};
+use {defmt_rtt as _, panic_probe as _};
+
+use embassy_stm32::hash::*;
+use sha2::{Digest, Sha256};
+
+const TEST_STRING_1: &[u8] = b"hello world";
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+ let config = Config::default();
+ let p = embassy_stm32::init(config);
+
+ let hw_start_time = Instant::now();
+
+ // Compute a digest in hardware.
+ let mut hw_hasher = Hash::new(p.HASH);
+ let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
+ hw_hasher.update(&mut context, TEST_STRING_1);
+ let mut buffer: [u8; 32] = [0; 32];
+ let hw_digest = hw_hasher.finish(context, &mut buffer);
+
+ let hw_end_time = Instant::now();
+ let hw_execution_time = hw_end_time - hw_start_time;
+
+ let sw_start_time = Instant::now();
+
+ // Compute a digest in software.
+ let mut sw_hasher = Sha256::new();
+ sw_hasher.update(TEST_STRING_1);
+ let sw_digest = sw_hasher.finalize();
+
+ let sw_end_time = Instant::now();
+ let sw_execution_time = sw_end_time - sw_start_time;
+
+ info!("Hardware Digest: {:?}", hw_digest);
+ info!("Software Digest: {:?}", sw_digest[..]);
+ info!("Hardware Execution Time: {:?}", hw_execution_time);
+ info!("Software Execution Time: {:?}", sw_execution_time);
+ assert_eq!(*hw_digest, sw_digest[..]);
+
+ loop {}
+}
From 15e9b60abbceb8843781b6eec398dafb45cc111d Mon Sep 17 00:00:00 2001
From: Sam Lakerveld <dark@dark.red>
Date: Thu, 1 Feb 2024 13:47:07 +0100
Subject: [PATCH 103/392] sync/pipe: be able to be zero-initialized
---
embassy-sync/src/ring_buffer.rs | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/embassy-sync/src/ring_buffer.rs b/embassy-sync/src/ring_buffer.rs
index d95ffa7c9..81e60c42b 100644
--- a/embassy-sync/src/ring_buffer.rs
+++ b/embassy-sync/src/ring_buffer.rs
@@ -3,7 +3,7 @@ use core::ops::Range;
pub struct RingBuffer<const N: usize> {
start: usize,
end: usize,
- empty: bool,
+ full: bool,
}
impl<const N: usize> RingBuffer<N> {
@@ -11,13 +11,13 @@ impl<const N: usize> RingBuffer<N> {
Self {
start: 0,
end: 0,
- empty: true,
+ full: false,
}
}
pub fn push_buf(&mut self) -> Range<usize> {
- if self.start == self.end && !self.empty {
- trace!(" ringbuf: push_buf empty");
+ if self.is_full() {
+ trace!(" ringbuf: push_buf full");
return 0..0;
}
@@ -38,11 +38,11 @@ impl<const N: usize> RingBuffer<N> {
}
self.end = self.wrap(self.end + n);
- self.empty = false;
+ self.full = self.start == self.end;
}
pub fn pop_buf(&mut self) -> Range<usize> {
- if self.empty {
+ if self.is_empty() {
trace!(" ringbuf: pop_buf empty");
return 0..0;
}
@@ -64,20 +64,20 @@ impl<const N: usize> RingBuffer<N> {
}
self.start = self.wrap(self.start + n);
- self.empty = self.start == self.end;
+ self.full = false;
}
pub fn is_full(&self) -> bool {
- self.start == self.end && !self.empty
+ self.full
}
pub fn is_empty(&self) -> bool {
- self.empty
+ self.start == self.end && !self.full
}
#[allow(unused)]
pub fn len(&self) -> usize {
- if self.empty {
+ if self.is_empty() {
0
} else if self.start < self.end {
self.end - self.start
@@ -89,7 +89,7 @@ impl<const N: usize> RingBuffer<N> {
pub fn clear(&mut self) {
self.start = 0;
self.end = 0;
- self.empty = true;
+ self.full = false;
}
fn wrap(&self, n: usize) -> usize {
From 1dbfa5ab72e3596932ccb6bd258fac70d2efa563 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Thu, 1 Feb 2024 10:28:12 -0500
Subject: [PATCH 104/392] Added hash v1/v2 configs.
---
embassy-stm32/src/hash/mod.rs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index e3d2d7b16..622777b02 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -9,7 +9,11 @@ use crate::peripherals::HASH;
use crate::rcc::sealed::RccPeripheral;
use crate::Peripheral;
+#[cfg(hash_v1)]
+const NUM_CONTEXT_REGS: usize = 51;
+#[cfg(hash_v2)]
const NUM_CONTEXT_REGS: usize = 54;
+
const HASH_BUFFER_LEN: usize = 68;
const DIGEST_BLOCK_SIZE: usize = 64;
@@ -20,8 +24,10 @@ pub enum Algorithm {
SHA1 = 0,
/// MD5 Algorithm
MD5 = 1,
+ #[cfg(hash_v2)]
/// SHA-224 Algorithm
SHA224 = 2,
+ #[cfg(hash_v2)]
/// SHA-256 Algorithm
SHA256 = 3,
}
From 72ca5a022b44fe621fbae52a33ac7e45b9cc66a2 Mon Sep 17 00:00:00 2001
From: Taylor Carpenter <taylor@tokenring.com>
Date: Thu, 1 Feb 2024 10:41:41 -0500
Subject: [PATCH 105/392] Add scatter memory files for extended BLE stack
Build script chooses the 'x.in' to copy over to 'tl_mbox.x' based on features
---
embassy-stm32-wpan/Cargo.toml | 2 ++
embassy-stm32-wpan/build.rs | 17 +++++++++++++++--
embassy-stm32-wpan/tl_mbox_extended_wb1.x.in | 16 ++++++++++++++++
embassy-stm32-wpan/tl_mbox_extended_wbx5.x.in | 16 ++++++++++++++++
4 files changed, 49 insertions(+), 2 deletions(-)
create mode 100644 embassy-stm32-wpan/tl_mbox_extended_wb1.x.in
create mode 100644 embassy-stm32-wpan/tl_mbox_extended_wbx5.x.in
diff --git a/embassy-stm32-wpan/Cargo.toml b/embassy-stm32-wpan/Cargo.toml
index 4f53a400a..360ca5f4b 100644
--- a/embassy-stm32-wpan/Cargo.toml
+++ b/embassy-stm32-wpan/Cargo.toml
@@ -44,6 +44,8 @@ defmt = ["dep:defmt", "embassy-sync/defmt", "embassy-embedded-hal/defmt", "embas
ble = ["dep:stm32wb-hci"]
mac = ["dep:bitflags", "dep:embassy-net-driver" ]
+extended = []
+
stm32wb10cc = [ "embassy-stm32/stm32wb10cc" ]
stm32wb15cc = [ "embassy-stm32/stm32wb15cc" ]
stm32wb30ce = [ "embassy-stm32/stm32wb30ce" ]
diff --git a/embassy-stm32-wpan/build.rs b/embassy-stm32-wpan/build.rs
index 94aac070d..7ab458bf2 100644
--- a/embassy-stm32-wpan/build.rs
+++ b/embassy-stm32-wpan/build.rs
@@ -18,9 +18,22 @@ fn main() {
// stm32wb tl_mbox link sections
let out_file = out_dir.join("tl_mbox.x").to_string_lossy().to_string();
- fs::write(out_file, fs::read_to_string("tl_mbox.x.in").unwrap()).unwrap();
+ let in_file;
+ if env::var_os("CARGO_FEATURE_EXTENDED").is_some() {
+ if env::vars()
+ .map(|(a, _)| a)
+ .any(|x| x.starts_with("CARGO_FEATURE_STM32WB1"))
+ {
+ in_file = "tl_mbox_extended_wb1.x.in";
+ } else {
+ in_file = "tl_mbox_extended_wbx5.x.in";
+ }
+ } else {
+ in_file = "tl_mbox.x.in";
+ }
+ fs::write(out_file, fs::read_to_string(in_file).unwrap()).unwrap();
println!("cargo:rustc-link-search={}", out_dir.display());
- println!("cargo:rerun-if-changed=tl_mbox.x.in");
+ println!("cargo:rerun-if-changed={}", in_file);
}
enum GetOneError {
diff --git a/embassy-stm32-wpan/tl_mbox_extended_wb1.x.in b/embassy-stm32-wpan/tl_mbox_extended_wb1.x.in
new file mode 100644
index 000000000..4cffdaddd
--- /dev/null
+++ b/embassy-stm32-wpan/tl_mbox_extended_wb1.x.in
@@ -0,0 +1,16 @@
+MEMORY
+{
+ RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 4K
+ RAMB_SHARED (xrw) : ORIGIN = 0x20030028, LENGTH = 4K
+}
+
+/*
+ * Scatter the mailbox interface memory sections in shared memory
+ */
+SECTIONS
+{
+ TL_REF_TABLE (NOLOAD) : { *(TL_REF_TABLE) } >RAM_SHARED
+
+ MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAMB_SHARED
+ MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAMB_SHARED
+}
diff --git a/embassy-stm32-wpan/tl_mbox_extended_wbx5.x.in b/embassy-stm32-wpan/tl_mbox_extended_wbx5.x.in
new file mode 100644
index 000000000..281d637a9
--- /dev/null
+++ b/embassy-stm32-wpan/tl_mbox_extended_wbx5.x.in
@@ -0,0 +1,16 @@
+MEMORY
+{
+ RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 2K
+ RAMB_SHARED (xrw) : ORIGIN = 0x20038000, LENGTH = 10K
+}
+
+/*
+ * Scatter the mailbox interface memory sections in shared memory
+ */
+SECTIONS
+{
+ TL_REF_TABLE (NOLOAD) : { *(TL_REF_TABLE) } >RAM_SHARED
+
+ MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAMB_SHARED
+ MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAMB_SHARED
+}
From aa767272a87bddc9ac7fbce3962989342390d689 Mon Sep 17 00:00:00 2001
From: Romain Goyet <romain.goyet@numworks.com>
Date: Thu, 1 Feb 2024 13:39:14 -0500
Subject: [PATCH 106/392] STM32WBA's high speed external clock has to run at 32
MHz
---
embassy-stm32/src/rcc/wba.rs | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index c0cd91507..1d04d480a 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -6,26 +6,28 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
+// HSE speed
+pub const HSE_FREQ: Hertz = Hertz(32_000_000);
pub use crate::pac::pwr::vals::Vos as VoltageScale;
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
#[derive(Copy, Clone)]
pub enum ClockSrc {
- HSE(Hertz),
+ HSE,
HSI,
}
#[derive(Clone, Copy, Debug)]
pub enum PllSource {
- HSE(Hertz),
+ HSE,
HSI,
}
impl Into<Pllsrc> for PllSource {
fn into(self) -> Pllsrc {
match self {
- PllSource::HSE(..) => Pllsrc::HSE,
+ PllSource::HSE => Pllsrc::HSE,
PllSource::HSI => Pllsrc::HSI,
}
}
@@ -34,7 +36,7 @@ impl Into<Pllsrc> for PllSource {
impl Into<Sw> for ClockSrc {
fn into(self) -> Sw {
match self {
- ClockSrc::HSE(..) => Sw::HSE,
+ ClockSrc::HSE => Sw::HSE,
ClockSrc::HSI => Sw::HSI,
}
}
@@ -64,11 +66,11 @@ impl Default for Config {
pub(crate) unsafe fn init(config: Config) {
let sys_clk = match config.mux {
- ClockSrc::HSE(freq) => {
+ ClockSrc::HSE => {
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
- freq
+ HSE_FREQ
}
ClockSrc::HSI => {
RCC.cr().write(|w| w.set_hsion(true));
From 21024e863820d4a3ddb9e72041251c72d10ee5a6 Mon Sep 17 00:00:00 2001
From: Joonas Javanainen <joonas.javanainen@gmail.com>
Date: Thu, 1 Feb 2024 21:48:29 +0200
Subject: [PATCH 107/392] Fix F2 temperature sensor ADC channel
On all F2 devices (F205/207/215/217) the sensor is connected to
ADC1_IN16, and is not shared with VBAT which is connected to ADC1_IN18.
---
embassy-stm32/src/adc/v2.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 4622b40a9..036a4ec37 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -34,7 +34,7 @@ impl AdcPin<ADC1> for Temperature {}
impl super::sealed::AdcPin<ADC1> for Temperature {
fn channel(&self) -> u8 {
cfg_if::cfg_if! {
- if #[cfg(any(stm32f40, stm32f41))] {
+ if #[cfg(any(stm32f2, stm32f40, stm32f41))] {
16
} else {
18
From 7e0f287431f7e5bdfc562164bf67afb214ac4700 Mon Sep 17 00:00:00 2001
From: Joonas Javanainen <joonas.javanainen@gmail.com>
Date: Thu, 1 Feb 2024 21:58:36 +0200
Subject: [PATCH 108/392] Fix ADC max frequency for F2
---
embassy-stm32/src/adc/v2.rs | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 036a4ec37..b37ac5a5d 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -67,7 +67,11 @@ enum Prescaler {
impl Prescaler {
fn from_pclk2(freq: Hertz) -> Self {
+ // Datasheet for F2 specifies min frequency 0.6 MHz, and max 30 MHz (with VDDA 2.4-3.6V).
+ #[cfg(stm32f2)]
+ const MAX_FREQUENCY: Hertz = Hertz(30_000_000);
// Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
+ #[cfg(not(stm32f2))]
const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
let raw_div = freq.0 / MAX_FREQUENCY.0;
match raw_div {
From e7d1119750dff876e76adbb04f57ac274e913772 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Thu, 1 Feb 2024 23:15:17 +0100
Subject: [PATCH 109/392] stm32: automatically use refcounting for rcc bits
used multiple times.
---
embassy-stm32/build.rs | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 69848762a..74cc3f8b9 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -449,7 +449,16 @@ fn main() {
// ========
// Generate RccPeripheral impls
- let refcounted_peripherals = HashSet::from(["usart", "adc", "can"]);
+ // count how many times each xxENR field is used, to enable refcounting if used more than once.
+ let mut rcc_field_count: HashMap<_, usize> = HashMap::new();
+ for p in METADATA.peripherals {
+ if let Some(rcc) = &p.rcc {
+ let en = rcc.enable.as_ref().unwrap();
+ *rcc_field_count.entry((en.register, en.field)).or_insert(0) += 1;
+ }
+ }
+
+ let force_refcount = HashSet::from(["usart"]);
let mut refcount_statics = BTreeSet::new();
for p in METADATA.peripherals {
@@ -487,7 +496,9 @@ fn main() {
let en_reg = format_ident!("{}", en.register);
let set_en_field = format_ident!("set_{}", en.field);
- let (before_enable, before_disable) = if refcounted_peripherals.contains(ptype) {
+ let refcount =
+ force_refcount.contains(ptype) || *rcc_field_count.get(&(en.register, en.field)).unwrap() > 1;
+ let (before_enable, before_disable) = if refcount {
let refcount_static =
format_ident!("{}_{}", en.register.to_ascii_uppercase(), en.field.to_ascii_uppercase());
From 10275309021d933d5dfe4c0a96928432e11cd8b4 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Thu, 1 Feb 2024 17:27:25 -0500
Subject: [PATCH 110/392] Added hash interrupts for async.
---
embassy-stm32/src/hash/mod.rs | 171 ++++++++++++++++++++++++++--------
1 file changed, 134 insertions(+), 37 deletions(-)
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 622777b02..4e37e60e1 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -1,22 +1,47 @@
//! Hash generator (HASH)
use core::cmp::min;
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::task::Poll;
use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_sync::waitqueue::AtomicWaker;
+
+use crate::peripherals::HASH;
use stm32_metapac::hash::regs::*;
-use crate::pac::HASH as PAC_HASH;
-use crate::peripherals::HASH;
+use crate::interrupt::typelevel::Interrupt;
use crate::rcc::sealed::RccPeripheral;
-use crate::Peripheral;
+use crate::{interrupt, pac, peripherals, Peripheral};
#[cfg(hash_v1)]
const NUM_CONTEXT_REGS: usize = 51;
#[cfg(hash_v2)]
const NUM_CONTEXT_REGS: usize = 54;
-
const HASH_BUFFER_LEN: usize = 68;
const DIGEST_BLOCK_SIZE: usize = 64;
+static HASH_WAKER: AtomicWaker = AtomicWaker::new();
+
+/// HASH interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+ _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+ unsafe fn on_interrupt() {
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ T::regs().imr().modify(|reg| reg.set_dinie(false));
+ HASH_WAKER.wake();
+ }
+ if bits.dcis() {
+ T::regs().imr().modify(|reg| reg.set_dcie(false));
+ HASH_WAKER.wake();
+ }
+ }
+}
+
///Hash algorithm selection
#[derive(PartialEq)]
pub enum Algorithm {
@@ -61,23 +86,27 @@ pub struct Context {
}
/// HASH driver.
-pub struct Hash<'d> {
- _peripheral: PeripheralRef<'d, HASH>,
+pub struct Hash<'d, T: Instance> {
+ _peripheral: PeripheralRef<'d, T>,
}
-impl<'d> Hash<'d> {
+impl<'d, T: Instance> Hash<'d, T> {
/// Instantiates, resets, and enables the HASH peripheral.
- pub fn new(peripheral: impl Peripheral<P = HASH> + 'd) -> Self {
+ pub fn new(peripheral: impl Peripheral<P = T> + 'd) -> Self {
HASH::enable_and_reset();
into_ref!(peripheral);
let instance = Self {
_peripheral: peripheral,
};
+
+ T::Interrupt::unpend();
+ unsafe { T::Interrupt::enable() };
+
instance
}
/// Starts computation of a new hash and returns the saved peripheral state.
- pub fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
+ pub async fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
// Define a context for this new computation.
let mut ctx = Context {
first_word_sent: false,
@@ -92,7 +121,7 @@ impl<'d> Hash<'d> {
};
// Set the data type in the peripheral.
- PAC_HASH.cr().modify(|w| w.set_datatype(ctx.format as u8));
+ T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
// Select the algorithm.
let mut algo0 = false;
@@ -103,18 +132,19 @@ impl<'d> Hash<'d> {
if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
algo1 = true;
}
- PAC_HASH.cr().modify(|w| w.set_algo0(algo0));
- PAC_HASH.cr().modify(|w| w.set_algo1(algo1));
- PAC_HASH.cr().modify(|w| w.set_init(true));
+ T::regs().cr().modify(|w| w.set_algo0(algo0));
+ T::regs().cr().modify(|w| w.set_algo1(algo1));
+ T::regs().cr().modify(|w| w.set_init(true));
// Store and return the state of the peripheral.
- self.store_context(&mut ctx);
+ self.store_context(&mut ctx).await;
ctx
}
/// Restores the peripheral state using the given context,
/// then updates the state with the provided data.
- pub fn update(&mut self, ctx: &mut Context, input: &[u8]) {
+ /// Peripheral state is saved upon return.
+ pub async fn update(&mut self, ctx: &mut Context, input: &[u8]) {
let mut data_waiting = input.len() + ctx.buflen;
if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
// There isn't enough data to digest a block, so append it to the buffer.
@@ -123,7 +153,7 @@ impl<'d> Hash<'d> {
return;
}
- //Restore the peripheral state.
+ // Restore the peripheral state.
self.load_context(&ctx);
let mut ilen_remaining = input.len();
@@ -154,6 +184,7 @@ impl<'d> Hash<'d> {
ctx.buflen += ilen_remaining;
} else {
let mut total_data_sent = 0;
+
// First ingest the data in the buffer.
let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
if empty_len > 0 {
@@ -188,25 +219,43 @@ impl<'d> Hash<'d> {
}
// Save the peripheral context.
- self.store_context(ctx);
+ self.store_context(ctx).await;
}
/// Computes a digest for the given context. A slice of the provided digest buffer is returned.
/// The length of the returned slice is dependent on the digest length of the selected algorithm.
- pub fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; 32]) -> &'a [u8] {
+ pub async fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; 32]) -> &'a [u8] {
// Restore the peripheral state.
self.load_context(&ctx);
+
// Hash the leftover bytes, if any.
self.accumulate(&ctx.buffer[0..ctx.buflen]);
ctx.buflen = 0;
//Start the digest calculation.
- PAC_HASH.str().write(|w| w.set_dcal(true));
+ T::regs().str().write(|w| w.set_dcal(true));
- //Wait for completion.
- while !PAC_HASH.sr().read().dcis() {}
+ // Wait for completion.
+ poll_fn(|cx| {
+ // Check if already done.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ return Poll::Ready(());
+ }
+ // Register waker, then enable interrupts.
+ HASH_WAKER.register(cx.waker());
+ T::regs().imr().modify(|reg| reg.set_dinie(true));
+ // Check for completion.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
+ .await;
- //Return the digest.
+ // Return the digest.
let digest_words = match ctx.algo {
Algorithm::SHA1 => 5,
Algorithm::MD5 => 4,
@@ -215,37 +264,57 @@ impl<'d> Hash<'d> {
};
let mut i = 0;
while i < digest_words {
- let word = PAC_HASH.hr(i).read();
+ let word = T::regs().hr(i).read();
digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
i += 1;
}
&digest[0..digest_words * 4]
}
+ /// Push data into the hash core.
fn accumulate(&mut self, input: &[u8]) {
- //Set the number of valid bits.
+ // Set the number of valid bits.
let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
- PAC_HASH.str().modify(|w| w.set_nblw(num_valid_bits));
+ T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
let mut i = 0;
while i < input.len() {
let mut word: [u8; 4] = [0; 4];
let copy_idx = min(i + 4, input.len());
word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
- PAC_HASH.din().write_value(u32::from_ne_bytes(word));
+ T::regs().din().write_value(u32::from_ne_bytes(word));
i += 4;
}
}
/// Save the peripheral state to a context.
- fn store_context(&mut self, ctx: &mut Context) {
- while !PAC_HASH.sr().read().dinis() {}
- ctx.imr = PAC_HASH.imr().read().0;
- ctx.str = PAC_HASH.str().read().0;
- ctx.cr = PAC_HASH.cr().read().0;
+ async fn store_context(&mut self, ctx: &mut Context) {
+ // Wait for interrupt.
+ poll_fn(|cx| {
+ // Check if already done.
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ return Poll::Ready(());
+ }
+ // Register waker, then enable interrupts.
+ HASH_WAKER.register(cx.waker());
+ T::regs().imr().modify(|reg| reg.set_dinie(true));
+ // Check for completion.
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
+ .await;
+
+ ctx.imr = T::regs().imr().read().0;
+ ctx.str = T::regs().str().read().0;
+ ctx.cr = T::regs().cr().read().0;
let mut i = 0;
while i < NUM_CONTEXT_REGS {
- ctx.csr[i] = PAC_HASH.csr(i).read();
+ ctx.csr[i] = T::regs().csr(i).read();
i += 1;
}
}
@@ -253,14 +322,42 @@ impl<'d> Hash<'d> {
/// Restore the peripheral state from a context.
fn load_context(&mut self, ctx: &Context) {
// Restore the peripheral state from the context.
- PAC_HASH.imr().write_value(Imr { 0: ctx.imr });
- PAC_HASH.str().write_value(Str { 0: ctx.str });
- PAC_HASH.cr().write_value(Cr { 0: ctx.cr });
- PAC_HASH.cr().modify(|w| w.set_init(true));
+ T::regs().imr().write_value(Imr { 0: ctx.imr });
+ T::regs().str().write_value(Str { 0: ctx.str });
+ T::regs().cr().write_value(Cr { 0: ctx.cr });
+ T::regs().cr().modify(|w| w.set_init(true));
let mut i = 0;
while i < NUM_CONTEXT_REGS {
- PAC_HASH.csr(i).write_value(ctx.csr[i]);
+ T::regs().csr(i).write_value(ctx.csr[i]);
i += 1;
}
}
}
+
+pub(crate) mod sealed {
+ use super::*;
+
+ pub trait Instance {
+ fn regs() -> pac::hash::Hash;
+ }
+}
+
+/// HASH instance trait.
+pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+ /// Interrupt for this HASH instance.
+ type Interrupt: interrupt::typelevel::Interrupt;
+}
+
+foreach_interrupt!(
+ ($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
+ impl Instance for peripherals::$inst {
+ type Interrupt = crate::interrupt::typelevel::$irq;
+ }
+
+ impl sealed::Instance for peripherals::$inst {
+ fn regs() -> crate::pac::hash::Hash {
+ crate::pac::$inst
+ }
+ }
+ };
+);
From e05c8e2f44d3b210affa10a6e7fc7e9a3c991683 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Thu, 1 Feb 2024 23:47:30 +0100
Subject: [PATCH 111/392] stm32/dac: use autogenerated RCC impls.
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/dac/mod.rs | 23 -----------------------
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 698febf71..aed9f7a46 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-768b3e8e3199e03de0acd0d4590d06f51eebb7dd" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-768b3e8e3199e03de0acd0d4590d06f51eebb7dd", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 31dedf06e..60f9404c2 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -504,29 +504,6 @@ pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
foreach_peripheral!(
(dac, $inst:ident) => {
- // H7 uses single bit for both DAC1 and DAC2, this is a hack until a proper fix is implemented
- #[cfg(any(rcc_h7, rcc_h7rm0433))]
- impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
- fn frequency() -> crate::time::Hertz {
- critical_section::with(|_| unsafe { crate::rcc::get_freqs().pclk1 })
- }
-
- fn enable_and_reset_with_cs(_cs: critical_section::CriticalSection) {
- // TODO: Increment refcount?
- crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
- crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
- crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
- }
-
- fn disable_with_cs(_cs: critical_section::CriticalSection) {
- // TODO: Decrement refcount?
- crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false))
- }
- }
-
- #[cfg(any(rcc_h7, rcc_h7rm0433))]
- impl crate::rcc::RccPeripheral for peripherals::$inst {}
-
impl crate::dac::sealed::Instance for peripherals::$inst {
fn regs() -> &'static crate::pac::dac::Dac {
&crate::pac::$inst
From 92690d8590301360cca8889fe9d118eb3cc30202 Mon Sep 17 00:00:00 2001
From: Romain Goyet <romain@goyet.com>
Date: Fri, 2 Feb 2024 13:53:16 -0500
Subject: [PATCH 112/392] Migrate STM32WBA to RCCv3
---
embassy-stm32/src/rcc/wba.rs | 195 +++++++++++++++++++----------------
1 file changed, 104 insertions(+), 91 deletions(-)
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 1d04d480a..dfa236484 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -1,5 +1,8 @@
-use stm32_metapac::rcc::vals::{Pllsrc, Sw};
-
+pub use crate::pac::pwr::vals::Vos as VoltageScale;
+use crate::pac::rcc::regs::Cfgr1;
+pub use crate::pac::rcc::vals::{
+ Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc,
+};
use crate::pac::{FLASH, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@@ -9,82 +12,108 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
// HSE speed
pub const HSE_FREQ: Hertz = Hertz(32_000_000);
-pub use crate::pac::pwr::vals::Vos as VoltageScale;
-pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
-
-#[derive(Copy, Clone)]
-pub enum ClockSrc {
- HSE,
- HSI,
-}
-
-#[derive(Clone, Copy, Debug)]
-pub enum PllSource {
- HSE,
- HSI,
-}
-
-impl Into<Pllsrc> for PllSource {
- fn into(self) -> Pllsrc {
- match self {
- PllSource::HSE => Pllsrc::HSE,
- PllSource::HSI => Pllsrc::HSI,
- }
- }
-}
-
-impl Into<Sw> for ClockSrc {
- fn into(self) -> Sw {
- match self {
- ClockSrc::HSE => Sw::HSE,
- ClockSrc::HSI => Sw::HSI,
- }
- }
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+ pub prescaler: HsePrescaler,
}
+/// Clocks configuration
pub struct Config {
+ // base clock sources
+ pub hsi: bool,
+ pub hse: Option<Hse>,
+
+ // sysclk, buses.
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub apb7_pre: APBPrescaler,
+
+ // low speed LSI/LSE/RTC
pub ls: super::LsConfig,
+
+ pub adc_clock_source: AdcClockSource,
+
+ pub voltage_scale: VoltageScale,
}
impl Default for Config {
- fn default() -> Self {
- Self {
+ #[inline]
+ fn default() -> Config {
+ Config {
+ hse: None,
+ hsi: true,
mux: ClockSrc::HSI,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
apb7_pre: APBPrescaler::DIV1,
ls: Default::default(),
+ adc_clock_source: AdcClockSource::HCLK1,
+ voltage_scale: VoltageScale::RANGE2,
}
}
}
+fn hsi_enable() {
+ RCC.cr().modify(|w| w.set_hsion(true));
+ while !RCC.cr().read().hsirdy() {}
+}
+
pub(crate) unsafe fn init(config: Config) {
+ // Switch to HSI to prevent problems with PLL configuration.
+ if !RCC.cr().read().hsion() {
+ hsi_enable()
+ }
+ if RCC.cfgr1().read().sws() != ClockSrc::HSI {
+ // Set HSI as a clock source, reset prescalers.
+ RCC.cfgr1().write_value(Cfgr1::default());
+ // Wait for clock switch status bits to change.
+ while RCC.cfgr1().read().sws() != ClockSrc::HSI {}
+ }
+
+ // Set voltage scale
+ crate::pac::PWR.vosr().write(|w| w.set_vos(config.voltage_scale));
+ while !crate::pac::PWR.vosr().read().vosrdy() {}
+
+ let rtc = config.ls.init();
+
+ let hsi = config.hsi.then(|| {
+ hsi_enable();
+
+ HSI_FREQ
+ });
+
+ let hse = config.hse.map(|hse| {
+ RCC.cr().write(|w| {
+ w.set_hseon(true);
+ w.set_hsepre(hse.prescaler);
+ });
+ while !RCC.cr().read().hserdy() {}
+
+ HSE_FREQ
+ });
+
let sys_clk = match config.mux {
- ClockSrc::HSE => {
- RCC.cr().write(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
-
- HSE_FREQ
- }
- ClockSrc::HSI => {
- RCC.cr().write(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
-
- HSI_FREQ
- }
+ ClockSrc::HSE => hse.unwrap(),
+ ClockSrc::HSI => hsi.unwrap(),
+ ClockSrc::_RESERVED_1 => unreachable!(),
+ ClockSrc::PLL1_R => todo!(),
};
- // TODO make configurable
- let power_vos = VoltageScale::RANGE1;
+ assert!(sys_clk.0 <= 100_000_000);
- // states and programming delay
- let wait_states = match power_vos {
+ let hclk1 = sys_clk / config.ahb_pre;
+ let hclk2 = hclk1;
+ let hclk4 = hclk1;
+ // TODO: hclk5
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
+ let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
+ let (pclk7, _) = super::util::calc_pclk(hclk1, config.apb7_pre);
+
+ // Set flash wait states
+ let flash_latency = match config.voltage_scale {
VoltageScale::RANGE1 => match sys_clk.0 {
..=32_000_000 => 0,
..=64_000_000 => 1,
@@ -99,13 +128,24 @@ pub(crate) unsafe fn init(config: Config) {
},
};
- FLASH.acr().modify(|w| {
- w.set_latency(wait_states);
- });
+ FLASH.acr().modify(|w| w.set_latency(flash_latency));
+ while FLASH.acr().read().latency() != flash_latency {}
+
+ // Set sram wait states
+ let _sram_latency = match config.voltage_scale {
+ VoltageScale::RANGE1 => 0,
+ VoltageScale::RANGE2 => match sys_clk.0 {
+ ..=12_000_000 => 0,
+ ..=16_000_000 => 1,
+ _ => 2,
+ },
+ };
+ // TODO: Set the SRAM wait states
RCC.cfgr1().modify(|w| {
- w.set_sw(config.mux.into());
+ w.set_sw(config.mux);
});
+ while RCC.cfgr1().read().sws() != config.mux {}
RCC.cfgr2().modify(|w| {
w.set_hpre(config.ahb_pre);
@@ -113,45 +153,18 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre2(config.apb2_pre);
});
- RCC.cfgr3().modify(|w| {
- w.set_ppre7(config.apb7_pre);
- });
-
- let ahb_freq = sys_clk / config.ahb_pre;
- let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
- let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
- let (apb7_freq, _apb7_tim_freq) = match config.apb7_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
-
- let rtc = config.ls.init();
+ RCC.ccipr3().modify(|w| w.set_adcsel(config.adc_clock_source));
set_freqs(Clocks {
sys: sys_clk,
- hclk1: ahb_freq,
- hclk2: ahb_freq,
- hclk4: ahb_freq,
- pclk1: apb1_freq,
- pclk2: apb2_freq,
- pclk7: apb7_freq,
- pclk1_tim: apb1_tim_freq,
- pclk2_tim: apb2_tim_freq,
+ hclk1,
+ hclk2,
+ hclk4,
+ pclk1,
+ pclk2,
+ pclk7,
+ pclk1_tim,
+ pclk2_tim,
rtc,
});
}
From 98668473756b144cb5e5d7bb2be4b54b947412ff Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Fri, 2 Feb 2024 22:42:32 +0100
Subject: [PATCH 113/392] stm32: autogenerate clocks struct, enable mux for all
chips.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/build.rs | 69 ++++++++-----
embassy-stm32/src/adc/f1.rs | 3 +-
embassy-stm32/src/adc/f3.rs | 2 +-
embassy-stm32/src/adc/mod.rs | 7 --
embassy-stm32/src/eth/mod.rs | 3 +-
embassy-stm32/src/eth/v1/mod.rs | 4 +-
embassy-stm32/src/eth/v2/mod.rs | 4 +-
embassy-stm32/src/hrtim/mod.rs | 4 +-
embassy-stm32/src/hrtim/traits.rs | 16 +--
embassy-stm32/src/i2s.rs | 9 +-
embassy-stm32/src/rcc/c0.rs | 15 ++-
embassy-stm32/src/rcc/f.rs | 57 ++++++-----
embassy-stm32/src/rcc/f0.rs | 21 ++--
embassy-stm32/src/rcc/f1.rs | 19 ++--
embassy-stm32/src/rcc/f3.rs | 22 +++--
embassy-stm32/src/rcc/g0.rs | 15 ++-
embassy-stm32/src/rcc/g4.rs | 23 +++--
embassy-stm32/src/rcc/h.rs | 59 ++++-------
embassy-stm32/src/rcc/l.rs | 75 ++++++++------
embassy-stm32/src/rcc/mod.rs | 159 +-----------------------------
embassy-stm32/src/rcc/u5.rs | 46 ++++++---
embassy-stm32/src/rcc/wba.rs | 32 +++---
embassy-stm32/src/sdmmc/mod.rs | 64 +-----------
embassy-stm32/src/usb/usb.rs | 2 +-
25 files changed, 284 insertions(+), 450 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index aed9f7a46..c412e13d5 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-768b3e8e3199e03de0acd0d4590d06f51eebb7dd" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3e3b53df78b4c90ae9c44a58b4f9f93c93a415b7" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-768b3e8e3199e03de0acd0d4590d06f51eebb7dd", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3e3b53df78b4c90ae9c44a58b4f9f93c93a415b7", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 74cc3f8b9..3885c5d18 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -461,6 +461,8 @@ fn main() {
let force_refcount = HashSet::from(["usart"]);
let mut refcount_statics = BTreeSet::new();
+ let mut clock_names = BTreeSet::new();
+
for p in METADATA.peripherals {
if !singletons.contains(&p.name.to_string()) {
continue;
@@ -492,7 +494,6 @@ fn main() {
let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
let pname = format_ident!("{}", p.name);
- let clk = format_ident!("{}", rcc.clock);
let en_reg = format_ident!("{}", en.register);
let set_en_field = format_ident!("set_{}", en.field);
@@ -522,14 +523,7 @@ fn main() {
(TokenStream::new(), TokenStream::new())
};
- let mux_supported = HashSet::from(["c0", "h5", "h50", "h7", "h7ab", "h7rm0433", "g0", "g4", "l4"])
- .contains(rcc_registers.version);
let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
- // restrict mux implementation to supported versions
- if !mux_supported {
- return None;
- }
-
let mux = mux?;
let fieldset = rcc_enum_map.get(mux.register)?;
let enumm = fieldset.get(mux.field)?;
@@ -550,15 +544,9 @@ fn main() {
.map(|v| {
let variant_name = format_ident!("{}", v.name);
let clock_name = format_ident!("{}", v.name.to_ascii_lowercase());
-
- if v.name.starts_with("HCLK") || v.name.starts_with("PCLK") || v.name == "SYS" {
- quote! {
- #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name },
- }
- } else {
- quote! {
- #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name.unwrap() },
- }
+ clock_names.insert(v.name.to_ascii_lowercase());
+ quote! {
+ #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name.unwrap() },
}
})
.collect();
@@ -569,19 +557,21 @@ fn main() {
#[allow(unreachable_patterns)]
match crate::pac::RCC.#fieldset_name().read().#field_name() {
#match_arms
-
_ => unreachable!(),
}
}
}
- None => quote! {
- unsafe { crate::rcc::get_freqs().#clk }
- },
+ None => {
+ let clock_name = format_ident!("{}", rcc.clock);
+ clock_names.insert(rcc.clock.to_string());
+ quote! {
+ unsafe { crate::rcc::get_freqs().#clock_name.unwrap() }
+ }
+ }
};
/*
A refcount leak can result if the same field is shared by peripherals with different stop modes
-
This condition should be checked in stm32-data
*/
let stop_refcount = match rcc.stop_mode {
@@ -628,6 +618,39 @@ fn main() {
}
}
+ // Generate RCC
+ clock_names.insert("sys".to_string());
+ clock_names.insert("rtc".to_string());
+ let clock_idents: Vec<_> = clock_names.iter().map(|n| format_ident!("{}", n)).collect();
+ g.extend(quote! {
+ #[derive(Clone, Copy, Debug)]
+ #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+ pub struct Clocks {
+ #(
+ pub #clock_idents: Option<crate::time::Hertz>,
+ )*
+ }
+ });
+
+ let clocks_macro = quote!(
+ macro_rules! set_clocks {
+ ($($(#[$m:meta])* $k:ident: $v:expr,)*) => {
+ {
+ #[allow(unused)]
+ struct Temp {
+ $($(#[$m])* $k: Option<crate::time::Hertz>,)*
+ }
+ let all = Temp {
+ $($(#[$m])* $k: $v,)*
+ };
+ crate::rcc::set_freqs(crate::rcc::Clocks {
+ #( #clock_idents: all.#clock_idents, )*
+ });
+ }
+ };
+ }
+ );
+
let refcount_mod: TokenStream = refcount_statics
.iter()
.map(|refcount_static| {
@@ -1349,7 +1372,7 @@ fn main() {
}
}
- let mut m = String::new();
+ let mut m = clocks_macro.to_string();
// DO NOT ADD more macros like these.
// These turned to be a bad idea!
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index fb27bb87b..c896d8e3a 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -6,7 +6,6 @@ use embassy_hal_internal::into_ref;
use embedded_hal_02::blocking::delay::DelayUs;
use crate::adc::{Adc, AdcPin, Instance, SampleTime};
-use crate::rcc::get_freqs;
use crate::time::Hertz;
use crate::{interrupt, Peripheral};
@@ -80,7 +79,7 @@ impl<'d, T: Instance> Adc<'d, T> {
}
fn freq() -> Hertz {
- unsafe { get_freqs() }.adc.unwrap()
+ T::frequency()
}
pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 6f59c230f..6606a2b9c 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -102,7 +102,7 @@ impl<'d, T: Instance> Adc<'d, T> {
}
fn freq() -> Hertz {
- <T as crate::adc::sealed::Instance>::frequency()
+ <T as crate::rcc::sealed::RccPeripheral>::frequency()
}
pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index e4dd35c34..d21c3053f 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -61,8 +61,6 @@ pub(crate) mod sealed {
fn regs() -> crate::pac::adc::Adc;
#[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
fn common_regs() -> crate::pac::adccommon::AdcCommon;
- #[cfg(adc_f3)]
- fn frequency() -> crate::time::Hertz;
#[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
fn state() -> &'static State;
}
@@ -103,11 +101,6 @@ foreach_adc!(
return crate::pac::$common_inst
}
- #[cfg(adc_f3)]
- fn frequency() -> crate::time::Hertz {
- unsafe { crate::rcc::get_freqs() }.$clock.unwrap()
- }
-
#[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
fn state() -> &'static sealed::State {
static STATE: sealed::State = sealed::State::new();
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index fbcdd7fae..71fe09c3f 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -13,6 +13,7 @@ use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
use embassy_sync::waitqueue::AtomicWaker;
pub use self::_version::{InterruptHandler, *};
+use crate::rcc::RccPeripheral;
#[allow(unused)]
const MTU: usize = 1514;
@@ -183,7 +184,7 @@ pub(crate) mod sealed {
}
/// Ethernet instance.
-pub trait Instance: sealed::Instance + Send + 'static {}
+pub trait Instance: sealed::Instance + RccPeripheral + Send + 'static {}
impl sealed::Instance for crate::peripherals::ETH {
fn regs() -> crate::pac::eth::Eth {
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 2ce5b3927..e5b7b0452 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -20,6 +20,7 @@ use crate::pac::AFIO;
#[cfg(any(eth_v1b, eth_v1c))]
use crate::pac::SYSCFG;
use crate::pac::{ETH, RCC};
+use crate::rcc::sealed::RccPeripheral;
use crate::{interrupt, Peripheral};
/// Interrupt handler.
@@ -191,8 +192,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
// TODO MTU size setting not found for v1 ethernet, check if correct
- // NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
- let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
+ let hclk = <T as RccPeripheral>::frequency();
let hclk_mhz = hclk.0 / 1_000_000;
// Set the MDC clock frequency in the range 1MHz - 2.5MHz
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 4b22d1d21..8d69561d4 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -11,6 +11,7 @@ use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::{AnyPin, Speed};
use crate::interrupt::InterruptExt;
use crate::pac::ETH;
+use crate::rcc::sealed::RccPeripheral;
use crate::{interrupt, Peripheral};
/// Interrupt handler.
@@ -264,8 +265,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
w.set_rbsz(RX_BUFFER_SIZE as u16);
});
- // NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
- let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
+ let hclk = <T as RccPeripheral>::frequency();
let hclk_mhz = hclk.0 / 1_000_000;
// Set the MDC clock frequency in the range 1MHz - 2.5MHz
diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index faefaabbc..3ec646fc3 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -10,8 +10,6 @@ pub use traits::Instance;
#[allow(unused_imports)]
use crate::gpio::sealed::{AFType, Pin};
use crate::gpio::AnyPin;
-#[cfg(stm32f334)]
-use crate::rcc::get_freqs;
use crate::time::Hertz;
use crate::Peripheral;
@@ -182,7 +180,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
T::enable_and_reset();
#[cfg(stm32f334)]
- if unsafe { get_freqs() }.hrtim.is_some() {
+ if crate::pac::RCC.cfgr3().read().hrtim1sw() == crate::pac::rcc::vals::Timsw::PLL1_P {
// Enable and and stabilize the DLL
T::regs().dllcr().modify(|w| {
w.set_cal(true);
diff --git a/embassy-stm32/src/hrtim/traits.rs b/embassy-stm32/src/hrtim/traits.rs
index cfd31c47c..dcc2b9ef4 100644
--- a/embassy-stm32/src/hrtim/traits.rs
+++ b/embassy-stm32/src/hrtim/traits.rs
@@ -80,10 +80,12 @@ pub(crate) mod sealed {
fn set_master_frequency(frequency: Hertz) {
let f = frequency.0;
- #[cfg(not(stm32f334))]
+
+ // TODO: wire up HRTIM to the RCC mux infra.
+ //#[cfg(stm32f334)]
+ //let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
+ //#[cfg(not(stm32f334))]
let timer_f = Self::frequency().0;
- #[cfg(stm32f334)]
- let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
let psc_min = (timer_f / f) / (u16::MAX as u32 / 32);
let psc = if Self::regs().isr().read().dllrdy() {
@@ -103,10 +105,12 @@ pub(crate) mod sealed {
fn set_channel_frequency(channel: usize, frequency: Hertz) {
let f = frequency.0;
- #[cfg(not(stm32f334))]
+
+ // TODO: wire up HRTIM to the RCC mux infra.
+ //#[cfg(stm32f334)]
+ //let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
+ //#[cfg(not(stm32f334))]
let timer_f = Self::frequency().0;
- #[cfg(stm32f334)]
- let timer_f = unsafe { crate::rcc::get_freqs() }.hrtim.unwrap_or(Self::frequency()).0;
let psc_min = (timer_f / f) / (u16::MAX as u32 / 32);
let psc = if Self::regs().isr().read().dllrdy() {
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index 1f85c0bc5..e9065dce6 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -4,7 +4,6 @@ use embassy_hal_internal::into_ref;
use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::AnyPin;
use crate::pac::spi::vals;
-use crate::rcc::get_freqs;
use crate::spi::{Config as SpiConfig, *};
use crate::time::Hertz;
use crate::{Peripheral, PeripheralRef};
@@ -193,10 +192,10 @@ impl<'d, T: Instance, Tx, Rx> I2S<'d, T, Tx, Rx> {
spi_cfg.frequency = freq;
let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg);
- #[cfg(all(rcc_f4, not(stm32f410)))]
- let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
-
- #[cfg(stm32f410)]
+ // TODO move i2s to the new mux infra.
+ //#[cfg(all(rcc_f4, not(stm32f410)))]
+ //let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
+ //#[cfg(stm32f410)]
let pclk = T::frequency();
let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index 68f029ca0..ca1222185 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -2,7 +2,6 @@ use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::Sw;
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Ppre as APBPrescaler};
use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -133,13 +132,13 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- set_freqs(Clocks {
+ set_clocks!(
hsi: None,
lse: None,
- sys: sys_clk,
- hclk1: ahb_freq,
- pclk1: apb_freq,
- pclk1_tim: apb_tim_freq,
- rtc,
- });
+ sys: Some(sys_clk),
+ hclk1: Some(ahb_freq),
+ pclk1: Some(apb_freq),
+ pclk1_tim: Some(apb_tim_freq),
+ rtc: rtc,
+ );
}
diff --git a/embassy-stm32/src/rcc/f.rs b/embassy-stm32/src/rcc/f.rs
index 36d9f178f..e306d478d 100644
--- a/embassy-stm32/src/rcc/f.rs
+++ b/embassy-stm32/src/rcc/f.rs
@@ -7,7 +7,6 @@ pub use crate::pac::rcc::vals::{
#[cfg(any(stm32f4, stm32f7))]
use crate::pac::PWR;
use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
// TODO: on some F4s, PLLM is shared between all PLLs. Enforce that.
@@ -183,9 +182,9 @@ pub(crate) unsafe fn init(config: Config) {
};
let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
#[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
- let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
+ let plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
- let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
+ let pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
// Configure sysclk
let sys = match config.sys {
@@ -257,27 +256,41 @@ pub(crate) unsafe fn init(config: Config) {
});
while RCC.cfgr().read().sws() != config.sys {}
- set_freqs(Clocks {
- sys,
- hclk1: hclk,
- hclk2: hclk,
- hclk3: hclk,
- pclk1,
- pclk2,
- pclk1_tim,
- pclk2_tim,
- rtc,
+ set_clocks!(
+ hsi: hsi,
+ hse: hse,
+ lse: None, // TODO
+ lsi: None, // TODO
+ sys: Some(sys),
+ hclk1: Some(hclk),
+ hclk2: Some(hclk),
+ hclk3: Some(hclk),
+ pclk1: Some(pclk1),
+ pclk2: Some(pclk2),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2_tim: Some(pclk2_tim),
+ rtc: rtc,
pll1_q: pll.q,
- #[cfg(all(rcc_f4, not(stm32f410)))]
- plli2s1_q: _plli2s.q,
- #[cfg(all(rcc_f4, not(stm32f410)))]
- plli2s1_r: _plli2s.r,
- #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
- pllsai1_q: _pllsai.q,
- #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
- pllsai1_r: _pllsai.r,
- });
+ #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
+ plli2s1_p: plli2s.p,
+ #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
+ plli2s1_q: plli2s.q,
+ #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
+ plli2s1_r: plli2s.r,
+
+ #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+ pllsai1_p: pllsai.p,
+ #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+ pllsai1_q: pllsai.q,
+ #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
+ pllsai1_r: pllsai.r,
+
+ clk48: pll.q,
+
+ hsi_hse: None,
+ afif: None,
+ );
}
struct PllInput {
diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
index feaa2f4c0..a6b627887 100644
--- a/embassy-stm32/src/rcc/f0.rs
+++ b/embassy-stm32/src/rcc/f0.rs
@@ -1,6 +1,5 @@
use stm32_metapac::flash::vals::Latency;
-use super::{set_freqs, Clocks};
use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
@@ -160,13 +159,15 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
- set_freqs(Clocks {
- sys: Hertz(real_sysclk),
- pclk1: Hertz(pclk),
- pclk2: Hertz(pclk),
- pclk1_tim: Hertz(pclk * timer_mul),
- pclk2_tim: Hertz(pclk * timer_mul),
- hclk1: Hertz(hclk),
- rtc,
- });
+ set_clocks!(
+ hsi: None,
+ lse: None,
+ sys: Some(Hertz(real_sysclk)),
+ pclk1: Some(Hertz(pclk)),
+ pclk2: Some(Hertz(pclk)),
+ pclk1_tim: Some(Hertz(pclk * timer_mul)),
+ pclk2_tim: Some(Hertz(pclk * timer_mul)),
+ hclk1: Some(Hertz(hclk)),
+ rtc: rtc,
+ );
}
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index 169551e45..7f0adab27 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -1,6 +1,5 @@
use core::convert::TryFrom;
-use super::{set_freqs, Clocks};
use crate::pac::flash::vals::Latency;
use crate::pac::rcc::vals::*;
use crate::pac::{FLASH, RCC};
@@ -179,14 +178,14 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
- set_freqs(Clocks {
- sys: Hertz(real_sysclk),
- pclk1: Hertz(pclk1),
- pclk2: Hertz(pclk2),
- pclk1_tim: Hertz(pclk1 * timer_mul1),
- pclk2_tim: Hertz(pclk2 * timer_mul2),
- hclk1: Hertz(hclk),
+ set_clocks!(
+ sys: Some(Hertz(real_sysclk)),
+ pclk1: Some(Hertz(pclk1)),
+ pclk2: Some(Hertz(pclk2)),
+ pclk1_tim: Some(Hertz(pclk1 * timer_mul1)),
+ pclk2_tim: Some(Hertz(pclk2 * timer_mul2)),
+ hclk1: Some(Hertz(hclk)),
adc: Some(Hertz(adcclk)),
- rtc,
- });
+ rtc: rtc,
+ );
}
diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f3.rs
index bf035fd25..25866e446 100644
--- a/embassy-stm32/src/rcc/f3.rs
+++ b/embassy-stm32/src/rcc/f3.rs
@@ -4,7 +4,6 @@ use crate::pac::flash::vals::Latency;
pub use crate::pac::rcc::vals::Adcpres;
use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -279,13 +278,16 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
- set_freqs(Clocks {
- sys: sysclk,
- pclk1: pclk1,
- pclk2: pclk2,
- pclk1_tim: pclk1 * timer_mul1,
- pclk2_tim: pclk2 * timer_mul2,
- hclk1: hclk,
+ set_clocks!(
+ hsi: None,
+ lse: None,
+ pll1_p: None,
+ sys: Some(sysclk),
+ pclk1: Some(pclk1),
+ pclk2: Some(pclk2),
+ pclk1_tim: Some(pclk1 * timer_mul1),
+ pclk2_tim: Some(pclk2 * timer_mul2),
+ hclk1: Some(hclk),
#[cfg(rcc_f3)]
adc: adc,
#[cfg(all(rcc_f3, adc3_common))]
@@ -294,8 +296,8 @@ pub(crate) unsafe fn init(config: Config) {
adc34: None,
#[cfg(stm32f334)]
hrtim: hrtim,
- rtc,
- });
+ rtc: rtc,
+ );
}
#[inline]
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index b38fe1dcc..e3cd46fb9 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -4,7 +4,6 @@ pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
};
use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -352,11 +351,11 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(not(any(stm32g0b1, stm32g0c1, stm32g0b0)))]
let hsi48_freq: Option<Hertz> = None;
- set_freqs(Clocks {
- sys: sys_clk,
- hclk1: ahb_freq,
- pclk1: apb_freq,
- pclk1_tim: apb_tim_freq,
+ set_clocks!(
+ sys: Some(sys_clk),
+ hclk1: Some(ahb_freq),
+ pclk1: Some(apb_freq),
+ pclk1_tim: Some(apb_tim_freq),
hsi: hsi_freq,
hsi48: hsi48_freq,
hsi_div_8: hsi_div_8_freq,
@@ -365,6 +364,6 @@ pub(crate) unsafe fn init(config: Config) {
lsi: lsi_freq,
pll1_q: pll1_q_freq,
pll1_p: pll1_p_freq,
- rtc,
- });
+ rtc: rtc,
+ );
}
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 891f0490b..3e20bf6af 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -7,7 +7,6 @@ pub use crate::pac::rcc::vals::{
Pllp as PllP, Pllq as PllQ, Pllr as PllR, Ppre as APBPrescaler,
};
use crate::pac::{PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -307,20 +306,20 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
- set_freqs(Clocks {
- sys: sys_clk,
- hclk1: ahb_freq,
- hclk2: ahb_freq,
- hclk3: ahb_freq,
- pclk1: apb1_freq,
- pclk1_tim: apb1_tim_freq,
- pclk2: apb2_freq,
- pclk2_tim: apb2_tim_freq,
+ set_clocks!(
+ sys: Some(sys_clk),
+ hclk1: Some(ahb_freq),
+ hclk2: Some(ahb_freq),
+ hclk3: Some(ahb_freq),
+ pclk1: Some(apb1_freq),
+ pclk1_tim: Some(apb1_tim_freq),
+ pclk2: Some(apb2_freq),
+ pclk2_tim: Some(apb2_tim_freq),
adc: adc12_ck,
adc34: adc345_ck,
pll1_p: None,
pll1_q: None, // TODO
hse: None, // TODO
- rtc,
- });
+ rtc: rtc,
+ );
}
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index dcaf2dced..9ac2115f0 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -12,7 +12,6 @@ pub use crate::pac::rcc::vals::{
};
use crate::pac::rcc::vals::{Ckpersel, Pllrge, Pllvcosel, Timpre};
use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -430,7 +429,7 @@ pub(crate) unsafe fn init(config: Config) {
};
// Configure HSI48.
- let _hsi48 = config.hsi48.map(super::init_hsi48);
+ let hsi48 = config.hsi48.map(super::init_hsi48);
// Configure CSI.
RCC.cr().modify(|w| w.set_csion(config.csi));
@@ -614,45 +613,33 @@ pub(crate) unsafe fn init(config: Config) {
while !pac::SYSCFG.cccsr().read().ready() {}
}
- set_freqs(Clocks {
- sys,
- hclk1: hclk,
- hclk2: hclk,
- hclk3: hclk,
- hclk4: hclk,
- pclk1: apb1,
- pclk2: apb2,
- pclk3: apb3,
+ set_clocks!(
+ sys: Some(sys),
+ hclk1: Some(hclk),
+ hclk2: Some(hclk),
+ hclk3: Some(hclk),
+ hclk4: Some(hclk),
+ pclk1: Some(apb1),
+ pclk2: Some(apb2),
+ pclk3: Some(apb3),
#[cfg(stm32h7)]
- pclk4: apb4,
- #[cfg(stm32h5)]
- pclk4: Hertz(1),
- pclk1_tim: apb1_tim,
- pclk2_tim: apb2_tim,
- adc,
- rtc,
+ pclk4: Some(apb4),
+ pclk1_tim: Some(apb1_tim),
+ pclk2_tim: Some(apb2_tim),
+ adc: adc,
+ rtc: rtc,
- #[cfg(any(stm32h5, stm32h7))]
- hsi: None,
- #[cfg(stm32h5)]
- hsi48: None,
- #[cfg(stm32h5)]
- lsi: None,
- #[cfg(any(stm32h5, stm32h7))]
- csi: None,
+ hsi: hsi,
+ hsi48: hsi48,
+ csi: csi,
+ hse: hse,
- #[cfg(any(stm32h5, stm32h7))]
lse: None,
- #[cfg(any(stm32h5, stm32h7))]
- hse: None,
+ lsi: None,
- #[cfg(any(stm32h5, stm32h7))]
pll1_q: pll1.q,
- #[cfg(any(stm32h5, stm32h7))]
pll2_p: pll2.p,
- #[cfg(any(stm32h5, stm32h7))]
pll2_q: pll2.q,
- #[cfg(any(stm32h5, stm32h7))]
pll2_r: pll2.r,
#[cfg(any(rcc_h5, stm32h7))]
pll3_p: pll3.p,
@@ -670,12 +657,8 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h5)]
audioclk: None,
- #[cfg(any(stm32h5, stm32h7))]
per: None,
-
- #[cfg(stm32h7)]
- rcc_pclk_d3: None,
- });
+ );
}
struct PllInput {
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 257fd83fe..ab1681dd4 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -9,7 +9,6 @@ pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc};
use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -262,7 +261,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(stm32l4, stm32l5, stm32wb))]
let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
- let _pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
+ let pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
let sys_clk = match config.mux {
ClockSrc::HSE => hse.unwrap(),
@@ -274,12 +273,12 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
#[cfg(any(rcc_l0_v2))]
- let _clk48 = match config.clk48_src {
+ let clk48 = match config.clk48_src {
Clk48Src::HSI48 => _hsi48,
Clk48Src::PLL1_VCO_DIV_2 => pll.clk48,
};
#[cfg(any(stm32l4, stm32l5, stm32wb))]
- let _clk48 = match config.clk48_src {
+ let clk48 = match config.clk48_src {
Clk48Src::HSI48 => _hsi48,
Clk48Src::MSI => msi,
Clk48Src::PLLSAI1_Q => pllsai1.q,
@@ -376,37 +375,53 @@ pub(crate) unsafe fn init(config: Config) {
while !RCC.extcfgr().read().c2hpref() {}
}
- set_freqs(Clocks {
- sys: sys_clk,
- hclk1,
+ set_clocks!(
+ sys: Some(sys_clk),
+ hclk1: Some(hclk1),
#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
- hclk2,
+ hclk2: Some(hclk2),
#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
- hclk3,
- pclk1,
- pclk2,
- pclk1_tim,
- pclk2_tim,
+ hclk3: Some(hclk3),
+ pclk1: Some(pclk1),
+ pclk2: Some(pclk2),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2_tim: Some(pclk2_tim),
#[cfg(stm32wl)]
- pclk3: hclk3,
- #[cfg(rcc_l4)]
- hsi: None,
- #[cfg(rcc_l4)]
- lse: None,
- #[cfg(rcc_l4)]
- pllsai1_p: None,
- #[cfg(rcc_l4)]
- pllsai2_p: None,
- #[cfg(rcc_l4)]
- pll1_p: None,
- #[cfg(rcc_l4)]
- pll1_q: None,
- #[cfg(rcc_l4)]
+ pclk3: Some(hclk3),
+ hsi: hsi,
+ hse: hse,
+ msi: msi,
+ #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
+ clk48: clk48,
+
+ #[cfg(not(any(stm32l0, stm32l1)))]
+ pll1_p: pll.p,
+ #[cfg(not(any(stm32l0, stm32l1)))]
+ pll1_q: pll.q,
+ pll1_r: pll.r,
+
+ #[cfg(any(stm32l4, stm32l5, stm32wb))]
+ pllsai1_p: pllsai1.p,
+ #[cfg(any(stm32l4, stm32l5, stm32wb))]
+ pllsai1_q: pllsai1.q,
+ #[cfg(any(stm32l4, stm32l5, stm32wb))]
+ pllsai1_r: pllsai1.r,
+
+ #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
+ pllsai2_p: pllsai2.p,
+ #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
+ pllsai2_q: pllsai2.q,
+ #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
+ pllsai2_r: pllsai2.r,
+
+ rtc: rtc,
+
+ // TODO
sai1_extclk: None,
- #[cfg(rcc_l4)]
sai2_extclk: None,
- rtc,
- });
+ lsi: None,
+ lse: None,
+ );
}
#[cfg(any(stm32l0, stm32l1))]
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 240ffc6d2..280da7ae3 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -5,8 +5,6 @@
use core::mem::MaybeUninit;
-use crate::time::Hertz;
-
mod bd;
mod mco;
pub use bd::*;
@@ -32,162 +30,7 @@ mod _version;
pub use _version::*;
-// Model Clock Configuration
-//
-// pub struct Clocks {
-// hse: Option<Hertz>,
-// hsi: bool,
-// lse: Option<Hertz>,
-// lsi: bool,
-// rtc: RtcSource,
-// }
-
-#[derive(Clone, Copy, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct Clocks {
- pub sys: Hertz,
-
- // APB
- pub pclk1: Hertz,
- pub pclk1_tim: Hertz,
- #[cfg(not(any(rcc_c0, rcc_g0)))]
- pub pclk2: Hertz,
- #[cfg(not(any(rcc_c0, rcc_g0)))]
- pub pclk2_tim: Hertz,
- #[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_u5))]
- pub pclk3: Hertz,
- #[cfg(any(rcc_h7, rcc_h7rm0433, rcc_h7ab, stm32h5))]
- pub pclk4: Hertz,
- #[cfg(any(rcc_wba))]
- pub pclk7: Hertz,
-
- // AHB
- pub hclk1: Hertz,
- #[cfg(any(
- rcc_l4,
- rcc_l4plus,
- rcc_l5,
- rcc_f2,
- rcc_f4,
- rcc_f410,
- rcc_f7,
- rcc_h5,
- rcc_h50,
- rcc_h7,
- rcc_h7rm0433,
- rcc_h7ab,
- rcc_g4,
- rcc_u5,
- rcc_wb,
- rcc_wba,
- rcc_wl5,
- rcc_wle
- ))]
- pub hclk2: Hertz,
- #[cfg(any(
- rcc_l4,
- rcc_l4plus,
- rcc_l5,
- rcc_f2,
- rcc_f4,
- rcc_f410,
- rcc_f7,
- rcc_h5,
- rcc_h50,
- rcc_h7,
- rcc_h7rm0433,
- rcc_h7ab,
- rcc_u5,
- rcc_g4,
- rcc_wb,
- rcc_wl5,
- rcc_wle
- ))]
- pub hclk3: Hertz,
- #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))]
- pub hclk4: Hertz,
-
- #[cfg(all(rcc_f4, not(stm32f410)))]
- pub plli2s1_q: Option<Hertz>,
- #[cfg(all(rcc_f4, not(stm32f410)))]
- pub plli2s1_r: Option<Hertz>,
-
- #[cfg(rcc_l4)]
- pub pllsai1_p: Option<Hertz>,
- #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
- pub pllsai1_q: Option<Hertz>,
- #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
- pub pllsai1_r: Option<Hertz>,
- #[cfg(rcc_l4)]
- pub pllsai2_p: Option<Hertz>,
-
- #[cfg(any(stm32g0, stm32g4, rcc_l4))]
- pub pll1_p: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7, stm32f2, stm32f4, stm32f7, rcc_l4, stm32g0, stm32g4))]
- pub pll1_q: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub pll2_p: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub pll2_q: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub pll2_r: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub pll3_p: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub pll3_q: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub pll3_r: Option<Hertz>,
-
- #[cfg(any(
- rcc_f1,
- rcc_f100,
- rcc_f1cl,
- rcc_h5,
- rcc_h50,
- rcc_h7,
- rcc_h7rm0433,
- rcc_h7ab,
- rcc_f3,
- rcc_g4
- ))]
- pub adc: Option<Hertz>,
-
- #[cfg(any(rcc_f3, rcc_g4))]
- pub adc34: Option<Hertz>,
-
- #[cfg(stm32f334)]
- pub hrtim: Option<Hertz>,
-
- pub rtc: Option<Hertz>,
-
- #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
- pub hsi: Option<Hertz>,
- #[cfg(any(stm32h5, stm32g0))]
- pub hsi48: Option<Hertz>,
- #[cfg(stm32g0)]
- pub hsi_div_8: Option<Hertz>,
- #[cfg(any(stm32g0, stm32h5))]
- pub lsi: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub csi: Option<Hertz>,
-
- #[cfg(any(stm32h5, stm32h7, rcc_l4, rcc_c0, stm32g0))]
- pub lse: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7, stm32g0, stm32g4))]
- pub hse: Option<Hertz>,
-
- #[cfg(stm32h5)]
- pub audioclk: Option<Hertz>,
- #[cfg(any(stm32h5, stm32h7))]
- pub per: Option<Hertz>,
-
- #[cfg(stm32h7)]
- pub rcc_pclk_d3: Option<Hertz>,
- #[cfg(rcc_l4)]
- pub sai1_extclk: Option<Hertz>,
- #[cfg(rcc_l4)]
- pub sai2_extclk: Option<Hertz>,
-}
+pub use crate::_generated::Clocks;
#[cfg(feature = "low-power")]
/// Must be written within a critical section
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index dff08dc9b..9cec6c96c 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -1,7 +1,6 @@
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange, Plldiv, Pllm, Plln, Ppre as APBPrescaler};
use crate::pac::rcc::vals::{Msirgsel, Pllmboost, Pllrge, Pllsrc, Sw};
use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -338,7 +337,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- let _hsi48 = config.hsi48.map(super::init_hsi48);
+ let hsi48 = config.hsi48.map(super::init_hsi48);
// The clock source is ready
// Calculate and set the flash wait states
@@ -448,18 +447,37 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
- set_freqs(Clocks {
- sys: sys_clk,
- hclk1: ahb_freq,
- hclk2: ahb_freq,
- hclk3: ahb_freq,
- pclk1: apb1_freq,
- pclk2: apb2_freq,
- pclk3: apb3_freq,
- pclk1_tim: apb1_tim_freq,
- pclk2_tim: apb2_tim_freq,
- rtc,
- });
+ set_clocks!(
+ sys: Some(sys_clk),
+ hclk1: Some(ahb_freq),
+ hclk2: Some(ahb_freq),
+ hclk3: Some(ahb_freq),
+ pclk1: Some(apb1_freq),
+ pclk2: Some(apb2_freq),
+ pclk3: Some(apb3_freq),
+ pclk1_tim: Some(apb1_tim_freq),
+ pclk2_tim: Some(apb2_tim_freq),
+ hsi48: hsi48,
+ rtc: rtc,
+
+ // TODO
+ hse: None,
+ hsi: None,
+ audioclk: None,
+ hsi48_div_2: None,
+ lse: None,
+ lsi: None,
+ msik: None,
+ pll1_p: None,
+ pll1_q: None,
+ pll1_r: None,
+ pll2_p: None,
+ pll2_q: None,
+ pll2_r: None,
+ pll3_p: None,
+ pll3_q: None,
+ pll3_r: None,
+ );
}
fn msirange_to_hertz(range: Msirange) -> Hertz {
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index dfa236484..47ce4783c 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -4,7 +4,6 @@ pub use crate::pac::rcc::vals::{
Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc,
};
use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
@@ -155,16 +154,23 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr3().modify(|w| w.set_adcsel(config.adc_clock_source));
- set_freqs(Clocks {
- sys: sys_clk,
- hclk1,
- hclk2,
- hclk4,
- pclk1,
- pclk2,
- pclk7,
- pclk1_tim,
- pclk2_tim,
- rtc,
- });
+ set_clocks!(
+ sys: Some(sys_clk),
+ hclk1: Some(hclk1),
+ hclk2: Some(hclk2),
+ hclk4: Some(hclk4),
+ pclk1: Some(pclk1),
+ pclk2: Some(pclk2),
+ pclk7: Some(pclk7),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2_tim: Some(pclk2_tim),
+ rtc: rtc,
+ hse: hse,
+ hsi: hsi,
+
+ // TODO
+ lse: None,
+ lsi: None,
+ pll1_q: None,
+ );
}
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index debe26c88..61589a215 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -670,7 +670,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
_ => panic!("Invalid Bus Width"),
};
- let ker_ck = T::kernel_clk();
+ let ker_ck = T::frequency();
let (_bypass, clkdiv, new_clock) = clk_div(ker_ck, freq)?;
// Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7
@@ -1023,7 +1023,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
/// specified frequency.
pub async fn init_card(&mut self, freq: Hertz) -> Result<(), Error> {
let regs = T::regs();
- let ker_ck = T::kernel_clk();
+ let ker_ck = T::frequency();
let bus_width = match self.d3.is_some() {
true => BusWidth::Four,
@@ -1429,7 +1429,6 @@ pub(crate) mod sealed {
fn regs() -> RegBlock;
fn state() -> &'static AtomicWaker;
- fn kernel_clk() -> Hertz;
}
pub trait Pins<T: Instance> {}
@@ -1461,61 +1460,6 @@ pub trait SdmmcDma<T: Instance> {}
#[cfg(sdmmc_v2)]
impl<T: Instance> SdmmcDma<T> for NoDma {}
-cfg_if::cfg_if! {
- // TODO, these could not be implemented, because required clocks are not exposed in RCC:
- // - H7 uses pll1_q_ck or pll2_r_ck depending on SDMMCSEL
- // - L1 uses pll48
- // - L4 uses clk48(pll48)
- // - L4+, L5, U5 uses clk48(pll48) or PLLSAI3CLK(PLLP) depending on SDMMCSEL
- if #[cfg(stm32f1)] {
- // F1 uses AHB1(HCLK), which is correct in PAC
- macro_rules! kernel_clk {
- ($inst:ident) => {
- <peripherals::$inst as crate::rcc::sealed::RccPeripheral>::frequency()
- }
- }
- } else if #[cfg(any(stm32f2, stm32f4))] {
- // F2, F4 always use pll48
- macro_rules! kernel_clk {
- ($inst:ident) => {
- critical_section::with(|_| unsafe {
- unwrap!(crate::rcc::get_freqs().pll1_q)
- })
- }
- }
- } else if #[cfg(stm32f7)] {
- macro_rules! kernel_clk {
- (SDMMC1) => {
- critical_section::with(|_| unsafe {
- let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc1sel();
- if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
- crate::rcc::get_freqs().sys
- } else {
- unwrap!(crate::rcc::get_freqs().pll1_q)
- }
- })
- };
- (SDMMC2) => {
- critical_section::with(|_| unsafe {
- let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc2sel();
- if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
- crate::rcc::get_freqs().sys
- } else {
- unwrap!(crate::rcc::get_freqs().pll1_q)
- }
- })
- };
- }
- } else {
- // Use default peripheral clock and hope it works
- macro_rules! kernel_clk {
- ($inst:ident) => {
- <peripherals::$inst as crate::rcc::sealed::RccPeripheral>::frequency()
- }
- }
- }
-}
-
foreach_peripheral!(
(sdmmc, $inst:ident) => {
impl sealed::Instance for peripherals::$inst {
@@ -1529,10 +1473,6 @@ foreach_peripheral!(
static WAKER: ::embassy_sync::waitqueue::AtomicWaker = ::embassy_sync::waitqueue::AtomicWaker::new();
&WAKER
}
-
- fn kernel_clk() -> Hertz {
- kernel_clk!($inst)
- }
}
impl Instance for peripherals::$inst {}
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index f39915906..34d6b52fd 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -280,7 +280,7 @@ impl<'d, T: Instance> Driver<'d, T> {
#[cfg(time)]
embassy_time::block_for(embassy_time::Duration::from_millis(100));
#[cfg(not(time))]
- cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.0 / 10);
+ cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.unwrap().0 / 10);
#[cfg(not(usb_v4))]
regs.btable().write(|w| w.set_btable(0));
From 4650a3566161ece4a743948129112402b9bb6e48 Mon Sep 17 00:00:00 2001
From: Matous Hybl <hyblmatous@gmail.com>
Date: Sat, 3 Feb 2024 09:41:14 +0100
Subject: [PATCH 114/392] docs: Embassy in the wild - add air quality
monitoring system
---
docs/modules/ROOT/pages/embassy_in_the_wild.adoc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/docs/modules/ROOT/pages/embassy_in_the_wild.adoc b/docs/modules/ROOT/pages/embassy_in_the_wild.adoc
index a1c31bfc7..dfe9fd6e3 100644
--- a/docs/modules/ROOT/pages/embassy_in_the_wild.adoc
+++ b/docs/modules/ROOT/pages/embassy_in_the_wild.adoc
@@ -7,3 +7,5 @@ Here are known examples of real-world projects which make use of Embassy. Feel f
* link:https://github.com/card-io-ecg/card-io-fw[Card/IO firmware] - firmware for an open source ECG device
** Targets the ESP32-S3 or ESP32-C6 MCU
* The link:https://github.com/lora-rs/lora-rs[lora-rs] project includes link:https://github.com/lora-rs/lora-rs/tree/main/examples/stm32l0/src/bin[various standalone examples] for NRF52840, RP2040, STM32L0 and STM32WL
+** link:https://github.com/matoushybl/air-force-one[Air force one: A simple air quality monitoring system]
+* Targets nRF52 and uses nrf-softdevice
From b9d0069671b33107e35af6bdaa662e9c7be8e3f9 Mon Sep 17 00:00:00 2001
From: Stefan Gehr <stefan@gehr.xyz>
Date: Sat, 3 Feb 2024 14:56:31 +0100
Subject: [PATCH 115/392] correct spelling of the word "receive"
---
embassy-net/src/tcp.rs | 4 ++--
embassy-stm32/src/eth/v2/descriptors.rs | 2 +-
embassy-sync/src/priority_channel.rs | 2 +-
examples/rp/src/bin/i2c_slave.rs | 6 +++---
tests/rp/src/bin/i2c.rs | 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/embassy-net/src/tcp.rs b/embassy-net/src/tcp.rs
index 72b0677b4..c508ff97a 100644
--- a/embassy-net/src/tcp.rs
+++ b/embassy-net/src/tcp.rs
@@ -342,7 +342,7 @@ impl<'a> TcpSocket<'a> {
self.io.with(|s, _| s.may_send())
}
- /// return whether the recieve half of the full-duplex connection is open.
+ /// return whether the receive half of the full-duplex connection is open.
/// This function returns true if it’s possible to receive data from the remote endpoint.
/// It will return true while there is data in the receive buffer, and if there isn’t,
/// as long as the remote endpoint has not closed the connection.
@@ -471,7 +471,7 @@ impl<'d> TcpIo<'d> {
s.register_recv_waker(cx.waker());
Poll::Pending
} else {
- // if we can't receive because the recieve half of the duplex connection is closed then return an error
+ // if we can't receive because the receive half of the duplex connection is closed then return an error
Poll::Ready(Err(Error::ConnectionReset))
}
} else {
diff --git a/embassy-stm32/src/eth/v2/descriptors.rs b/embassy-stm32/src/eth/v2/descriptors.rs
index 01ea8e574..645bfdb14 100644
--- a/embassy-stm32/src/eth/v2/descriptors.rs
+++ b/embassy-stm32/src/eth/v2/descriptors.rs
@@ -129,7 +129,7 @@ impl<'a> TDesRing<'a> {
/// Receive Descriptor representation
///
-/// * rdes0: recieve buffer address
+/// * rdes0: receive buffer address
/// * rdes1:
/// * rdes2:
/// * rdes3: OWN and Status
diff --git a/embassy-sync/src/priority_channel.rs b/embassy-sync/src/priority_channel.rs
index bd75c0135..e77678c24 100644
--- a/embassy-sync/src/priority_channel.rs
+++ b/embassy-sync/src/priority_channel.rs
@@ -325,7 +325,7 @@ where
///
/// Sent data may be reordered based on their priorty within the channel.
/// For example, in a [`Max`](heapless::binary_heap::Max) [`PriorityChannel`]
-/// containing `u32`'s, data sent in the following order `[1, 2, 3]` will be recieved as `[3, 2, 1]`.
+/// containing `u32`'s, data sent in the following order `[1, 2, 3]` will be received as `[3, 2, 1]`.
pub struct PriorityChannel<M, T, K, const N: usize>
where
T: Ord,
diff --git a/examples/rp/src/bin/i2c_slave.rs b/examples/rp/src/bin/i2c_slave.rs
index 479f9a16a..ac470d2be 100644
--- a/examples/rp/src/bin/i2c_slave.rs
+++ b/examples/rp/src/bin/i2c_slave.rs
@@ -26,7 +26,7 @@ async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
loop {
let mut buf = [0u8; 128];
match dev.listen(&mut buf).await {
- Ok(i2c_slave::Command::GeneralCall(len)) => info!("Device recieved general call write: {}", buf[..len]),
+ Ok(i2c_slave::Command::GeneralCall(len)) => info!("Device received general call write: {}", buf[..len]),
Ok(i2c_slave::Command::Read) => loop {
match dev.respond_to_read(&[state]).await {
Ok(x) => match x {
@@ -40,9 +40,9 @@ async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
Err(e) => error!("error while responding {}", e),
}
},
- Ok(i2c_slave::Command::Write(len)) => info!("Device recieved write: {}", buf[..len]),
+ Ok(i2c_slave::Command::Write(len)) => info!("Device received write: {}", buf[..len]),
Ok(i2c_slave::Command::WriteRead(len)) => {
- info!("device recieved write read: {:x}", buf[..len]);
+ info!("device received write read: {:x}", buf[..len]);
match buf[0] {
// Set the state
0xC2 => {
diff --git a/tests/rp/src/bin/i2c.rs b/tests/rp/src/bin/i2c.rs
index 77d628cf6..a0aed1a42 100644
--- a/tests/rp/src/bin/i2c.rs
+++ b/tests/rp/src/bin/i2c.rs
@@ -80,7 +80,7 @@ async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
_ => panic!("Invalid write length {}", len),
},
Ok(i2c_slave::Command::WriteRead(len)) => {
- info!("device recieved write read: {:x}", buf[..len]);
+ info!("device received write read: {:x}", buf[..len]);
match buf[0] {
0xC2 => {
let resp_buff = [0xD1, 0xD2, 0xD3, 0xD4];
From 72bbfec39d3f826c1a8dd485af2da4bcbdd32e35 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sat, 3 Feb 2024 16:10:00 -0500
Subject: [PATCH 116/392] Added hash DMA implementation.
---
embassy-stm32/build.rs | 1 +
embassy-stm32/src/hash/mod.rs | 143 ++++++++++++++-----------------
examples/stm32f7/src/bin/hash.rs | 20 +++--
3 files changed, 79 insertions(+), 85 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 948ce3aff..1a68dfc9d 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -1015,6 +1015,7 @@ fn main() {
(("dac", "CH1"), quote!(crate::dac::DacDma1)),
(("dac", "CH2"), quote!(crate::dac::DacDma2)),
(("timer", "UP"), quote!(crate::timer::UpDma)),
+ (("hash", "IN"), quote!(crate::hash::Dma)),
]
.into();
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 4e37e60e1..ac4854f80 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -2,11 +2,13 @@
use core::cmp::min;
use core::future::poll_fn;
use core::marker::PhantomData;
+use core::ptr;
use core::task::Poll;
use embassy_hal_internal::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
+use crate::dma::Transfer;
use crate::peripherals::HASH;
use stm32_metapac::hash::regs::*;
@@ -18,7 +20,6 @@ use crate::{interrupt, pac, peripherals, Peripheral};
const NUM_CONTEXT_REGS: usize = 51;
#[cfg(hash_v2)]
const NUM_CONTEXT_REGS: usize = 54;
-const HASH_BUFFER_LEN: usize = 68;
const DIGEST_BLOCK_SIZE: usize = 64;
static HASH_WAKER: AtomicWaker = AtomicWaker::new();
@@ -74,8 +75,7 @@ pub enum DataType {
/// Stores the state of the HASH peripheral for suspending/resuming
/// digest calculation.
pub struct Context {
- first_word_sent: bool,
- buffer: [u8; HASH_BUFFER_LEN],
+ buffer: [u8; DIGEST_BLOCK_SIZE],
buflen: usize,
algo: Algorithm,
format: DataType,
@@ -86,17 +86,19 @@ pub struct Context {
}
/// HASH driver.
-pub struct Hash<'d, T: Instance> {
+pub struct Hash<'d, T: Instance, D: Dma<T>> {
_peripheral: PeripheralRef<'d, T>,
+ dma: PeripheralRef<'d, D>,
}
-impl<'d, T: Instance> Hash<'d, T> {
+impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
/// Instantiates, resets, and enables the HASH peripheral.
- pub fn new(peripheral: impl Peripheral<P = T> + 'd) -> Self {
+ pub fn new(peripheral: impl Peripheral<P = T> + 'd, dma: impl Peripheral<P = D> + 'd) -> Self {
HASH::enable_and_reset();
- into_ref!(peripheral);
+ into_ref!(peripheral, dma);
let instance = Self {
_peripheral: peripheral,
+ dma: dma,
};
T::Interrupt::unpend();
@@ -109,8 +111,7 @@ impl<'d, T: Instance> Hash<'d, T> {
pub async fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
// Define a context for this new computation.
let mut ctx = Context {
- first_word_sent: false,
- buffer: [0; 68],
+ buffer: [0; DIGEST_BLOCK_SIZE],
buflen: 0,
algo: algorithm,
format: format,
@@ -134,6 +135,11 @@ impl<'d, T: Instance> Hash<'d, T> {
}
T::regs().cr().modify(|w| w.set_algo0(algo0));
T::regs().cr().modify(|w| w.set_algo1(algo1));
+
+ // Enable multiple DMA transfers.
+ T::regs().cr().modify(|w| w.set_mdmat(true));
+
+ // Set init to load the context registers. Necessary before storing context.
T::regs().cr().modify(|w| w.set_init(true));
// Store and return the state of the peripheral.
@@ -145,8 +151,8 @@ impl<'d, T: Instance> Hash<'d, T> {
/// then updates the state with the provided data.
/// Peripheral state is saved upon return.
pub async fn update(&mut self, ctx: &mut Context, input: &[u8]) {
- let mut data_waiting = input.len() + ctx.buflen;
- if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
+ let data_waiting = input.len() + ctx.buflen;
+ if data_waiting < DIGEST_BLOCK_SIZE {
// There isn't enough data to digest a block, so append it to the buffer.
ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
ctx.buflen += input.len();
@@ -159,65 +165,35 @@ impl<'d, T: Instance> Hash<'d, T> {
let mut ilen_remaining = input.len();
let mut input_start = 0;
- // Handle first block.
- if !ctx.first_word_sent {
- let empty_len = ctx.buffer.len() - ctx.buflen;
+ // First ingest the data in the buffer.
+ let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
+ if empty_len > 0 {
let copy_len = min(empty_len, ilen_remaining);
- // Fill the buffer.
- if copy_len > 0 {
- ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[0..copy_len]);
- ctx.buflen += copy_len;
- ilen_remaining -= copy_len;
- input_start += copy_len;
- }
- assert_eq!(ctx.buflen, HASH_BUFFER_LEN);
- self.accumulate(ctx.buffer.as_slice());
- data_waiting -= ctx.buflen;
- ctx.buflen = 0;
- ctx.first_word_sent = true;
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[input_start..input_start + copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
}
+ self.accumulate(&ctx.buffer).await;
+ ctx.buflen = 0;
- if data_waiting < 64 {
- // There isn't enough data remaining to process another block, so store it.
- assert_eq!(ctx.buflen, 0);
- ctx.buffer[0..ilen_remaining].copy_from_slice(&input[input_start..input_start + ilen_remaining]);
- ctx.buflen += ilen_remaining;
+ // Move any extra data to the now-empty buffer.
+ let leftovers = ilen_remaining % DIGEST_BLOCK_SIZE;
+ if leftovers > 0 {
+ assert!(ilen_remaining >= leftovers);
+ ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
+ ctx.buflen += leftovers;
+ ilen_remaining -= leftovers;
} else {
- let mut total_data_sent = 0;
-
- // First ingest the data in the buffer.
- let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
- if empty_len > 0 {
- let copy_len = min(empty_len, ilen_remaining);
- ctx.buffer[ctx.buflen..ctx.buflen + copy_len]
- .copy_from_slice(&input[input_start..input_start + copy_len]);
- ctx.buflen += copy_len;
- ilen_remaining -= copy_len;
- input_start += copy_len;
- }
- assert_eq!(ctx.buflen % 64, 0);
- self.accumulate(&ctx.buffer[0..64]);
- total_data_sent += ctx.buflen;
- ctx.buflen = 0;
-
- // Move any extra data to the now-empty buffer.
- let leftovers = ilen_remaining % 64;
- if leftovers > 0 {
- assert!(ilen_remaining >= leftovers);
- ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
- ctx.buflen += leftovers;
- ilen_remaining -= leftovers;
- }
- assert_eq!(ilen_remaining % 64, 0);
-
- // Hash the remaining data.
- self.accumulate(&input[input_start..input_start + ilen_remaining]);
-
- total_data_sent += ilen_remaining;
- assert_eq!(total_data_sent % 64, 0);
- assert!(total_data_sent >= 64);
+ ctx.buffer
+ .copy_from_slice(&input[input.len() - DIGEST_BLOCK_SIZE..input.len()]);
+ ctx.buflen += DIGEST_BLOCK_SIZE;
+ ilen_remaining -= DIGEST_BLOCK_SIZE;
}
+ // Hash the remaining data.
+ self.accumulate(&input[input_start..input_start + ilen_remaining]).await;
+
// Save the peripheral context.
self.store_context(ctx).await;
}
@@ -228,12 +204,12 @@ impl<'d, T: Instance> Hash<'d, T> {
// Restore the peripheral state.
self.load_context(&ctx);
- // Hash the leftover bytes, if any.
- self.accumulate(&ctx.buffer[0..ctx.buflen]);
- ctx.buflen = 0;
+ // Must be cleared prior to the last DMA transfer.
+ T::regs().cr().modify(|w| w.set_mdmat(false));
- //Start the digest calculation.
- T::regs().str().write(|w| w.set_dcal(true));
+ // Hash the leftover bytes, if any.
+ self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
+ ctx.buflen = 0;
// Wait for completion.
poll_fn(|cx| {
@@ -272,19 +248,30 @@ impl<'d, T: Instance> Hash<'d, T> {
}
/// Push data into the hash core.
- fn accumulate(&mut self, input: &[u8]) {
+ async fn accumulate(&mut self, input: &[u8]) {
+ // Ignore an input length of 0.
+ if input.len() == 0 {
+ return;
+ }
+
// Set the number of valid bits.
let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
- let mut i = 0;
- while i < input.len() {
- let mut word: [u8; 4] = [0; 4];
- let copy_idx = min(i + 4, input.len());
- word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
- T::regs().din().write_value(u32::from_ne_bytes(word));
- i += 4;
+ // Configure DMA to transfer input to hash core.
+ let dma_request = self.dma.request();
+ let dst_ptr = T::regs().din().as_ptr();
+ let mut num_words = input.len() / 4;
+ if input.len() % 4 > 0 {
+ num_words += 1;
}
+ let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
+ let dma_transfer =
+ unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) };
+ T::regs().cr().modify(|w| w.set_dmae(true));
+
+ // Wait for the transfer to complete.
+ dma_transfer.await;
}
/// Save the peripheral state to a context.
@@ -361,3 +348,5 @@ foreach_interrupt!(
}
};
);
+
+dma_trait!(Dma, Instance);
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index 1fd0e87eb..a9f5aa197 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -4,27 +4,30 @@
use defmt::info;
use embassy_executor::Spawner;
use embassy_stm32::Config;
-use embassy_time::{Duration, Instant};
+use embassy_time::Instant;
use {defmt_rtt as _, panic_probe as _};
use embassy_stm32::hash::*;
use sha2::{Digest, Sha256};
-const TEST_STRING_1: &[u8] = b"hello world";
-
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
let config = Config::default();
let p = embassy_stm32::init(config);
+ let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
+ let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
+
+ let mut hw_hasher = Hash::new(p.HASH, p.DMA2_CH7);
+
let hw_start_time = Instant::now();
// Compute a digest in hardware.
- let mut hw_hasher = Hash::new(p.HASH);
- let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
- hw_hasher.update(&mut context, TEST_STRING_1);
+ let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
+ hw_hasher.update(&mut context, test_1).await;
+ hw_hasher.update(&mut context, test_2).await;
let mut buffer: [u8; 32] = [0; 32];
- let hw_digest = hw_hasher.finish(context, &mut buffer);
+ let hw_digest = hw_hasher.finish(context, &mut buffer).await;
let hw_end_time = Instant::now();
let hw_execution_time = hw_end_time - hw_start_time;
@@ -33,7 +36,8 @@ async fn main(_spawner: Spawner) -> ! {
// Compute a digest in software.
let mut sw_hasher = Sha256::new();
- sw_hasher.update(TEST_STRING_1);
+ sw_hasher.update(test_1);
+ sw_hasher.update(test_2);
let sw_digest = sw_hasher.finalize();
let sw_end_time = Instant::now();
From 87a52f5eadbff91ff4fe2df807aa4e7bb3b29d79 Mon Sep 17 00:00:00 2001
From: Grant Miller <GrantM11235@gmail.com>
Date: Sat, 3 Feb 2024 17:04:20 -0600
Subject: [PATCH 117/392] stm32/usart: Add doc links to buffered uarts
---
embassy-stm32/src/usart/buffered.rs | 4 ++++
embassy-stm32/src/usart/ringbuffered.rs | 2 ++
2 files changed, 6 insertions(+)
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index c78752883..c11e3382f 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -140,11 +140,15 @@ pub struct BufferedUart<'d, T: BasicInstance> {
}
/// Tx-only buffered UART
+///
+/// Created with [BufferedUart::split]
pub struct BufferedUartTx<'d, T: BasicInstance> {
phantom: PhantomData<&'d mut T>,
}
/// Rx-only buffered UART
+///
+/// Created with [BufferedUart::split]
pub struct BufferedUartRx<'d, T: BasicInstance> {
phantom: PhantomData<&'d mut T>,
}
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 4391bfef7..a0ab060a3 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -12,6 +12,8 @@ use crate::dma::ReadableRingBuffer;
use crate::usart::{Regs, Sr};
/// Rx-only Ring-buffered UART Driver
+///
+/// Created with [UartRx::into_ring_buffered]
pub struct RingBufferedUartRx<'d, T: BasicInstance, RxDma: super::RxDma<T>> {
_peri: PeripheralRef<'d, T>,
ring_buf: ReadableRingBuffer<'d, RxDma, u8>,
From d5d86b866fd5ceb8081cbfcce832be4c68b82691 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sun, 4 Feb 2024 21:36:19 +0100
Subject: [PATCH 118/392] nrf/gpiote: add support for nrf51.
---
ci.sh | 1 +
embassy-nrf/src/gpiote.rs | 56 +++++++++++++++++++++++++-------
examples/nrf51/Cargo.toml | 2 +-
tests/nrf51422/Cargo.toml | 3 +-
tests/nrf51422/src/bin/gpiote.rs | 47 +++++++++++++++++++++++++++
5 files changed, 95 insertions(+), 14 deletions(-)
create mode 100644 tests/nrf51422/src/bin/gpiote.rs
diff --git a/ci.sh b/ci.sh
index 6a5e6e3f5..ba250fa67 100755
--- a/ci.sh
+++ b/ci.sh
@@ -47,6 +47,7 @@ cargo batch \
--- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip \
--- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip,medium-ethernet \
--- build --release --manifest-path embassy-net/Cargo.toml --target thumbv7em-none-eabi --features defmt,tcp,udp,dns,proto-ipv4,proto-ipv6,medium-ip,medium-ethernet,medium-ieee802154 \
+ --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv6m-none-eabi --features nrf51,gpiote,time,time-driver-rtc1 \
--- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52805,gpiote,time,time-driver-rtc1 \
--- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52810,gpiote,time,time-driver-rtc1 \
--- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52811,gpiote,time,time-driver-rtc1 \
diff --git a/embassy-nrf/src/gpiote.rs b/embassy-nrf/src/gpiote.rs
index a459446a2..12f4ed0a0 100644
--- a/embassy-nrf/src/gpiote.rs
+++ b/embassy-nrf/src/gpiote.rs
@@ -13,6 +13,10 @@ use crate::interrupt::InterruptExt;
use crate::ppi::{Event, Task};
use crate::{interrupt, pac, peripherals};
+#[cfg(feature = "nrf51")]
+/// Amount of GPIOTE channels in the chip.
+const CHANNEL_COUNT: usize = 4;
+#[cfg(not(feature = "_nrf51"))]
/// Amount of GPIOTE channels in the chip.
const CHANNEL_COUNT: usize = 8;
@@ -61,16 +65,20 @@ fn regs() -> &'static pac::gpiote::RegisterBlock {
}
pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
- #[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
- let ports = unsafe { &[&*pac::P0::ptr(), &*pac::P1::ptr()] };
- #[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
- let ports = unsafe { &[&*pac::P0::ptr()] };
+ // no latched GPIO detect in nrf51.
+ #[cfg(not(feature = "_nrf51"))]
+ {
+ #[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
+ let ports = unsafe { &[&*pac::P0::ptr(), &*pac::P1::ptr()] };
+ #[cfg(not(any(feature = "_nrf51", feature = "nrf52833", feature = "nrf52840")))]
+ let ports = unsafe { &[&*pac::P0::ptr()] };
- for &p in ports {
- // Enable latched detection
- p.detectmode.write(|w| w.detectmode().ldetect());
- // Clear latch
- p.latch.write(|w| unsafe { w.bits(0xFFFFFFFF) })
+ for &p in ports {
+ // Enable latched detection
+ p.detectmode.write(|w| w.detectmode().ldetect());
+ // Clear latch
+ p.latch.write(|w| unsafe { w.bits(0xFFFFFFFF) })
+ }
}
// Enable interrupts
@@ -78,7 +86,7 @@ pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
let irq = interrupt::GPIOTE0;
#[cfg(any(feature = "nrf5340-app-ns", feature = "nrf9160-ns"))]
let irq = interrupt::GPIOTE1;
- #[cfg(any(feature = "_nrf52", feature = "nrf5340-net"))]
+ #[cfg(any(feature = "_nrf51", feature = "_nrf52", feature = "nrf5340-net"))]
let irq = interrupt::GPIOTE;
irq.unpend();
@@ -103,7 +111,7 @@ fn GPIOTE1() {
unsafe { handle_gpiote_interrupt() };
}
-#[cfg(any(feature = "_nrf52", feature = "nrf5340-net"))]
+#[cfg(any(feature = "_nrf51", feature = "_nrf52", feature = "nrf5340-net"))]
#[cfg(feature = "rt")]
#[interrupt]
fn GPIOTE() {
@@ -125,9 +133,29 @@ unsafe fn handle_gpiote_interrupt() {
#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
let ports = &[&*pac::P0::ptr(), &*pac::P1::ptr()];
- #[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
+ #[cfg(not(any(feature = "_nrf51", feature = "nrf52833", feature = "nrf52840")))]
let ports = &[&*pac::P0::ptr()];
+ #[cfg(feature = "_nrf51")]
+ let ports = unsafe { &[&*pac::GPIO::ptr()] };
+ #[cfg(feature = "_nrf51")]
+ for (port, &p) in ports.iter().enumerate() {
+ let inp = p.in_.read().bits();
+ for pin in 0..32 {
+ let fired = match p.pin_cnf[pin as usize].read().sense().variant() {
+ Some(pac::gpio::pin_cnf::SENSE_A::HIGH) => inp & (1 << pin) != 0,
+ Some(pac::gpio::pin_cnf::SENSE_A::LOW) => inp & (1 << pin) == 0,
+ _ => false,
+ };
+
+ if fired {
+ PORT_WAKERS[port * 32 + pin as usize].wake();
+ p.pin_cnf[pin as usize].modify(|_, w| w.sense().disabled());
+ }
+ }
+ }
+
+ #[cfg(not(feature = "_nrf51"))]
for (port, &p) in ports.iter().enumerate() {
let bits = p.latch.read().bits();
for pin in BitIter(bits) {
@@ -476,9 +504,13 @@ impl_channel!(GPIOTE_CH0, 0);
impl_channel!(GPIOTE_CH1, 1);
impl_channel!(GPIOTE_CH2, 2);
impl_channel!(GPIOTE_CH3, 3);
+#[cfg(not(feature = "nrf51"))]
impl_channel!(GPIOTE_CH4, 4);
+#[cfg(not(feature = "nrf51"))]
impl_channel!(GPIOTE_CH5, 5);
+#[cfg(not(feature = "nrf51"))]
impl_channel!(GPIOTE_CH6, 6);
+#[cfg(not(feature = "nrf51"))]
impl_channel!(GPIOTE_CH7, 7);
// ====================
diff --git a/examples/nrf51/Cargo.toml b/examples/nrf51/Cargo.toml
index d1e919a33..06c3d20cb 100644
--- a/examples/nrf51/Cargo.toml
+++ b/examples/nrf51/Cargo.toml
@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
[dependencies]
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-4096", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
+embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "gpiote", "time-driver-rtc1", "unstable-pac", "time", "rt"] }
defmt = "0.3"
defmt-rtt = "0.4"
diff --git a/tests/nrf51422/Cargo.toml b/tests/nrf51422/Cargo.toml
index 2cab20ac0..07236987b 100644
--- a/tests/nrf51422/Cargo.toml
+++ b/tests/nrf51422/Cargo.toml
@@ -7,10 +7,11 @@ license = "MIT OR Apache-2.0"
[dependencies]
teleprobe-meta = "1"
+embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt", ] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "task-arena-size-128", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac", "time"] }
+embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf51", "time-driver-rtc1", "unstable-pac", "time", "gpiote"] }
embedded-io-async = { version = "0.6.1", features = ["defmt-03"] }
embedded-hal-async = { version = "1.0" }
diff --git a/tests/nrf51422/src/bin/gpiote.rs b/tests/nrf51422/src/bin/gpiote.rs
new file mode 100644
index 000000000..330fe993e
--- /dev/null
+++ b/tests/nrf51422/src/bin/gpiote.rs
@@ -0,0 +1,47 @@
+#![no_std]
+#![no_main]
+teleprobe_meta::target!(b"nrf51-dk");
+
+use defmt::{assert, info};
+use embassy_executor::Spawner;
+use embassy_futures::join::join;
+use embassy_nrf::gpio::{Input, Level, Output, OutputDrive, Pull};
+use embassy_time::{Duration, Instant, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p = embassy_nrf::init(Default::default());
+
+ let mut input = Input::new(p.P0_13, Pull::Up);
+ let mut output = Output::new(p.P0_14, Level::Low, OutputDrive::Standard);
+
+ let fut1 = async {
+ Timer::after_millis(100).await;
+ output.set_high();
+ };
+ let fut2 = async {
+ let start = Instant::now();
+ input.wait_for_high().await;
+ let dur = Instant::now() - start;
+ assert!((Duration::from_millis(90)..Duration::from_millis(110)).contains(&dur));
+ };
+
+ join(fut1, fut2).await;
+
+ let fut1 = async {
+ Timer::after_millis(100).await;
+ output.set_low();
+ };
+ let fut2 = async {
+ let start = Instant::now();
+ input.wait_for_low().await;
+ let dur = Instant::now() - start;
+ assert!((Duration::from_millis(90)..Duration::from_millis(110)).contains(&dur));
+ };
+
+ join(fut1, fut2).await;
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
From e3fe08428f3728e8273fcb184776a762955bb376 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sun, 4 Feb 2024 22:07:17 +0100
Subject: [PATCH 119/392] stm32/rcc: fix build for some f0 and l4 chips.
Fixes #2531
---
ci.sh | 2 ++
embassy-stm32/src/rcc/f0.rs | 32 +++++++++++++++++++++++++++-----
embassy-stm32/src/rcc/l.rs | 19 ++++++++++++-------
3 files changed, 41 insertions(+), 12 deletions(-)
diff --git a/ci.sh b/ci.sh
index 6a5e6e3f5..aa0d98d34 100755
--- a/ci.sh
+++ b/ci.sh
@@ -84,6 +84,7 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f405zg,defmt,exti,time-driver-any \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f407zg,defmt,exti,time-driver-any \
@@ -110,6 +111,7 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi-cm7,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h725re,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7b3ai,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l431cb,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l476vg,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l422cb,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb15cc,defmt,exti,time-driver-any,time \
diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
index a6b627887..d99fd0476 100644
--- a/embassy-stm32/src/rcc/f0.rs
+++ b/embassy-stm32/src/rcc/f0.rs
@@ -11,14 +11,13 @@ pub const HSI_FREQ: Hertz = Hertz(8_000_000);
///
/// hse takes precedence over hsi48 if both are enabled
#[non_exhaustive]
-#[derive(Default)]
pub struct Config {
pub hse: Option<Hertz>,
pub bypass_hse: bool,
pub usb_pll: bool,
- #[cfg(not(stm32f0x0))]
- pub hsi48: bool,
+ #[cfg(crs)]
+ pub hsi48: Option<super::Hsi48Config>,
pub sys_ck: Option<Hertz>,
pub hclk: Option<Hertz>,
@@ -27,12 +26,31 @@ pub struct Config {
pub ls: super::LsConfig,
}
+impl Default for Config {
+ fn default() -> Self {
+ Self {
+ hse: Default::default(),
+ bypass_hse: Default::default(),
+ usb_pll: Default::default(),
+ hsi48: Some(Default::default()),
+ sys_ck: Default::default(),
+ hclk: Default::default(),
+ pclk: Default::default(),
+ ls: Default::default(),
+ }
+ }
+}
+
pub(crate) unsafe fn init(config: Config) {
let sysclk = config.sys_ck.map(|v| v.0).unwrap_or(HSI_FREQ.0);
+ #[cfg(crs)]
+ let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
+ #[cfg(not(crs))]
+ let hsi48: Option<Hertz> = None;
+
let (src_clk, use_hsi48) = config.hse.map(|v| (v.0, false)).unwrap_or_else(|| {
- #[cfg(not(stm32f0x0))]
- if config.hsi48 {
+ if hsi48.is_some() {
return (48_000_000, true);
}
(HSI_FREQ.0, false)
@@ -169,5 +187,9 @@ pub(crate) unsafe fn init(config: Config) {
pclk2_tim: Some(Hertz(pclk * timer_mul)),
hclk1: Some(Hertz(hclk)),
rtc: rtc,
+ hsi48: hsi48,
+
+ // TODO:
+ pll1_p: None,
);
}
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index ab1681dd4..04ea81ec4 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -215,12 +215,9 @@ pub(crate) unsafe fn init(config: Config) {
});
#[cfg(crs)]
- let _hsi48 = config.hsi48.map(|config| {
- //
- super::init_hsi48(config)
- });
+ let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
#[cfg(not(crs))]
- let _hsi48: Option<Hertz> = None;
+ let hsi48: Option<Hertz> = None;
let _plls = [
&config.pll,
@@ -274,12 +271,12 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
#[cfg(any(rcc_l0_v2))]
let clk48 = match config.clk48_src {
- Clk48Src::HSI48 => _hsi48,
+ Clk48Src::HSI48 => hsi48,
Clk48Src::PLL1_VCO_DIV_2 => pll.clk48,
};
#[cfg(any(stm32l4, stm32l5, stm32wb))]
let clk48 = match config.clk48_src {
- Clk48Src::HSI48 => _hsi48,
+ Clk48Src::HSI48 => hsi48,
Clk48Src::MSI => msi,
Clk48Src::PLLSAI1_Q => pllsai1.q,
Clk48Src::PLL1_Q => pll.q,
@@ -393,6 +390,7 @@ pub(crate) unsafe fn init(config: Config) {
msi: msi,
#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
clk48: clk48,
+ hsi48: hsi48,
#[cfg(not(any(stm32l0, stm32l1)))]
pll1_p: pll.p,
@@ -407,6 +405,13 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(stm32l4, stm32l5, stm32wb))]
pllsai1_r: pllsai1.r,
+ #[cfg(not(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5)))]
+ pllsai2_p: None,
+ #[cfg(not(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5)))]
+ pllsai2_q: None,
+ #[cfg(not(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5)))]
+ pllsai2_r: None,
+
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
pllsai2_p: pllsai2.p,
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
From 6c72638ed0c94df0b8f19ff4d6cefde8b61dfe23 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sun, 4 Feb 2024 22:47:15 +0100
Subject: [PATCH 120/392] stm32/rcc: fix more build failures.
---
ci.sh | 3 +++
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/rcc/f0.rs | 1 +
embassy-stm32/src/rcc/mod.rs | 5 ++++-
4 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/ci.sh b/ci.sh
index 4dc76cb69..df9e09848 100755
--- a/ci.sh
+++ b/ci.sh
@@ -85,6 +85,8 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f405zg,defmt,exti,time-driver-any \
@@ -135,6 +137,7 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f100c4,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32h503rb,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32h562ag,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32wb35ce,defmt,exti,time-driver-any,time \
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features ''\
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'log' \
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'defmt' \
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index c412e13d5..8f0fc1c59 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3e3b53df78b4c90ae9c44a58b4f9f93c93a415b7" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e702b4d564bc9e3c8a5c0141a11efdc5f7ee8f24" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3e3b53df78b4c90ae9c44a58b4f9f93c93a415b7", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e702b4d564bc9e3c8a5c0141a11efdc5f7ee8f24", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
index d99fd0476..1042a1cb2 100644
--- a/embassy-stm32/src/rcc/f0.rs
+++ b/embassy-stm32/src/rcc/f0.rs
@@ -32,6 +32,7 @@ impl Default for Config {
hse: Default::default(),
bypass_hse: Default::default(),
usb_pll: Default::default(),
+ #[cfg(crs)]
hsi48: Some(Default::default()),
sys_ck: Default::default(),
hclk: Default::default(),
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 280da7ae3..05937cc5d 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -6,8 +6,11 @@
use core::mem::MaybeUninit;
mod bd;
-mod mco;
pub use bd::*;
+
+#[cfg(any(mco, mco1, mco2))]
+mod mco;
+#[cfg(any(mco, mco1, mco2))]
pub use mco::*;
#[cfg(crs)]
From 66f44b95d70547be8e32daac1ab611eec5fbe28a Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 4 Feb 2024 17:16:33 -0500
Subject: [PATCH 121/392] Addressed hash CI build issues.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/hash/mod.rs | 357 +---------------------------
embassy-stm32/src/hash/v1.rs | 334 +++++++++++++++++++++++++++
embassy-stm32/src/hash/v2v3.rs | 385 +++++++++++++++++++++++++++++++
examples/stm32f7/src/bin/eth.rs | 2 +-
examples/stm32f7/src/bin/hash.rs | 6 +-
6 files changed, 731 insertions(+), 357 deletions(-)
create mode 100644 embassy-stm32/src/hash/v1.rs
create mode 100644 embassy-stm32/src/hash/v2v3.rs
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index d8a4c65fa..00d8a5f63 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-aa5dbf859fae743306f5d816905f166de824241f" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -87,7 +87,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-0cb3a4fcaec702c93b3700715de796636d562b15", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-aa5dbf859fae743306f5d816905f166de824241f", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index ac4854f80..6b23f3b55 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -1,352 +1,7 @@
-//! Hash generator (HASH)
-use core::cmp::min;
-use core::future::poll_fn;
-use core::marker::PhantomData;
-use core::ptr;
-use core::task::Poll;
+//! Hash Accelerator (HASH)
+#[cfg_attr(hash_v1, path = "v1.rs")]
+#[cfg_attr(hash_v2, path = "v2v3.rs")]
+#[cfg_attr(hash_v3, path = "v2v3.rs")]
+mod _version;
-use embassy_hal_internal::{into_ref, PeripheralRef};
-use embassy_sync::waitqueue::AtomicWaker;
-
-use crate::dma::Transfer;
-use crate::peripherals::HASH;
-use stm32_metapac::hash::regs::*;
-
-use crate::interrupt::typelevel::Interrupt;
-use crate::rcc::sealed::RccPeripheral;
-use crate::{interrupt, pac, peripherals, Peripheral};
-
-#[cfg(hash_v1)]
-const NUM_CONTEXT_REGS: usize = 51;
-#[cfg(hash_v2)]
-const NUM_CONTEXT_REGS: usize = 54;
-const DIGEST_BLOCK_SIZE: usize = 64;
-
-static HASH_WAKER: AtomicWaker = AtomicWaker::new();
-
-/// HASH interrupt handler.
-pub struct InterruptHandler<T: Instance> {
- _phantom: PhantomData<T>,
-}
-
-impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
- unsafe fn on_interrupt() {
- let bits = T::regs().sr().read();
- if bits.dinis() {
- T::regs().imr().modify(|reg| reg.set_dinie(false));
- HASH_WAKER.wake();
- }
- if bits.dcis() {
- T::regs().imr().modify(|reg| reg.set_dcie(false));
- HASH_WAKER.wake();
- }
- }
-}
-
-///Hash algorithm selection
-#[derive(PartialEq)]
-pub enum Algorithm {
- /// SHA-1 Algorithm
- SHA1 = 0,
- /// MD5 Algorithm
- MD5 = 1,
- #[cfg(hash_v2)]
- /// SHA-224 Algorithm
- SHA224 = 2,
- #[cfg(hash_v2)]
- /// SHA-256 Algorithm
- SHA256 = 3,
-}
-
-/// Input data width selection
-#[repr(u8)]
-#[derive(Clone, Copy)]
-pub enum DataType {
- ///32-bit data, no data is swapped.
- Width32 = 0,
- ///16-bit data, each half-word is swapped.
- Width16 = 1,
- ///8-bit data, all bytes are swapped.
- Width8 = 2,
- ///1-bit data, all bits are swapped.
- Width1 = 3,
-}
-
-/// Stores the state of the HASH peripheral for suspending/resuming
-/// digest calculation.
-pub struct Context {
- buffer: [u8; DIGEST_BLOCK_SIZE],
- buflen: usize,
- algo: Algorithm,
- format: DataType,
- imr: u32,
- str: u32,
- cr: u32,
- csr: [u32; NUM_CONTEXT_REGS],
-}
-
-/// HASH driver.
-pub struct Hash<'d, T: Instance, D: Dma<T>> {
- _peripheral: PeripheralRef<'d, T>,
- dma: PeripheralRef<'d, D>,
-}
-
-impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
- /// Instantiates, resets, and enables the HASH peripheral.
- pub fn new(peripheral: impl Peripheral<P = T> + 'd, dma: impl Peripheral<P = D> + 'd) -> Self {
- HASH::enable_and_reset();
- into_ref!(peripheral, dma);
- let instance = Self {
- _peripheral: peripheral,
- dma: dma,
- };
-
- T::Interrupt::unpend();
- unsafe { T::Interrupt::enable() };
-
- instance
- }
-
- /// Starts computation of a new hash and returns the saved peripheral state.
- pub async fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
- // Define a context for this new computation.
- let mut ctx = Context {
- buffer: [0; DIGEST_BLOCK_SIZE],
- buflen: 0,
- algo: algorithm,
- format: format,
- imr: 0,
- str: 0,
- cr: 0,
- csr: [0; NUM_CONTEXT_REGS],
- };
-
- // Set the data type in the peripheral.
- T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
-
- // Select the algorithm.
- let mut algo0 = false;
- let mut algo1 = false;
- if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
- algo0 = true;
- }
- if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
- algo1 = true;
- }
- T::regs().cr().modify(|w| w.set_algo0(algo0));
- T::regs().cr().modify(|w| w.set_algo1(algo1));
-
- // Enable multiple DMA transfers.
- T::regs().cr().modify(|w| w.set_mdmat(true));
-
- // Set init to load the context registers. Necessary before storing context.
- T::regs().cr().modify(|w| w.set_init(true));
-
- // Store and return the state of the peripheral.
- self.store_context(&mut ctx).await;
- ctx
- }
-
- /// Restores the peripheral state using the given context,
- /// then updates the state with the provided data.
- /// Peripheral state is saved upon return.
- pub async fn update(&mut self, ctx: &mut Context, input: &[u8]) {
- let data_waiting = input.len() + ctx.buflen;
- if data_waiting < DIGEST_BLOCK_SIZE {
- // There isn't enough data to digest a block, so append it to the buffer.
- ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
- ctx.buflen += input.len();
- return;
- }
-
- // Restore the peripheral state.
- self.load_context(&ctx);
-
- let mut ilen_remaining = input.len();
- let mut input_start = 0;
-
- // First ingest the data in the buffer.
- let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
- if empty_len > 0 {
- let copy_len = min(empty_len, ilen_remaining);
- ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[input_start..input_start + copy_len]);
- ctx.buflen += copy_len;
- ilen_remaining -= copy_len;
- input_start += copy_len;
- }
- self.accumulate(&ctx.buffer).await;
- ctx.buflen = 0;
-
- // Move any extra data to the now-empty buffer.
- let leftovers = ilen_remaining % DIGEST_BLOCK_SIZE;
- if leftovers > 0 {
- assert!(ilen_remaining >= leftovers);
- ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
- ctx.buflen += leftovers;
- ilen_remaining -= leftovers;
- } else {
- ctx.buffer
- .copy_from_slice(&input[input.len() - DIGEST_BLOCK_SIZE..input.len()]);
- ctx.buflen += DIGEST_BLOCK_SIZE;
- ilen_remaining -= DIGEST_BLOCK_SIZE;
- }
-
- // Hash the remaining data.
- self.accumulate(&input[input_start..input_start + ilen_remaining]).await;
-
- // Save the peripheral context.
- self.store_context(ctx).await;
- }
-
- /// Computes a digest for the given context. A slice of the provided digest buffer is returned.
- /// The length of the returned slice is dependent on the digest length of the selected algorithm.
- pub async fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; 32]) -> &'a [u8] {
- // Restore the peripheral state.
- self.load_context(&ctx);
-
- // Must be cleared prior to the last DMA transfer.
- T::regs().cr().modify(|w| w.set_mdmat(false));
-
- // Hash the leftover bytes, if any.
- self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
- ctx.buflen = 0;
-
- // Wait for completion.
- poll_fn(|cx| {
- // Check if already done.
- let bits = T::regs().sr().read();
- if bits.dcis() {
- return Poll::Ready(());
- }
- // Register waker, then enable interrupts.
- HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dinie(true));
- // Check for completion.
- let bits = T::regs().sr().read();
- if bits.dcis() {
- Poll::Ready(())
- } else {
- Poll::Pending
- }
- })
- .await;
-
- // Return the digest.
- let digest_words = match ctx.algo {
- Algorithm::SHA1 => 5,
- Algorithm::MD5 => 4,
- Algorithm::SHA224 => 7,
- Algorithm::SHA256 => 8,
- };
- let mut i = 0;
- while i < digest_words {
- let word = T::regs().hr(i).read();
- digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
- i += 1;
- }
- &digest[0..digest_words * 4]
- }
-
- /// Push data into the hash core.
- async fn accumulate(&mut self, input: &[u8]) {
- // Ignore an input length of 0.
- if input.len() == 0 {
- return;
- }
-
- // Set the number of valid bits.
- let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
- T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
-
- // Configure DMA to transfer input to hash core.
- let dma_request = self.dma.request();
- let dst_ptr = T::regs().din().as_ptr();
- let mut num_words = input.len() / 4;
- if input.len() % 4 > 0 {
- num_words += 1;
- }
- let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
- let dma_transfer =
- unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) };
- T::regs().cr().modify(|w| w.set_dmae(true));
-
- // Wait for the transfer to complete.
- dma_transfer.await;
- }
-
- /// Save the peripheral state to a context.
- async fn store_context(&mut self, ctx: &mut Context) {
- // Wait for interrupt.
- poll_fn(|cx| {
- // Check if already done.
- let bits = T::regs().sr().read();
- if bits.dinis() {
- return Poll::Ready(());
- }
- // Register waker, then enable interrupts.
- HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dinie(true));
- // Check for completion.
- let bits = T::regs().sr().read();
- if bits.dinis() {
- Poll::Ready(())
- } else {
- Poll::Pending
- }
- })
- .await;
-
- ctx.imr = T::regs().imr().read().0;
- ctx.str = T::regs().str().read().0;
- ctx.cr = T::regs().cr().read().0;
- let mut i = 0;
- while i < NUM_CONTEXT_REGS {
- ctx.csr[i] = T::regs().csr(i).read();
- i += 1;
- }
- }
-
- /// Restore the peripheral state from a context.
- fn load_context(&mut self, ctx: &Context) {
- // Restore the peripheral state from the context.
- T::regs().imr().write_value(Imr { 0: ctx.imr });
- T::regs().str().write_value(Str { 0: ctx.str });
- T::regs().cr().write_value(Cr { 0: ctx.cr });
- T::regs().cr().modify(|w| w.set_init(true));
- let mut i = 0;
- while i < NUM_CONTEXT_REGS {
- T::regs().csr(i).write_value(ctx.csr[i]);
- i += 1;
- }
- }
-}
-
-pub(crate) mod sealed {
- use super::*;
-
- pub trait Instance {
- fn regs() -> pac::hash::Hash;
- }
-}
-
-/// HASH instance trait.
-pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
- /// Interrupt for this HASH instance.
- type Interrupt: interrupt::typelevel::Interrupt;
-}
-
-foreach_interrupt!(
- ($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
- impl Instance for peripherals::$inst {
- type Interrupt = crate::interrupt::typelevel::$irq;
- }
-
- impl sealed::Instance for peripherals::$inst {
- fn regs() -> crate::pac::hash::Hash {
- crate::pac::$inst
- }
- }
- };
-);
-
-dma_trait!(Dma, Instance);
+pub use _version::*;
diff --git a/embassy-stm32/src/hash/v1.rs b/embassy-stm32/src/hash/v1.rs
new file mode 100644
index 000000000..50f9adc83
--- /dev/null
+++ b/embassy-stm32/src/hash/v1.rs
@@ -0,0 +1,334 @@
+//! Hash generator (HASH)
+use core::cmp::min;
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::task::Poll;
+
+use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_sync::waitqueue::AtomicWaker;
+use stm32_metapac::hash::regs::*;
+
+use crate::interrupt::typelevel::Interrupt;
+use crate::peripherals::HASH;
+use crate::rcc::sealed::RccPeripheral;
+use crate::{interrupt, pac, peripherals, Peripheral};
+
+const NUM_CONTEXT_REGS: usize = 51;
+const HASH_BUFFER_LEN: usize = 68;
+const DIGEST_BLOCK_SIZE: usize = 64;
+const MAX_DIGEST_SIZE: usize = 20;
+
+static HASH_WAKER: AtomicWaker = AtomicWaker::new();
+
+/// HASH interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+ _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+ unsafe fn on_interrupt() {
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ T::regs().imr().modify(|reg| reg.set_dinie(false));
+ HASH_WAKER.wake();
+ }
+ if bits.dcis() {
+ T::regs().imr().modify(|reg| reg.set_dcie(false));
+ HASH_WAKER.wake();
+ }
+ }
+}
+
+///Hash algorithm selection
+#[derive(PartialEq)]
+pub enum Algorithm {
+ /// SHA-1 Algorithm
+ SHA1 = 0,
+ /// MD5 Algorithm
+ MD5 = 1,
+}
+
+/// Input data width selection
+#[repr(u8)]
+#[derive(Clone, Copy)]
+pub enum DataType {
+ ///32-bit data, no data is swapped.
+ Width32 = 0,
+ ///16-bit data, each half-word is swapped.
+ Width16 = 1,
+ ///8-bit data, all bytes are swapped.
+ Width8 = 2,
+ ///1-bit data, all bits are swapped.
+ Width1 = 3,
+}
+
+/// Stores the state of the HASH peripheral for suspending/resuming
+/// digest calculation.
+pub struct Context {
+ first_word_sent: bool,
+ buffer: [u8; HASH_BUFFER_LEN],
+ buflen: usize,
+ algo: Algorithm,
+ format: DataType,
+ imr: u32,
+ str: u32,
+ cr: u32,
+ csr: [u32; NUM_CONTEXT_REGS],
+}
+
+/// HASH driver.
+pub struct Hash<'d, T: Instance> {
+ _peripheral: PeripheralRef<'d, T>,
+}
+
+impl<'d, T: Instance> Hash<'d, T> {
+ /// Instantiates, resets, and enables the HASH peripheral.
+ pub fn new(peripheral: impl Peripheral<P = T> + 'd) -> Self {
+ HASH::enable_and_reset();
+ into_ref!(peripheral);
+ let instance = Self {
+ _peripheral: peripheral,
+ };
+
+ T::Interrupt::unpend();
+ unsafe { T::Interrupt::enable() };
+
+ instance
+ }
+
+ /// Starts computation of a new hash and returns the saved peripheral state.
+ pub async fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
+ // Define a context for this new computation.
+ let mut ctx = Context {
+ first_word_sent: false,
+ buffer: [0; HASH_BUFFER_LEN],
+ buflen: 0,
+ algo: algorithm,
+ format: format,
+ imr: 0,
+ str: 0,
+ cr: 0,
+ csr: [0; NUM_CONTEXT_REGS],
+ };
+
+ // Set the data type in the peripheral.
+ T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
+
+ // Select the algorithm.
+ if ctx.algo == Algorithm::MD5 {
+ T::regs().cr().modify(|w| w.set_algo(true));
+ }
+
+ // Store and return the state of the peripheral.
+ self.store_context(&mut ctx).await;
+ ctx
+ }
+
+ /// Restores the peripheral state using the given context,
+ /// then updates the state with the provided data.
+ /// Peripheral state is saved upon return.
+ pub async fn update(&mut self, ctx: &mut Context, input: &[u8]) {
+ let mut data_waiting = input.len() + ctx.buflen;
+ if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
+ // There isn't enough data to digest a block, so append it to the buffer.
+ ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
+ ctx.buflen += input.len();
+ return;
+ }
+
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ let mut ilen_remaining = input.len();
+ let mut input_start = 0;
+
+ // Handle first block.
+ if !ctx.first_word_sent {
+ let empty_len = ctx.buffer.len() - ctx.buflen;
+ let copy_len = min(empty_len, ilen_remaining);
+ // Fill the buffer.
+ if copy_len > 0 {
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[0..copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ self.accumulate(ctx.buffer.as_slice());
+ data_waiting -= ctx.buflen;
+ ctx.buflen = 0;
+ ctx.first_word_sent = true;
+ }
+
+ if data_waiting < DIGEST_BLOCK_SIZE {
+ // There isn't enough data remaining to process another block, so store it.
+ ctx.buffer[0..ilen_remaining].copy_from_slice(&input[input_start..input_start + ilen_remaining]);
+ ctx.buflen += ilen_remaining;
+ } else {
+ // First ingest the data in the buffer.
+ let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
+ if empty_len > 0 {
+ let copy_len = min(empty_len, ilen_remaining);
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len]
+ .copy_from_slice(&input[input_start..input_start + copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ self.accumulate(&ctx.buffer[0..64]);
+ ctx.buflen = 0;
+
+ // Move any extra data to the now-empty buffer.
+ let leftovers = ilen_remaining % 64;
+ if leftovers > 0 {
+ ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
+ ctx.buflen += leftovers;
+ ilen_remaining -= leftovers;
+ }
+
+ // Hash the remaining data.
+ self.accumulate(&input[input_start..input_start + ilen_remaining]);
+ }
+
+ // Save the peripheral context.
+ self.store_context(ctx).await;
+ }
+
+ /// Computes a digest for the given context. A slice of the provided digest buffer is returned.
+ /// The length of the returned slice is dependent on the digest length of the selected algorithm.
+ pub async fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; MAX_DIGEST_SIZE]) -> &'a [u8] {
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ // Hash the leftover bytes, if any.
+ self.accumulate(&ctx.buffer[0..ctx.buflen]);
+ ctx.buflen = 0;
+
+ //Start the digest calculation.
+ T::regs().str().write(|w| w.set_dcal(true));
+
+ // Wait for completion.
+ poll_fn(|cx| {
+ // Check if already done.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ return Poll::Ready(());
+ }
+ // Register waker, then enable interrupts.
+ HASH_WAKER.register(cx.waker());
+ T::regs().imr().modify(|reg| reg.set_dinie(true));
+ // Check for completion.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
+ .await;
+
+ // Return the digest.
+ let digest_words = match ctx.algo {
+ Algorithm::SHA1 => 5,
+ Algorithm::MD5 => 4,
+ };
+ let mut i = 0;
+ while i < digest_words {
+ let word = T::regs().hr(i).read();
+ digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
+ i += 1;
+ }
+ &digest[0..digest_words * 4]
+ }
+
+ /// Push data into the hash core.
+ fn accumulate(&mut self, input: &[u8]) {
+ // Set the number of valid bits.
+ let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
+ T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
+
+ let mut i = 0;
+ while i < input.len() {
+ let mut word: [u8; 4] = [0; 4];
+ let copy_idx = min(i + 4, input.len());
+ word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
+ T::regs().din().write_value(u32::from_ne_bytes(word));
+ i += 4;
+ }
+ }
+
+ /// Save the peripheral state to a context.
+ async fn store_context(&mut self, ctx: &mut Context) {
+ // Wait for interrupt.
+ poll_fn(|cx| {
+ // Check if already done.
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ return Poll::Ready(());
+ }
+ // Register waker, then enable interrupts.
+ HASH_WAKER.register(cx.waker());
+ T::regs().imr().modify(|reg| reg.set_dinie(true));
+ // Check for completion.
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
+ .await;
+
+ ctx.imr = T::regs().imr().read().0;
+ ctx.str = T::regs().str().read().0;
+ ctx.cr = T::regs().cr().read().0;
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ ctx.csr[i] = T::regs().csr(i).read();
+ i += 1;
+ }
+ }
+
+ /// Restore the peripheral state from a context.
+ fn load_context(&mut self, ctx: &Context) {
+ // Restore the peripheral state from the context.
+ T::regs().imr().write_value(Imr { 0: ctx.imr });
+ T::regs().str().write_value(Str { 0: ctx.str });
+ T::regs().cr().write_value(Cr { 0: ctx.cr });
+ T::regs().cr().modify(|w| w.set_init(true));
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ T::regs().csr(i).write_value(ctx.csr[i]);
+ i += 1;
+ }
+ }
+}
+
+pub(crate) mod sealed {
+ use super::*;
+
+ pub trait Instance {
+ fn regs() -> pac::hash::Hash;
+ }
+}
+
+/// HASH instance trait.
+pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+ /// Interrupt for this HASH instance.
+ type Interrupt: interrupt::typelevel::Interrupt;
+}
+
+foreach_interrupt!(
+ ($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
+ impl Instance for peripherals::$inst {
+ type Interrupt = crate::interrupt::typelevel::$irq;
+ }
+
+ impl sealed::Instance for peripherals::$inst {
+ fn regs() -> crate::pac::hash::Hash {
+ crate::pac::$inst
+ }
+ }
+ };
+);
+
+dma_trait!(Dma, Instance);
diff --git a/embassy-stm32/src/hash/v2v3.rs b/embassy-stm32/src/hash/v2v3.rs
new file mode 100644
index 000000000..058864568
--- /dev/null
+++ b/embassy-stm32/src/hash/v2v3.rs
@@ -0,0 +1,385 @@
+//! Hash generator (HASH)
+use core::cmp::min;
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::ptr;
+use core::task::Poll;
+
+use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_sync::waitqueue::AtomicWaker;
+use stm32_metapac::hash::regs::*;
+
+use crate::dma::Transfer;
+use crate::interrupt::typelevel::Interrupt;
+use crate::peripherals::HASH;
+use crate::rcc::sealed::RccPeripheral;
+use crate::{interrupt, pac, peripherals, Peripheral};
+
+#[cfg(hash_v2)]
+const NUM_CONTEXT_REGS: usize = 54;
+#[cfg(hash_v3)]
+const NUM_CONTEXT_REGS: usize = 103;
+const DIGEST_BLOCK_SIZE: usize = 64;
+const MAX_DIGEST_SIZE: usize = 64;
+
+static HASH_WAKER: AtomicWaker = AtomicWaker::new();
+
+/// HASH interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+ _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+ unsafe fn on_interrupt() {
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ T::regs().imr().modify(|reg| reg.set_dinie(false));
+ HASH_WAKER.wake();
+ }
+ if bits.dcis() {
+ T::regs().imr().modify(|reg| reg.set_dcie(false));
+ HASH_WAKER.wake();
+ }
+ }
+}
+
+///Hash algorithm selection
+#[derive(Clone, Copy, PartialEq)]
+pub enum Algorithm {
+ /// SHA-1 Algorithm
+ SHA1 = 0,
+
+ #[cfg(hash_v2)]
+ /// MD5 Algorithm
+ MD5 = 1,
+
+ /// SHA-224 Algorithm
+ SHA224 = 2,
+
+ /// SHA-256 Algorithm
+ SHA256 = 3,
+
+ #[cfg(hash_v3)]
+ /// SHA-384 Algorithm
+ SHA384 = 12,
+
+ #[cfg(hash_v3)]
+ /// SHA-512/224 Algorithm
+ SHA512_224 = 13,
+
+ #[cfg(hash_v3)]
+ /// SHA-512/256 Algorithm
+ SHA512_256 = 14,
+
+ #[cfg(hash_v3)]
+ /// SHA-256 Algorithm
+ SHA512 = 15,
+}
+
+/// Input data width selection
+#[repr(u8)]
+#[derive(Clone, Copy)]
+pub enum DataType {
+ ///32-bit data, no data is swapped.
+ Width32 = 0,
+ ///16-bit data, each half-word is swapped.
+ Width16 = 1,
+ ///8-bit data, all bytes are swapped.
+ Width8 = 2,
+ ///1-bit data, all bits are swapped.
+ Width1 = 3,
+}
+
+/// Stores the state of the HASH peripheral for suspending/resuming
+/// digest calculation.
+pub struct Context {
+ buffer: [u8; DIGEST_BLOCK_SIZE],
+ buflen: usize,
+ algo: Algorithm,
+ format: DataType,
+ imr: u32,
+ str: u32,
+ cr: u32,
+ csr: [u32; NUM_CONTEXT_REGS],
+}
+
+/// HASH driver.
+pub struct Hash<'d, T: Instance, D: Dma<T>> {
+ _peripheral: PeripheralRef<'d, T>,
+ dma: PeripheralRef<'d, D>,
+}
+
+impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
+ /// Instantiates, resets, and enables the HASH peripheral.
+ pub fn new(peripheral: impl Peripheral<P = T> + 'd, dma: impl Peripheral<P = D> + 'd) -> Self {
+ HASH::enable_and_reset();
+ into_ref!(peripheral, dma);
+ let instance = Self {
+ _peripheral: peripheral,
+ dma: dma,
+ };
+
+ T::Interrupt::unpend();
+ unsafe { T::Interrupt::enable() };
+
+ instance
+ }
+
+ /// Starts computation of a new hash and returns the saved peripheral state.
+ pub async fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
+ // Define a context for this new computation.
+ let mut ctx = Context {
+ buffer: [0; DIGEST_BLOCK_SIZE],
+ buflen: 0,
+ algo: algorithm,
+ format: format,
+ imr: 0,
+ str: 0,
+ cr: 0,
+ csr: [0; NUM_CONTEXT_REGS],
+ };
+
+ // Set the data type in the peripheral.
+ T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
+
+ #[cfg(hash_v2)]
+ {
+ // Select the algorithm.
+ let mut algo0 = false;
+ let mut algo1 = false;
+ if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
+ algo0 = true;
+ }
+ if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
+ algo1 = true;
+ }
+ T::regs().cr().modify(|w| w.set_algo0(algo0));
+ T::regs().cr().modify(|w| w.set_algo1(algo1));
+ }
+
+ #[cfg(hash_v3)]
+ T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
+
+ // Enable multiple DMA transfers.
+ T::regs().cr().modify(|w| w.set_mdmat(true));
+
+ // Set init to load the context registers. Necessary before storing context.
+ T::regs().cr().modify(|w| w.set_init(true));
+
+ // Store and return the state of the peripheral.
+ self.store_context(&mut ctx).await;
+ ctx
+ }
+
+ /// Restores the peripheral state using the given context,
+ /// then updates the state with the provided data.
+ /// Peripheral state is saved upon return.
+ pub async fn update(&mut self, ctx: &mut Context, input: &[u8]) {
+ let data_waiting = input.len() + ctx.buflen;
+ if data_waiting < DIGEST_BLOCK_SIZE {
+ // There isn't enough data to digest a block, so append it to the buffer.
+ ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
+ ctx.buflen += input.len();
+ return;
+ }
+
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ let mut ilen_remaining = input.len();
+ let mut input_start = 0;
+
+ // First ingest the data in the buffer.
+ let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
+ if empty_len > 0 {
+ let copy_len = min(empty_len, ilen_remaining);
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[input_start..input_start + copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ self.accumulate(&ctx.buffer).await;
+ ctx.buflen = 0;
+
+ // Move any extra data to the now-empty buffer.
+ let leftovers = ilen_remaining % DIGEST_BLOCK_SIZE;
+ if leftovers > 0 {
+ assert!(ilen_remaining >= leftovers);
+ ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
+ ctx.buflen += leftovers;
+ ilen_remaining -= leftovers;
+ } else {
+ ctx.buffer
+ .copy_from_slice(&input[input.len() - DIGEST_BLOCK_SIZE..input.len()]);
+ ctx.buflen += DIGEST_BLOCK_SIZE;
+ ilen_remaining -= DIGEST_BLOCK_SIZE;
+ }
+
+ // Hash the remaining data.
+ self.accumulate(&input[input_start..input_start + ilen_remaining]).await;
+
+ // Save the peripheral context.
+ self.store_context(ctx).await;
+ }
+
+ /// Computes a digest for the given context. A slice of the provided digest buffer is returned.
+ /// The length of the returned slice is dependent on the digest length of the selected algorithm.
+ pub async fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; MAX_DIGEST_SIZE]) -> &'a [u8] {
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ // Must be cleared prior to the last DMA transfer.
+ T::regs().cr().modify(|w| w.set_mdmat(false));
+
+ // Hash the leftover bytes, if any.
+ self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
+ ctx.buflen = 0;
+
+ // Wait for completion.
+ poll_fn(|cx| {
+ // Check if already done.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ return Poll::Ready(());
+ }
+ // Register waker, then enable interrupts.
+ HASH_WAKER.register(cx.waker());
+ T::regs().imr().modify(|reg| reg.set_dinie(true));
+ // Check for completion.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
+ .await;
+
+ // Return the digest.
+ let digest_words = match ctx.algo {
+ Algorithm::SHA1 => 5,
+ #[cfg(hash_v2)]
+ Algorithm::MD5 => 4,
+ Algorithm::SHA224 => 7,
+ Algorithm::SHA256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA384 => 12,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_224 => 7,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512 => 16,
+ };
+ let mut i = 0;
+ while i < digest_words {
+ let word = T::regs().hr(i).read();
+ digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
+ i += 1;
+ }
+ &digest[0..digest_words * 4]
+ }
+
+ /// Push data into the hash core.
+ async fn accumulate(&mut self, input: &[u8]) {
+ // Ignore an input length of 0.
+ if input.len() == 0 {
+ return;
+ }
+
+ // Set the number of valid bits.
+ let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
+ T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
+
+ // Configure DMA to transfer input to hash core.
+ let dma_request = self.dma.request();
+ let dst_ptr = T::regs().din().as_ptr();
+ let mut num_words = input.len() / 4;
+ if input.len() % 4 > 0 {
+ num_words += 1;
+ }
+ let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
+ let dma_transfer =
+ unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) };
+ T::regs().cr().modify(|w| w.set_dmae(true));
+
+ // Wait for the transfer to complete.
+ dma_transfer.await;
+ }
+
+ /// Save the peripheral state to a context.
+ async fn store_context(&mut self, ctx: &mut Context) {
+ // Wait for interrupt.
+ poll_fn(|cx| {
+ // Check if already done.
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ return Poll::Ready(());
+ }
+ // Register waker, then enable interrupts.
+ HASH_WAKER.register(cx.waker());
+ T::regs().imr().modify(|reg| reg.set_dinie(true));
+ // Check for completion.
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
+ .await;
+
+ ctx.imr = T::regs().imr().read().0;
+ ctx.str = T::regs().str().read().0;
+ ctx.cr = T::regs().cr().read().0;
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ ctx.csr[i] = T::regs().csr(i).read();
+ i += 1;
+ }
+ }
+
+ /// Restore the peripheral state from a context.
+ fn load_context(&mut self, ctx: &Context) {
+ // Restore the peripheral state from the context.
+ T::regs().imr().write_value(Imr { 0: ctx.imr });
+ T::regs().str().write_value(Str { 0: ctx.str });
+ T::regs().cr().write_value(Cr { 0: ctx.cr });
+ T::regs().cr().modify(|w| w.set_init(true));
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ T::regs().csr(i).write_value(ctx.csr[i]);
+ i += 1;
+ }
+ }
+}
+
+pub(crate) mod sealed {
+ use super::*;
+
+ pub trait Instance {
+ fn regs() -> pac::hash::Hash;
+ }
+}
+
+/// HASH instance trait.
+pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+ /// Interrupt for this HASH instance.
+ type Interrupt: interrupt::typelevel::Interrupt;
+}
+
+foreach_interrupt!(
+ ($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
+ impl Instance for peripherals::$inst {
+ type Interrupt = crate::interrupt::typelevel::$irq;
+ }
+
+ impl sealed::Instance for peripherals::$inst {
+ fn regs() -> crate::pac::hash::Hash {
+ crate::pac::$inst
+ }
+ }
+ };
+);
+
+dma_trait!(Dma, Instance);
diff --git a/examples/stm32f7/src/bin/eth.rs b/examples/stm32f7/src/bin/eth.rs
index 5bff48197..9a608e909 100644
--- a/examples/stm32f7/src/bin/eth.rs
+++ b/examples/stm32f7/src/bin/eth.rs
@@ -19,7 +19,7 @@ use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
ETH => eth::InterruptHandler;
- RNG => rng::InterruptHandler<peripherals::RNG>;
+ HASH_RNG => rng::InterruptHandler<peripherals::RNG>;
});
type Device = Ethernet<'static, ETH, GenericSMI>;
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index a9f5aa197..cf52cea5c 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -3,12 +3,12 @@
use defmt::info;
use embassy_executor::Spawner;
+use embassy_stm32::hash::*;
use embassy_stm32::Config;
use embassy_time::Instant;
-use {defmt_rtt as _, panic_probe as _};
-use embassy_stm32::hash::*;
use sha2::{Digest, Sha256};
+use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
@@ -26,7 +26,7 @@ async fn main(_spawner: Spawner) -> ! {
let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
hw_hasher.update(&mut context, test_1).await;
hw_hasher.update(&mut context, test_2).await;
- let mut buffer: [u8; 32] = [0; 32];
+ let mut buffer: [u8; 64] = [0; 64];
let hw_digest = hw_hasher.finish(context, &mut buffer).await;
let hw_end_time = Instant::now();
From a260c0a701b0385691b57a22a19d86d7ce4788b8 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 4 Feb 2024 17:21:16 -0500
Subject: [PATCH 122/392] Format hash example.
---
examples/stm32f7/src/bin/hash.rs | 1 -
1 file changed, 1 deletion(-)
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index cf52cea5c..4bd9b4e2e 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -6,7 +6,6 @@ use embassy_executor::Spawner;
use embassy_stm32::hash::*;
use embassy_stm32::Config;
use embassy_time::Instant;
-
use sha2::{Digest, Sha256};
use {defmt_rtt as _, panic_probe as _};
From 7817c8b17c2a65e799fb3f64e5e3a703ad4ace33 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Mon, 5 Feb 2024 09:10:53 +0100
Subject: [PATCH 123/392] docs: fix bullet point indentation
---
docs/modules/ROOT/pages/embassy_in_the_wild.adoc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/modules/ROOT/pages/embassy_in_the_wild.adoc b/docs/modules/ROOT/pages/embassy_in_the_wild.adoc
index dfe9fd6e3..85ad7f4a2 100644
--- a/docs/modules/ROOT/pages/embassy_in_the_wild.adoc
+++ b/docs/modules/ROOT/pages/embassy_in_the_wild.adoc
@@ -8,4 +8,4 @@ Here are known examples of real-world projects which make use of Embassy. Feel f
** Targets the ESP32-S3 or ESP32-C6 MCU
* The link:https://github.com/lora-rs/lora-rs[lora-rs] project includes link:https://github.com/lora-rs/lora-rs/tree/main/examples/stm32l0/src/bin[various standalone examples] for NRF52840, RP2040, STM32L0 and STM32WL
** link:https://github.com/matoushybl/air-force-one[Air force one: A simple air quality monitoring system]
-* Targets nRF52 and uses nrf-softdevice
+*** Targets nRF52 and uses nrf-softdevice
From 079bb7b4901b3fa6787c2ca5d8c022de3533ad8c Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Mon, 5 Feb 2024 14:36:02 -0500
Subject: [PATCH 124/392] Added STM32 hash test.
---
tests/stm32/Cargo.toml | 23 ++++++++-----
tests/stm32/src/bin/hash.rs | 66 +++++++++++++++++++++++++++++++++++++
tests/stm32/src/common.rs | 7 ++++
3 files changed, 88 insertions(+), 8 deletions(-)
create mode 100644 tests/stm32/src/bin/hash.rs
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index cb1bd9a50..d02f1a253 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -15,22 +15,23 @@ stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma"
stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng", "fdcan"]
-stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng"]
-stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan"]
-stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan"]
+stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "hash"]
+stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan", "hash"]
+stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan", "hash"]
stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
-stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng"]
+stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng", "hash"]
stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"]
-stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng"]
-stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng"]
-stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
+stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash"]
+stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng", "hash"]
+stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng", "hash"]
stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
-stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng"]
+stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"]
stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
+hash = []
eth = ["embassy-executor/task-arena-size-16384"]
rng = []
sdmmc = []
@@ -74,6 +75,7 @@ static_cell = "2"
portable-atomic = { version = "1.5", features = [] }
chrono = { version = "^0.4", default-features = false, optional = true}
+sha2 = { version = "0.10.8", default-features = false }
# BEGIN TESTS
# Generated by gen_test.py. DO NOT EDIT.
@@ -107,6 +109,11 @@ name = "gpio"
path = "src/bin/gpio.rs"
required-features = []
+[[bin]]
+name = "hash"
+path = "src/bin/hash.rs"
+required-features = [ "hash",]
+
[[bin]]
name = "rng"
path = "src/bin/rng.rs"
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
new file mode 100644
index 000000000..60a60b0f1
--- /dev/null
+++ b/tests/stm32/src/bin/hash.rs
@@ -0,0 +1,66 @@
+// required-features: hash
+#![no_std]
+#![no_main]
+
+#[path = "../common.rs"]
+mod common;
+use common::*;
+use embassy_executor::Spawner;
+use embassy_stm32::hash::*;
+use embassy_stm32::{bind_interrupts, peripherals, hash};
+use sha2::{Digest, Sha224, Sha256};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
+ let dma = peri!(p, HASH_DMA);
+ let mut hw_hasher = Hash::new(p.HASH, dma);
+
+ let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
+ let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
+ let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
+
+ // Start an SHA-256 digest.
+ let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
+ hw_hasher.update(&mut sha256context, test_1).await;
+
+ // Interrupt the SHA-256 digest to compute an SHA-224 digest.
+ let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8).await;
+ hw_hasher.update(&mut sha224context, test_3).await;
+ let mut sha224_digest_buffer: [u8; 64] = [0; 64];
+ let sha224_digest = hw_hasher.finish(sha224context, &mut sha224_digest_buffer).await;
+
+ // Finish the SHA-256 digest.
+ hw_hasher.update(&mut sha256context, test_2).await;
+ let mut sha_256_digest_buffer: [u8; 64] = [0; 64];
+ let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await;
+
+ // Compute the SHA-256 digest in software.
+ let mut sw_sha256_hasher = Sha256::new();
+ sw_sha256_hasher.update(test_1);
+ sw_sha256_hasher.update(test_2);
+ let sw_sha256_digest = sw_sha256_hasher.finalize();
+
+ //Compute the SHA-224 digest in software.
+ let mut sw_sha224_hasher = Sha224::new();
+ sw_sha224_hasher.update(test_3);
+ let sw_sha224_digest = sw_sha224_hasher.finalize();
+
+ // Compare the SHA-256 digests.
+ info!("Hardware SHA-256 Digest: {:?}", sha256_digest);
+ info!("Software SHA-256 Digest: {:?}", sw_sha256_digest[..]);
+ defmt::assert!(*sha256_digest == sw_sha256_digest[..]);
+
+ // Compare the SHA-224 digests.
+ info!("Hardware SHA-256 Digest: {:?}", sha224_digest);
+ info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
+ defmt::assert!(*sha224_digest == sw_sha224_digest[..]);
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index fefe72c86..7e7915b2e 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -128,6 +128,7 @@ define_peris!(
);
#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
define_peris!(
+ HASH_DMA = DMA1_CH0,
UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
@@ -141,18 +142,21 @@ define_peris!(
);
#[cfg(feature = "stm32u585ai")]
define_peris!(
+ HASH_DMA = GPDMA1_CH0,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
);
#[cfg(feature = "stm32u5a5zj")]
define_peris!(
+ HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PG7, UART_RX = PG8, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
);
#[cfg(feature = "stm32h563zi")]
define_peris!(
+ HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
@@ -171,6 +175,7 @@ define_peris!(
);
#[cfg(feature = "stm32l4a6zg")]
define_peris!(
+ HASH_DMA = DMA2_CH7,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -196,6 +201,7 @@ define_peris!(
);
#[cfg(feature = "stm32l552ze")]
define_peris!(
+ HASH_DMA = DMA1_CH0,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -226,6 +232,7 @@ define_peris!(
);
#[cfg(feature = "stm32wba52cg")]
define_peris!(
+ HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
From 09973ad4827222251a46cb7b1f48841245b54709 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Mon, 5 Feb 2024 14:44:50 -0500
Subject: [PATCH 125/392] Corrected hash CI build issues.
---
tests/stm32/src/bin/hash.rs | 4 ++--
tests/stm32/src/common.rs | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 60a60b0f1..05b61a10c 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -7,7 +7,7 @@ mod common;
use common::*;
use embassy_executor::Spawner;
use embassy_stm32::hash::*;
-use embassy_stm32::{bind_interrupts, peripherals, hash};
+use embassy_stm32::{bind_interrupts, hash, peripherals};
use sha2::{Digest, Sha224, Sha256};
use {defmt_rtt as _, panic_probe as _};
@@ -39,7 +39,7 @@ async fn main(_spawner: Spawner) {
hw_hasher.update(&mut sha256context, test_2).await;
let mut sha_256_digest_buffer: [u8; 64] = [0; 64];
let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await;
-
+
// Compute the SHA-256 digest in software.
let mut sw_sha256_hasher = Sha256::new();
sw_sha256_hasher.update(test_1);
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 7e7915b2e..14d5b6d7b 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -201,7 +201,7 @@ define_peris!(
);
#[cfg(feature = "stm32l552ze")]
define_peris!(
- HASH_DMA = DMA1_CH0,
+ HASH_DMA = DMA1_CH1,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
From 0b70d67bf645708c6681220c4f1c2e3ffb69dc35 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Mon, 5 Feb 2024 14:54:17 -0500
Subject: [PATCH 126/392] Separated hash interrupt bindings.
---
tests/stm32/src/bin/hash.rs | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 05b61a10c..53dd0551f 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -11,10 +11,26 @@ use embassy_stm32::{bind_interrupts, hash, peripherals};
use sha2::{Digest, Sha224, Sha256};
use {defmt_rtt as _, panic_probe as _};
+#[cfg(any(
+ feature = "stm32l4a6zg",
+ feature = "stm32h755zi",
+ feature = "stm32h753zi"
+))]
bind_interrupts!(struct Irqs {
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
});
+#[cfg(any(
+ feature = "stm32wba52cg",
+ feature = "stm32l552ze",
+ feature = "stm32h563zi",
+ feature = "stm32u5a5zj",
+ feature = "stm32u585ai"
+))]
+bind_interrupts!(struct Irqs {
+ HASH => hash::InterruptHandler<peripherals::HASH>;
+ });
+
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
From 2575f597cc3aafeb9925511b12adf30f6a67bccb Mon Sep 17 00:00:00 2001
From: Justin Beaurivage <justin@wearableavionics.com>
Date: Mon, 5 Feb 2024 18:05:59 -0500
Subject: [PATCH 127/392] Address @Dirbaio's comments
---
embassy-nrf/src/uarte.rs | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index f29b5061b..de2966ba5 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -66,18 +66,16 @@ bitflags::bitflags! {
}
}
-impl TryFrom<ErrorSource> for () {
- type Error = Error;
-
+impl ErrorSource {
#[inline]
- fn try_from(errors: ErrorSource) -> Result<Self, Self::Error> {
- if errors.contains(ErrorSource::OVERRUN) {
+ fn check(self) -> Result<(), Error> {
+ if self.contains(ErrorSource::OVERRUN) {
Err(Error::Overrun)
- } else if errors.contains(ErrorSource::PARITY) {
+ } else if self.contains(ErrorSource::PARITY) {
Err(Error::Parity)
- } else if errors.contains(ErrorSource::FRAMING) {
+ } else if self.contains(ErrorSource::FRAMING) {
Err(Error::Framing)
- } else if errors.contains(ErrorSource::BREAK) {
+ } else if self.contains(ErrorSource::BREAK) {
Err(Error::Break)
} else {
Ok(())
@@ -539,7 +537,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
let r = T::regs();
let err_bits = r.errorsrc.read().bits();
r.errorsrc.write(|w| unsafe { w.bits(err_bits) });
- ErrorSource::from_bits_truncate(err_bits).try_into()
+ ErrorSource::from_bits_truncate(err_bits).check()
}
fn new_inner(
@@ -677,6 +675,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
s.endrx_waker.register(cx.waker());
if let Err(e) = self.check_and_clear_errors() {
+ r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
return Poll::Ready(Err(e));
}
if r.events_endrx.read().bits() != 0 {
@@ -823,6 +822,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
s.endrx_waker.register(cx.waker());
if let Err(e) = self.rx.check_and_clear_errors() {
+ r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
return Poll::Ready(Err(e));
}
if r.events_endrx.read().bits() != 0 {
From e72cc9fb24340ddf1151078779b3f00de9bff3ab Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Tue, 23 Jan 2024 16:33:47 +0100
Subject: [PATCH 128/392] fix(stm32/h7): use correct unit in vco clock check
---
embassy-stm32/src/rcc/h.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 9ac2115f0..352e10816 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -721,7 +721,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {
Pllvcosel::WIDEVCO
} else {
- panic!("pll vco_clk out of range: {} mhz", vco_clk.0)
+ panic!("pll vco_clk out of range: {} hz", vco_clk.0)
};
let p = config.divp.map(|div| {
From aab5da1d3bfe10966bef88217492870b4148b28f Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Tue, 6 Feb 2024 12:30:04 +0100
Subject: [PATCH 129/392] fix(stm32h7/flash): enhance resilience to program
sequence errors (pgserr)
---
embassy-stm32/src/flash/h7.rs | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/flash/h7.rs b/embassy-stm32/src/flash/h7.rs
index ae395d568..743925e17 100644
--- a/embassy-stm32/src/flash/h7.rs
+++ b/embassy-stm32/src/flash/h7.rs
@@ -77,12 +77,12 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
}
}
- bank.cr().write(|w| w.set_pg(false));
-
cortex_m::asm::isb();
cortex_m::asm::dsb();
fence(Ordering::SeqCst);
+ bank.cr().write(|w| w.set_pg(false));
+
res.unwrap()
}
@@ -100,6 +100,10 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
w.set_start(true);
});
+ cortex_m::asm::isb();
+ cortex_m::asm::dsb();
+ fence(Ordering::SeqCst);
+
let ret: Result<(), Error> = blocking_wait_ready(bank);
bank.cr().modify(|w| w.set_ser(false));
bank_clear_all_err(bank);
From c267cb9ab764176bc8514535f4db8ac2331e30ce Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Tue, 6 Feb 2024 16:25:45 +0100
Subject: [PATCH 130/392] feat: enhance bootloader for multiple flash support
---
embassy-boot/src/boot_loader.rs | 20 ++++---
embassy-boot/src/firmware_updater/asynch.rs | 13 +++--
embassy-boot/src/firmware_updater/blocking.rs | 14 +++--
.../bootloader/stm32-dual-bank/Cargo.toml | 57 +++++++++++++++++++
.../boot/bootloader/stm32-dual-bank/README.md | 44 ++++++++++++++
.../boot/bootloader/stm32-dual-bank/build.rs | 27 +++++++++
.../boot/bootloader/stm32-dual-bank/memory.x | 18 ++++++
.../bootloader/stm32-dual-bank/src/main.rs | 53 +++++++++++++++++
examples/boot/bootloader/stm32/src/main.rs | 2 +-
.../boot/bootloader/stm32wb-dfu/src/main.rs | 4 +-
10 files changed, 231 insertions(+), 21 deletions(-)
create mode 100644 examples/boot/bootloader/stm32-dual-bank/Cargo.toml
create mode 100644 examples/boot/bootloader/stm32-dual-bank/README.md
create mode 100644 examples/boot/bootloader/stm32-dual-bank/build.rs
create mode 100644 examples/boot/bootloader/stm32-dual-bank/memory.x
create mode 100644 examples/boot/bootloader/stm32-dual-bank/src/main.rs
diff --git a/embassy-boot/src/boot_loader.rs b/embassy-boot/src/boot_loader.rs
index e568001bc..54ae8a34b 100644
--- a/embassy-boot/src/boot_loader.rs
+++ b/embassy-boot/src/boot_loader.rs
@@ -49,16 +49,20 @@ pub struct BootLoaderConfig<ACTIVE, DFU, STATE> {
pub state: STATE,
}
-impl<'a, FLASH: NorFlash>
+impl<'a, ActiveFlash: NorFlash, DFUFlash: NorFlash, StateFlash: NorFlash>
BootLoaderConfig<
- BlockingPartition<'a, NoopRawMutex, FLASH>,
- BlockingPartition<'a, NoopRawMutex, FLASH>,
- BlockingPartition<'a, NoopRawMutex, FLASH>,
+ BlockingPartition<'a, NoopRawMutex, ActiveFlash>,
+ BlockingPartition<'a, NoopRawMutex, DFUFlash>,
+ BlockingPartition<'a, NoopRawMutex, StateFlash>,
>
{
/// Create a bootloader config from the flash and address symbols defined in the linkerfile
// #[cfg(target_os = "none")]
- pub fn from_linkerfile_blocking(flash: &'a Mutex<NoopRawMutex, RefCell<FLASH>>) -> Self {
+ pub fn from_linkerfile_blocking(
+ active_flash: &'a Mutex<NoopRawMutex, RefCell<ActiveFlash>>,
+ dfu_flash: &'a Mutex<NoopRawMutex, RefCell<DFUFlash>>,
+ state_flash: &'a Mutex<NoopRawMutex, RefCell<StateFlash>>,
+ ) -> Self {
extern "C" {
static __bootloader_state_start: u32;
static __bootloader_state_end: u32;
@@ -73,21 +77,21 @@ impl<'a, FLASH: NorFlash>
let end = &__bootloader_active_end as *const u32 as u32;
trace!("ACTIVE: 0x{:x} - 0x{:x}", start, end);
- BlockingPartition::new(flash, start, end - start)
+ BlockingPartition::new(active_flash, start, end - start)
};
let dfu = unsafe {
let start = &__bootloader_dfu_start as *const u32 as u32;
let end = &__bootloader_dfu_end as *const u32 as u32;
trace!("DFU: 0x{:x} - 0x{:x}", start, end);
- BlockingPartition::new(flash, start, end - start)
+ BlockingPartition::new(dfu_flash, start, end - start)
};
let state = unsafe {
let start = &__bootloader_state_start as *const u32 as u32;
let end = &__bootloader_state_end as *const u32 as u32;
trace!("STATE: 0x{:x} - 0x{:x}", start, end);
- BlockingPartition::new(flash, start, end - start)
+ BlockingPartition::new(state_flash, start, end - start)
};
Self { active, dfu, state }
diff --git a/embassy-boot/src/firmware_updater/asynch.rs b/embassy-boot/src/firmware_updater/asynch.rs
index 2e43e1cc1..5634b48d4 100644
--- a/embassy-boot/src/firmware_updater/asynch.rs
+++ b/embassy-boot/src/firmware_updater/asynch.rs
@@ -16,11 +16,14 @@ pub struct FirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
}
#[cfg(target_os = "none")]
-impl<'a, FLASH: NorFlash>
- FirmwareUpdaterConfig<Partition<'a, NoopRawMutex, FLASH>, Partition<'a, NoopRawMutex, FLASH>>
+impl<'a, DFUFlash: NorFlash, StateFlash: NorFlash>
+ FirmwareUpdaterConfig<Partition<'a, NoopRawMutex, DFUFlash>, Partition<'a, NoopRawMutex, StateFlash>>
{
/// Create a firmware updater config from the flash and address symbols defined in the linkerfile
- pub fn from_linkerfile(flash: &'a embassy_sync::mutex::Mutex<NoopRawMutex, FLASH>) -> Self {
+ pub fn from_linkerfile(
+ dfu_flash: &'a embassy_sync::mutex::Mutex<NoopRawMutex, DFUFlash>,
+ state_flash: &'a embassy_sync::mutex::Mutex<NoopRawMutex, StateFlash>,
+ ) -> Self {
extern "C" {
static __bootloader_state_start: u32;
static __bootloader_state_end: u32;
@@ -33,14 +36,14 @@ impl<'a, FLASH: NorFlash>
let end = &__bootloader_dfu_end as *const u32 as u32;
trace!("DFU: 0x{:x} - 0x{:x}", start, end);
- Partition::new(flash, start, end - start)
+ Partition::new(dfu_flash, start, end - start)
};
let state = unsafe {
let start = &__bootloader_state_start as *const u32 as u32;
let end = &__bootloader_state_end as *const u32 as u32;
trace!("STATE: 0x{:x} - 0x{:x}", start, end);
- Partition::new(flash, start, end - start)
+ Partition::new(state_flash, start, end - start)
};
Self { dfu, state }
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index f1368540d..3814b6c31 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -16,12 +16,16 @@ pub struct BlockingFirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
}
#[cfg(target_os = "none")]
-impl<'a, FLASH: NorFlash>
- FirmwareUpdaterConfig<BlockingPartition<'a, NoopRawMutex, FLASH>, BlockingPartition<'a, NoopRawMutex, FLASH>>
+impl<'a, DFUFlash: NorFlash, StateFlash: NorFlash>
+ FirmwareUpdaterConfig<
+ BlockingPartition<'a, NoopRawMutex, DFUFlash>,
+ BlockingPartition<'a, NoopRawMutex, StateFlash>,
+ >
{
/// Create a firmware updater config from the flash and address symbols defined in the linkerfile
pub fn from_linkerfile_blocking(
- flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<FLASH>>,
+ dfu_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<DFUFlash>>,
+ state_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<StateFlash>>,
) -> Self {
extern "C" {
static __bootloader_state_start: u32;
@@ -35,14 +39,14 @@ impl<'a, FLASH: NorFlash>
let end = &__bootloader_dfu_end as *const u32 as u32;
trace!("DFU: 0x{:x} - 0x{:x}", start, end);
- BlockingPartition::new(flash, start, end - start)
+ BlockingPartition::new(dfu_flash, start, end - start)
};
let state = unsafe {
let start = &__bootloader_state_start as *const u32 as u32;
let end = &__bootloader_state_end as *const u32 as u32;
trace!("STATE: 0x{:x} - 0x{:x}", start, end);
- BlockingPartition::new(flash, start, end - start)
+ BlockingPartition::new(state_flash, start, end - start)
};
Self { dfu, state }
diff --git a/examples/boot/bootloader/stm32-dual-bank/Cargo.toml b/examples/boot/bootloader/stm32-dual-bank/Cargo.toml
new file mode 100644
index 000000000..313187adc
--- /dev/null
+++ b/examples/boot/bootloader/stm32-dual-bank/Cargo.toml
@@ -0,0 +1,57 @@
+[package]
+edition = "2021"
+name = "stm32-bootloader-dual-bank-flash-example"
+version = "0.1.0"
+description = "Example bootloader for dual-bank flash STM32 chips"
+license = "MIT OR Apache-2.0"
+
+[dependencies]
+defmt = { version = "0.3", optional = true }
+defmt-rtt = { version = "0.4", optional = true }
+
+embassy-stm32 = { path = "../../../../embassy-stm32", features = [] }
+embassy-boot-stm32 = { path = "../../../../embassy-boot-stm32" }
+cortex-m = { version = "0.7.6", features = [
+ "inline-asm",
+ "critical-section-single-core",
+] }
+embassy-sync = { version = "0.5.0", path = "../../../../embassy-sync" }
+cortex-m-rt = { version = "0.7" }
+embedded-storage = "0.3.1"
+embedded-storage-async = "0.4.0"
+cfg-if = "1.0.0"
+
+[features]
+defmt = ["dep:defmt", "embassy-boot-stm32/defmt", "embassy-stm32/defmt"]
+debug = ["defmt-rtt", "defmt"]
+
+[profile.dev]
+debug = 2
+debug-assertions = true
+incremental = false
+opt-level = 'z'
+overflow-checks = true
+
+[profile.release]
+codegen-units = 1
+debug = 2
+debug-assertions = false
+incremental = false
+lto = 'fat'
+opt-level = 'z'
+overflow-checks = false
+
+# do not optimize proc-macro crates = faster builds from scratch
+[profile.dev.build-override]
+codegen-units = 8
+debug = false
+debug-assertions = false
+opt-level = 0
+overflow-checks = false
+
+[profile.release.build-override]
+codegen-units = 8
+debug = false
+debug-assertions = false
+opt-level = 0
+overflow-checks = false
diff --git a/examples/boot/bootloader/stm32-dual-bank/README.md b/examples/boot/bootloader/stm32-dual-bank/README.md
new file mode 100644
index 000000000..3de3171cd
--- /dev/null
+++ b/examples/boot/bootloader/stm32-dual-bank/README.md
@@ -0,0 +1,44 @@
+# STM32 dual-bank flash Bootloader
+
+## Overview
+
+This bootloader leverages `embassy-boot` to interact with the flash.
+This example targets STM32 devices with dual-bank flash memory, with a primary focus on the STM32H747XI series.
+Users must modify the `memory.x` configuration file to match with the memory layout of their specific STM32 device.
+
+Additionally, this example can be extended to utilize external flash memory, such as QSPI, for storing partitions.
+
+## Memory Configuration
+
+In this example's `memory.x` file, various symbols are defined to assist in effective memory management within the bootloader environment.
+For dual-bank STM32 devices, it's crucial to assign these symbols correctly to their respective memory banks.
+
+### Symbol Definitions
+
+The bootloader's state and active symbols are anchored to the flash origin of **bank 1**:
+
+- `__bootloader_state_start` and `__bootloader_state_end`
+- `__bootloader_active_start` and `__bootloader_active_end`
+
+In contrast, the Device Firmware Upgrade (DFU) symbols are aligned with the DFU flash origin in **bank 2**:
+
+- `__bootloader_dfu_start` and `__bootloader_dfu_end`
+
+```rust
+__bootloader_state_start = ORIGIN(BOOTLOADER_STATE) - ORIGIN(**FLASH**);
+__bootloader_state_end = ORIGIN(BOOTLOADER_STATE) + LENGTH(BOOTLOADER_STATE) - ORIGIN(**FLASH**);
+
+__bootloader_active_start = ORIGIN(ACTIVE) - ORIGIN(**FLASH**);
+__bootloader_active_end = ORIGIN(ACTIVE) + LENGTH(ACTIVE) - ORIGIN(**FLASH**);
+
+__bootloader_dfu_start = ORIGIN(DFU) - ORIGIN(**DFU**);
+__bootloader_dfu_end = ORIGIN(DFU) + LENGTH(DFU) - ORIGIN(**DFU**);
+```
+
+## Flashing the Bootloader
+
+To flash the bootloader onto your STM32H747XI device, use the following command:
+
+```bash
+cargo flash --features embassy-stm32/stm32h747xi-cm7 --release --chip STM32H747XIHx
+```
diff --git a/examples/boot/bootloader/stm32-dual-bank/build.rs b/examples/boot/bootloader/stm32-dual-bank/build.rs
new file mode 100644
index 000000000..fd605991f
--- /dev/null
+++ b/examples/boot/bootloader/stm32-dual-bank/build.rs
@@ -0,0 +1,27 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+ // Put `memory.x` in our output directory and ensure it's
+ // on the linker search path.
+ let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+ File::create(out.join("memory.x"))
+ .unwrap()
+ .write_all(include_bytes!("memory.x"))
+ .unwrap();
+ println!("cargo:rustc-link-search={}", out.display());
+
+ // By default, Cargo will re-run a build script whenever
+ // any file in the project changes. By specifying `memory.x`
+ // here, we ensure the build script is only re-run when
+ // `memory.x` is changed.
+ println!("cargo:rerun-if-changed=memory.x");
+
+ println!("cargo:rustc-link-arg-bins=--nmagic");
+ println!("cargo:rustc-link-arg-bins=-Tlink.x");
+ if env::var("CARGO_FEATURE_DEFMT").is_ok() {
+ println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
+ }
+}
diff --git a/examples/boot/bootloader/stm32-dual-bank/memory.x b/examples/boot/bootloader/stm32-dual-bank/memory.x
new file mode 100644
index 000000000..665da7139
--- /dev/null
+++ b/examples/boot/bootloader/stm32-dual-bank/memory.x
@@ -0,0 +1,18 @@
+MEMORY
+{
+ /* NOTE 1 K = 1 KiBi = 1024 bytes */
+ FLASH : ORIGIN = 0x08000000, LENGTH = 128K
+ BOOTLOADER_STATE : ORIGIN = 0x08020000, LENGTH = 128K
+ ACTIVE : ORIGIN = 0x08040000, LENGTH = 512K
+ DFU : ORIGIN = 0x08100000, LENGTH = 640K
+ RAM (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
+}
+
+__bootloader_state_start = ORIGIN(BOOTLOADER_STATE) - ORIGIN(FLASH);
+__bootloader_state_end = ORIGIN(BOOTLOADER_STATE) + LENGTH(BOOTLOADER_STATE) - ORIGIN(FLASH);
+
+__bootloader_active_start = ORIGIN(ACTIVE) - ORIGIN(FLASH);
+__bootloader_active_end = ORIGIN(ACTIVE) + LENGTH(ACTIVE) - ORIGIN(FLASH);
+
+__bootloader_dfu_start = ORIGIN(DFU) - ORIGIN(DFU);
+__bootloader_dfu_end = ORIGIN(DFU) + LENGTH(DFU) - ORIGIN(DFU);
diff --git a/examples/boot/bootloader/stm32-dual-bank/src/main.rs b/examples/boot/bootloader/stm32-dual-bank/src/main.rs
new file mode 100644
index 000000000..4d2e82d26
--- /dev/null
+++ b/examples/boot/bootloader/stm32-dual-bank/src/main.rs
@@ -0,0 +1,53 @@
+#![no_std]
+#![no_main]
+
+use core::cell::RefCell;
+
+use cortex_m_rt::{entry, exception};
+#[cfg(feature = "defmt")]
+use defmt_rtt as _;
+use embassy_boot_stm32::*;
+use embassy_stm32::flash::{Flash, BANK1_REGION};
+use embassy_sync::blocking_mutex::Mutex;
+
+#[entry]
+fn main() -> ! {
+ let p = embassy_stm32::init(Default::default());
+
+ // Uncomment this if you are debugging the bootloader with debugger/RTT attached,
+ // as it prevents a hard fault when accessing flash 'too early' after boot.
+ /*
+ for i in 0..10000000 {
+ cortex_m::asm::nop();
+ }
+ */
+
+ let layout = Flash::new_blocking(p.FLASH).into_blocking_regions();
+ let flash_bank1 = Mutex::new(RefCell::new(layout.bank1_region));
+ let flash_bank2 = Mutex::new(RefCell::new(layout.bank2_region));
+
+ let config = BootLoaderConfig::from_linkerfile_blocking(&flash_bank1, &flash_bank2, &flash_bank1);
+ let active_offset = config.active.offset();
+ let bl = BootLoader::prepare::<_, _, _, 2048>(config);
+
+ unsafe { bl.load(BANK1_REGION.base + active_offset) }
+}
+
+#[no_mangle]
+#[cfg_attr(target_os = "none", link_section = ".HardFault.user")]
+unsafe extern "C" fn HardFault() {
+ cortex_m::peripheral::SCB::sys_reset();
+}
+
+#[exception]
+unsafe fn DefaultHandler(_: i16) -> ! {
+ const SCB_ICSR: *const u32 = 0xE000_ED04 as *const u32;
+ let irqn = core::ptr::read_volatile(SCB_ICSR) as u8 as i16 - 16;
+
+ panic!("DefaultHandler #{:?}", irqn);
+}
+
+#[panic_handler]
+fn panic(_info: &core::panic::PanicInfo) -> ! {
+ cortex_m::asm::udf();
+}
diff --git a/examples/boot/bootloader/stm32/src/main.rs b/examples/boot/bootloader/stm32/src/main.rs
index 5fd9ea588..99a7a6a6b 100644
--- a/examples/boot/bootloader/stm32/src/main.rs
+++ b/examples/boot/bootloader/stm32/src/main.rs
@@ -25,7 +25,7 @@ fn main() -> ! {
let layout = Flash::new_blocking(p.FLASH).into_blocking_regions();
let flash = Mutex::new(RefCell::new(layout.bank1_region));
- let config = BootLoaderConfig::from_linkerfile_blocking(&flash);
+ let config = BootLoaderConfig::from_linkerfile_blocking(&flash, &flash, &flash);
let active_offset = config.active.offset();
let bl = BootLoader::prepare::<_, _, _, 2048>(config);
diff --git a/examples/boot/bootloader/stm32wb-dfu/src/main.rs b/examples/boot/bootloader/stm32wb-dfu/src/main.rs
index a7ab813b6..d989fbfdf 100644
--- a/examples/boot/bootloader/stm32wb-dfu/src/main.rs
+++ b/examples/boot/bootloader/stm32wb-dfu/src/main.rs
@@ -35,7 +35,7 @@ fn main() -> ! {
let layout = Flash::new_blocking(p.FLASH).into_blocking_regions();
let flash = Mutex::new(RefCell::new(layout.bank1_region));
- let config = BootLoaderConfig::from_linkerfile_blocking(&flash);
+ let config = BootLoaderConfig::from_linkerfile_blocking(&flash, &flash, &flash);
let active_offset = config.active.offset();
let bl = BootLoader::prepare::<_, _, _, 2048>(config);
if bl.state == State::DfuDetach {
@@ -45,7 +45,7 @@ fn main() -> ! {
config.product = Some("USB-DFU Bootloader example");
config.serial_number = Some("1235678");
- let fw_config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash);
+ let fw_config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash, &flash);
let mut buffer = AlignedBuffer([0; WRITE_SIZE]);
let updater = BlockingFirmwareUpdater::new(fw_config, &mut buffer.0[..]);
From b7db75adff16eb0a4670e926dc664549433654fd Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 6 Feb 2024 10:44:52 -0500
Subject: [PATCH 131/392] Updated stm32-metapac.
---
embassy-stm32/Cargo.toml | 4 ++--
tests/stm32/src/bin/hash.rs | 8 ++------
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 63bc32197..ef6063656 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-aa5dbf859fae743306f5d816905f166de824241f" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5674011dd7db845c9d70d6a20a16129221026d25" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-aa5dbf859fae743306f5d816905f166de824241f", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5674011dd7db845c9d70d6a20a16129221026d25", default-features = false, features = ["metadata"]}
[features]
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 53dd0551f..2867115dc 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -11,11 +11,7 @@ use embassy_stm32::{bind_interrupts, hash, peripherals};
use sha2::{Digest, Sha224, Sha256};
use {defmt_rtt as _, panic_probe as _};
-#[cfg(any(
- feature = "stm32l4a6zg",
- feature = "stm32h755zi",
- feature = "stm32h753zi"
-))]
+#[cfg(any(feature = "stm32l4a6zg", feature = "stm32h755zi", feature = "stm32h753zi"))]
bind_interrupts!(struct Irqs {
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
});
@@ -29,7 +25,7 @@ bind_interrupts!(struct Irqs {
))]
bind_interrupts!(struct Irqs {
HASH => hash::InterruptHandler<peripherals::HASH>;
- });
+});
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
From 5f36108896d909ed990a587941d74e0488bcd190 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?xgroleau=F0=9F=90=A2?= <xavgroleau@gmail.com>
Date: Tue, 6 Feb 2024 10:38:48 -0500
Subject: [PATCH 132/392] fix: rtos-usage time missing
---
embassy-executor/Cargo.toml | 4 ++++
embassy-executor/src/raw/mod.rs | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index 409df0d75..0762e2434 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -34,6 +34,7 @@ log = { version = "0.4.14", optional = true }
rtos-trace = { version = "0.1.2", optional = true }
embassy-executor-macros = { version = "0.4.0", path = "../embassy-executor-macros" }
+embassy-time = { version = "0.3.0", path = "../embassy-time", optional = true }
embassy-time-driver = { version = "0.1.0", path = "../embassy-time-driver", optional = true }
embassy-time-queue-driver = { version = "0.1.0", path = "../embassy-time-queue-driver", optional = true }
critical-section = "1.1"
@@ -71,6 +72,9 @@ turbowakers = []
## Use the executor-integrated `embassy-time` timer queue.
integrated-timers = ["dep:embassy-time-driver", "dep:embassy-time-queue-driver"]
+# Support for rtos trace require time
+rtos-trace = ["dep:rtos-trace", "dep:embassy-time"]
+
#! ### Architecture
_arch = [] # some arch was picked
## std
diff --git a/embassy-executor/src/raw/mod.rs b/embassy-executor/src/raw/mod.rs
index 3f00be4a8..fbc0481c2 100644
--- a/embassy-executor/src/raw/mod.rs
+++ b/embassy-executor/src/raw/mod.rs
@@ -588,7 +588,7 @@ impl rtos_trace::RtosTraceOSCallbacks for Executor {
}
#[cfg(feature = "integrated-timers")]
fn time() -> u64 {
- Instant::now().as_micros()
+ embassy_time::Instant::now().as_millis()
}
#[cfg(not(feature = "integrated-timers"))]
fn time() -> u64 {
From bfa67c29932ba9b326da0c661b1b03dcee2ef3fe Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 6 Feb 2024 18:37:48 -0500
Subject: [PATCH 133/392] Fix digest interrupt enable.
---
embassy-stm32/src/hash/v1.rs | 2 +-
embassy-stm32/src/hash/v2v3.rs | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/hash/v1.rs b/embassy-stm32/src/hash/v1.rs
index 50f9adc83..36beb7c3e 100644
--- a/embassy-stm32/src/hash/v1.rs
+++ b/embassy-stm32/src/hash/v1.rs
@@ -215,7 +215,7 @@ impl<'d, T: Instance> Hash<'d, T> {
}
// Register waker, then enable interrupts.
HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dinie(true));
+ T::regs().imr().modify(|reg| reg.set_dcie(true));
// Check for completion.
let bits = T::regs().sr().read();
if bits.dcis() {
diff --git a/embassy-stm32/src/hash/v2v3.rs b/embassy-stm32/src/hash/v2v3.rs
index 058864568..ba1e05f0c 100644
--- a/embassy-stm32/src/hash/v2v3.rs
+++ b/embassy-stm32/src/hash/v2v3.rs
@@ -244,7 +244,7 @@ impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
}
// Register waker, then enable interrupts.
HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dinie(true));
+ T::regs().imr().modify(|reg| reg.set_dcie(true));
// Check for completion.
let bits = T::regs().sr().read();
if bits.dcis() {
From af2b4df833902fa8d42cb133c52733fe0b848bc7 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 11:32:13 +0100
Subject: [PATCH 134/392] refactor(boot): change generics name to match
existing convention
---
embassy-boot/src/boot_loader.rs | 14 +++++++-------
embassy-boot/src/firmware_updater/asynch.rs | 8 ++++----
embassy-boot/src/firmware_updater/blocking.rs | 11 ++++-------
3 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/embassy-boot/src/boot_loader.rs b/embassy-boot/src/boot_loader.rs
index 54ae8a34b..c433ce439 100644
--- a/embassy-boot/src/boot_loader.rs
+++ b/embassy-boot/src/boot_loader.rs
@@ -49,19 +49,19 @@ pub struct BootLoaderConfig<ACTIVE, DFU, STATE> {
pub state: STATE,
}
-impl<'a, ActiveFlash: NorFlash, DFUFlash: NorFlash, StateFlash: NorFlash>
+impl<'a, ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>
BootLoaderConfig<
- BlockingPartition<'a, NoopRawMutex, ActiveFlash>,
- BlockingPartition<'a, NoopRawMutex, DFUFlash>,
- BlockingPartition<'a, NoopRawMutex, StateFlash>,
+ BlockingPartition<'a, NoopRawMutex, ACTIVE>,
+ BlockingPartition<'a, NoopRawMutex, DFU>,
+ BlockingPartition<'a, NoopRawMutex, STATE>,
>
{
/// Create a bootloader config from the flash and address symbols defined in the linkerfile
// #[cfg(target_os = "none")]
pub fn from_linkerfile_blocking(
- active_flash: &'a Mutex<NoopRawMutex, RefCell<ActiveFlash>>,
- dfu_flash: &'a Mutex<NoopRawMutex, RefCell<DFUFlash>>,
- state_flash: &'a Mutex<NoopRawMutex, RefCell<StateFlash>>,
+ active_flash: &'a Mutex<NoopRawMutex, RefCell<ACTIVE>>,
+ dfu_flash: &'a Mutex<NoopRawMutex, RefCell<DFU>>,
+ state_flash: &'a Mutex<NoopRawMutex, RefCell<STATE>>,
) -> Self {
extern "C" {
static __bootloader_state_start: u32;
diff --git a/embassy-boot/src/firmware_updater/asynch.rs b/embassy-boot/src/firmware_updater/asynch.rs
index 5634b48d4..668f16f16 100644
--- a/embassy-boot/src/firmware_updater/asynch.rs
+++ b/embassy-boot/src/firmware_updater/asynch.rs
@@ -16,13 +16,13 @@ pub struct FirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
}
#[cfg(target_os = "none")]
-impl<'a, DFUFlash: NorFlash, StateFlash: NorFlash>
- FirmwareUpdaterConfig<Partition<'a, NoopRawMutex, DFUFlash>, Partition<'a, NoopRawMutex, StateFlash>>
+impl<'a, DFU: NorFlash, STATE: NorFlash>
+ FirmwareUpdaterConfig<Partition<'a, NoopRawMutex, DFU>, Partition<'a, NoopRawMutex, STATE>>
{
/// Create a firmware updater config from the flash and address symbols defined in the linkerfile
pub fn from_linkerfile(
- dfu_flash: &'a embassy_sync::mutex::Mutex<NoopRawMutex, DFUFlash>,
- state_flash: &'a embassy_sync::mutex::Mutex<NoopRawMutex, StateFlash>,
+ dfu_flash: &'a embassy_sync::mutex::Mutex<NoopRawMutex, DFU>,
+ state_flash: &'a embassy_sync::mutex::Mutex<NoopRawMutex, STATE>,
) -> Self {
extern "C" {
static __bootloader_state_start: u32;
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index 3814b6c31..cf850fce3 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -16,16 +16,13 @@ pub struct BlockingFirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
}
#[cfg(target_os = "none")]
-impl<'a, DFUFlash: NorFlash, StateFlash: NorFlash>
- FirmwareUpdaterConfig<
- BlockingPartition<'a, NoopRawMutex, DFUFlash>,
- BlockingPartition<'a, NoopRawMutex, StateFlash>,
- >
+impl<'a, DFU: NorFlash, STATE: NorFlash>
+ FirmwareUpdaterConfig<BlockingPartition<'a, NoopRawMutex, DFU>, BlockingPartition<'a, NoopRawMutex, STATE>>
{
/// Create a firmware updater config from the flash and address symbols defined in the linkerfile
pub fn from_linkerfile_blocking(
- dfu_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<DFUFlash>>,
- state_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<StateFlash>>,
+ dfu_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<DFU>>,
+ state_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<STATE>>,
) -> Self {
extern "C" {
static __bootloader_state_start: u32;
From 4a72f946e42dde3dbfbf46a676d5b40617e4c92f Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 11:38:05 +0100
Subject: [PATCH 135/392] fix(boot): update stm32wb-dfu example readme
---
examples/boot/bootloader/stm32wb-dfu/Cargo.toml | 2 +-
examples/boot/bootloader/stm32wb-dfu/README.md | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/examples/boot/bootloader/stm32wb-dfu/Cargo.toml b/examples/boot/bootloader/stm32wb-dfu/Cargo.toml
index 96635afa2..854f94d85 100644
--- a/examples/boot/bootloader/stm32wb-dfu/Cargo.toml
+++ b/examples/boot/bootloader/stm32wb-dfu/Cargo.toml
@@ -9,7 +9,7 @@ license = "MIT OR Apache-2.0"
defmt = { version = "0.3", optional = true }
defmt-rtt = { version = "0.4", optional = true }
-embassy-stm32 = { path = "../../../../embassy-stm32", features = ["stm32wb55rg"] }
+embassy-stm32 = { path = "../../../../embassy-stm32", features = [] }
embassy-boot-stm32 = { path = "../../../../embassy-boot-stm32" }
cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-single-core"] }
embassy-sync = { version = "0.5.0", path = "../../../../embassy-sync" }
diff --git a/examples/boot/bootloader/stm32wb-dfu/README.md b/examples/boot/bootloader/stm32wb-dfu/README.md
index a82b730b9..d5c6ea57c 100644
--- a/examples/boot/bootloader/stm32wb-dfu/README.md
+++ b/examples/boot/bootloader/stm32wb-dfu/README.md
@@ -7,5 +7,5 @@ The bootloader uses `embassy-boot` to interact with the flash.
Flash the bootloader
```
-cargo flash --features embassy-stm32/stm32wl55jc-cm4 --release --chip STM32WLE5JCIx
+cargo flash --features embassy-stm32/stm32wb55rg --release --chip STM32WB55RGVx
```
From cfc3e966331310b7210c94339cf8f111a65d9e53 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 12:50:48 +0100
Subject: [PATCH 136/392] fix(boot): update examples
---
examples/boot/application/nrf/src/bin/a.rs | 2 +-
examples/boot/application/rp/src/bin/a.rs | 2 +-
examples/boot/application/stm32f3/memory.x | 4 ++--
.../boot/application/stm32f3/src/bin/a.rs | 2 +-
.../boot/application/stm32f7/src/bin/a.rs | 2 +-
.../boot/application/stm32h7/src/bin/a.rs | 2 +-
examples/boot/application/stm32l0/memory.x | 4 ++--
.../boot/application/stm32l0/src/bin/a.rs | 2 +-
examples/boot/application/stm32l1/memory.x | 4 ++--
.../boot/application/stm32l1/src/bin/a.rs | 2 +-
examples/boot/application/stm32l4/memory.x | 4 ++--
.../boot/application/stm32l4/src/bin/a.rs | 2 +-
.../boot/application/stm32wb-dfu/README.md | 24 ++-----------------
.../boot/application/stm32wb-dfu/src/main.rs | 2 +-
examples/boot/application/stm32wl/memory.x | 4 ++--
.../boot/application/stm32wl/src/bin/a.rs | 2 +-
examples/boot/bootloader/nrf/src/main.rs | 2 +-
examples/boot/bootloader/rp/src/main.rs | 2 +-
18 files changed, 24 insertions(+), 44 deletions(-)
diff --git a/examples/boot/application/nrf/src/bin/a.rs b/examples/boot/application/nrf/src/bin/a.rs
index f3abfddbc..851a3d721 100644
--- a/examples/boot/application/nrf/src/bin/a.rs
+++ b/examples/boot/application/nrf/src/bin/a.rs
@@ -50,7 +50,7 @@ async fn main(_spawner: Spawner) {
let nvmc = Nvmc::new(p.NVMC);
let nvmc = Mutex::new(BlockingAsync::new(nvmc));
- let config = FirmwareUpdaterConfig::from_linkerfile(&nvmc);
+ let config = FirmwareUpdaterConfig::from_linkerfile(&nvmc, &nvmc);
let mut magic = [0; 4];
let mut updater = FirmwareUpdater::new(config, &mut magic);
loop {
diff --git a/examples/boot/application/rp/src/bin/a.rs b/examples/boot/application/rp/src/bin/a.rs
index 3f0bf90e2..ede0c07da 100644
--- a/examples/boot/application/rp/src/bin/a.rs
+++ b/examples/boot/application/rp/src/bin/a.rs
@@ -36,7 +36,7 @@ async fn main(_s: Spawner) {
let flash = Flash::<_, _, FLASH_SIZE>::new_blocking(p.FLASH);
let flash = Mutex::new(RefCell::new(flash));
- let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash, &flash);
let mut aligned = AlignedBuffer([0; 1]);
let mut updater = BlockingFirmwareUpdater::new(config, &mut aligned.0);
diff --git a/examples/boot/application/stm32f3/memory.x b/examples/boot/application/stm32f3/memory.x
index f51875766..02ebe3ecf 100644
--- a/examples/boot/application/stm32f3/memory.x
+++ b/examples/boot/application/stm32f3/memory.x
@@ -3,8 +3,8 @@ MEMORY
/* NOTE 1 K = 1 KiBi = 1024 bytes */
BOOTLOADER : ORIGIN = 0x08000000, LENGTH = 24K
BOOTLOADER_STATE : ORIGIN = 0x08006000, LENGTH = 4K
- FLASH : ORIGIN = 0x08008000, LENGTH = 32K
- DFU : ORIGIN = 0x08010000, LENGTH = 36K
+ FLASH : ORIGIN = 0x08008000, LENGTH = 64K
+ DFU : ORIGIN = 0x08018000, LENGTH = 66K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
}
diff --git a/examples/boot/application/stm32f3/src/bin/a.rs b/examples/boot/application/stm32f3/src/bin/a.rs
index 3f9ebe5c8..8858ae3da 100644
--- a/examples/boot/application/stm32f3/src/bin/a.rs
+++ b/examples/boot/application/stm32f3/src/bin/a.rs
@@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) {
let mut led = Output::new(p.PA5, Level::Low, Speed::Low);
led.set_high();
- let config = FirmwareUpdaterConfig::from_linkerfile(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut updater = FirmwareUpdater::new(config, &mut magic.0);
button.wait_for_falling_edge().await;
diff --git a/examples/boot/application/stm32f7/src/bin/a.rs b/examples/boot/application/stm32f7/src/bin/a.rs
index c57c29263..d3df11fe4 100644
--- a/examples/boot/application/stm32f7/src/bin/a.rs
+++ b/examples/boot/application/stm32f7/src/bin/a.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
let mut led = Output::new(p.PB7, Level::Low, Speed::Low);
led.set_high();
- let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut updater = BlockingFirmwareUpdater::new(config, &mut magic.0);
let writer = updater.prepare_update().unwrap();
diff --git a/examples/boot/application/stm32h7/src/bin/a.rs b/examples/boot/application/stm32h7/src/bin/a.rs
index a00d17408..f61ac1f71 100644
--- a/examples/boot/application/stm32h7/src/bin/a.rs
+++ b/examples/boot/application/stm32h7/src/bin/a.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
let mut led = Output::new(p.PB14, Level::Low, Speed::Low);
led.set_high();
- let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut updater = BlockingFirmwareUpdater::new(config, &mut magic.0);
let writer = updater.prepare_update().unwrap();
diff --git a/examples/boot/application/stm32l0/memory.x b/examples/boot/application/stm32l0/memory.x
index a99330145..8866506a8 100644
--- a/examples/boot/application/stm32l0/memory.x
+++ b/examples/boot/application/stm32l0/memory.x
@@ -3,8 +3,8 @@ MEMORY
/* NOTE 1 K = 1 KiBi = 1024 bytes */
BOOTLOADER : ORIGIN = 0x08000000, LENGTH = 24K
BOOTLOADER_STATE : ORIGIN = 0x08006000, LENGTH = 4K
- FLASH : ORIGIN = 0x08008000, LENGTH = 32K
- DFU : ORIGIN = 0x08010000, LENGTH = 36K
+ FLASH : ORIGIN = 0x08008000, LENGTH = 64K
+ DFU : ORIGIN = 0x08018000, LENGTH = 66K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
}
diff --git a/examples/boot/application/stm32l0/src/bin/a.rs b/examples/boot/application/stm32l0/src/bin/a.rs
index dbec49d44..f066c1139 100644
--- a/examples/boot/application/stm32l0/src/bin/a.rs
+++ b/examples/boot/application/stm32l0/src/bin/a.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
led.set_high();
- let config = FirmwareUpdaterConfig::from_linkerfile(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut updater = FirmwareUpdater::new(config, &mut magic.0);
button.wait_for_falling_edge().await;
diff --git a/examples/boot/application/stm32l1/memory.x b/examples/boot/application/stm32l1/memory.x
index a99330145..caa525278 100644
--- a/examples/boot/application/stm32l1/memory.x
+++ b/examples/boot/application/stm32l1/memory.x
@@ -3,8 +3,8 @@ MEMORY
/* NOTE 1 K = 1 KiBi = 1024 bytes */
BOOTLOADER : ORIGIN = 0x08000000, LENGTH = 24K
BOOTLOADER_STATE : ORIGIN = 0x08006000, LENGTH = 4K
- FLASH : ORIGIN = 0x08008000, LENGTH = 32K
- DFU : ORIGIN = 0x08010000, LENGTH = 36K
+ FLASH : ORIGIN = 0x08008000, LENGTH = 46K
+ DFU : ORIGIN = 0x08013800, LENGTH = 54K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
}
diff --git a/examples/boot/application/stm32l1/src/bin/a.rs b/examples/boot/application/stm32l1/src/bin/a.rs
index dbec49d44..f066c1139 100644
--- a/examples/boot/application/stm32l1/src/bin/a.rs
+++ b/examples/boot/application/stm32l1/src/bin/a.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
led.set_high();
- let config = FirmwareUpdaterConfig::from_linkerfile(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut updater = FirmwareUpdater::new(config, &mut magic.0);
button.wait_for_falling_edge().await;
diff --git a/examples/boot/application/stm32l4/memory.x b/examples/boot/application/stm32l4/memory.x
index f51875766..e1d4e7fa8 100644
--- a/examples/boot/application/stm32l4/memory.x
+++ b/examples/boot/application/stm32l4/memory.x
@@ -3,8 +3,8 @@ MEMORY
/* NOTE 1 K = 1 KiBi = 1024 bytes */
BOOTLOADER : ORIGIN = 0x08000000, LENGTH = 24K
BOOTLOADER_STATE : ORIGIN = 0x08006000, LENGTH = 4K
- FLASH : ORIGIN = 0x08008000, LENGTH = 32K
- DFU : ORIGIN = 0x08010000, LENGTH = 36K
+ FLASH : ORIGIN = 0x08008000, LENGTH = 64K
+ DFU : ORIGIN = 0x08018000, LENGTH = 68K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
}
diff --git a/examples/boot/application/stm32l4/src/bin/a.rs b/examples/boot/application/stm32l4/src/bin/a.rs
index e946c3cdf..a0079ee33 100644
--- a/examples/boot/application/stm32l4/src/bin/a.rs
+++ b/examples/boot/application/stm32l4/src/bin/a.rs
@@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) {
let mut led = Output::new(p.PB14, Level::Low, Speed::Low);
led.set_high();
- let config = FirmwareUpdaterConfig::from_linkerfile(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut updater = FirmwareUpdater::new(config, &mut magic.0);
button.wait_for_falling_edge().await;
diff --git a/examples/boot/application/stm32wb-dfu/README.md b/examples/boot/application/stm32wb-dfu/README.md
index c8dce0387..7f656cde6 100644
--- a/examples/boot/application/stm32wb-dfu/README.md
+++ b/examples/boot/application/stm32wb-dfu/README.md
@@ -1,29 +1,9 @@
# Examples using bootloader
-Example for STM32WL demonstrating the bootloader. The example consists of application binaries, 'a'
-which allows you to press a button to start the DFU process, and 'b' which is the updated
-application.
-
-
-## Prerequisites
-
-* `cargo-binutils`
-* `cargo-flash`
-* `embassy-boot-stm32`
+Example for STM32WB demonstrating the USB DFU application.
## Usage
```
-# Flash bootloader
-cargo flash --manifest-path ../../bootloader/stm32/Cargo.toml --release --features embassy-stm32/stm32wl55jc-cm4 --chip STM32WLE5JCIx
-# Build 'b'
-cargo build --release --bin b
-# Generate binary for 'b'
-cargo objcopy --release --bin b -- -O binary b.bin
-```
-
-# Flash `a` (which includes b.bin)
-
-```
-cargo flash --release --bin a --chip STM32WLE5JCIx
+cargo flash --release --chip STM32WB55RGVx
```
diff --git a/examples/boot/application/stm32wb-dfu/src/main.rs b/examples/boot/application/stm32wb-dfu/src/main.rs
index b2ccb9e1a..37c3d7d90 100644
--- a/examples/boot/application/stm32wb-dfu/src/main.rs
+++ b/examples/boot/application/stm32wb-dfu/src/main.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
let flash = Flash::new_blocking(p.FLASH);
let flash = Mutex::new(RefCell::new(flash));
- let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut firmware_state = BlockingFirmwareState::from_config(config, &mut magic.0);
firmware_state.mark_booted().expect("Failed to mark booted");
diff --git a/examples/boot/application/stm32wl/memory.x b/examples/boot/application/stm32wl/memory.x
index f51875766..e1d4e7fa8 100644
--- a/examples/boot/application/stm32wl/memory.x
+++ b/examples/boot/application/stm32wl/memory.x
@@ -3,8 +3,8 @@ MEMORY
/* NOTE 1 K = 1 KiBi = 1024 bytes */
BOOTLOADER : ORIGIN = 0x08000000, LENGTH = 24K
BOOTLOADER_STATE : ORIGIN = 0x08006000, LENGTH = 4K
- FLASH : ORIGIN = 0x08008000, LENGTH = 32K
- DFU : ORIGIN = 0x08010000, LENGTH = 36K
+ FLASH : ORIGIN = 0x08008000, LENGTH = 64K
+ DFU : ORIGIN = 0x08018000, LENGTH = 68K
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
}
diff --git a/examples/boot/application/stm32wl/src/bin/a.rs b/examples/boot/application/stm32wl/src/bin/a.rs
index b582d8b25..2fb16bdc4 100644
--- a/examples/boot/application/stm32wl/src/bin/a.rs
+++ b/examples/boot/application/stm32wl/src/bin/a.rs
@@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) {
let mut led = Output::new(p.PB9, Level::Low, Speed::Low);
led.set_high();
- let config = FirmwareUpdaterConfig::from_linkerfile(&flash);
+ let config = FirmwareUpdaterConfig::from_linkerfile(&flash, &flash);
let mut magic = AlignedBuffer([0; WRITE_SIZE]);
let mut updater = FirmwareUpdater::new(config, &mut magic.0);
button.wait_for_falling_edge().await;
diff --git a/examples/boot/bootloader/nrf/src/main.rs b/examples/boot/bootloader/nrf/src/main.rs
index 74e2e293f..67c700437 100644
--- a/examples/boot/bootloader/nrf/src/main.rs
+++ b/examples/boot/bootloader/nrf/src/main.rs
@@ -31,7 +31,7 @@ fn main() -> ! {
let flash = WatchdogFlash::start(Nvmc::new(p.NVMC), p.WDT, wdt_config);
let flash = Mutex::new(RefCell::new(flash));
- let config = BootLoaderConfig::from_linkerfile_blocking(&flash);
+ let config = BootLoaderConfig::from_linkerfile_blocking(&flash, &flash, &flash);
let active_offset = config.active.offset();
let bl: BootLoader = BootLoader::prepare(config);
diff --git a/examples/boot/bootloader/rp/src/main.rs b/examples/boot/bootloader/rp/src/main.rs
index c0e75d1ea..25b1657b8 100644
--- a/examples/boot/bootloader/rp/src/main.rs
+++ b/examples/boot/bootloader/rp/src/main.rs
@@ -27,7 +27,7 @@ fn main() -> ! {
let flash = WatchdogFlash::<FLASH_SIZE>::start(p.FLASH, p.WATCHDOG, Duration::from_secs(8));
let flash = Mutex::new(RefCell::new(flash));
- let config = BootLoaderConfig::from_linkerfile_blocking(&flash);
+ let config = BootLoaderConfig::from_linkerfile_blocking(&flash, &flash, &flash);
let active_offset = config.active.offset();
let bl: BootLoader = BootLoader::prepare(config);
From 634c409c55c71ca2871cd05d4a7754654926db48 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 13:06:48 +0100
Subject: [PATCH 137/392] docs(boot): document from_linkerfile_blocking method
---
embassy-boot/src/boot_loader.rs | 33 ++++++++++++++++++-
embassy-boot/src/firmware_updater/blocking.rs | 32 +++++++++++++++++-
2 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/embassy-boot/src/boot_loader.rs b/embassy-boot/src/boot_loader.rs
index c433ce439..2a5f024f6 100644
--- a/embassy-boot/src/boot_loader.rs
+++ b/embassy-boot/src/boot_loader.rs
@@ -56,7 +56,38 @@ impl<'a, ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>
BlockingPartition<'a, NoopRawMutex, STATE>,
>
{
- /// Create a bootloader config from the flash and address symbols defined in the linkerfile
+ /// Constructs a `BootLoaderConfig` instance from flash memory and address symbols defined in the linker file.
+ ///
+ /// This method initializes `BlockingPartition` instances for the active, DFU (Device Firmware Update),
+ /// and state partitions, leveraging start and end addresses specified by the linker. These partitions
+ /// are critical for managing firmware updates, application state, and boot operations within the bootloader.
+ ///
+ /// # Parameters
+ /// - `active_flash`: A reference to a mutex-protected `RefCell` for the active partition's flash interface.
+ /// - `dfu_flash`: A reference to a mutex-protected `RefCell` for the DFU partition's flash interface.
+ /// - `state_flash`: A reference to a mutex-protected `RefCell` for the state partition's flash interface.
+ ///
+ /// # Safety
+ /// The method contains `unsafe` blocks for dereferencing raw pointers that represent the start and end addresses
+ /// of the bootloader's partitions in flash memory. It is crucial that these addresses are accurately defined
+ /// in the memory.x file to prevent undefined behavior.
+ ///
+ /// The caller must ensure that the memory regions defined by these symbols are valid and that the flash memory
+ /// interfaces provided are compatible with these regions.
+ ///
+ /// # Returns
+ /// A `BootLoaderConfig` instance with `BlockingPartition` instances for the active, DFU, and state partitions.
+ ///
+ /// # Example
+ /// ```no_run
+ /// // Assume `active_flash`, `dfu_flash`, and `state_flash` all share the same flash memory interface.
+ /// let layout = Flash::new_blocking(p.FLASH).into_blocking_regions();
+ /// let flash = Mutex::new(RefCell::new(layout.bank1_region));
+ ///
+ /// let config = BootLoaderConfig::from_linkerfile_blocking(&flash, &flash, &flash);
+ /// // `config` can now be used to create a `BootLoader` instance for managing boot operations.
+ /// ```
+ /// Working examples can be found in the bootloader examples folder.
// #[cfg(target_os = "none")]
pub fn from_linkerfile_blocking(
active_flash: &'a Mutex<NoopRawMutex, RefCell<ACTIVE>>,
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index cf850fce3..a29efabf0 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -19,7 +19,37 @@ pub struct BlockingFirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
impl<'a, DFU: NorFlash, STATE: NorFlash>
FirmwareUpdaterConfig<BlockingPartition<'a, NoopRawMutex, DFU>, BlockingPartition<'a, NoopRawMutex, STATE>>
{
- /// Create a firmware updater config from the flash and address symbols defined in the linkerfile
+ /// Constructs a `FirmwareUpdaterConfig` instance from flash memory and address symbols defined in the linker file.
+ ///
+ /// This method initializes `BlockingPartition` instances for the DFU (Device Firmware Update), and state
+ /// partitions, leveraging start and end addresses specified by the linker. These partitions are critical
+ /// for managing firmware updates, application state, and boot operations within the bootloader.
+ ///
+ /// # Parameters
+ /// - `dfu_flash`: A reference to a mutex-protected `RefCell` for the DFU partition's flash interface.
+ /// - `state_flash`: A reference to a mutex-protected `RefCell` for the state partition's flash interface.
+ ///
+ /// # Safety
+ /// The method contains `unsafe` blocks for dereferencing raw pointers that represent the start and end addresses
+ /// of the bootloader's partitions in flash memory. It is crucial that these addresses are accurately defined
+ /// in the memory.x file to prevent undefined behavior.
+ ///
+ /// The caller must ensure that the memory regions defined by these symbols are valid and that the flash memory
+ /// interfaces provided are compatible with these regions.
+ ///
+ /// # Returns
+ /// A `FirmwareUpdaterConfig` instance with `BlockingPartition` instances for the DFU, and state partitions.
+ ///
+ /// # Example
+ /// ```no_run
+ /// // Assume `dfu_flash`, and `state_flash` share the same flash memory interface.
+ /// let layout = Flash::new_blocking(p.FLASH).into_blocking_regions();
+ /// let flash = Mutex::new(RefCell::new(layout.bank1_region));
+ ///
+ /// let config = FirmwareUpdaterConfig::from_linkerfile_blocking(&flash, &flash);
+ /// // `config` can now be used to create a `FirmwareUpdater` instance for managing boot operations.
+ /// ```
+ /// Working examples can be found in the bootloader examples folder.
pub fn from_linkerfile_blocking(
dfu_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<DFU>>,
state_flash: &'a embassy_sync::blocking_mutex::Mutex<NoopRawMutex, core::cell::RefCell<STATE>>,
From e391b9b74c95090548c50b6f05a859f0220c42f9 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 14:37:38 +0100
Subject: [PATCH 138/392] docs(boot): ignore partial non-compilable example in
rustdoc
---
embassy-boot/src/boot_loader.rs | 2 +-
embassy-boot/src/firmware_updater/blocking.rs | 2 +-
embassy-boot/src/firmware_updater/mod.rs | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/embassy-boot/src/boot_loader.rs b/embassy-boot/src/boot_loader.rs
index 2a5f024f6..ca1a1b10c 100644
--- a/embassy-boot/src/boot_loader.rs
+++ b/embassy-boot/src/boot_loader.rs
@@ -79,7 +79,7 @@ impl<'a, ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>
/// A `BootLoaderConfig` instance with `BlockingPartition` instances for the active, DFU, and state partitions.
///
/// # Example
- /// ```no_run
+ /// ```ignore
/// // Assume `active_flash`, `dfu_flash`, and `state_flash` all share the same flash memory interface.
/// let layout = Flash::new_blocking(p.FLASH).into_blocking_regions();
/// let flash = Mutex::new(RefCell::new(layout.bank1_region));
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index a29efabf0..4044871f0 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -41,7 +41,7 @@ impl<'a, DFU: NorFlash, STATE: NorFlash>
/// A `FirmwareUpdaterConfig` instance with `BlockingPartition` instances for the DFU, and state partitions.
///
/// # Example
- /// ```no_run
+ /// ```ignore
/// // Assume `dfu_flash`, and `state_flash` share the same flash memory interface.
/// let layout = Flash::new_blocking(p.FLASH).into_blocking_regions();
/// let flash = Mutex::new(RefCell::new(layout.bank1_region));
diff --git a/embassy-boot/src/firmware_updater/mod.rs b/embassy-boot/src/firmware_updater/mod.rs
index 4814786bf..4c4f4f10b 100644
--- a/embassy-boot/src/firmware_updater/mod.rs
+++ b/embassy-boot/src/firmware_updater/mod.rs
@@ -8,7 +8,7 @@ use embedded_storage::nor_flash::{NorFlashError, NorFlashErrorKind};
/// Firmware updater flash configuration holding the two flashes used by the updater
///
/// If only a single flash is actually used, then that flash should be partitioned into two partitions before use.
-/// The easiest way to do this is to use [`FirmwareUpdaterConfig::from_linkerfile`] or [`FirmwareUpdaterConfig::from_linkerfile_blocking`] which will partition
+/// The easiest way to do this is to use [`FirmwareUpdaterConfig::from_linkerfile_blocking`] or [`FirmwareUpdaterConfig::from_linkerfile_blocking`] which will partition
/// the provided flash according to symbols defined in the linkerfile.
pub struct FirmwareUpdaterConfig<DFU, STATE> {
/// The dfu flash partition
From 74fbe27a87fc95f75f8c9251520a8dea889159cc Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 14:55:08 +0100
Subject: [PATCH 139/392] ci(boot): add new example and fix
bootloader/stm32wb-dfu
---
ci.sh | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/ci.sh b/ci.sh
index df9e09848..f3742ad76 100755
--- a/ci.sh
+++ b/ci.sh
@@ -194,7 +194,8 @@ cargo batch \
--- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns \
--- build --release --manifest-path examples/boot/bootloader/rp/Cargo.toml --target thumbv6m-none-eabi \
--- build --release --manifest-path examples/boot/bootloader/stm32/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32wl55jc-cm4 \
- --- build --release --manifest-path examples/boot/bootloader/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabihf \
+ --- build --release --manifest-path examples/boot/bootloader/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabihf --features embassy-stm32/stm32wb55rg \
+ --- build --release --manifest-path examples/boot/bootloader/stm32-dual-bank/Cargo.toml --target thumbv7em-none-eabihf --features embassy-stm32/stm32h747xi-cm7 \
--- build --release --manifest-path examples/wasm/Cargo.toml --target wasm32-unknown-unknown --out-dir out/examples/wasm \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103c8 --out-dir out/tests/stm32f103c8 \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi --out-dir out/tests/stm32f429zi \
From 847b8be81480b249a2e8b1ff502e6188d2dadf04 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 7 Feb 2024 15:25:07 +0100
Subject: [PATCH 140/392] feat/implement ble radio on nrf
---
embassy-nrf/Cargo.toml | 5 +
embassy-nrf/src/chips/nrf52805.rs | 6 +
embassy-nrf/src/chips/nrf52810.rs | 6 +
embassy-nrf/src/chips/nrf52811.rs | 6 +
embassy-nrf/src/chips/nrf52820.rs | 6 +
embassy-nrf/src/chips/nrf52832.rs | 6 +
embassy-nrf/src/chips/nrf52833.rs | 6 +
embassy-nrf/src/chips/nrf52840.rs | 6 +
embassy-nrf/src/chips/nrf5340_net.rs | 6 +
embassy-nrf/src/lib.rs | 6 +
embassy-nrf/src/radio/ble.rs | 432 ++++++++++++++++++
embassy-nrf/src/radio/mod.rs | 89 ++++
examples/nrf52840/Cargo.toml | 8 +-
.../nrf52840/src/bin/radio_ble_advertising.rs | 42 ++
14 files changed, 628 insertions(+), 2 deletions(-)
create mode 100644 embassy-nrf/src/radio/ble.rs
create mode 100644 embassy-nrf/src/radio/mod.rs
create mode 100644 examples/nrf52840/src/bin/radio_ble_advertising.rs
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 7e161df9b..dcdc7f313 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -57,6 +57,9 @@ unstable-pac = []
## Enable GPIO tasks and events
gpiote = []
+## Enable radio driver
+radio = ["dep:jewel"]
+
## Use RTC1 as the time driver for `embassy-time`, with a tick rate of 32.768khz
time-driver-rtc1 = ["_time-driver"]
@@ -150,6 +153,8 @@ embedded-storage-async = "0.4.0"
cfg-if = "1.0.0"
document-features = "0.2.7"
+jewel = { version = "0.1.0", git = "https://github.com/jewel-rs/jewel", optional = true }
+
nrf51-pac = { version = "0.12.0", optional = true }
nrf52805-pac = { version = "0.12.0", optional = true }
nrf52810-pac = { version = "0.12.0", optional = true }
diff --git a/embassy-nrf/src/chips/nrf52805.rs b/embassy-nrf/src/chips/nrf52805.rs
index 624d6613d..b97c85f9e 100644
--- a/embassy-nrf/src/chips/nrf52805.rs
+++ b/embassy-nrf/src/chips/nrf52805.rs
@@ -129,6 +129,9 @@ embassy_hal_internal::peripherals! {
// QDEC
QDEC,
+
+ // RADIO
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -209,6 +212,9 @@ impl_ppi_channel!(PPI_CH31, 31 => static);
impl_saadc_input!(P0_04, ANALOG_INPUT2);
impl_saadc_input!(P0_05, ANALOG_INPUT3);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52810.rs b/embassy-nrf/src/chips/nrf52810.rs
index 002feab3b..03548d03f 100644
--- a/embassy-nrf/src/chips/nrf52810.rs
+++ b/embassy-nrf/src/chips/nrf52810.rs
@@ -135,6 +135,9 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
+
+ // Radio
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -235,6 +238,9 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52811.rs b/embassy-nrf/src/chips/nrf52811.rs
index 5952907f8..992fbd129 100644
--- a/embassy-nrf/src/chips/nrf52811.rs
+++ b/embassy-nrf/src/chips/nrf52811.rs
@@ -135,6 +135,9 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
+
+ // Radio
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -237,6 +240,9 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52820.rs b/embassy-nrf/src/chips/nrf52820.rs
index c2f792cb9..f241f4ea3 100644
--- a/embassy-nrf/src/chips/nrf52820.rs
+++ b/embassy-nrf/src/chips/nrf52820.rs
@@ -130,6 +130,9 @@ embassy_hal_internal::peripherals! {
// QDEC
QDEC,
+
+ // Radio
+ RADIO,
}
impl_usb!(USBD, USBD, USBD);
@@ -224,6 +227,9 @@ impl_ppi_channel!(PPI_CH29, 29 => static);
impl_ppi_channel!(PPI_CH30, 30 => static);
impl_ppi_channel!(PPI_CH31, 31 => static);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs
index 65d52364d..6bbdd9a63 100644
--- a/embassy-nrf/src/chips/nrf52832.rs
+++ b/embassy-nrf/src/chips/nrf52832.rs
@@ -150,6 +150,9 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
+
+ // Radio
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -264,6 +267,9 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs
index 7c9b66d69..e137e4dc6 100644
--- a/embassy-nrf/src/chips/nrf52833.rs
+++ b/embassy-nrf/src/chips/nrf52833.rs
@@ -170,6 +170,9 @@ embassy_hal_internal::peripherals! {
// I2S
I2S,
+
+ // Radio
+ RADIO,
}
impl_usb!(USBD, USBD, USBD);
@@ -306,6 +309,9 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52840.rs b/embassy-nrf/src/chips/nrf52840.rs
index 51c55cd4d..2d805f871 100644
--- a/embassy-nrf/src/chips/nrf52840.rs
+++ b/embassy-nrf/src/chips/nrf52840.rs
@@ -173,6 +173,9 @@ embassy_hal_internal::peripherals! {
// I2S
I2S,
+
+ // Radio
+ RADIO,
}
impl_usb!(USBD, USBD, USBD);
@@ -311,6 +314,9 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
index a7cf82872..3248bde52 100644
--- a/embassy-nrf/src/chips/nrf5340_net.rs
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -248,6 +248,9 @@ embassy_hal_internal::peripherals! {
P1_13,
P1_14,
P1_15,
+
+ // Radio
+ RADIO,
}
impl_uarte!(SERIAL0, UARTE0, SERIAL0);
@@ -345,6 +348,9 @@ impl_ppi_channel!(PPI_CH29, 29 => configurable);
impl_ppi_channel!(PPI_CH30, 30 => configurable);
impl_ppi_channel!(PPI_CH31, 31 => configurable);
+#[cfg(feature = "radio")]
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
CLOCK_POWER,
RADIO,
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 358a7cc27..961928d11 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -45,6 +45,12 @@ pub mod buffered_uarte;
pub mod gpio;
#[cfg(feature = "gpiote")]
pub mod gpiote;
+
+#[cfg(feature = "radio")]
+pub mod radio;
+#[cfg(all(feature = "radio", feature = "_nrf9160"))]
+compile_error!("feature `radio` is not valid for nRF91 series chips.");
+
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
pub mod i2s;
pub mod nvmc;
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
new file mode 100644
index 000000000..a5d9f447b
--- /dev/null
+++ b/embassy-nrf/src/radio/ble.rs
@@ -0,0 +1,432 @@
+//! Radio driver implementation focused on Bluetooth Low-Energy transmission.
+//!
+//! The radio can calculate the CRC, perform data whitening,
+//! automatically send the right preamble.
+//! Most of the configuration is done automatically when you choose the mode and this driver.
+//!
+//! Some configuration can just be done when de device is disabled,
+//! and the configuration varies depending if is a transmitter or a receiver.
+//! Because of that we have a state machine to keep track of the state of the radio.
+//! The Radio is the disable radio which configure the common parameters between
+//! the bluetooth protocols, like the package format, the CRC and the whitening.
+//! The TxRadio radio enable and configured as a transmitter with the specific parameters.
+
+use core::future::poll_fn;
+use core::sync::atomic::{compiler_fence, Ordering};
+use core::task::Poll;
+
+use embassy_hal_internal::drop::OnDrop;
+use embassy_hal_internal::{into_ref, PeripheralRef};
+use jewel::phy::{
+ AdvertisingChannel, Channel, ChannelTrait, HeaderSize, Mode, Radio as BleRadio, ADV_ADDRESS, ADV_CRC_INIT,
+ CRC_POLY, MAX_PDU_LENGTH,
+};
+use pac::radio::mode::MODE_A as PacMode;
+use pac::radio::pcnf0::PLEN_A as PreambleLength;
+// Re-export SVD variants to allow user to directly set values.
+pub use pac::radio::{state::STATE_A as RadioState, txpower::TXPOWER_A as TxPower};
+
+use crate::interrupt::typelevel::Interrupt;
+use crate::radio::*;
+use crate::util::slice_in_ram_or;
+
+/// UART error.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+ /// Buffer was too long.
+ BufferTooLong,
+ /// Buffer was to short.
+ BufferTooShort,
+ /// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
+ BufferNotInRAM,
+}
+
+/// Radio driver.
+pub struct Radio<'d, T: Instance> {
+ _p: PeripheralRef<'d, T>,
+}
+
+impl<'d, T: Instance> Radio<'d, T> {
+ /// Create a new radio driver.
+ pub fn new(
+ radio: impl Peripheral<P = T> + 'd,
+ _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+ ) -> Self {
+ // From 5.4.1 of the nRF52840 Product Specification:
+ // > The HFXO must be running to use the RADIO or the calibration mechanism associated with the 32.768 kHz RC oscillator.
+ // Currently the jewel crate don't implement the calibration mechanism, so we need to ensure that the HFXO is running
+ utils::check_xtal();
+
+ into_ref!(radio);
+
+ let r = T::regs();
+
+ r.pcnf1.write(|w| unsafe {
+ // It is 0 bytes long in a standard BLE packet
+ w.statlen()
+ .bits(0)
+ // MaxLen configures the maximum packet payload plus add-on size in
+ // number of bytes that can be transmitted or received by the RADIO. This feature can be used to ensure
+ // that the RADIO does not overwrite, or read beyond, the RAM assigned to the packet payload. This means
+ // that if the packet payload length defined by PCNF1.STATLEN and the LENGTH field in the packet specifies a
+ // packet larger than MAXLEN, the payload will be truncated at MAXLEN
+ //
+ // To simplify the implementation, I'm setting the max length to the maximum value
+ // and I'm using only the length field to truncate the payload
+ .maxlen()
+ .bits(255)
+ // Configure the length of the address field in the packet
+ // The prefix after the address fields is always appended, so is always 1 byte less than the size of the address
+ // The base address is truncated from the least significant byte if the BALEN is less than 4
+ //
+ // BLE address is always 4 bytes long
+ .balen()
+ .bits(3) // 3 bytes base address (+ 1 prefix);
+ // Configure the endianess
+ // For BLE is always little endian (LSB first)
+ .endian()
+ .little()
+ // Data whitening is used to avoid long sequences of zeros or
+ // ones, e.g., 0b0000000 or 0b1111111, in the data bit stream.
+ // The whitener and de-whitener are defined the same way,
+ // using a 7-bit linear feedback shift register with the
+ // polynomial x7 + x4 + 1.
+ //
+ // In BLE Whitening shall be applied on the PDU and CRC of all
+ // Link Layer packets and is performed after the CRC generation
+ // in the transmitter. No other parts of the packets are whitened.
+ // De-whitening is performed before the CRC checking in the receiver
+ // Before whitening or de-whitening, the shift register should be
+ // initialized based on the channel index.
+ .whiteen()
+ .set_bit() // Enable whitening
+ });
+
+ // Configure CRC
+ r.crccnf.write(|w| {
+ // In BLE the CRC shall be calculated on the PDU of all Link Layer
+ // packets (even if the packet is encrypted).
+ // So here we skip the address field
+ w.skipaddr()
+ .skip()
+ // In BLE 24-bit CRC = 3 bytes
+ .len()
+ .three()
+ });
+
+ r.crcpoly.write(|w| unsafe {
+ // Configure the CRC polynomial
+ // Each term in the CRC polynomial is mapped to a bit in this
+ // register which index corresponds to the term's exponent.
+ // The least significant term/bit is hard-wired internally to
+ // 1, and bit number 0 of the register content is ignored by
+ // the hardware. The following example is for an 8 bit CRC
+ // polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .
+ w.crcpoly().bits(CRC_POLY & 0xFFFFFF)
+ });
+ // The CRC initial value varies depending of the PDU type
+
+ // Ch map between 2400 MHZ .. 2500 MHz
+ // All modes use this range
+ r.frequency.write(|w| w.map().default());
+
+ // Configure shortcuts to simplify and speed up sending and receiving packets.
+ r.shorts.write(|w| {
+ // start transmission/recv immediately after ramp-up
+ // disable radio when transmission/recv is done
+ w.ready_start().enabled().end_disable().enabled()
+ });
+
+ // Enable NVIC interrupt
+ T::Interrupt::unpend();
+ unsafe { T::Interrupt::enable() };
+
+ let mut radio = Self { _p: radio };
+
+ // set defaults
+ radio.set_mode(Mode::Ble1mbit);
+ radio.set_tx_power(0);
+ radio.set_header_size(HeaderSize::TwoBytes);
+ radio.set_access_address(ADV_ADDRESS);
+ radio.set_crc_init(ADV_CRC_INIT);
+ radio.set_channel(AdvertisingChannel::Ch39.into());
+
+ radio
+ }
+
+ #[allow(dead_code)]
+ fn trace_state(&self) {
+ let r = T::regs();
+
+ match r.state.read().state().variant().unwrap() {
+ RadioState::DISABLED => trace!("radio:state:DISABLED"),
+ RadioState::RX_RU => trace!("radio:state:RX_RU"),
+ RadioState::RX_IDLE => trace!("radio:state:RX_IDLE"),
+ RadioState::RX => trace!("radio:state:RX"),
+ RadioState::RX_DISABLE => trace!("radio:state:RX_DISABLE"),
+ RadioState::TX_RU => trace!("radio:state:TX_RU"),
+ RadioState::TX_IDLE => trace!("radio:state:TX_IDLE"),
+ RadioState::TX => trace!("radio:state:TX"),
+ RadioState::TX_DISABLE => trace!("radio:state:TX_DISABLE"),
+ }
+ }
+
+ async fn trigger_and_wait_end(&mut self, trigger: impl FnOnce() -> ()) {
+ //self.trace_state();
+
+ let r = T::regs();
+ let s = T::state();
+
+ // If the Future is dropped before the end of the transmission
+ // we need to disable the interrupt and stop the transmission
+ // to keep the state consistent
+ let drop = OnDrop::new(|| {
+ trace!("radio drop: stopping");
+
+ r.intenclr.write(|w| w.end().clear());
+ r.events_end.reset();
+
+ r.tasks_stop.write(|w| w.tasks_stop().set_bit());
+
+ // The docs don't explicitly mention any event to acknowledge the stop task
+ // So I guess it's the same as end
+ while r.events_end.read().events_end().bit_is_clear() {}
+
+ trace!("radio drop: stopped");
+ });
+
+ /* Config interrupt */
+ // trace!("radio:enable interrupt");
+ // Clear some remnant side-effects (I'm unsure if this is needed)
+ r.events_end.reset();
+
+ // Enable interrupt
+ r.intenset.write(|w| w.end().set());
+
+ compiler_fence(Ordering::SeqCst);
+
+ // Trigger the transmission
+ trigger();
+ // self.trace_state();
+
+ // On poll check if interrupt happen
+ poll_fn(|cx| {
+ s.end_waker.register(cx.waker());
+ if r.events_end.read().events_end().bit_is_set() {
+ // trace!("radio:end");
+ return core::task::Poll::Ready(());
+ }
+ Poll::Pending
+ })
+ .await;
+
+ compiler_fence(Ordering::SeqCst);
+ r.events_disabled.reset(); // ACK
+
+ // Everthing ends fine, so we can disable the drop
+ drop.defuse();
+ }
+
+ /// Disable the radio.
+ fn disable(&mut self) {
+ let r = T::regs();
+
+ compiler_fence(Ordering::SeqCst);
+ // If is already disabled, do nothing
+ if !r.state.read().state().is_disabled() {
+ trace!("radio:disable");
+ // Trigger the disable task
+ r.tasks_disable.write(|w| w.tasks_disable().set_bit());
+
+ // Wait until the radio is disabled
+ while r.events_disabled.read().events_disabled().bit_is_clear() {}
+
+ compiler_fence(Ordering::SeqCst);
+
+ // Acknowledge it
+ r.events_disabled.reset();
+ }
+ }
+}
+
+impl<'d, T: Instance> BleRadio for Radio<'d, T> {
+ type Error = Error;
+
+ fn set_mode(&mut self, mode: Mode) {
+ let r = T::regs();
+ r.mode.write(|w| {
+ w.mode().variant(match mode {
+ Mode::Ble1mbit => PacMode::BLE_1MBIT,
+ //Mode::Ble2mbit => PacMode::BLE_2MBIT,
+ })
+ });
+
+ r.pcnf0.write(|w| {
+ w.plen().variant(match mode {
+ Mode::Ble1mbit => PreambleLength::_8BIT,
+ //Mode::Ble2mbit => PreambleLength::_16BIT,
+ })
+ });
+ }
+
+ fn set_header_size(&mut self, header_size: HeaderSize) {
+ let r = T::regs();
+
+ let s1len: u8 = match header_size {
+ HeaderSize::TwoBytes => 0,
+ HeaderSize::ThreeBytes => 8, // bits
+ };
+
+ r.pcnf0.write(|w| unsafe {
+ w
+ // Configure S0 to 1 byte length, this will represent the Data/Adv header flags
+ .s0len()
+ .set_bit()
+ // Configure the length (in bits) field to 1 byte length, this will represent the length of the payload
+ // and also be used to know how many bytes to read/write from/to the buffer
+ .lflen()
+ .bits(8)
+ // Configure the lengh (in bits) of bits in the S1 field. It could be used to represent the CTEInfo for data packages in BLE.
+ .s1len()
+ .bits(s1len)
+ });
+ }
+
+ fn set_channel(&mut self, channel: Channel) {
+ let r = T::regs();
+
+ r.frequency
+ .write(|w| unsafe { w.frequency().bits((channel.central_frequency() - 2400) as u8) });
+ r.datawhiteiv
+ .write(|w| unsafe { w.datawhiteiv().bits(channel.whitening_init()) });
+ }
+
+ fn set_access_address(&mut self, access_address: u32) {
+ let r = T::regs();
+
+ // Configure logical address
+ // The byte ordering on air is always least significant byte first for the address
+ // So for the address 0xAA_BB_CC_DD, the address on air will be DD CC BB AA
+ // The package order is BASE, PREFIX so BASE=0xBB_CC_DD and PREFIX=0xAA
+ r.prefix0
+ .write(|w| unsafe { w.ap0().bits((access_address >> 24) as u8) });
+
+ // The base address is truncated from the least significant byte (because the BALEN is less than 4)
+ // So we need to shift the address to the right
+ r.base0.write(|w| unsafe { w.bits(access_address << 8) });
+
+ // Don't match tx address
+ r.txaddress.write(|w| unsafe { w.txaddress().bits(0) });
+
+ // Match on logical address
+ // For what I understand, this config only filter the packets
+ // by the address, so only packages send to the previous address
+ // will finish the reception
+ r.rxaddresses.write(|w| {
+ w.addr0()
+ .enabled()
+ .addr1()
+ .enabled()
+ .addr2()
+ .enabled()
+ .addr3()
+ .enabled()
+ .addr4()
+ .enabled()
+ });
+ }
+
+ fn set_crc_init(&mut self, crc_init: u32) {
+ let r = T::regs();
+
+ r.crcinit.write(|w| unsafe { w.crcinit().bits(crc_init & 0xFFFFFF) });
+ }
+
+ fn set_tx_power(&mut self, power_db: i8) {
+ let r = T::regs();
+
+ let tx_power: TxPower = match power_db {
+ 8..=i8::MAX => TxPower::POS8D_BM,
+ 7 => TxPower::POS7D_BM,
+ 6 => TxPower::POS6D_BM,
+ 5 => TxPower::POS5D_BM,
+ 4 => TxPower::POS4D_BM,
+ 3 => TxPower::POS3D_BM,
+ 1..=2 => TxPower::POS2D_BM,
+ -3..=0 => TxPower::_0D_BM,
+ -7..=-4 => TxPower::NEG4D_BM,
+ -11..=-8 => TxPower::NEG8D_BM,
+ -15..=-12 => TxPower::NEG12D_BM,
+ -19..=-16 => TxPower::NEG16D_BM,
+ -29..=-20 => TxPower::NEG20D_BM,
+ -39..=-30 => TxPower::NEG30D_BM,
+ i8::MIN..=-40 => TxPower::NEG40D_BM,
+ };
+
+ r.txpower.write(|w| w.txpower().variant(tx_power));
+ }
+
+ fn set_buffer(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
+ // Because we are serializing the buffer, we should always have the buffer in RAM
+ slice_in_ram_or(buffer, Error::BufferNotInRAM)?;
+
+ if buffer.len() > MAX_PDU_LENGTH {
+ return Err(Error::BufferTooLong);
+ }
+
+ let r = T::regs();
+
+ // Here we are considering that the length of the packet is
+ // correctly set in the buffer, otherwise we will sending
+ // unowned regions of memory
+ let ptr = buffer.as_ptr();
+
+ // Configure the payload
+ r.packetptr.write(|w| unsafe { w.bits(ptr as u32) });
+
+ Ok(())
+ }
+
+ /// Send packet
+ async fn transmit(&mut self) {
+ let r = T::regs();
+
+ self.trigger_and_wait_end(move || {
+ // Initialize the transmission
+ // trace!("txen");
+ r.tasks_txen.write(|w| w.tasks_txen().set_bit());
+ })
+ .await;
+ }
+
+ /// Send packet
+ async fn receive(&mut self) {
+ let r = T::regs();
+
+ self.trigger_and_wait_end(move || {
+ // Initialize the transmission
+ // trace!("rxen");
+ r.tasks_rxen.write(|w| w.tasks_rxen().set_bit());
+
+ // Await until ready
+ while r.events_ready.read().events_ready().bit_is_clear() {}
+
+ compiler_fence(Ordering::SeqCst);
+
+ // Acknowledge it
+ r.events_ready.reset();
+
+ // trace!("radio:start");
+ r.tasks_start.write(|w| w.tasks_start().set_bit());
+ })
+ .await;
+ }
+}
+
+impl<'d, T: Instance> Drop for Radio<'d, T> {
+ fn drop(&mut self) {
+ self.disable();
+ }
+}
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
new file mode 100644
index 000000000..91cc2c0a7
--- /dev/null
+++ b/embassy-nrf/src/radio/mod.rs
@@ -0,0 +1,89 @@
+//! Integrated 2.4 GHz Radio
+//!
+//! The 2.4 GHz radio transceiver is compatible with multiple radio standards
+//! such as 1Mbps, 2Mbps and Long Range Bluetooth Low Energy.
+
+#![macro_use]
+
+/// Bluetooth Low Energy Radio driver.
+pub mod ble;
+
+use core::marker::PhantomData;
+
+use crate::{interrupt, pac, Peripheral};
+
+/// Interrupt handler
+pub struct InterruptHandler<T: Instance> {
+ _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+ unsafe fn on_interrupt() {
+ let r = T::regs();
+ let s = T::state();
+
+ if r.events_end.read().events_end().bit_is_set() {
+ s.end_waker.wake();
+ r.intenclr.write(|w| w.end().clear());
+ }
+ }
+}
+
+pub(crate) mod utils {
+ use super::*;
+
+ // Check if the HFCLK is XTAL is enabled
+ pub fn check_xtal() {
+ // safe: only reading the value
+ let is_xtal = unsafe {
+ let r = &*pac::CLOCK::ptr();
+ r.hfclkstat.read().src().is_xtal()
+ };
+ assert!(is_xtal, "HFCLK must be XTAL");
+ }
+}
+
+pub(crate) mod sealed {
+ use embassy_sync::waitqueue::AtomicWaker;
+
+ pub struct State {
+ /// end packet transmission or reception
+ pub end_waker: AtomicWaker,
+ }
+ impl State {
+ pub const fn new() -> Self {
+ Self {
+ end_waker: AtomicWaker::new(),
+ }
+ }
+ }
+
+ pub trait Instance {
+ fn regs() -> &'static crate::pac::radio::RegisterBlock;
+ fn state() -> &'static State;
+ }
+}
+
+macro_rules! impl_radio {
+ ($type:ident, $pac_type:ident, $irq:ident) => {
+ impl crate::radio::sealed::Instance for peripherals::$type {
+ fn regs() -> &'static pac::radio::RegisterBlock {
+ unsafe { &*pac::$pac_type::ptr() }
+ }
+
+ fn state() -> &'static crate::radio::sealed::State {
+ static STATE: crate::radio::sealed::State = crate::radio::sealed::State::new();
+ &STATE
+ }
+ }
+ impl crate::radio::Instance for peripherals::$type {
+ type Interrupt = crate::interrupt::typelevel::$irq;
+ }
+ };
+}
+
+/// Radio peripheral instance.
+pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
+ /// Interrupt for this peripheral.
+ type Interrupt: interrupt::typelevel::Interrupt;
+}
diff --git a/examples/nrf52840/Cargo.toml b/examples/nrf52840/Cargo.toml
index abb995be6..0239583cd 100644
--- a/examples/nrf52840/Cargo.toml
+++ b/examples/nrf52840/Cargo.toml
@@ -8,8 +8,8 @@ license = "MIT OR Apache-2.0"
embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
-embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
+embassy-time = { version = "0.3.0", features = ["defmt", "defmt-timestamp-uptime"] }
+embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time", "radio"]}
embassy-net = { version = "0.4.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
embedded-io = { version = "0.6.0", features = ["defmt-03"] }
@@ -35,6 +35,10 @@ embedded-hal-async = { version = "1.0" }
embedded-hal-bus = { version = "0.1", features = ["async"] }
num-integer = { version = "0.1.45", default-features = false }
microfft = "0.5.0"
+jewel = { version = "0.1.0", git = "https://github.com/jewel-rs/jewel"}
+
+[patch.crates-io]
+embassy-time = { version = "0.3.0", path = "../../embassy-time"}
[profile.release]
debug = 2
diff --git a/examples/nrf52840/src/bin/radio_ble_advertising.rs b/examples/nrf52840/src/bin/radio_ble_advertising.rs
new file mode 100644
index 000000000..8898c2418
--- /dev/null
+++ b/examples/nrf52840/src/bin/radio_ble_advertising.rs
@@ -0,0 +1,42 @@
+#![no_std]
+#![no_main]
+
+use defmt::{info, unwrap};
+use embassy_executor::Spawner;
+use embassy_nrf::{bind_interrupts, peripherals, radio};
+use embassy_time::Timer;
+use jewel::phy::Radio;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ RADIO => radio::InterruptHandler<peripherals::RADIO>;
+});
+
+// For a high-level API look on jewel examples
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let mut config = embassy_nrf::config::Config::default();
+ config.hfclk_source = embassy_nrf::config::HfclkSource::ExternalXtal;
+ let p = embassy_nrf::init(config);
+
+ info!("Starting BLE radio");
+ let mut radio = radio::ble::Radio::new(p.RADIO, Irqs);
+
+ let pdu = [
+ 0x46u8, // ADV_NONCONN_IND, Random address,
+ 0x18, // Length of payload
+ 0x27, 0xdc, 0xd0, 0xe8, 0xe1, 0xff, // Adress
+ 0x02, 0x01, 0x06, // Flags
+ 0x03, 0x03, 0x09, 0x18, // Complete list of 16-bit UUIDs available
+ 0x0A, 0x09, // Length, Type: Device name
+ b'H', b'e', b'l', b'l', b'o', b'R', b'u', b's', b't',
+ ];
+
+ unwrap!(radio.set_buffer(pdu.as_ref()));
+
+ loop {
+ info!("Sending packet");
+ radio.transmit().await;
+ Timer::after_millis(500).await;
+ }
+}
From 2e8b7d259057a0cf345396b250cacfc04a0e64a0 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 16:40:24 +0100
Subject: [PATCH 141/392] feat(boot): introduce non-erase flash write method
---
embassy-boot/src/firmware_updater/blocking.rs | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index f1368540d..514070639 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -194,6 +194,41 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
Ok(())
}
+ /// Write data directly to a flash page without erasing it first.
+ ///
+ /// This function writes the provided data to the specified offset in the flash memory,
+ /// without performing an erase operation beforehand. It is crucial that the area being
+ /// written to is either already erased.
+ /// This method is intended to be used in conjunction with the `prepare_update` method.
+ ///
+ /// The buffer must follow the alignment requirements of the target flash and be a multiple of
+ /// the page size. This is essential to ensure data integrity and prevent corruption.
+ ///
+ /// # Safety
+ ///
+ /// This function requires careful management of the memory being written to. Writing to a
+ /// non-erased page or not adhering to alignment and size requirements may result in a panic.
+ ///
+ /// Ensure that the data being written is compatible with the current contents of the flash
+ /// memory, as no erase operation will be performed to reset the page content to a default state.
+ ///
+ /// # Parameters
+ ///
+ /// - `offset`: The offset within the DFU partition where the data will be written. Must be
+ /// aligned according to the flash's requirements and within the writable memory range.
+ /// - `data`: A reference to the slice of bytes to be written. The length of the data must not
+ /// exceed the partition size and must follow the flash's alignment requirements.
+ ///
+ /// # Returns
+ ///
+ /// A result indicating the success or failure of the write operation. On success, returns `Ok(())`.
+ /// On failure, returns an `Err` with a `FirmwareUpdaterError` detailing the cause of the failure.
+ pub fn write_firmware_without_erase(&mut self, offset: usize, data: &[u8]) -> Result<(), FirmwareUpdaterError> {
+ self.dfu.write(offset as u32, data)?;
+
+ Ok(())
+ }
+
/// Prepare for an incoming DFU update by erasing the entire DFU area and
/// returning its `Partition`.
///
From c95bf6895adfcd33b5238c02620e83c6713205ce Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Wed, 7 Feb 2024 16:41:58 +0100
Subject: [PATCH 142/392] feat(usb-dfu): change usb dfu chunks write mechanism
---
embassy-usb-dfu/src/dfu.rs | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/embassy-usb-dfu/src/dfu.rs b/embassy-usb-dfu/src/dfu.rs
index e99aa70c3..5f2c98684 100644
--- a/embassy-usb-dfu/src/dfu.rs
+++ b/embassy-usb-dfu/src/dfu.rs
@@ -60,6 +60,21 @@ impl<'d, DFU: NorFlash, STATE: NorFlash, RST: Reset, const BLOCK_SIZE: usize> Ha
}
Ok(Request::Dnload) if self.attrs.contains(DfuAttributes::CAN_DOWNLOAD) => {
if req.value == 0 {
+ match self.updater.prepare_update() {
+ Ok(_) => {
+ self.status = Status::Ok;
+ }
+ Err(e) => {
+ self.state = State::Error;
+ match e {
+ embassy_boot::FirmwareUpdaterError::Flash(e) => match e {
+ NorFlashErrorKind::NotAligned => self.status = Status::ErrErase,
+ _ => self.status = Status::ErrUnknown,
+ },
+ _ => self.status = Status::ErrUnknown,
+ }
+ }
+ }
self.state = State::Download;
self.offset = 0;
}
@@ -93,7 +108,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash, RST: Reset, const BLOCK_SIZE: usize> Ha
self.state = State::Error;
return Some(OutResponse::Rejected);
}
- match self.updater.write_firmware(self.offset, buf.as_ref()) {
+ match self.updater.write_firmware_without_erase(self.offset, buf.as_ref()) {
Ok(_) => {
self.status = Status::Ok;
self.state = State::DlSync;
From d408056a66be2183dbcde6840e69e53beb4a764b Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 7 Feb 2024 17:16:46 +0100
Subject: [PATCH 143/392] remove default on radio
---
embassy-nrf/src/radio/ble.rs | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index a5d9f447b..64428fff5 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -17,10 +17,7 @@ use core::task::Poll;
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
-use jewel::phy::{
- AdvertisingChannel, Channel, ChannelTrait, HeaderSize, Mode, Radio as BleRadio, ADV_ADDRESS, ADV_CRC_INIT,
- CRC_POLY, MAX_PDU_LENGTH,
-};
+use jewel::phy::{Channel, ChannelTrait, HeaderSize, Mode, Radio as BleRadio, CRC_POLY, MAX_PDU_LENGTH};
use pac::radio::mode::MODE_A as PacMode;
use pac::radio::pcnf0::PLEN_A as PreambleLength;
// Re-export SVD variants to allow user to directly set values.
@@ -145,14 +142,6 @@ impl<'d, T: Instance> Radio<'d, T> {
let mut radio = Self { _p: radio };
- // set defaults
- radio.set_mode(Mode::Ble1mbit);
- radio.set_tx_power(0);
- radio.set_header_size(HeaderSize::TwoBytes);
- radio.set_access_address(ADV_ADDRESS);
- radio.set_crc_init(ADV_CRC_INIT);
- radio.set_channel(AdvertisingChannel::Ch39.into());
-
radio
}
From 5f1b80d40b6d2ae1636fa46e8e5334c03adeb67d Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 7 Feb 2024 18:04:29 +0100
Subject: [PATCH 144/392] remove jewel dependency
---
embassy-nrf/Cargo.toml | 4 +-
embassy-nrf/src/radio/ble.rs | 160 ++++++++++--------
embassy-nrf/src/radio/mod.rs | 14 --
examples/nrf52840/Cargo.toml | 4 -
.../nrf52840/src/bin/radio_ble_advertising.rs | 42 -----
5 files changed, 86 insertions(+), 138 deletions(-)
delete mode 100644 examples/nrf52840/src/bin/radio_ble_advertising.rs
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index dcdc7f313..9f35bd241 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -58,7 +58,7 @@ unstable-pac = []
gpiote = []
## Enable radio driver
-radio = ["dep:jewel"]
+radio = []
## Use RTC1 as the time driver for `embassy-time`, with a tick rate of 32.768khz
time-driver-rtc1 = ["_time-driver"]
@@ -153,8 +153,6 @@ embedded-storage-async = "0.4.0"
cfg-if = "1.0.0"
document-features = "0.2.7"
-jewel = { version = "0.1.0", git = "https://github.com/jewel-rs/jewel", optional = true }
-
nrf51-pac = { version = "0.12.0", optional = true }
nrf52805-pac = { version = "0.12.0", optional = true }
nrf52810-pac = { version = "0.12.0", optional = true }
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index 64428fff5..def941796 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -17,11 +17,10 @@ use core::task::Poll;
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
-use jewel::phy::{Channel, ChannelTrait, HeaderSize, Mode, Radio as BleRadio, CRC_POLY, MAX_PDU_LENGTH};
-use pac::radio::mode::MODE_A as PacMode;
+pub use pac::radio::mode::MODE_A as Mode;
use pac::radio::pcnf0::PLEN_A as PreambleLength;
-// Re-export SVD variants to allow user to directly set values.
-pub use pac::radio::{state::STATE_A as RadioState, txpower::TXPOWER_A as TxPower};
+use pac::radio::state::STATE_A as RadioState;
+pub use pac::radio::txpower::TXPOWER_A as TxPower;
use crate::interrupt::typelevel::Interrupt;
use crate::radio::*;
@@ -51,11 +50,6 @@ impl<'d, T: Instance> Radio<'d, T> {
radio: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
) -> Self {
- // From 5.4.1 of the nRF52840 Product Specification:
- // > The HFXO must be running to use the RADIO or the calibration mechanism associated with the 32.768 kHz RC oscillator.
- // Currently the jewel crate don't implement the calibration mechanism, so we need to ensure that the HFXO is running
- utils::check_xtal();
-
into_ref!(radio);
let r = T::regs();
@@ -113,18 +107,6 @@ impl<'d, T: Instance> Radio<'d, T> {
.three()
});
- r.crcpoly.write(|w| unsafe {
- // Configure the CRC polynomial
- // Each term in the CRC polynomial is mapped to a bit in this
- // register which index corresponds to the term's exponent.
- // The least significant term/bit is hard-wired internally to
- // 1, and bit number 0 of the register content is ignored by
- // the hardware. The following example is for an 8 bit CRC
- // polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .
- w.crcpoly().bits(CRC_POLY & 0xFFFFFF)
- });
- // The CRC initial value varies depending of the PDU type
-
// Ch map between 2400 MHZ .. 2500 MHz
// All modes use this range
r.frequency.write(|w| w.map().default());
@@ -140,9 +122,7 @@ impl<'d, T: Instance> Radio<'d, T> {
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
- let mut radio = Self { _p: radio };
-
- radio
+ Self { _p: radio }
}
#[allow(dead_code)]
@@ -186,7 +166,6 @@ impl<'d, T: Instance> Radio<'d, T> {
trace!("radio drop: stopped");
});
- /* Config interrupt */
// trace!("radio:enable interrupt");
// Clear some remnant side-effects (I'm unsure if this is needed)
r.events_end.reset();
@@ -238,34 +217,34 @@ impl<'d, T: Instance> Radio<'d, T> {
r.events_disabled.reset();
}
}
-}
-impl<'d, T: Instance> BleRadio for Radio<'d, T> {
- type Error = Error;
-
- fn set_mode(&mut self, mode: Mode) {
+ /// Set the radio mode
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_mode(&mut self, mode: Mode) {
let r = T::regs();
- r.mode.write(|w| {
- w.mode().variant(match mode {
- Mode::Ble1mbit => PacMode::BLE_1MBIT,
- //Mode::Ble2mbit => PacMode::BLE_2MBIT,
- })
- });
+ r.mode.write(|w| w.mode().variant(mode));
r.pcnf0.write(|w| {
w.plen().variant(match mode {
- Mode::Ble1mbit => PreambleLength::_8BIT,
- //Mode::Ble2mbit => PreambleLength::_16BIT,
+ Mode::BLE_1MBIT => PreambleLength::_8BIT,
+ Mode::BLE_2MBIT => PreambleLength::_16BIT,
+ Mode::BLE_LR125KBIT | Mode::BLE_LR500KBIT => PreambleLength::LONG_RANGE,
+ _ => unimplemented!(),
})
});
}
- fn set_header_size(&mut self, header_size: HeaderSize) {
+ /// Set the header size changing the S1 field
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_header_expansion(&mut self, use_s1_field: bool) {
let r = T::regs();
- let s1len: u8 = match header_size {
- HeaderSize::TwoBytes => 0,
- HeaderSize::ThreeBytes => 8, // bits
+ // s1 len in bits
+ let s1len: u8 = match use_s1_field {
+ false => 0,
+ true => 8,
};
r.pcnf0.write(|w| unsafe {
@@ -283,16 +262,36 @@ impl<'d, T: Instance> BleRadio for Radio<'d, T> {
});
}
- fn set_channel(&mut self, channel: Channel) {
+ /// Set initial data whitening value
+ /// Data whitening is used to avoid long sequences of zeros or ones, e.g., 0b0000000 or 0b1111111, in the data bit stream
+ /// On BLE the initial value is the channel index | 0x40
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_whitening_init(&mut self, whitening_init: u8) {
+ let r = T::regs();
+
+ r.datawhiteiv.write(|w| unsafe { w.datawhiteiv().bits(whitening_init) });
+ }
+
+ /// Set the central frequency to be used
+ /// It should be in the range 2400..2500
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_frequency(&mut self, frequency: u32) {
+ assert!(2400 <= frequency && frequency <= 2500);
let r = T::regs();
r.frequency
- .write(|w| unsafe { w.frequency().bits((channel.central_frequency() - 2400) as u8) });
- r.datawhiteiv
- .write(|w| unsafe { w.datawhiteiv().bits(channel.whitening_init()) });
+ .write(|w| unsafe { w.frequency().bits((frequency - 2400) as u8) });
}
- fn set_access_address(&mut self, access_address: u32) {
+ /// Set the acess address
+ /// This address is always constants for advertising
+ /// And a random value generate on each connection
+ /// It is used to filter the packages
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_access_address(&mut self, access_address: u32) {
let r = T::regs();
// Configure logical address
@@ -327,44 +326,55 @@ impl<'d, T: Instance> BleRadio for Radio<'d, T> {
});
}
- fn set_crc_init(&mut self, crc_init: u32) {
+ /// Set the CRC polynomial
+ /// It only uses the 24 least significant bits
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_crc_poly(&mut self, crc_poly: u32) {
+ let r = T::regs();
+
+ r.crcpoly.write(|w| unsafe {
+ // Configure the CRC polynomial
+ // Each term in the CRC polynomial is mapped to a bit in this
+ // register which index corresponds to the term's exponent.
+ // The least significant term/bit is hard-wired internally to
+ // 1, and bit number 0 of the register content is ignored by
+ // the hardware. The following example is for an 8 bit CRC
+ // polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .
+ w.crcpoly().bits(crc_poly & 0xFFFFFF)
+ });
+ }
+
+ /// Set the CRC init value
+ /// It only uses the 24 least significant bits
+ /// The CRC initial value varies depending of the PDU type
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_crc_init(&mut self, crc_init: u32) {
let r = T::regs();
r.crcinit.write(|w| unsafe { w.crcinit().bits(crc_init & 0xFFFFFF) });
}
- fn set_tx_power(&mut self, power_db: i8) {
+ /// Set the radio tx power
+ ///
+ /// The radio must be disabled before calling this function
+ pub fn set_tx_power(&mut self, tx_power: TxPower) {
let r = T::regs();
- let tx_power: TxPower = match power_db {
- 8..=i8::MAX => TxPower::POS8D_BM,
- 7 => TxPower::POS7D_BM,
- 6 => TxPower::POS6D_BM,
- 5 => TxPower::POS5D_BM,
- 4 => TxPower::POS4D_BM,
- 3 => TxPower::POS3D_BM,
- 1..=2 => TxPower::POS2D_BM,
- -3..=0 => TxPower::_0D_BM,
- -7..=-4 => TxPower::NEG4D_BM,
- -11..=-8 => TxPower::NEG8D_BM,
- -15..=-12 => TxPower::NEG12D_BM,
- -19..=-16 => TxPower::NEG16D_BM,
- -29..=-20 => TxPower::NEG20D_BM,
- -39..=-30 => TxPower::NEG30D_BM,
- i8::MIN..=-40 => TxPower::NEG40D_BM,
- };
-
r.txpower.write(|w| w.txpower().variant(tx_power));
}
- fn set_buffer(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
+ /// Set buffer to read/write
+ ///
+ /// This method is unsound. You should guarantee that the buffer will live
+ /// for the life time of the transmission or if the buffer will be modified.
+ /// Also if the buffer is smaller than the packet length, the radio will
+ /// read/write memory out of the buffer bounds.
+ pub fn set_buffer(&mut self, buffer: &[u8]) -> Result<(), Error> {
// Because we are serializing the buffer, we should always have the buffer in RAM
slice_in_ram_or(buffer, Error::BufferNotInRAM)?;
- if buffer.len() > MAX_PDU_LENGTH {
- return Err(Error::BufferTooLong);
- }
-
let r = T::regs();
// Here we are considering that the length of the packet is
@@ -379,7 +389,7 @@ impl<'d, T: Instance> BleRadio for Radio<'d, T> {
}
/// Send packet
- async fn transmit(&mut self) {
+ pub async fn transmit(&mut self) {
let r = T::regs();
self.trigger_and_wait_end(move || {
@@ -390,8 +400,8 @@ impl<'d, T: Instance> BleRadio for Radio<'d, T> {
.await;
}
- /// Send packet
- async fn receive(&mut self) {
+ /// Receive packet
+ pub async fn receive(&mut self) {
let r = T::regs();
self.trigger_and_wait_end(move || {
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 91cc2c0a7..03f967f87 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -29,20 +29,6 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
}
}
-pub(crate) mod utils {
- use super::*;
-
- // Check if the HFCLK is XTAL is enabled
- pub fn check_xtal() {
- // safe: only reading the value
- let is_xtal = unsafe {
- let r = &*pac::CLOCK::ptr();
- r.hfclkstat.read().src().is_xtal()
- };
- assert!(is_xtal, "HFCLK must be XTAL");
- }
-}
-
pub(crate) mod sealed {
use embassy_sync::waitqueue::AtomicWaker;
diff --git a/examples/nrf52840/Cargo.toml b/examples/nrf52840/Cargo.toml
index 0239583cd..78dabe347 100644
--- a/examples/nrf52840/Cargo.toml
+++ b/examples/nrf52840/Cargo.toml
@@ -35,10 +35,6 @@ embedded-hal-async = { version = "1.0" }
embedded-hal-bus = { version = "0.1", features = ["async"] }
num-integer = { version = "0.1.45", default-features = false }
microfft = "0.5.0"
-jewel = { version = "0.1.0", git = "https://github.com/jewel-rs/jewel"}
-
-[patch.crates-io]
-embassy-time = { version = "0.3.0", path = "../../embassy-time"}
[profile.release]
debug = 2
diff --git a/examples/nrf52840/src/bin/radio_ble_advertising.rs b/examples/nrf52840/src/bin/radio_ble_advertising.rs
deleted file mode 100644
index 8898c2418..000000000
--- a/examples/nrf52840/src/bin/radio_ble_advertising.rs
+++ /dev/null
@@ -1,42 +0,0 @@
-#![no_std]
-#![no_main]
-
-use defmt::{info, unwrap};
-use embassy_executor::Spawner;
-use embassy_nrf::{bind_interrupts, peripherals, radio};
-use embassy_time::Timer;
-use jewel::phy::Radio;
-use {defmt_rtt as _, panic_probe as _};
-
-bind_interrupts!(struct Irqs {
- RADIO => radio::InterruptHandler<peripherals::RADIO>;
-});
-
-// For a high-level API look on jewel examples
-#[embassy_executor::main]
-async fn main(_spawner: Spawner) {
- let mut config = embassy_nrf::config::Config::default();
- config.hfclk_source = embassy_nrf::config::HfclkSource::ExternalXtal;
- let p = embassy_nrf::init(config);
-
- info!("Starting BLE radio");
- let mut radio = radio::ble::Radio::new(p.RADIO, Irqs);
-
- let pdu = [
- 0x46u8, // ADV_NONCONN_IND, Random address,
- 0x18, // Length of payload
- 0x27, 0xdc, 0xd0, 0xe8, 0xe1, 0xff, // Adress
- 0x02, 0x01, 0x06, // Flags
- 0x03, 0x03, 0x09, 0x18, // Complete list of 16-bit UUIDs available
- 0x0A, 0x09, // Length, Type: Device name
- b'H', b'e', b'l', b'l', b'o', b'R', b'u', b's', b't',
- ];
-
- unwrap!(radio.set_buffer(pdu.as_ref()));
-
- loop {
- info!("Sending packet");
- radio.transmit().await;
- Timer::after_millis(500).await;
- }
-}
From add78943146cb929d51830c1f1c74c51dd3a5d57 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 7 Feb 2024 18:09:10 +0100
Subject: [PATCH 145/392] remove radio feature
---
embassy-nrf/Cargo.toml | 3 ---
embassy-nrf/src/chips/nrf52805.rs | 1 -
embassy-nrf/src/chips/nrf52810.rs | 1 -
embassy-nrf/src/chips/nrf52811.rs | 1 -
embassy-nrf/src/chips/nrf52820.rs | 1 -
embassy-nrf/src/chips/nrf52832.rs | 1 -
embassy-nrf/src/chips/nrf52833.rs | 1 -
embassy-nrf/src/chips/nrf52840.rs | 1 -
embassy-nrf/src/chips/nrf5340_net.rs | 1 -
embassy-nrf/src/lib.rs | 13 ++++++++++---
examples/nrf52840/Cargo.toml | 4 ++--
11 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 9f35bd241..7e161df9b 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -57,9 +57,6 @@ unstable-pac = []
## Enable GPIO tasks and events
gpiote = []
-## Enable radio driver
-radio = []
-
## Use RTC1 as the time driver for `embassy-time`, with a tick rate of 32.768khz
time-driver-rtc1 = ["_time-driver"]
diff --git a/embassy-nrf/src/chips/nrf52805.rs b/embassy-nrf/src/chips/nrf52805.rs
index b97c85f9e..c172dd107 100644
--- a/embassy-nrf/src/chips/nrf52805.rs
+++ b/embassy-nrf/src/chips/nrf52805.rs
@@ -212,7 +212,6 @@ impl_ppi_channel!(PPI_CH31, 31 => static);
impl_saadc_input!(P0_04, ANALOG_INPUT2);
impl_saadc_input!(P0_05, ANALOG_INPUT3);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/chips/nrf52810.rs b/embassy-nrf/src/chips/nrf52810.rs
index 03548d03f..c607586db 100644
--- a/embassy-nrf/src/chips/nrf52810.rs
+++ b/embassy-nrf/src/chips/nrf52810.rs
@@ -238,7 +238,6 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/chips/nrf52811.rs b/embassy-nrf/src/chips/nrf52811.rs
index 992fbd129..5f70365b4 100644
--- a/embassy-nrf/src/chips/nrf52811.rs
+++ b/embassy-nrf/src/chips/nrf52811.rs
@@ -240,7 +240,6 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/chips/nrf52820.rs b/embassy-nrf/src/chips/nrf52820.rs
index f241f4ea3..82d097407 100644
--- a/embassy-nrf/src/chips/nrf52820.rs
+++ b/embassy-nrf/src/chips/nrf52820.rs
@@ -227,7 +227,6 @@ impl_ppi_channel!(PPI_CH29, 29 => static);
impl_ppi_channel!(PPI_CH30, 30 => static);
impl_ppi_channel!(PPI_CH31, 31 => static);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs
index 6bbdd9a63..67b32fe5f 100644
--- a/embassy-nrf/src/chips/nrf52832.rs
+++ b/embassy-nrf/src/chips/nrf52832.rs
@@ -267,7 +267,6 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs
index e137e4dc6..20f14e2d6 100644
--- a/embassy-nrf/src/chips/nrf52833.rs
+++ b/embassy-nrf/src/chips/nrf52833.rs
@@ -309,7 +309,6 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/chips/nrf52840.rs b/embassy-nrf/src/chips/nrf52840.rs
index 2d805f871..d3272b2e8 100644
--- a/embassy-nrf/src/chips/nrf52840.rs
+++ b/embassy-nrf/src/chips/nrf52840.rs
@@ -314,7 +314,6 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
index 3248bde52..65e8f9653 100644
--- a/embassy-nrf/src/chips/nrf5340_net.rs
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -348,7 +348,6 @@ impl_ppi_channel!(PPI_CH29, 29 => configurable);
impl_ppi_channel!(PPI_CH30, 30 => configurable);
impl_ppi_channel!(PPI_CH31, 31 => configurable);
-#[cfg(feature = "radio")]
impl_radio!(RADIO, RADIO, RADIO);
embassy_hal_internal::interrupt_mod!(
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 961928d11..0f64f30f2 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -46,10 +46,17 @@ pub mod gpio;
#[cfg(feature = "gpiote")]
pub mod gpiote;
-#[cfg(feature = "radio")]
+#[cfg(any(
+ feature = "nrf52805",
+ feature = "nrf52810",
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52832",
+ feature = "nrf52833",
+ feature = "nrf52840",
+ feature = "_nrf5340-net"
+))]
pub mod radio;
-#[cfg(all(feature = "radio", feature = "_nrf9160"))]
-compile_error!("feature `radio` is not valid for nRF91 series chips.");
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
pub mod i2s;
diff --git a/examples/nrf52840/Cargo.toml b/examples/nrf52840/Cargo.toml
index 78dabe347..abb995be6 100644
--- a/examples/nrf52840/Cargo.toml
+++ b/examples/nrf52840/Cargo.toml
@@ -8,8 +8,8 @@ license = "MIT OR Apache-2.0"
embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
-embassy-time = { version = "0.3.0", features = ["defmt", "defmt-timestamp-uptime"] }
-embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time", "radio"]}
+embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
+embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
embassy-net = { version = "0.4.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
embedded-io = { version = "0.6.0", features = ["defmt-03"] }
From 3ad45655ecea36d54f8024b5fbdad461dc07ed69 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 7 Feb 2024 18:22:47 +0100
Subject: [PATCH 146/392] ci rerun
---
embassy-nrf/src/radio/ble.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index def941796..369b49c55 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -35,7 +35,7 @@ pub enum Error {
BufferTooLong,
/// Buffer was to short.
BufferTooShort,
- /// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
+ /// The buffer is not in data RAM. It is most likely in flash, and nRF's DMA cannot access flash.
BufferNotInRAM,
}
From ea8bfb4f382bddda2ca5fbe5ce4c595cd0421bd1 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 7 Feb 2024 18:25:06 +0100
Subject: [PATCH 147/392] remove some supports
---
embassy-nrf/src/lib.rs | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 0f64f30f2..767293230 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -47,11 +47,11 @@ pub mod gpio;
pub mod gpiote;
#[cfg(any(
- feature = "nrf52805",
- feature = "nrf52810",
+ //feature = "nrf52805",
+ //feature = "nrf52810",
feature = "nrf52811",
feature = "nrf52820",
- feature = "nrf52832",
+ //feature = "nrf52832",
feature = "nrf52833",
feature = "nrf52840",
feature = "_nrf5340-net"
From 9527d1d934a46a50bfc8f26bd942c6f6e5c5b31b Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 7 Feb 2024 18:31:05 +0100
Subject: [PATCH 148/392] remove radio implementation on chips not tested
---
embassy-nrf/src/chips/nrf52805.rs | 5 -----
embassy-nrf/src/chips/nrf52810.rs | 5 -----
embassy-nrf/src/chips/nrf52811.rs | 5 -----
embassy-nrf/src/chips/nrf52820.rs | 5 -----
embassy-nrf/src/chips/nrf52832.rs | 5 -----
embassy-nrf/src/chips/nrf52833.rs | 5 -----
embassy-nrf/src/chips/nrf5340_net.rs | 5 -----
embassy-nrf/src/lib.rs | 11 +----------
8 files changed, 1 insertion(+), 45 deletions(-)
diff --git a/embassy-nrf/src/chips/nrf52805.rs b/embassy-nrf/src/chips/nrf52805.rs
index c172dd107..624d6613d 100644
--- a/embassy-nrf/src/chips/nrf52805.rs
+++ b/embassy-nrf/src/chips/nrf52805.rs
@@ -129,9 +129,6 @@ embassy_hal_internal::peripherals! {
// QDEC
QDEC,
-
- // RADIO
- RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -212,8 +209,6 @@ impl_ppi_channel!(PPI_CH31, 31 => static);
impl_saadc_input!(P0_04, ANALOG_INPUT2);
impl_saadc_input!(P0_05, ANALOG_INPUT3);
-impl_radio!(RADIO, RADIO, RADIO);
-
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52810.rs b/embassy-nrf/src/chips/nrf52810.rs
index c607586db..002feab3b 100644
--- a/embassy-nrf/src/chips/nrf52810.rs
+++ b/embassy-nrf/src/chips/nrf52810.rs
@@ -135,9 +135,6 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
-
- // Radio
- RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -238,8 +235,6 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
-impl_radio!(RADIO, RADIO, RADIO);
-
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52811.rs b/embassy-nrf/src/chips/nrf52811.rs
index 5f70365b4..5952907f8 100644
--- a/embassy-nrf/src/chips/nrf52811.rs
+++ b/embassy-nrf/src/chips/nrf52811.rs
@@ -135,9 +135,6 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
-
- // Radio
- RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -240,8 +237,6 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
-impl_radio!(RADIO, RADIO, RADIO);
-
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52820.rs b/embassy-nrf/src/chips/nrf52820.rs
index 82d097407..c2f792cb9 100644
--- a/embassy-nrf/src/chips/nrf52820.rs
+++ b/embassy-nrf/src/chips/nrf52820.rs
@@ -130,9 +130,6 @@ embassy_hal_internal::peripherals! {
// QDEC
QDEC,
-
- // Radio
- RADIO,
}
impl_usb!(USBD, USBD, USBD);
@@ -227,8 +224,6 @@ impl_ppi_channel!(PPI_CH29, 29 => static);
impl_ppi_channel!(PPI_CH30, 30 => static);
impl_ppi_channel!(PPI_CH31, 31 => static);
-impl_radio!(RADIO, RADIO, RADIO);
-
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs
index 67b32fe5f..65d52364d 100644
--- a/embassy-nrf/src/chips/nrf52832.rs
+++ b/embassy-nrf/src/chips/nrf52832.rs
@@ -150,9 +150,6 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
-
- // Radio
- RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -267,8 +264,6 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
-impl_radio!(RADIO, RADIO, RADIO);
-
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs
index 20f14e2d6..7c9b66d69 100644
--- a/embassy-nrf/src/chips/nrf52833.rs
+++ b/embassy-nrf/src/chips/nrf52833.rs
@@ -170,9 +170,6 @@ embassy_hal_internal::peripherals! {
// I2S
I2S,
-
- // Radio
- RADIO,
}
impl_usb!(USBD, USBD, USBD);
@@ -309,8 +306,6 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
-impl_radio!(RADIO, RADIO, RADIO);
-
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
index 65e8f9653..a7cf82872 100644
--- a/embassy-nrf/src/chips/nrf5340_net.rs
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -248,9 +248,6 @@ embassy_hal_internal::peripherals! {
P1_13,
P1_14,
P1_15,
-
- // Radio
- RADIO,
}
impl_uarte!(SERIAL0, UARTE0, SERIAL0);
@@ -348,8 +345,6 @@ impl_ppi_channel!(PPI_CH29, 29 => configurable);
impl_ppi_channel!(PPI_CH30, 30 => configurable);
impl_ppi_channel!(PPI_CH31, 31 => configurable);
-impl_radio!(RADIO, RADIO, RADIO);
-
embassy_hal_internal::interrupt_mod!(
CLOCK_POWER,
RADIO,
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 767293230..5dba6f975 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -46,16 +46,7 @@ pub mod gpio;
#[cfg(feature = "gpiote")]
pub mod gpiote;
-#[cfg(any(
- //feature = "nrf52805",
- //feature = "nrf52810",
- feature = "nrf52811",
- feature = "nrf52820",
- //feature = "nrf52832",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
-))]
+#[cfg(any(feature = "nrf52840"))] // needs to be tested on other chips
pub mod radio;
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
From 2e15d1371a891cc3456d7b9fd22a68291770df41 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Thu, 8 Feb 2024 00:31:21 +0100
Subject: [PATCH 149/392] Delete tests/stm32/teleprobe.sh
---
tests/stm32/teleprobe.sh | 12 ------------
1 file changed, 12 deletions(-)
delete mode 100755 tests/stm32/teleprobe.sh
diff --git a/tests/stm32/teleprobe.sh b/tests/stm32/teleprobe.sh
deleted file mode 100755
index 6eec6ca93..000000000
--- a/tests/stm32/teleprobe.sh
+++ /dev/null
@@ -1,12 +0,0 @@
-echo Running target=$1 elf=$2
-STATUSCODE=$(
- curl \
- -sS \
- --output /dev/stderr \
- --write-out "%{http_code}" \
- -H "Authorization: Bearer $TELEPROBE_TOKEN" \
- https://teleprobe.embassy.dev/targets/$1/run --data-binary @$2
-)
-echo
-echo HTTP Status code: $STATUSCODE
-test "$STATUSCODE" -eq 200
From ab8f25fd78582aab68c9820e4b4dd9771a1ded65 Mon Sep 17 00:00:00 2001
From: shufps <shufps80@gmail.com>
Date: Thu, 8 Feb 2024 10:47:26 +0100
Subject: [PATCH 150/392] added support for ADC of L0s
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/adc/mod.rs | 23 ++++++++++++-----------
embassy-stm32/src/adc/resolution.rs | 8 ++++----
embassy-stm32/src/adc/sample_time.rs | 2 +-
embassy-stm32/src/adc/v1.rs | 21 +++++++++++++++++++++
5 files changed, 40 insertions(+), 18 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 8f0fc1c59..61d70b732 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e702b4d564bc9e3c8a5c0141a11efdc5f7ee8f24" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7c933984fe0cbd120b6aaa7742bd585f89fa786" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e702b4d564bc9e3c8a5c0141a11efdc5f7ee8f24", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7c933984fe0cbd120b6aaa7742bd585f89fa786", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index d21c3053f..51b4b5fcc 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -8,6 +8,7 @@
#[cfg_attr(adc_f3, path = "f3.rs")]
#[cfg_attr(adc_f3_v1_1, path = "f3_v1_1.rs")]
#[cfg_attr(adc_v1, path = "v1.rs")]
+#[cfg_attr(adc_l0, path = "v1.rs")]
#[cfg_attr(adc_v2, path = "v2.rs")]
#[cfg_attr(any(adc_v3, adc_g0), path = "v3.rs")]
#[cfg_attr(adc_v4, path = "v4.rs")]
@@ -36,15 +37,15 @@ pub struct Adc<'d, T: Instance> {
}
pub(crate) mod sealed {
- #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
+ #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
use embassy_sync::waitqueue::AtomicWaker;
- #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
+ #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
pub struct State {
pub waker: AtomicWaker,
}
- #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
+ #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
impl State {
pub const fn new() -> Self {
Self {
@@ -59,14 +60,14 @@ pub(crate) mod sealed {
pub trait Instance: InterruptableInstance {
fn regs() -> crate::pac::adc::Adc;
- #[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
+ #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
fn common_regs() -> crate::pac::adccommon::AdcCommon;
- #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
+ #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
fn state() -> &'static State;
}
pub trait AdcPin<T: Instance> {
- #[cfg(any(adc_v1, adc_v2))]
+ #[cfg(any(adc_v1, adc_l0, adc_v2))]
fn set_as_analog(&mut self) {}
fn channel(&self) -> u8;
@@ -78,10 +79,10 @@ pub(crate) mod sealed {
}
/// ADC instance.
-#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0)))]
+#[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0)))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
/// ADC instance.
-#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0))]
+#[cfg(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
/// ADC pin.
@@ -96,12 +97,12 @@ foreach_adc!(
crate::pac::$inst
}
- #[cfg(not(any(adc_f1, adc_v1, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
+ #[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_f3_v2, adc_f3_v1_1, adc_g0)))]
fn common_regs() -> crate::pac::adccommon::AdcCommon {
return crate::pac::$common_inst
}
- #[cfg(any(adc_f1, adc_f3, adc_v1, adc_f3_v1_1))]
+ #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
fn state() -> &'static sealed::State {
static STATE: sealed::State = sealed::State::new();
&STATE
@@ -125,7 +126,7 @@ macro_rules! impl_adc_pin {
impl crate::adc::AdcPin<peripherals::$inst> for crate::peripherals::$pin {}
impl crate::adc::sealed::AdcPin<peripherals::$inst> for crate::peripherals::$pin {
- #[cfg(any(adc_v1, adc_v2))]
+ #[cfg(any(adc_v1, adc_l0, adc_v2))]
fn set_as_analog(&mut self) {
<Self as crate::gpio::sealed::Pin>::set_as_analog(self);
}
diff --git a/embassy-stm32/src/adc/resolution.rs b/embassy-stm32/src/adc/resolution.rs
index 9513e1df7..0e6c45c65 100644
--- a/embassy-stm32/src/adc/resolution.rs
+++ b/embassy-stm32/src/adc/resolution.rs
@@ -1,6 +1,6 @@
/// ADC resolution
#[allow(missing_docs)]
-#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
+#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Resolution {
@@ -25,7 +25,7 @@ pub enum Resolution {
impl Default for Resolution {
fn default() -> Self {
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
+ #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
{
Self::TwelveBit
}
@@ -46,7 +46,7 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
+ #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
}
}
@@ -65,7 +65,7 @@ impl Resolution {
Resolution::TwelveBit => (1 << 12) - 1,
Resolution::TenBit => (1 << 10) - 1,
Resolution::EightBit => (1 << 8) - 1,
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0, adc_f3, adc_f3_v1_1))]
+ #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
Resolution::SixBit => (1 << 6) - 1,
}
}
diff --git a/embassy-stm32/src/adc/sample_time.rs b/embassy-stm32/src/adc/sample_time.rs
index 5a06f1a5a..f4b22b462 100644
--- a/embassy-stm32/src/adc/sample_time.rs
+++ b/embassy-stm32/src/adc/sample_time.rs
@@ -83,7 +83,7 @@ impl_sample_time!(
)
);
-#[cfg(adc_g0)]
+#[cfg(any(adc_l0, adc_g0))]
impl_sample_time!(
"1.5",
Cycles1_5,
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 852b027df..13a7ead3e 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -6,6 +6,10 @@ use embassy_hal_internal::into_ref;
use embedded_hal_02::blocking::delay::DelayUs;
use crate::adc::{Adc, AdcPin, Instance, Resolution, SampleTime};
+
+#[cfg(adc_l0)]
+use stm32_metapac::adc::vals::Ckmode;
+
use crate::interrupt::typelevel::Interrupt;
use crate::peripherals::ADC;
use crate::{interrupt, Peripheral};
@@ -30,8 +34,13 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
}
}
+#[cfg(not(adc_l0))]
pub struct Vbat;
+
+#[cfg(not(adc_l0))]
impl AdcPin<ADC> for Vbat {}
+
+#[cfg(not(adc_l0))]
impl super::sealed::AdcPin<ADC> for Vbat {
fn channel(&self) -> u8 {
18
@@ -72,6 +81,11 @@ impl<'d, T: Instance> Adc<'d, T> {
// A.7.1 ADC calibration code example
T::regs().cfgr1().modify(|reg| reg.set_dmaen(false));
T::regs().cr().modify(|reg| reg.set_adcal(true));
+
+ #[cfg(adc_l0)]
+ while !T::regs().isr().read().eocal() {}
+
+ #[cfg(not(adc_l0))]
while T::regs().cr().read().adcal() {}
// A.7.2 ADC enable sequence code example
@@ -97,6 +111,7 @@ impl<'d, T: Instance> Adc<'d, T> {
}
}
+ #[cfg(not(adc_l0))]
pub fn enable_vbat(&self, _delay: &mut impl DelayUs<u32>) -> Vbat {
// SMP must be ≥ 56 ADC clock cycles when using HSI14.
//
@@ -133,6 +148,12 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
}
+ #[cfg(adc_l0)]
+ pub fn set_ckmode(&mut self, ckmode: Ckmode) {
+ // set ADC clock mode
+ T::regs().cfgr2().modify(|reg| reg.set_ckmode(ckmode));
+ }
+
pub async fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
let channel = pin.channel();
pin.set_as_analog();
From 8dff89bfd99140bc7de48bb5de600a2aeb920681 Mon Sep 17 00:00:00 2001
From: shufps <shufps80@gmail.com>
Date: Thu, 8 Feb 2024 11:07:30 +0100
Subject: [PATCH 151/392] added ADC example running on L0
---
examples/stm32l0/src/bin/adc.rs | 46 +++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 examples/stm32l0/src/bin/adc.rs
diff --git a/examples/stm32l0/src/bin/adc.rs b/examples/stm32l0/src/bin/adc.rs
new file mode 100644
index 000000000..93bf5adc6
--- /dev/null
+++ b/examples/stm32l0/src/bin/adc.rs
@@ -0,0 +1,46 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_stm32::Config;
+use embassy_executor::Spawner;
+use embassy_stm32::adc::{Adc, SampleTime};
+use embassy_stm32::peripherals::ADC;
+use embassy_stm32::{adc, bind_interrupts};
+use embassy_time::{Delay, Timer};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ ADC1_COMP => adc::InterruptHandler<ADC>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ // enable HSI because default is MSI but ADC doesn't support
+ // this as clock source on L0s and uses HSI by default
+ let mut config = Config::default();
+ config.rcc.hsi = true;
+ let p = embassy_stm32::init(config);
+
+ info!("Hello World!");
+
+ let mut adc = Adc::new(p.ADC, Irqs, &mut Delay);
+ adc.set_sample_time(SampleTime::Cycles79_5);
+ let mut pin = p.PA1;
+
+ let mut vrefint = adc.enable_vref(&mut Delay);
+ let vrefint_sample = adc.read(&mut vrefint).await;
+ let convert_to_millivolts = |sample| {
+ // From https://www.st.com/resource/en/datasheet/stm32l051c6.pdf
+ // 6.3.3 Embedded internal reference voltage
+ const VREFINT_MV: u32 = 1224; // mV
+
+ (u32::from(sample) * VREFINT_MV / u32::from(vrefint_sample)) as u16
+ };
+
+ loop {
+ let v = adc.read(&mut pin).await;
+ info!("--> {} - {} mV", v, convert_to_millivolts(v));
+ Timer::after_millis(100).await;
+ }
+}
From 158d7dbc8f4714c94cf58e48942543726d717f57 Mon Sep 17 00:00:00 2001
From: shufps <shufps80@gmail.com>
Date: Thu, 8 Feb 2024 11:11:13 +0100
Subject: [PATCH 152/392] cargo fmt
---
examples/stm32l0/src/bin/adc.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/stm32l0/src/bin/adc.rs b/examples/stm32l0/src/bin/adc.rs
index 93bf5adc6..f94bf907f 100644
--- a/examples/stm32l0/src/bin/adc.rs
+++ b/examples/stm32l0/src/bin/adc.rs
@@ -2,10 +2,10 @@
#![no_main]
use defmt::*;
-use embassy_stm32::Config;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
use embassy_stm32::peripherals::ADC;
+use embassy_stm32::Config;
use embassy_stm32::{adc, bind_interrupts};
use embassy_time::{Delay, Timer};
use {defmt_rtt as _, panic_probe as _};
From 8d0a9bbefb29cab54ba37106a54e5e1f1f04a383 Mon Sep 17 00:00:00 2001
From: shufps <shufps80@gmail.com>
Date: Thu, 8 Feb 2024 11:14:14 +0100
Subject: [PATCH 153/392] clippy
---
embassy-stm32/src/adc/v1.rs | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 13a7ead3e..92529b036 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -5,11 +5,10 @@ use core::task::Poll;
use embassy_hal_internal::into_ref;
use embedded_hal_02::blocking::delay::DelayUs;
-use crate::adc::{Adc, AdcPin, Instance, Resolution, SampleTime};
-
#[cfg(adc_l0)]
use stm32_metapac::adc::vals::Ckmode;
+use crate::adc::{Adc, AdcPin, Instance, Resolution, SampleTime};
use crate::interrupt::typelevel::Interrupt;
use crate::peripherals::ADC;
use crate::{interrupt, Peripheral};
From b2b2abeb333f9bacaa43910d1b75308a3f1c5c4e Mon Sep 17 00:00:00 2001
From: shufps <shufps80@gmail.com>
Date: Thu, 8 Feb 2024 11:14:29 +0100
Subject: [PATCH 154/392] clippy
---
examples/stm32l0/src/bin/adc.rs | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/examples/stm32l0/src/bin/adc.rs b/examples/stm32l0/src/bin/adc.rs
index f94bf907f..eee69211c 100644
--- a/examples/stm32l0/src/bin/adc.rs
+++ b/examples/stm32l0/src/bin/adc.rs
@@ -5,8 +5,7 @@ use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
use embassy_stm32::peripherals::ADC;
-use embassy_stm32::Config;
-use embassy_stm32::{adc, bind_interrupts};
+use embassy_stm32::{adc, bind_interrupts, Config};
use embassy_time::{Delay, Timer};
use {defmt_rtt as _, panic_probe as _};
From dabe48c3bd647f13d62d15bbb17983be541f7583 Mon Sep 17 00:00:00 2001
From: shufps <shufps80@gmail.com>
Date: Thu, 8 Feb 2024 11:15:28 +0100
Subject: [PATCH 155/392] fmt
---
embassy-stm32/src/adc/v1.rs | 1 -
1 file changed, 1 deletion(-)
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 92529b036..83bf5aece 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -4,7 +4,6 @@ use core::task::Poll;
use embassy_hal_internal::into_ref;
use embedded_hal_02::blocking::delay::DelayUs;
-
#[cfg(adc_l0)]
use stm32_metapac::adc::vals::Ckmode;
From 34c71b58cf281e7a0d5517a3f3939477dadb5575 Mon Sep 17 00:00:00 2001
From: shufps <shufps80@gmail.com>
Date: Thu, 8 Feb 2024 11:28:53 +0100
Subject: [PATCH 156/392] made adc example working with default clock
configuration and switched in `v1` to PCLK/2 per default
---
embassy-stm32/src/adc/v1.rs | 4 ++++
examples/stm32l0/src/bin/adc.rs | 9 ++-------
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 83bf5aece..37115dfab 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -76,6 +76,10 @@ impl<'d, T: Instance> Adc<'d, T> {
// tstab = 14 * 1/fadc
delay.delay_us(1);
+ // set default PCKL/2 on L0s because HSI is disabled in the default clock config
+ #[cfg(adc_l0)]
+ T::regs().cfgr2().modify(|reg| reg.set_ckmode(Ckmode::PCLK_DIV2));
+
// A.7.1 ADC calibration code example
T::regs().cfgr1().modify(|reg| reg.set_dmaen(false));
T::regs().cr().modify(|reg| reg.set_adcal(true));
diff --git a/examples/stm32l0/src/bin/adc.rs b/examples/stm32l0/src/bin/adc.rs
index eee69211c..adeaa208a 100644
--- a/examples/stm32l0/src/bin/adc.rs
+++ b/examples/stm32l0/src/bin/adc.rs
@@ -5,7 +5,7 @@ use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
use embassy_stm32::peripherals::ADC;
-use embassy_stm32::{adc, bind_interrupts, Config};
+use embassy_stm32::{adc, bind_interrupts};
use embassy_time::{Delay, Timer};
use {defmt_rtt as _, panic_probe as _};
@@ -15,12 +15,7 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
- // enable HSI because default is MSI but ADC doesn't support
- // this as clock source on L0s and uses HSI by default
- let mut config = Config::default();
- config.rcc.hsi = true;
- let p = embassy_stm32::init(config);
-
+ let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let mut adc = Adc::new(p.ADC, Irqs, &mut Delay);
From d48620d58f588936a5c74840063fe422764b749f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?xgroleau=F0=9F=90=A2?= <xavgroleau@gmail.com>
Date: Tue, 6 Feb 2024 15:50:28 -0500
Subject: [PATCH 157/392] fix: compilation for rtos trace
---
ci.sh | 2 ++
embassy-executor/Cargo.toml | 4 ----
embassy-executor/src/raw/mod.rs | 12 +++++++++++-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/ci.sh b/ci.sh
index df9e09848..4f28c5e92 100755
--- a/ci.sh
+++ b/ci.sh
@@ -23,6 +23,8 @@ cargo batch \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv6m-none-eabi --features defmt,arch-cortex-m,executor-thread,executor-interrupt,integrated-timers \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,integrated-timers \
+ --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,rtos-trace \
+ --- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,integrated-timers,rtos-trace \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,executor-thread \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,executor-thread,integrated-timers \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features arch-cortex-m,executor-interrupt \
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index 0762e2434..409df0d75 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -34,7 +34,6 @@ log = { version = "0.4.14", optional = true }
rtos-trace = { version = "0.1.2", optional = true }
embassy-executor-macros = { version = "0.4.0", path = "../embassy-executor-macros" }
-embassy-time = { version = "0.3.0", path = "../embassy-time", optional = true }
embassy-time-driver = { version = "0.1.0", path = "../embassy-time-driver", optional = true }
embassy-time-queue-driver = { version = "0.1.0", path = "../embassy-time-queue-driver", optional = true }
critical-section = "1.1"
@@ -72,9 +71,6 @@ turbowakers = []
## Use the executor-integrated `embassy-time` timer queue.
integrated-timers = ["dep:embassy-time-driver", "dep:embassy-time-queue-driver"]
-# Support for rtos trace require time
-rtos-trace = ["dep:rtos-trace", "dep:embassy-time"]
-
#! ### Architecture
_arch = [] # some arch was picked
## std
diff --git a/embassy-executor/src/raw/mod.rs b/embassy-executor/src/raw/mod.rs
index fbc0481c2..3d221c94b 100644
--- a/embassy-executor/src/raw/mod.rs
+++ b/embassy-executor/src/raw/mod.rs
@@ -581,6 +581,15 @@ impl embassy_time_queue_driver::TimerQueue for TimerQueue {
#[cfg(feature = "integrated-timers")]
embassy_time_queue_driver::timer_queue_impl!(static TIMER_QUEUE: TimerQueue = TimerQueue);
+#[cfg(all(feature = "rtos-trace", feature = "integrated-timers"))]
+const fn gcd(a: u64, b: u64) -> u64 {
+ if b == 0 {
+ a
+ } else {
+ gcd(b, a % b)
+ }
+}
+
#[cfg(feature = "rtos-trace")]
impl rtos_trace::RtosTraceOSCallbacks for Executor {
fn task_list() {
@@ -588,7 +597,8 @@ impl rtos_trace::RtosTraceOSCallbacks for Executor {
}
#[cfg(feature = "integrated-timers")]
fn time() -> u64 {
- embassy_time::Instant::now().as_millis()
+ const GCD_1M: u64 = gcd(embassy_time_driver::TICK_HZ, 1_000_000);
+ embassy_time_driver::now() * (1_000_00 / GCD_1M) / (embassy_time_driver::TICK_HZ / GCD_1M);
}
#[cfg(not(feature = "integrated-timers"))]
fn time() -> u64 {
From 09613e90de92ba43974796efec13e38adf4c3ac8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?xgroleau=F0=9F=90=A2?= <xavgroleau@gmail.com>
Date: Thu, 8 Feb 2024 09:01:07 -0500
Subject: [PATCH 158/392] fix: missing 0
---
embassy-executor/src/raw/mod.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-executor/src/raw/mod.rs b/embassy-executor/src/raw/mod.rs
index 3d221c94b..3c9407d39 100644
--- a/embassy-executor/src/raw/mod.rs
+++ b/embassy-executor/src/raw/mod.rs
@@ -598,7 +598,7 @@ impl rtos_trace::RtosTraceOSCallbacks for Executor {
#[cfg(feature = "integrated-timers")]
fn time() -> u64 {
const GCD_1M: u64 = gcd(embassy_time_driver::TICK_HZ, 1_000_000);
- embassy_time_driver::now() * (1_000_00 / GCD_1M) / (embassy_time_driver::TICK_HZ / GCD_1M);
+ embassy_time_driver::now() * (1_000_000 / GCD_1M) / (embassy_time_driver::TICK_HZ / GCD_1M);
}
#[cfg(not(feature = "integrated-timers"))]
fn time() -> u64 {
From 262518cfe5c303034f71393367914bec221c71be Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?xgroleau=F0=9F=90=A2?= <xavgroleau@gmail.com>
Date: Thu, 8 Feb 2024 09:02:07 -0500
Subject: [PATCH 159/392] fix: removed trailing comma
---
embassy-executor/src/raw/mod.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-executor/src/raw/mod.rs b/embassy-executor/src/raw/mod.rs
index 3c9407d39..3d5e3ab9f 100644
--- a/embassy-executor/src/raw/mod.rs
+++ b/embassy-executor/src/raw/mod.rs
@@ -598,7 +598,7 @@ impl rtos_trace::RtosTraceOSCallbacks for Executor {
#[cfg(feature = "integrated-timers")]
fn time() -> u64 {
const GCD_1M: u64 = gcd(embassy_time_driver::TICK_HZ, 1_000_000);
- embassy_time_driver::now() * (1_000_000 / GCD_1M) / (embassy_time_driver::TICK_HZ / GCD_1M);
+ embassy_time_driver::now() * (1_000_000 / GCD_1M) / (embassy_time_driver::TICK_HZ / GCD_1M)
}
#[cfg(not(feature = "integrated-timers"))]
fn time() -> u64 {
From 27411658d9710451b04efe014747606018646527 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Thu, 8 Feb 2024 21:43:05 +0200
Subject: [PATCH 160/392] nrf: spim/spis: Add size checks for EasyDMA buffer
On most nRF chips, maximum buffer size for EasyDMA is 255, thus
we never got any data when attempting to use 256 bytes as RX/TX buffer.
---
embassy-nrf/src/spim.rs | 14 +++++++++++---
embassy-nrf/src/spis.rs | 8 +++++++-
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index 6b6f79188..8937159df 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -13,7 +13,7 @@ pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MO
pub use pac::spim0::config::ORDER_A as BitOrder;
pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
-use crate::chip::FORCE_COPY_BUFFER_SIZE;
+use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::typelevel::Interrupt;
@@ -25,9 +25,9 @@ use crate::{interrupt, pac, Peripheral};
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
pub enum Error {
- /// TX buffer was too long.
+ /// Supplied TX buffer overflows EasyDMA transmit buffer
TxBufferTooLong,
- /// RX buffer was too long.
+ /// Supplied RX buffer overflows EasyDMA receive buffer
RxBufferTooLong,
/// EasyDMA can only read from data memory, read only buffers in flash will fail.
BufferNotInRAM,
@@ -220,11 +220,19 @@ impl<'d, T: Instance> Spim<'d, T> {
// Set up the DMA write.
let (ptr, tx_len) = slice_ptr_parts(tx);
+ if tx_len > EASY_DMA_SIZE {
+ return Err(Error::TxBufferTooLong);
+ }
+
r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(tx_len as _) });
// Set up the DMA read.
let (ptr, rx_len) = slice_ptr_parts_mut(rx);
+ if rx_len > EASY_DMA_SIZE {
+ return Err(Error::RxBufferTooLong);
+ }
+
r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(rx_len as _) });
diff --git a/embassy-nrf/src/spis.rs b/embassy-nrf/src/spis.rs
index 60f4c9865..772ca40cc 100644
--- a/embassy-nrf/src/spis.rs
+++ b/embassy-nrf/src/spis.rs
@@ -11,7 +11,7 @@ use embassy_hal_internal::{into_ref, PeripheralRef};
pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
pub use pac::spis0::config::ORDER_A as BitOrder;
-use crate::chip::FORCE_COPY_BUFFER_SIZE;
+use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin};
use crate::interrupt::typelevel::Interrupt;
@@ -227,11 +227,17 @@ impl<'d, T: Instance> Spis<'d, T> {
// Set up the DMA write.
let (ptr, len) = slice_ptr_parts(tx);
+ if len > EASY_DMA_SIZE {
+ return Err(Error::TxBufferTooLong);
+ }
r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
// Set up the DMA read.
let (ptr, len) = slice_ptr_parts_mut(rx);
+ if len > EASY_DMA_SIZE {
+ return Err(Error::RxBufferTooLong);
+ }
r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
From f6645750c95ac008f74b980b553117e7a390a833 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Thu, 8 Feb 2024 17:24:27 -0500
Subject: [PATCH 161/392] Removed hash DMA from unsupported configs.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/hash/mod.rs | 7 +-
embassy-stm32/src/hash/{v1.rs => v1v3v4.rs} | 77 +++++++++++++++++++--
embassy-stm32/src/hash/{v2v3.rs => v2.rs} | 6 +-
examples/stm32f7/.cargo/config.toml | 2 +-
examples/stm32f7/src/bin/hash.rs | 9 ++-
6 files changed, 89 insertions(+), 16 deletions(-)
rename embassy-stm32/src/hash/{v1.rs => v1v3v4.rs} (84%)
rename embassy-stm32/src/hash/{v2v3.rs => v2.rs} (98%)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index ef6063656..87815c63a 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5674011dd7db845c9d70d6a20a16129221026d25" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-36a3262735a169e31b702bcb0ac6c0067c3f078e" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5674011dd7db845c9d70d6a20a16129221026d25", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-36a3262735a169e31b702bcb0ac6c0067c3f078e", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 6b23f3b55..64c1a0a8c 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -1,7 +1,8 @@
//! Hash Accelerator (HASH)
-#[cfg_attr(hash_v1, path = "v1.rs")]
-#[cfg_attr(hash_v2, path = "v2v3.rs")]
-#[cfg_attr(hash_v3, path = "v2v3.rs")]
+#[cfg_attr(hash_v1, path = "v1v3v4.rs")]
+#[cfg_attr(hash_v2, path = "v2.rs")]
+#[cfg_attr(hash_v3, path = "v1v3v4.rs")]
+#[cfg_attr(hash_v4, path = "v1v3v4.rs")]
mod _version;
pub use _version::*;
diff --git a/embassy-stm32/src/hash/v1.rs b/embassy-stm32/src/hash/v1v3v4.rs
similarity index 84%
rename from embassy-stm32/src/hash/v1.rs
rename to embassy-stm32/src/hash/v1v3v4.rs
index 36beb7c3e..771144b11 100644
--- a/embassy-stm32/src/hash/v1.rs
+++ b/embassy-stm32/src/hash/v1v3v4.rs
@@ -13,10 +13,16 @@ use crate::peripherals::HASH;
use crate::rcc::sealed::RccPeripheral;
use crate::{interrupt, pac, peripherals, Peripheral};
+#[cfg(hash_v1)]
const NUM_CONTEXT_REGS: usize = 51;
-const HASH_BUFFER_LEN: usize = 68;
-const DIGEST_BLOCK_SIZE: usize = 64;
-const MAX_DIGEST_SIZE: usize = 20;
+#[cfg(hash_v3)]
+const NUM_CONTEXT_REGS: usize = 103;
+#[cfg(hash_v4)]
+const NUM_CONTEXT_REGS: usize = 54;
+
+const HASH_BUFFER_LEN: usize = 132;
+const DIGEST_BLOCK_SIZE: usize = 128;
+const MAX_DIGEST_SIZE: usize = 128;
static HASH_WAKER: AtomicWaker = AtomicWaker::new();
@@ -40,12 +46,36 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
}
///Hash algorithm selection
-#[derive(PartialEq)]
+#[derive(Clone, Copy, PartialEq)]
pub enum Algorithm {
/// SHA-1 Algorithm
SHA1 = 0,
+
+ #[cfg(any(hash_v1, hash_v4))]
/// MD5 Algorithm
MD5 = 1,
+
+ /// SHA-224 Algorithm
+ SHA224 = 2,
+
+ /// SHA-256 Algorithm
+ SHA256 = 3,
+
+ #[cfg(hash_v3)]
+ /// SHA-384 Algorithm
+ SHA384 = 12,
+
+ #[cfg(hash_v3)]
+ /// SHA-512/224 Algorithm
+ SHA512_224 = 13,
+
+ #[cfg(hash_v3)]
+ /// SHA-512/256 Algorithm
+ SHA512_256 = 14,
+
+ #[cfg(hash_v3)]
+ /// SHA-256 Algorithm
+ SHA512 = 15,
}
/// Input data width selection
@@ -83,7 +113,10 @@ pub struct Hash<'d, T: Instance> {
impl<'d, T: Instance> Hash<'d, T> {
/// Instantiates, resets, and enables the HASH peripheral.
- pub fn new(peripheral: impl Peripheral<P = T> + 'd) -> Self {
+ pub fn new(
+ peripheral: impl Peripheral<P = T> + 'd,
+ _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+ ) -> Self {
HASH::enable_and_reset();
into_ref!(peripheral);
let instance = Self {
@@ -115,10 +148,31 @@ impl<'d, T: Instance> Hash<'d, T> {
T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
// Select the algorithm.
+ #[cfg(hash_v1)]
if ctx.algo == Algorithm::MD5 {
T::regs().cr().modify(|w| w.set_algo(true));
}
+ #[cfg(hash_v2)]
+ {
+ // Select the algorithm.
+ let mut algo0 = false;
+ let mut algo1 = false;
+ if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
+ algo0 = true;
+ }
+ if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
+ algo1 = true;
+ }
+ T::regs().cr().modify(|w| w.set_algo0(algo0));
+ T::regs().cr().modify(|w| w.set_algo1(algo1));
+ }
+
+ #[cfg(any(hash_v3, hash_v4))]
+ T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
+
+ T::regs().cr().modify(|w| w.set_init(true));
+
// Store and return the state of the peripheral.
self.store_context(&mut ctx).await;
ctx
@@ -174,7 +228,7 @@ impl<'d, T: Instance> Hash<'d, T> {
ilen_remaining -= copy_len;
input_start += copy_len;
}
- self.accumulate(&ctx.buffer[0..64]);
+ self.accumulate(&ctx.buffer[0..DIGEST_BLOCK_SIZE]);
ctx.buflen = 0;
// Move any extra data to the now-empty buffer.
@@ -229,7 +283,18 @@ impl<'d, T: Instance> Hash<'d, T> {
// Return the digest.
let digest_words = match ctx.algo {
Algorithm::SHA1 => 5,
+ #[cfg(any(hash_v1, hash_v4))]
Algorithm::MD5 => 4,
+ Algorithm::SHA224 => 7,
+ Algorithm::SHA256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA384 => 12,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_224 => 7,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512 => 16,
};
let mut i = 0;
while i < digest_words {
diff --git a/embassy-stm32/src/hash/v2v3.rs b/embassy-stm32/src/hash/v2.rs
similarity index 98%
rename from embassy-stm32/src/hash/v2v3.rs
rename to embassy-stm32/src/hash/v2.rs
index ba1e05f0c..b8104c825 100644
--- a/embassy-stm32/src/hash/v2v3.rs
+++ b/embassy-stm32/src/hash/v2.rs
@@ -111,7 +111,11 @@ pub struct Hash<'d, T: Instance, D: Dma<T>> {
impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
/// Instantiates, resets, and enables the HASH peripheral.
- pub fn new(peripheral: impl Peripheral<P = T> + 'd, dma: impl Peripheral<P = D> + 'd) -> Self {
+ pub fn new(
+ peripheral: impl Peripheral<P = T> + 'd,
+ dma: impl Peripheral<P = D> + 'd,
+ _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+ ) -> Self {
HASH::enable_and_reset();
into_ref!(peripheral, dma);
let instance = Self {
diff --git a/examples/stm32f7/.cargo/config.toml b/examples/stm32f7/.cargo/config.toml
index 9088eea6e..086da2d78 100644
--- a/examples/stm32f7/.cargo/config.toml
+++ b/examples/stm32f7/.cargo/config.toml
@@ -1,6 +1,6 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
-runner = "probe-rs run --chip STM32F767ZITx"
+runner = "probe-rs run --chip STM32F777ZITx"
[build]
target = "thumbv7em-none-eabihf"
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index 4bd9b4e2e..7d96bd49c 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -3,12 +3,15 @@
use defmt::info;
use embassy_executor::Spawner;
-use embassy_stm32::hash::*;
-use embassy_stm32::Config;
+use embassy_stm32::{bind_interrupts, Config, hash, hash::*, peripherals};
use embassy_time::Instant;
use sha2::{Digest, Sha256};
use {defmt_rtt as _, panic_probe as _};
+bind_interrupts!(struct Irqs {
+ HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
+});
+
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
let config = Config::default();
@@ -17,7 +20,7 @@ async fn main(_spawner: Spawner) -> ! {
let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
- let mut hw_hasher = Hash::new(p.HASH, p.DMA2_CH7);
+ let mut hw_hasher = Hash::new(p.HASH, p.DMA2_CH7, Irqs);
let hw_start_time = Instant::now();
From bb743420be5f7347cab7e2cc19a427b93e90b1e8 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Fri, 9 Feb 2024 10:14:34 +0200
Subject: [PATCH 162/392] faq: Fix typo
---
docs/modules/ROOT/pages/best_practices.adoc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/docs/modules/ROOT/pages/best_practices.adoc b/docs/modules/ROOT/pages/best_practices.adoc
index 1e02f9ba9..bfcedec06 100644
--- a/docs/modules/ROOT/pages/best_practices.adoc
+++ b/docs/modules/ROOT/pages/best_practices.adoc
@@ -3,8 +3,10 @@
Over time, a couple of best practices have emerged. The following list should serve as a guideline for developers writing embedded software in _Rust_, especially in the context of the _Embassy_ framework.
== Passing Buffers by Reference
-It may be tempting to pass arrays or wrappers, like link:https://docs.rs/heapless/latest/heapless/[`heapless::Vec`], to a function or return one just like you would with a `std::Vec`. However, in most embedded applications you don't want to spend ressources on an allocator and end up placing buffers on the stack.
-This, however, can easily blow up your stack if you are not careful.
+It may be tempting to pass arrays or wrappers, like link:https://docs.rs/heapless/latest/heapless/[`heapless::Vec`],
+to a function or return one just like you would with a `std::Vec`. However, in most embedded applications you don't
+want to spend resources on an allocator and end up placing buffers on the stack. This, however, can easily blow up
+your stack if you are not careful.
Consider the following example:
[,rust]
From 6e2d54c40bfdb07b6bb28f5fd8009846d0695f67 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Fri, 9 Feb 2024 10:14:55 +0200
Subject: [PATCH 163/392] faq: Nightly is not required anymore
---
docs/modules/ROOT/pages/faq.adoc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/docs/modules/ROOT/pages/faq.adoc b/docs/modules/ROOT/pages/faq.adoc
index 05ff7c598..c8695a01a 100644
--- a/docs/modules/ROOT/pages/faq.adoc
+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -29,11 +29,10 @@ If you see an error like this:
You are likely missing some features of the `embassy-executor` crate.
-For Cortex-M targets, consider making sure that ALL of the following features are active in your `Cargo.toml` for the `embassy-executor` crate:
+For Cortex-M targets, check whether ALL of the following features are enabled in your `Cargo.toml` for the `embassy-executor` crate:
* `arch-cortex-m`
* `executor-thread`
-* `nightly`
For ESP32, consider using the executors and `#[main]` macro provided by your appropriate link:https://crates.io/crates/esp-hal-common[HAL crate].
From cbdc49ef8d92606f917d1df0d88e4baef7bb23df Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Fri, 9 Feb 2024 10:15:15 +0200
Subject: [PATCH 164/392] faq: embassy-time was split into three packages,
update faq accordingly
I ran into this issue when I had to pull in embassy-nrf from git,
though cargo didn't complain about conflicting embassy-time links.
---
docs/modules/ROOT/pages/faq.adoc | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/docs/modules/ROOT/pages/faq.adoc b/docs/modules/ROOT/pages/faq.adoc
index c8695a01a..7fb81e2ca 100644
--- a/docs/modules/ROOT/pages/faq.adoc
+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -124,15 +124,18 @@ You have multiple versions of the same crate in your dependency tree. This means
embassy crates are coming from crates.io, and some from git, each of them pulling in a different set
of dependencies.
-To resolve this issue, make sure to only use a single source for all your embassy crates! To do this,
-you should patch your dependencies to use git sources using `[patch.crates.io]` and maybe `[patch.'https://github.com/embassy-rs/embassy.git']`.
+To resolve this issue, make sure to only use a single source for all your embassy crates!
+To do this, you should patch your dependencies to use git sources using `[patch.crates.io]`
+and maybe `[patch.'https://github.com/embassy-rs/embassy.git']`.
Example:
[source,toml]
----
[patch.crates-io]
-embassy-time = { git = "https://github.com/embassy-rs/embassy.git", rev = "e5fdd35" }
+embassy-time-queue-driver = { git = "https://github.com/embassy-rs/embassy.git", rev = "e5fdd35" }
+embassy-time-driver = { git = "https://github.com/embassy-rs/embassy.git", rev = "e5fdd35" }
+# embassy-time = { git = "https://github.com/embassy-rs/embassy.git", rev = "e5fdd35" }
----
Note that the git revision should match any other embassy patches or git dependencies that you are using!
From 32f950cb5ebe478b2641a991dcaa00591ef081f6 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Fri, 9 Feb 2024 20:29:38 +0100
Subject: [PATCH 165/392] docs: use correct link to book
Fixes #2550
---
README.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/README.md b/README.md
index 24347a43f..b6f667f75 100644
--- a/README.md
+++ b/README.md
@@ -2,7 +2,7 @@
Embassy is the next-generation framework for embedded applications. Write safe, correct and energy-efficient embedded code faster, using the Rust programming language, its async facilities, and the Embassy libraries.
-## <a href="https://embassy.dev/dev/index.html">Documentation</a> - <a href="https://docs.embassy.dev/">API reference</a> - <a href="https://embassy.dev/">Website</a> - <a href="https://matrix.to/#/#embassy-rs:matrix.org">Chat</a>
+## <a href="https://embassy.dev/book/dev/index.html">Documentation</a> - <a href="https://docs.embassy.dev/">API reference</a> - <a href="https://embassy.dev/">Website</a> - <a href="https://matrix.to/#/#embassy-rs:matrix.org">Chat</a>
## Rust + async ❤️ embedded
The Rust programming language is blazingly fast and memory-efficient, with no runtime, garbage collector or OS. It catches a wide variety of bugs at compile time, thanks to its full memory- and thread-safety, and expressive type system.
From d6636ca11669c60925acb08c32d488c481ee1581 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Tue, 30 Jan 2024 16:54:06 +0800
Subject: [PATCH 166/392] minor fix
---
embassy-stm32/src/dma/ringbuffer.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs
index c5b42060a..23f1d67d5 100644
--- a/embassy-stm32/src/dma/ringbuffer.rs
+++ b/embassy-stm32/src/dma/ringbuffer.rs
@@ -37,6 +37,7 @@ pub struct ReadableDmaRingBuffer<'a, W: Word> {
}
#[derive(Debug, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct OverrunError;
pub trait DmaCtrl {
From dc4898ca89d2130158acf1ced1f8cb3b25efe4b8 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Tue, 30 Jan 2024 16:53:39 +0800
Subject: [PATCH 167/392] update timer mod after stm32-metapac timer_v2
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/time_driver.rs | 8 +-
embassy-stm32/src/timer/complementary_pwm.rs | 2 +-
embassy-stm32/src/timer/mod.rs | 526 ++++++++++++++-----
embassy-stm32/src/timer/qei.rs | 2 +-
embassy-stm32/src/timer/simple_pwm.rs | 6 +-
examples/stm32h7/src/bin/dac_dma.rs | 14 +-
examples/stm32l4/src/bin/dac_dma.rs | 14 +-
8 files changed, 433 insertions(+), 143 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 61d70b732..c6bc27f89 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7c933984fe0cbd120b6aaa7742bd585f89fa786" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", rev = "stm32-data-028efe4e6e0719b661cbdf8ffda3341e4d63d0df" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7c933984fe0cbd120b6aaa7742bd585f89fa786", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-028efe4e6e0719b661cbdf8ffda3341e4d63d0df", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 320b29ddb..29ff4a736 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -14,7 +14,7 @@ use crate::pac::timer::vals;
use crate::rcc::sealed::RccPeripheral;
#[cfg(feature = "low-power")]
use crate::rtc::Rtc;
-use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};
+use crate::timer::sealed::{CoreInstance, GeneralPurpose16bitInstance as Instance};
use crate::{interrupt, peripherals};
// NOTE regarding ALARM_COUNT:
@@ -234,8 +234,8 @@ impl RtcDriver {
w.set_ccie(0, true);
});
- <T as BasicInstance>::Interrupt::unpend();
- unsafe { <T as BasicInstance>::Interrupt::enable() };
+ <T as CoreInstance>::Interrupt::unpend();
+ unsafe { <T as CoreInstance>::Interrupt::enable() };
r.cr1().modify(|w| w.set_cen(true));
}
@@ -251,7 +251,7 @@ impl RtcDriver {
// Clear all interrupt flags. Bits in SR are "write 0 to clear", so write the bitwise NOT.
// Other approaches such as writing all zeros, or RMWing won't work, they can
// miss interrupts.
- r.sr().write_value(regs::SrGp(!sr.0));
+ r.sr().write_value(regs::SrGp16(!sr.0));
// Overflow
if sr.uif() {
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index eddce0404..0470e3048 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -52,7 +52,7 @@ pub struct ComplementaryPwm<'d, T> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
+impl<'d, T: GeneralPurpose16bitInstance + ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
/// Create a new complementary PWM driver.
#[allow(clippy::too_many_arguments)]
pub fn new(
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 210bf7153..f66b4d094 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -1,5 +1,19 @@
//! Timers, PWM, quadrature decoder.
+// Timer inheritance
+//
+// CaptureCompare16bitInstance ComplementaryCaptureCompare16bitInstance
+// v v
+// Core -------------------------> 1CH -------------------------> 1CH_CMP
+// | | ^ |
+// +--> Basic_NoCr2 --> Basic +--> 2CH --> GP16 --> GP32 | +--> 2CH_CMP --> ADV
+// | | | ^ | | ^ ^
+// | | +------|--|--------------|-----------+ |
+// | +--------------------+ +--------------|-----------|---------+
+// | | | |
+// | +--------------------------------------|-----------+
+// +----------------------------------------------------+
+
pub mod complementary_pwm;
pub mod qei;
pub mod simple_pwm;
@@ -19,32 +33,32 @@ pub mod low_level {
pub(crate) mod sealed {
use super::*;
- /// Basic 16-bit timer instance.
- pub trait Basic16bitInstance: RccPeripheral {
+ /// Virtual Core 16-bit timer instance.
+ pub trait CoreInstance: RccPeripheral {
/// Interrupt for this timer.
type Interrupt: interrupt::typelevel::Interrupt;
- /// Get access to the basic 16bit timer registers.
+ /// Get access to the virutal core 16bit timer registers.
///
/// Note: This works even if the timer is more capable, because registers
/// for the less capable timers are a subset. This allows writing a driver
/// for a given set of capabilities, and having it transparently work with
/// more capable timers.
- fn regs() -> crate::pac::timer::TimBasic;
+ fn regs_core() -> crate::pac::timer::TimCore;
/// Start the timer.
fn start(&mut self) {
- Self::regs().cr1().modify(|r| r.set_cen(true));
+ Self::regs_core().cr1().modify(|r| r.set_cen(true));
}
/// Stop the timer.
fn stop(&mut self) {
- Self::regs().cr1().modify(|r| r.set_cen(false));
+ Self::regs_core().cr1().modify(|r| r.set_cen(false));
}
/// Reset the counter value to 0
fn reset(&mut self) {
- Self::regs().cnt().write(|r| r.set_cnt(0));
+ Self::regs_core().cnt().write(|r| r.set_cnt(0));
}
/// Set the frequency of how many times per second the timer counts up to the max value or down to 0.
@@ -64,7 +78,7 @@ pub(crate) mod sealed {
// the timer counts `0..=arr`, we want it to count `0..divide_by`
let arr = unwrap!(u16::try_from(divide_by - 1));
- let regs = Self::regs();
+ let regs = Self::regs_core();
regs.psc().write(|r| r.set_psc(psc));
regs.arr().write(|r| r.set_arr(arr));
@@ -77,7 +91,7 @@ pub(crate) mod sealed {
///
/// Returns whether the update interrupt flag was set.
fn clear_update_interrupt(&mut self) -> bool {
- let regs = Self::regs();
+ let regs = Self::regs_core();
let sr = regs.sr().read();
if sr.uif() {
regs.sr().modify(|r| {
@@ -91,29 +105,19 @@ pub(crate) mod sealed {
/// Enable/disable the update interrupt.
fn enable_update_interrupt(&mut self, enable: bool) {
- Self::regs().dier().modify(|r| r.set_uie(enable));
- }
-
- /// Enable/disable the update dma.
- fn enable_update_dma(&mut self, enable: bool) {
- Self::regs().dier().modify(|r| r.set_ude(enable));
- }
-
- /// Get the update dma enable/disable state.
- fn get_update_dma_state(&self) -> bool {
- Self::regs().dier().read().ude()
+ Self::regs_core().dier().modify(|r| r.set_uie(enable));
}
/// Enable/disable autoreload preload.
fn set_autoreload_preload(&mut self, enable: bool) {
- Self::regs().cr1().modify(|r| r.set_arpe(enable));
+ Self::regs_core().cr1().modify(|r| r.set_arpe(enable));
}
/// Get the timer frequency.
fn get_frequency(&self) -> Hertz {
let timer_f = Self::frequency();
- let regs = Self::regs();
+ let regs = Self::regs_core();
let arr = regs.arr().read().arr();
let psc = regs.psc().read().psc();
@@ -121,8 +125,67 @@ pub(crate) mod sealed {
}
}
+ /// Virtual Basic without CR2 16-bit timer instance.
+ pub trait BasicNoCr2Instance: CoreInstance {
+ /// Get access to the Baisc 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_basic_no_cr2() -> crate::pac::timer::TimBasicNoCr2;
+
+ /// Enable/disable the update dma.
+ fn enable_update_dma(&mut self, enable: bool) {
+ Self::regs_basic_no_cr2().dier().modify(|r| r.set_ude(enable));
+ }
+
+ /// Get the update dma enable/disable state.
+ fn get_update_dma_state(&self) -> bool {
+ Self::regs_basic_no_cr2().dier().read().ude()
+ }
+ }
+
+ /// Basic 16-bit timer instance.
+ pub trait BasicInstance: BasicNoCr2Instance {
+ /// Get access to the Baisc 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_basic() -> crate::pac::timer::TimBasic;
+ }
+
+ /// Gneral-purpose 1 channel 16-bit timer instance.
+ pub trait GeneralPurpose1ChannelInstance: CoreInstance {
+ /// Get access to the general purpose 1 channel 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_1ch() -> crate::pac::timer::Tim1ch;
+
+ /// Set clock divider.
+ fn set_clock_division(&mut self, ckd: vals::Ckd) {
+ Self::regs_1ch().cr1().modify(|r| r.set_ckd(ckd));
+ }
+ }
+
+ /// Gneral-purpose 1 channel 16-bit timer instance.
+ pub trait GeneralPurpose2ChannelInstance: GeneralPurpose1ChannelInstance {
+ /// Get access to the general purpose 2 channel 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_2ch() -> crate::pac::timer::Tim2ch;
+ }
+
/// Gneral-purpose 16-bit timer instance.
- pub trait GeneralPurpose16bitInstance: Basic16bitInstance {
+ pub trait GeneralPurpose16bitInstance: BasicInstance + GeneralPurpose2ChannelInstance {
/// Get access to the general purpose 16bit timer registers.
///
/// Note: This works even if the timer is more capable, because registers
@@ -135,7 +198,7 @@ pub(crate) mod sealed {
fn set_counting_mode(&mut self, mode: CountingMode) {
let (cms, dir) = mode.into();
- let timer_enabled = Self::regs().cr1().read().cen();
+ let timer_enabled = Self::regs_core().cr1().read().cen();
// Changing from edge aligned to center aligned (and vice versa) is not allowed while the timer is running.
// Changing direction is discouraged while the timer is running.
assert!(!timer_enabled);
@@ -149,11 +212,6 @@ pub(crate) mod sealed {
let cr1 = Self::regs_gp16().cr1().read();
(cr1.cms(), cr1.dir()).into()
}
-
- /// Set clock divider.
- fn set_clock_division(&mut self, ckd: vals::Ckd) {
- Self::regs_gp16().cr1().modify(|r| r.set_ckd(ckd));
- }
}
/// Gneral-purpose 32-bit timer instance.
@@ -196,36 +254,67 @@ pub(crate) mod sealed {
}
}
+ /// Gneral-purpose 1 channel with one complementary 16-bit timer instance.
+ pub trait GeneralPurpose1ChannelComplementaryInstance: BasicNoCr2Instance + GeneralPurpose1ChannelInstance {
+ /// Get access to the general purpose 1 channel with one complementary 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_1ch_cmp() -> crate::pac::timer::Tim1chCmp;
+
+ /// Enable timer outputs.
+ fn enable_outputs(&mut self) {
+ Self::regs_1ch_cmp().bdtr().modify(|w| w.set_moe(true));
+ }
+ }
+
+ /// Gneral-purpose 2 channel with one complementary 16-bit timer instance.
+ pub trait GeneralPurpose2ChannelComplementaryInstance:
+ BasicInstance + GeneralPurpose1ChannelComplementaryInstance
+ {
+ /// Get access to the general purpose 2 channel with one complementary 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_2ch_cmp() -> crate::pac::timer::Tim2chCmp;
+ }
+
/// Advanced control timer instance.
- pub trait AdvancedControlInstance: GeneralPurpose16bitInstance {
+ pub trait AdvancedControlInstance:
+ GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance
+ {
/// Get access to the advanced timer registers.
fn regs_advanced() -> crate::pac::timer::TimAdv;
}
/// Capture/Compare 16-bit timer instance.
- pub trait CaptureCompare16bitInstance: GeneralPurpose16bitInstance {
+ pub trait CaptureCompare16bitInstance: GeneralPurpose1ChannelInstance {
/// Set input capture filter.
- fn set_input_capture_filter(&mut self, channel: Channel, icf: vals::Icf) {
+ fn set_input_capture_filter(&mut self, channel: Channel, icf: vals::FilterValue) {
let raw_channel = channel.index();
- Self::regs_gp16()
+ Self::regs_1ch()
.ccmr_input(raw_channel / 2)
.modify(|r| r.set_icf(raw_channel % 2, icf));
}
/// Clear input interrupt.
fn clear_input_interrupt(&mut self, channel: Channel) {
- Self::regs_gp16().sr().modify(|r| r.set_ccif(channel.index(), false));
+ Self::regs_1ch().sr().modify(|r| r.set_ccif(channel.index(), false));
}
/// Enable input interrupt.
fn enable_input_interrupt(&mut self, channel: Channel, enable: bool) {
- Self::regs_gp16().dier().modify(|r| r.set_ccie(channel.index(), enable));
+ Self::regs_1ch().dier().modify(|r| r.set_ccie(channel.index(), enable));
}
/// Set input capture prescaler.
fn set_input_capture_prescaler(&mut self, channel: Channel, factor: u8) {
let raw_channel = channel.index();
- Self::regs_gp16()
+ Self::regs_1ch()
.ccmr_input(raw_channel / 2)
.modify(|r| r.set_icpsc(raw_channel % 2, factor));
}
@@ -233,14 +322,14 @@ pub(crate) mod sealed {
/// Set input TI selection.
fn set_input_ti_selection(&mut self, channel: Channel, tisel: InputTISelection) {
let raw_channel = channel.index();
- Self::regs_gp16()
+ Self::regs_1ch()
.ccmr_input(raw_channel / 2)
.modify(|r| r.set_ccs(raw_channel % 2, tisel.into()));
}
/// Set input capture mode.
fn set_input_capture_mode(&mut self, channel: Channel, mode: InputCaptureMode) {
- Self::regs_gp16().ccer().modify(|r| match mode {
+ Self::regs_1ch().ccer().modify(|r| match mode {
InputCaptureMode::Rising => {
r.set_ccnp(channel.index(), false);
r.set_ccp(channel.index(), false);
@@ -256,12 +345,9 @@ pub(crate) mod sealed {
});
}
- /// Enable timer outputs.
- fn enable_outputs(&mut self);
-
/// Set output compare mode.
fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
- let r = Self::regs_gp16();
+ let r = Self::regs_1ch();
let raw_channel: usize = channel.index();
r.ccmr_output(raw_channel / 2)
.modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
@@ -269,45 +355,45 @@ pub(crate) mod sealed {
/// Set output polarity.
fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- Self::regs_gp16()
+ Self::regs_1ch()
.ccer()
.modify(|w| w.set_ccp(channel.index(), polarity.into()));
}
/// Enable/disable a channel.
fn enable_channel(&mut self, channel: Channel, enable: bool) {
- Self::regs_gp16().ccer().modify(|w| w.set_cce(channel.index(), enable));
+ Self::regs_1ch().ccer().modify(|w| w.set_cce(channel.index(), enable));
}
/// Get enable/disable state of a channel
fn get_channel_enable_state(&self, channel: Channel) -> bool {
- Self::regs_gp16().ccer().read().cce(channel.index())
+ Self::regs_1ch().ccer().read().cce(channel.index())
}
/// Set compare value for a channel.
fn set_compare_value(&mut self, channel: Channel, value: u16) {
- Self::regs_gp16().ccr(channel.index()).modify(|w| w.set_ccr(value));
+ Self::regs_1ch().ccr(channel.index()).modify(|w| w.set_ccr(value));
}
/// Get capture value for a channel.
fn get_capture_value(&mut self, channel: Channel) -> u16 {
- Self::regs_gp16().ccr(channel.index()).read().ccr()
+ Self::regs_1ch().ccr(channel.index()).read().ccr()
}
/// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
fn get_max_compare_value(&self) -> u16 {
- Self::regs_gp16().arr().read().arr()
+ Self::regs_1ch().arr().read().arr()
}
/// Get compare value for a channel.
fn get_compare_value(&self, channel: Channel) -> u16 {
- Self::regs_gp16().ccr(channel.index()).read().ccr()
+ Self::regs_1ch().ccr(channel.index()).read().ccr()
}
/// Set output compare preload.
fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
let channel_index = channel.index();
- Self::regs_gp16()
+ Self::regs_1ch()
.ccmr_output(channel_index / 2)
.modify(|w| w.set_ocpe(channel_index % 2, preload));
}
@@ -334,27 +420,29 @@ pub(crate) mod sealed {
}
/// Capture/Compare 16-bit timer instance with complementary pin support.
- pub trait ComplementaryCaptureCompare16bitInstance: CaptureCompare16bitInstance + AdvancedControlInstance {
+ pub trait ComplementaryCaptureCompare16bitInstance:
+ CaptureCompare16bitInstance + GeneralPurpose1ChannelComplementaryInstance
+ {
/// Set complementary output polarity.
fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- Self::regs_advanced()
+ Self::regs_1ch_cmp()
.ccer()
.modify(|w| w.set_ccnp(channel.index(), polarity.into()));
}
/// Set clock divider for the dead time.
fn set_dead_time_clock_division(&mut self, value: vals::Ckd) {
- Self::regs_advanced().cr1().modify(|w| w.set_ckd(value));
+ Self::regs_1ch_cmp().cr1().modify(|w| w.set_ckd(value));
}
/// Set dead time, as a fraction of the max duty value.
fn set_dead_time_value(&mut self, value: u8) {
- Self::regs_advanced().bdtr().modify(|w| w.set_dtg(value));
+ Self::regs_1ch_cmp().bdtr().modify(|w| w.set_dtg(value));
}
/// Enable/disable a complementary channel.
fn enable_complementary_channel(&mut self, channel: Channel, enable: bool) {
- Self::regs_advanced()
+ Self::regs_1ch_cmp()
.ccer()
.modify(|w| w.set_ccne(channel.index(), enable));
}
@@ -571,11 +659,29 @@ impl From<OutputPolarity> for bool {
}
}
-/// Basic 16-bit timer instance.
-pub trait Basic16bitInstance: sealed::Basic16bitInstance + 'static {}
+/// Virtual Core 16-bit timer instance.
+pub trait CoreInstance: sealed::CoreInstance + 'static {}
-/// Gneral-purpose 16-bit timer instance.
-pub trait GeneralPurpose16bitInstance: sealed::GeneralPurpose16bitInstance + Basic16bitInstance + 'static {}
+/// Virtual Basic 16-bit timer without CR2 register instance.
+pub trait BasicNoCr2Instance: sealed::BasicNoCr2Instance + CoreInstance + 'static {}
+
+/// Basic 16-bit timer instance.
+pub trait BasicInstance: sealed::BasicInstance + BasicNoCr2Instance + 'static {}
+
+/// 1 channel 16-bit instance.
+pub trait GeneralPurpose1ChannelInstance: sealed::GeneralPurpose1ChannelInstance + CoreInstance + 'static {}
+
+/// 2 channel 16-bit instance.
+pub trait GeneralPurpose2ChannelInstance:
+ sealed::GeneralPurpose2ChannelInstance + GeneralPurpose1ChannelInstance + 'static
+{
+}
+
+/// General-purpose 16-bit timer instance.
+pub trait GeneralPurpose16bitInstance:
+ sealed::GeneralPurpose16bitInstance + BasicInstance + GeneralPurpose2ChannelInstance + 'static
+{
+}
/// Gneral-purpose 32-bit timer instance.
pub trait GeneralPurpose32bitInstance:
@@ -583,18 +689,39 @@ pub trait GeneralPurpose32bitInstance:
{
}
+/// General-purpose 1 channel with one complementary 16-bit timer instance.
+pub trait GeneralPurpose1ChannelComplementaryInstance:
+ sealed::GeneralPurpose1ChannelComplementaryInstance + GeneralPurpose1ChannelInstance + 'static
+{
+}
+
+/// General-purpose 2 channel with one complementary 16-bit timer instance.
+pub trait GeneralPurpose2ChannelComplementaryInstance:
+ sealed::GeneralPurpose2ChannelComplementaryInstance
+ + BasicInstance
+ + GeneralPurpose1ChannelComplementaryInstance
+ + 'static
+{
+}
+
/// Advanced control timer instance.
-pub trait AdvancedControlInstance: sealed::AdvancedControlInstance + GeneralPurpose16bitInstance + 'static {}
+pub trait AdvancedControlInstance:
+ sealed::AdvancedControlInstance + GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance + 'static
+{
+}
/// Capture/Compare 16-bit timer instance.
pub trait CaptureCompare16bitInstance:
- sealed::CaptureCompare16bitInstance + GeneralPurpose16bitInstance + 'static
+ sealed::CaptureCompare16bitInstance + GeneralPurpose1ChannelInstance + 'static
{
}
/// Capture/Compare 16-bit timer instance with complementary pin support.
pub trait ComplementaryCaptureCompare16bitInstance:
- sealed::ComplementaryCaptureCompare16bitInstance + CaptureCompare16bitInstance + AdvancedControlInstance + 'static
+ sealed::ComplementaryCaptureCompare16bitInstance
+ + CaptureCompare16bitInstance
+ + GeneralPurpose1ChannelComplementaryInstance
+ + 'static
{
}
@@ -621,12 +748,34 @@ pin_trait!(BreakInput2Comparator1Pin, CaptureCompare16bitInstance);
pin_trait!(BreakInput2Comparator2Pin, CaptureCompare16bitInstance);
#[allow(unused)]
-macro_rules! impl_basic_16bit_timer {
+macro_rules! impl_core_timer {
($inst:ident, $irq:ident) => {
- impl sealed::Basic16bitInstance for crate::peripherals::$inst {
+ impl sealed::CoreInstance for crate::peripherals::$inst {
type Interrupt = crate::interrupt::typelevel::$irq;
- fn regs() -> crate::pac::timer::TimBasic {
+ fn regs_core() -> crate::pac::timer::TimCore {
+ unsafe { crate::pac::timer::TimCore::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_basic_no_cr2_timer {
+ ($inst:ident) => {
+ impl sealed::BasicNoCr2Instance for crate::peripherals::$inst {
+ fn regs_basic_no_cr2() -> crate::pac::timer::TimBasicNoCr2 {
+ unsafe { crate::pac::timer::TimBasicNoCr2::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_basic_timer {
+ ($inst:ident) => {
+ impl sealed::BasicInstance for crate::peripherals::$inst {
+ fn regs_basic() -> crate::pac::timer::TimBasic {
unsafe { crate::pac::timer::TimBasic::from_ptr(crate::pac::$inst.as_ptr()) }
}
}
@@ -634,7 +783,40 @@ macro_rules! impl_basic_16bit_timer {
}
#[allow(unused)]
-macro_rules! impl_32bit_timer {
+macro_rules! impl_1ch_timer {
+ ($inst:ident) => {
+ impl sealed::GeneralPurpose1ChannelInstance for crate::peripherals::$inst {
+ fn regs_1ch() -> crate::pac::timer::Tim1ch {
+ unsafe { crate::pac::timer::Tim1ch::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_2ch_timer {
+ ($inst:ident) => {
+ impl sealed::GeneralPurpose2ChannelInstance for crate::peripherals::$inst {
+ fn regs_2ch() -> crate::pac::timer::Tim2ch {
+ unsafe { crate::pac::timer::Tim2ch::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_gp_16bit_timer {
+ ($inst:ident) => {
+ impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
+ fn regs_gp16() -> crate::pac::timer::TimGp16 {
+ unsafe { crate::pac::timer::TimGp16::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_gp_32bit_timer {
($inst:ident) => {
impl sealed::GeneralPurpose32bitInstance for crate::peripherals::$inst {
fn regs_gp32() -> crate::pac::timer::TimGp32 {
@@ -644,84 +826,194 @@ macro_rules! impl_32bit_timer {
};
}
+#[allow(unused)]
+macro_rules! impl_1ch_cmp_timer {
+ ($inst:ident) => {
+ impl sealed::GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {
+ fn regs_1ch_cmp() -> crate::pac::timer::Tim1chCmp {
+ unsafe { crate::pac::timer::Tim1chCmp::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_2ch_cmp_timer {
+ ($inst:ident) => {
+ impl sealed::GeneralPurpose2ChannelComplementaryInstance for crate::peripherals::$inst {
+ fn regs_2ch_cmp() -> crate::pac::timer::Tim2chCmp {
+ unsafe { crate::pac::timer::Tim2chCmp::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_adv_timer {
+ ($inst:ident) => {
+ impl sealed::AdvancedControlInstance for crate::peripherals::$inst {
+ fn regs_advanced() -> crate::pac::timer::TimAdv {
+ unsafe { crate::pac::timer::TimAdv::from_ptr(crate::pac::$inst.as_ptr()) }
+ }
+ }
+ };
+}
+
#[allow(unused)]
macro_rules! impl_compare_capable_16bit {
($inst:ident) => {
- impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {
- fn enable_outputs(&mut self) {}
- }
+ impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_compare_capable_32bit {
+ ($inst:ident) => {
+ impl sealed::CaptureCompare32bitInstance for crate::peripherals::$inst {}
+ };
+}
+
+#[allow(unused)]
+macro_rules! impl_compare_capable_complementary_16bit {
+ ($inst:ident) => {
+ impl sealed::ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
}
foreach_interrupt! {
- ($inst:ident, timer, TIM_BASIC, UP, $irq:ident) => {
- impl_basic_16bit_timer!($inst, $irq);
- impl Basic16bitInstance for crate::peripherals::$inst {}
- };
- ($inst:ident, timer, TIM_GP16, UP, $irq:ident) => {
- impl_basic_16bit_timer!($inst, $irq);
- impl_compare_capable_16bit!($inst);
- impl Basic16bitInstance for crate::peripherals::$inst {}
- impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
- impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
- fn regs_gp16() -> crate::pac::timer::TimGp16 {
- crate::pac::$inst
- }
- }
+ ($inst:ident, timer, TIM_BASIC, UP, $irq:ident) => {
+ impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl BasicInstance for crate::peripherals::$inst {}
+ };
+
+ ($inst:ident, timer, TIM_1CH, UP, $irq:ident) => {
+ impl_core_timer!($inst, $irq);
+ impl_1ch_timer!($inst);
+ impl_compare_capable_16bit!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ };
+
+
+ ($inst:ident, timer, TIM_2CH, UP, $irq:ident) => {
+ impl_core_timer!($inst, $irq);
+ impl_1ch_timer!($inst);
+ impl_compare_capable_16bit!($inst);
+ impl_2ch_timer!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
+ };
+
+ ($inst:ident, timer, TIM_GP16, UP, $irq:ident) => {
+ impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
+ impl_1ch_timer!($inst);
+ impl_compare_capable_16bit!($inst);
+ impl_2ch_timer!($inst);
+ impl_gp_16bit_timer!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl BasicInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
};
($inst:ident, timer, TIM_GP32, UP, $irq:ident) => {
- impl_basic_16bit_timer!($inst, $irq);
- impl_32bit_timer!($inst);
+ impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
+ impl_1ch_timer!($inst);
impl_compare_capable_16bit!($inst);
- impl Basic16bitInstance for crate::peripherals::$inst {}
+ impl_compare_capable_32bit!($inst);
+ impl_2ch_timer!($inst);
+ impl_gp_16bit_timer!($inst);
+ impl_gp_32bit_timer!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl BasicInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl CaptureCompare32bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose32bitInstance for crate::peripherals::$inst {}
- impl sealed::CaptureCompare32bitInstance for crate::peripherals::$inst {}
-
- impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
- fn regs_gp16() -> crate::pac::timer::TimGp16 {
- unsafe { crate::pac::timer::TimGp16::from_ptr(crate::pac::$inst.as_ptr()) }
- }
- }
};
- ($inst:ident, timer, TIM_ADV, UP, $irq:ident) => {
- impl_basic_16bit_timer!($inst, $irq);
+ ($inst:ident, timer, TIM_1CH_CMP, UP, $irq:ident) => {
+ impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_1ch_timer!($inst);
+ impl_compare_capable_16bit!($inst);
+ impl_1ch_cmp_timer!($inst);
+ impl_compare_capable_complementary_16bit!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
+ impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
+ };
- impl Basic16bitInstance for crate::peripherals::$inst {}
+
+ ($inst:ident, timer, TIM_2CH_CMP, UP, $irq:ident) => {
+ impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
+ impl_1ch_timer!($inst);
+ impl_compare_capable_16bit!($inst);
+ impl_1ch_cmp_timer!($inst);
+ impl_compare_capable_complementary_16bit!($inst);
+ impl_2ch_cmp_timer!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl BasicInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
+ impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose2ChannelComplementaryInstance for crate::peripherals::$inst {}
+ };
+
+
+ ($inst:ident, timer, TIM_ADV, UP, $irq:ident) => {
+ impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
+ impl_1ch_timer!($inst);
+ impl_2ch_timer!($inst);
+ impl_compare_capable_16bit!($inst);
+ impl_1ch_cmp_timer!($inst);
+ impl_gp_16bit_timer!($inst);
+ impl_compare_capable_complementary_16bit!($inst);
+ impl_2ch_cmp_timer!($inst);
+ impl_adv_timer!($inst);
+ impl CoreInstance for crate::peripherals::$inst {}
+ impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl BasicInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose2ChannelComplementaryInstance for crate::peripherals::$inst {}
impl AdvancedControlInstance for crate::peripherals::$inst {}
- impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {
- fn enable_outputs(&mut self) {
- use crate::timer::sealed::AdvancedControlInstance;
- let r = Self::regs_advanced();
- r.bdtr().modify(|w| w.set_moe(true));
- }
- }
- impl sealed::ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
- impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
- fn regs_gp16() -> crate::pac::timer::TimGp16 {
- unsafe { crate::pac::timer::TimGp16::from_ptr(crate::pac::$inst.as_ptr()) }
- }
- }
-
- impl sealed::AdvancedControlInstance for crate::peripherals::$inst {
- fn regs_advanced() -> crate::pac::timer::TimAdv {
- crate::pac::$inst
- }
- }
};
}
// Update Event trigger DMA for every timer
-dma_trait!(UpDma, Basic16bitInstance);
+dma_trait!(UpDma, BasicNoCr2Instance);
dma_trait!(Ch1Dma, CaptureCompare16bitInstance);
dma_trait!(Ch2Dma, CaptureCompare16bitInstance);
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index 59efb72ba..75e5ab12a 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -57,7 +57,7 @@ pub struct Qei<'d, T> {
_inner: PeripheralRef<'d, T>,
}
-impl<'d, T: CaptureCompare16bitInstance> Qei<'d, T> {
+impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> Qei<'d, T> {
/// Create a new quadrature decoder driver.
pub fn new(tim: impl Peripheral<P = T> + 'd, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
Self::new_inner(tim)
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 0b4c1225f..1c665d456 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -59,7 +59,7 @@ pub struct SimplePwm<'d, T> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
+impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> SimplePwm<'d, T> {
/// Create a new simple PWM driver.
pub fn new(
tim: impl Peripheral<P = T> + 'd,
@@ -84,8 +84,6 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
this.set_frequency(freq);
this.inner.start();
- this.inner.enable_outputs();
-
[Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
.iter()
.for_each(|&channel| {
@@ -202,7 +200,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
&mut dma,
req,
duty,
- T::regs_gp16().ccr(channel.index()).as_ptr() as *mut _,
+ T::regs_1ch().ccr(channel.index()).as_ptr() as *mut _,
dma_transfer_option,
)
.await
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs
index 8e5c41a43..d88bd838f 100644
--- a/examples/stm32h7/src/bin/dac_dma.rs
+++ b/examples/stm32h7/src/bin/dac_dma.rs
@@ -8,7 +8,7 @@ use embassy_stm32::pac::timer::vals::Mms;
use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7};
use embassy_stm32::rcc::low_level::RccPeripheral;
use embassy_stm32::time::Hertz;
-use embassy_stm32::timer::low_level::Basic16bitInstance;
+use embassy_stm32::timer::low_level::BasicInstance;
use micromath::F32Ext;
use {defmt_rtt as _, panic_probe as _};
@@ -75,9 +75,9 @@ async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) {
dac.enable();
TIM6::enable_and_reset();
- TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
- TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
- TIM6::regs().cr1().modify(|w| {
+ TIM6::regs_basic().arr().modify(|w| w.set_arr(reload as u16 - 1));
+ TIM6::regs_basic().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+ TIM6::regs_basic().cr1().modify(|w| {
w.set_opm(false);
w.set_cen(true);
});
@@ -112,9 +112,9 @@ async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) {
}
TIM7::enable_and_reset();
- TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
- TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
- TIM7::regs().cr1().modify(|w| {
+ TIM7::regs_basic().arr().modify(|w| w.set_arr(reload as u16 - 1));
+ TIM7::regs_basic().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+ TIM7::regs_basic().cr1().modify(|w| {
w.set_opm(false);
w.set_cen(true);
});
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
index 8e5098557..f227812cd 100644
--- a/examples/stm32l4/src/bin/dac_dma.rs
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -8,7 +8,7 @@ use embassy_stm32::pac::timer::vals::Mms;
use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7};
use embassy_stm32::rcc::low_level::RccPeripheral;
use embassy_stm32::time::Hertz;
-use embassy_stm32::timer::low_level::Basic16bitInstance;
+use embassy_stm32::timer::low_level::BasicInstance;
use micromath::F32Ext;
use {defmt_rtt as _, panic_probe as _};
@@ -46,9 +46,9 @@ async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) {
dac.enable();
TIM6::enable_and_reset();
- TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
- TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
- TIM6::regs().cr1().modify(|w| {
+ TIM6::regs_basic().arr().modify(|w| w.set_arr(reload as u16 - 1));
+ TIM6::regs_basic().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+ TIM6::regs_basic().cr1().modify(|w| {
w.set_opm(false);
w.set_cen(true);
});
@@ -83,9 +83,9 @@ async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) {
}
TIM7::enable_and_reset();
- TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
- TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
- TIM7::regs().cr1().modify(|w| {
+ TIM7::regs_basic().arr().modify(|w| w.set_arr(reload as u16 - 1));
+ TIM7::regs_basic().cr2().modify(|w| w.set_mms(Mms::UPDATE));
+ TIM7::regs_basic().cr1().modify(|w| {
w.set_opm(false);
w.set_cen(true);
});
From 53bf0332e9e862fa5c09a1e9ab9a6d7116219ed7 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 10 Feb 2024 00:00:26 +0100
Subject: [PATCH 168/392] asdkf
---
embassy-stm32/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index c6bc27f89..eb67404d3 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", rev = "stm32-data-028efe4e6e0719b661cbdf8ffda3341e4d63d0df" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-028efe4e6e0719b661cbdf8ffda3341e4d63d0df" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
From d538829f2f3542c78ee9eb218c0b5c982acfb46b Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Thu, 1 Feb 2024 17:10:47 +0800
Subject: [PATCH 169/392] add methods with macro
---
embassy-stm32/src/timer/complementary_pwm.rs | 52 +-
embassy-stm32/src/timer/mod.rs | 522 ++++++++----------
embassy-stm32/src/timer/qei.rs | 4 +-
embassy-stm32/src/timer/simple_pwm.rs | 40 +-
.../stm32h7/src/bin/low_level_timer_api.rs | 4 +-
5 files changed, 298 insertions(+), 324 deletions(-)
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 0470e3048..b9cd044c9 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -1,6 +1,7 @@
//! PWM driver with complementary output support.
use core::marker::PhantomData;
+use core::ops::{Deref, DerefMut};
use embassy_hal_internal::{into_ref, PeripheralRef};
use stm32_metapac::timer::vals::Ckd;
@@ -23,7 +24,7 @@ pub struct ComplementaryPwmPin<'d, T, C> {
macro_rules! complementary_channel_impl {
($new_chx:ident, $channel:ident, $pin_trait:ident) => {
- impl<'d, T: CaptureCompare16bitInstance> ComplementaryPwmPin<'d, T, $channel> {
+ impl<'d, T: AdvancedControlInstance> ComplementaryPwmPin<'d, T, $channel> {
#[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
into_ref!(pin);
@@ -52,7 +53,7 @@ pub struct ComplementaryPwm<'d, T> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: GeneralPurpose16bitInstance + ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
+impl<'d, T: AdvancedControlInstance> ComplementaryPwm<'d, T> {
/// Create a new complementary PWM driver.
#[allow(clippy::too_many_arguments)]
pub fn new(
@@ -84,27 +85,30 @@ impl<'d, T: GeneralPurpose16bitInstance + ComplementaryCaptureCompare16bitInstan
this.inner.enable_outputs();
- this.inner
- .set_output_compare_mode(Channel::Ch1, OutputCompareMode::PwmMode1);
- this.inner
- .set_output_compare_mode(Channel::Ch2, OutputCompareMode::PwmMode1);
- this.inner
- .set_output_compare_mode(Channel::Ch3, OutputCompareMode::PwmMode1);
- this.inner
- .set_output_compare_mode(Channel::Ch4, OutputCompareMode::PwmMode1);
+ [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
+ .iter()
+ .for_each(|&channel| {
+ sealed::GeneralPurpose16bitInstance::set_output_compare_mode(
+ this.inner.deref_mut(),
+ channel,
+ OutputCompareMode::PwmMode1,
+ );
+ sealed::GeneralPurpose16bitInstance::set_output_compare_preload(this.inner.deref_mut(), channel, true);
+ });
+
this
}
/// Enable the given channel.
pub fn enable(&mut self, channel: Channel) {
- self.inner.enable_channel(channel, true);
- self.inner.enable_complementary_channel(channel, true);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
+ sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, true);
}
/// Disable the given channel.
pub fn disable(&mut self, channel: Channel) {
- self.inner.enable_complementary_channel(channel, false);
- self.inner.enable_channel(channel, false);
+ sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, false);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
}
/// Set PWM frequency.
@@ -132,13 +136,13 @@ impl<'d, T: GeneralPurpose16bitInstance + ComplementaryCaptureCompare16bitInstan
/// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
pub fn set_duty(&mut self, channel: Channel, duty: u16) {
assert!(duty <= self.get_max_duty());
- self.inner.set_compare_value(channel, duty)
+ sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
}
/// Set the output polarity for a given channel.
pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- self.inner.set_output_polarity(channel, polarity);
- self.inner.set_complementary_output_polarity(channel, polarity);
+ sealed::GeneralPurpose16bitInstance::set_output_polarity(self.inner.deref_mut(), channel, polarity);
+ sealed::AdvancedControlInstance::set_complementary_output_polarity(self.inner.deref_mut(), channel, polarity);
}
/// Set the dead time as a proportion of max_duty
@@ -150,19 +154,19 @@ impl<'d, T: GeneralPurpose16bitInstance + ComplementaryCaptureCompare16bitInstan
}
}
-impl<'d, T: ComplementaryCaptureCompare16bitInstance> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
+impl<'d, T: AdvancedControlInstance> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
type Channel = Channel;
type Time = Hertz;
type Duty = u16;
fn disable(&mut self, channel: Self::Channel) {
- self.inner.enable_complementary_channel(channel, false);
- self.inner.enable_channel(channel, false);
+ sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, false);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
}
fn enable(&mut self, channel: Self::Channel) {
- self.inner.enable_channel(channel, true);
- self.inner.enable_complementary_channel(channel, true);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
+ sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, true);
}
fn get_period(&self) -> Self::Time {
@@ -170,7 +174,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> embedded_hal_02::Pwm for C
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
- self.inner.get_compare_value(channel)
+ sealed::GeneralPurpose16bitInstance::get_compare_value(self.inner.deref(), channel)
}
fn get_max_duty(&self) -> Self::Duty {
@@ -179,7 +183,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> embedded_hal_02::Pwm for C
fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
assert!(duty <= self.get_max_duty());
- self.inner.set_compare_value(channel, duty)
+ sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
}
fn set_period<P>(&mut self, period: P)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index f66b4d094..2f5d5770a 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -2,8 +2,6 @@
// Timer inheritance
//
-// CaptureCompare16bitInstance ComplementaryCaptureCompare16bitInstance
-// v v
// Core -------------------------> 1CH -------------------------> 1CH_CMP
// | | ^ |
// +--> Basic_NoCr2 --> Basic +--> 2CH --> GP16 --> GP32 | +--> 2CH_CMP --> ADV
@@ -33,6 +31,156 @@ pub mod low_level {
pub(crate) mod sealed {
use super::*;
+ macro_rules! add_capture_compare_common_methods {
+ ($regs:ident) => {
+ /// Set input capture filter.
+ fn set_input_capture_filter(&mut self, channel: Channel, icf: vals::FilterValue) {
+ let raw_channel = channel.index();
+ Self::$regs()
+ .ccmr_input(raw_channel / 2)
+ .modify(|r| r.set_icf(raw_channel % 2, icf));
+ }
+
+ /// Clear input interrupt.
+ fn clear_input_interrupt(&mut self, channel: Channel) {
+ Self::$regs().sr().modify(|r| r.set_ccif(channel.index(), false));
+ }
+
+ /// Enable input interrupt.
+ fn enable_input_interrupt(&mut self, channel: Channel, enable: bool) {
+ Self::$regs()
+ .dier()
+ .modify(|r| r.set_ccie(channel.index(), enable));
+ }
+
+ /// Set input capture prescaler.
+ fn set_input_capture_prescaler(&mut self, channel: Channel, factor: u8) {
+ let raw_channel = channel.index();
+ Self::$regs()
+ .ccmr_input(raw_channel / 2)
+ .modify(|r| r.set_icpsc(raw_channel % 2, factor));
+ }
+
+ /// Set input TI selection.
+ fn set_input_ti_selection(&mut self, channel: Channel, tisel: InputTISelection) {
+ let raw_channel = channel.index();
+ Self::$regs()
+ .ccmr_input(raw_channel / 2)
+ .modify(|r| r.set_ccs(raw_channel % 2, tisel.into()));
+ }
+
+ /// Set input capture mode.
+ fn set_input_capture_mode(&mut self, channel: Channel, mode: InputCaptureMode) {
+ Self::$regs().ccer().modify(|r| match mode {
+ InputCaptureMode::Rising => {
+ r.set_ccnp(channel.index(), false);
+ r.set_ccp(channel.index(), false);
+ }
+ InputCaptureMode::Falling => {
+ r.set_ccnp(channel.index(), false);
+ r.set_ccp(channel.index(), true);
+ }
+ InputCaptureMode::BothEdges => {
+ r.set_ccnp(channel.index(), true);
+ r.set_ccp(channel.index(), true);
+ }
+ });
+ }
+
+ /// Set output compare mode.
+ fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
+ let r = Self::$regs();
+ let raw_channel: usize = channel.index();
+ r.ccmr_output(raw_channel / 2)
+ .modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
+ }
+
+ /// Set output polarity.
+ fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+ Self::$regs()
+ .ccer()
+ .modify(|w| w.set_ccp(channel.index(), polarity.into()));
+ }
+
+ /// Enable/disable a channel.
+ fn enable_channel(&mut self, channel: Channel, enable: bool) {
+ Self::$regs()
+ .ccer()
+ .modify(|w| w.set_cce(channel.index(), enable));
+ }
+
+ /// Get enable/disable state of a channel
+ fn get_channel_enable_state(&self, channel: Channel) -> bool {
+ Self::$regs().ccer().read().cce(channel.index())
+ }
+
+ /// Set compare value for a channel.
+ fn set_compare_value(&mut self, channel: Channel, value: u16) {
+ Self::$regs().ccr(channel.index()).modify(|w| w.set_ccr(value));
+ }
+
+ /// Get capture value for a channel.
+ fn get_capture_value(&mut self, channel: Channel) -> u16 {
+ Self::$regs().ccr(channel.index()).read().ccr()
+ }
+
+ /// Get compare value for a channel.
+ fn get_compare_value(&self, channel: Channel) -> u16 {
+ Self::$regs().ccr(channel.index()).read().ccr()
+ }
+
+ /// Set output compare preload.
+ fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
+ let channel_index = channel.index();
+ Self::regs_1ch()
+ .ccmr_output(channel_index / 2)
+ .modify(|w| w.set_ocpe(channel_index % 2, preload));
+ }
+ };
+ }
+
+ macro_rules! add_capture_compare_dma_methods {
+ ($regs:ident) => {
+ /// Get capture compare DMA selection
+ fn get_cc_dma_selection(&self) -> super::vals::Ccds {
+ Self::$regs().cr2().read().ccds()
+ }
+
+ /// Set capture compare DMA selection
+ fn set_cc_dma_selection(&mut self, ccds: super::vals::Ccds) {
+ Self::$regs().cr2().modify(|w| w.set_ccds(ccds))
+ }
+
+ /// Get capture compare DMA enable state
+ fn get_cc_dma_enable_state(&self, channel: Channel) -> bool {
+ Self::$regs().dier().read().ccde(channel.index())
+ }
+
+ /// Set capture compare DMA enable state
+ fn set_cc_dma_enable_state(&mut self, channel: Channel, ccde: bool) {
+ Self::$regs().dier().modify(|w| w.set_ccde(channel.index(), ccde))
+ }
+ };
+ }
+
+ macro_rules! add_complementary_capture_compare_methods {
+ ($regs:ident) => {
+ /// Set complementary output polarity.
+ fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+ Self::$regs()
+ .ccer()
+ .modify(|w| w.set_ccnp(channel.index(), polarity.into()));
+ }
+
+ /// Enable/disable a complementary channel.
+ fn enable_complementary_channel(&mut self, channel: Channel, enable: bool) {
+ Self::$regs()
+ .ccer()
+ .modify(|w| w.set_ccne(channel.index(), enable));
+ }
+ };
+ }
+
/// Virtual Core 16-bit timer instance.
pub trait CoreInstance: RccPeripheral {
/// Interrupt for this timer.
@@ -171,6 +319,13 @@ pub(crate) mod sealed {
fn set_clock_division(&mut self, ckd: vals::Ckd) {
Self::regs_1ch().cr1().modify(|r| r.set_ckd(ckd));
}
+
+ /// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
+ fn get_max_compare_value(&self) -> u16 {
+ Self::regs_1ch().arr().read().arr()
+ }
+
+ add_capture_compare_common_methods!(regs_1ch);
}
/// Gneral-purpose 1 channel 16-bit timer instance.
@@ -182,6 +337,8 @@ pub(crate) mod sealed {
/// for a given set of capabilities, and having it transparently work with
/// more capable timers.
fn regs_2ch() -> crate::pac::timer::Tim2ch;
+
+ add_capture_compare_common_methods!(regs_2ch);
}
/// Gneral-purpose 16-bit timer instance.
@@ -212,6 +369,9 @@ pub(crate) mod sealed {
let cr1 = Self::regs_gp16().cr1().read();
(cr1.cms(), cr1.dir()).into()
}
+
+ add_capture_compare_common_methods!(regs_gp16);
+ add_capture_compare_dma_methods!(regs_gp16);
}
/// Gneral-purpose 32-bit timer instance.
@@ -252,204 +412,7 @@ pub(crate) mod sealed {
timer_f / arr / (psc + 1)
}
- }
- /// Gneral-purpose 1 channel with one complementary 16-bit timer instance.
- pub trait GeneralPurpose1ChannelComplementaryInstance: BasicNoCr2Instance + GeneralPurpose1ChannelInstance {
- /// Get access to the general purpose 1 channel with one complementary 16bit timer registers.
- ///
- /// Note: This works even if the timer is more capable, because registers
- /// for the less capable timers are a subset. This allows writing a driver
- /// for a given set of capabilities, and having it transparently work with
- /// more capable timers.
- fn regs_1ch_cmp() -> crate::pac::timer::Tim1chCmp;
-
- /// Enable timer outputs.
- fn enable_outputs(&mut self) {
- Self::regs_1ch_cmp().bdtr().modify(|w| w.set_moe(true));
- }
- }
-
- /// Gneral-purpose 2 channel with one complementary 16-bit timer instance.
- pub trait GeneralPurpose2ChannelComplementaryInstance:
- BasicInstance + GeneralPurpose1ChannelComplementaryInstance
- {
- /// Get access to the general purpose 2 channel with one complementary 16bit timer registers.
- ///
- /// Note: This works even if the timer is more capable, because registers
- /// for the less capable timers are a subset. This allows writing a driver
- /// for a given set of capabilities, and having it transparently work with
- /// more capable timers.
- fn regs_2ch_cmp() -> crate::pac::timer::Tim2chCmp;
- }
-
- /// Advanced control timer instance.
- pub trait AdvancedControlInstance:
- GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance
- {
- /// Get access to the advanced timer registers.
- fn regs_advanced() -> crate::pac::timer::TimAdv;
- }
-
- /// Capture/Compare 16-bit timer instance.
- pub trait CaptureCompare16bitInstance: GeneralPurpose1ChannelInstance {
- /// Set input capture filter.
- fn set_input_capture_filter(&mut self, channel: Channel, icf: vals::FilterValue) {
- let raw_channel = channel.index();
- Self::regs_1ch()
- .ccmr_input(raw_channel / 2)
- .modify(|r| r.set_icf(raw_channel % 2, icf));
- }
-
- /// Clear input interrupt.
- fn clear_input_interrupt(&mut self, channel: Channel) {
- Self::regs_1ch().sr().modify(|r| r.set_ccif(channel.index(), false));
- }
-
- /// Enable input interrupt.
- fn enable_input_interrupt(&mut self, channel: Channel, enable: bool) {
- Self::regs_1ch().dier().modify(|r| r.set_ccie(channel.index(), enable));
- }
-
- /// Set input capture prescaler.
- fn set_input_capture_prescaler(&mut self, channel: Channel, factor: u8) {
- let raw_channel = channel.index();
- Self::regs_1ch()
- .ccmr_input(raw_channel / 2)
- .modify(|r| r.set_icpsc(raw_channel % 2, factor));
- }
-
- /// Set input TI selection.
- fn set_input_ti_selection(&mut self, channel: Channel, tisel: InputTISelection) {
- let raw_channel = channel.index();
- Self::regs_1ch()
- .ccmr_input(raw_channel / 2)
- .modify(|r| r.set_ccs(raw_channel % 2, tisel.into()));
- }
-
- /// Set input capture mode.
- fn set_input_capture_mode(&mut self, channel: Channel, mode: InputCaptureMode) {
- Self::regs_1ch().ccer().modify(|r| match mode {
- InputCaptureMode::Rising => {
- r.set_ccnp(channel.index(), false);
- r.set_ccp(channel.index(), false);
- }
- InputCaptureMode::Falling => {
- r.set_ccnp(channel.index(), false);
- r.set_ccp(channel.index(), true);
- }
- InputCaptureMode::BothEdges => {
- r.set_ccnp(channel.index(), true);
- r.set_ccp(channel.index(), true);
- }
- });
- }
-
- /// Set output compare mode.
- fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
- let r = Self::regs_1ch();
- let raw_channel: usize = channel.index();
- r.ccmr_output(raw_channel / 2)
- .modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
- }
-
- /// Set output polarity.
- fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- Self::regs_1ch()
- .ccer()
- .modify(|w| w.set_ccp(channel.index(), polarity.into()));
- }
-
- /// Enable/disable a channel.
- fn enable_channel(&mut self, channel: Channel, enable: bool) {
- Self::regs_1ch().ccer().modify(|w| w.set_cce(channel.index(), enable));
- }
-
- /// Get enable/disable state of a channel
- fn get_channel_enable_state(&self, channel: Channel) -> bool {
- Self::regs_1ch().ccer().read().cce(channel.index())
- }
-
- /// Set compare value for a channel.
- fn set_compare_value(&mut self, channel: Channel, value: u16) {
- Self::regs_1ch().ccr(channel.index()).modify(|w| w.set_ccr(value));
- }
-
- /// Get capture value for a channel.
- fn get_capture_value(&mut self, channel: Channel) -> u16 {
- Self::regs_1ch().ccr(channel.index()).read().ccr()
- }
-
- /// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
- fn get_max_compare_value(&self) -> u16 {
- Self::regs_1ch().arr().read().arr()
- }
-
- /// Get compare value for a channel.
- fn get_compare_value(&self, channel: Channel) -> u16 {
- Self::regs_1ch().ccr(channel.index()).read().ccr()
- }
-
- /// Set output compare preload.
- fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
- let channel_index = channel.index();
- Self::regs_1ch()
- .ccmr_output(channel_index / 2)
- .modify(|w| w.set_ocpe(channel_index % 2, preload));
- }
-
- /// Get capture compare DMA selection
- fn get_cc_dma_selection(&self) -> super::vals::Ccds {
- Self::regs_gp16().cr2().read().ccds()
- }
-
- /// Set capture compare DMA selection
- fn set_cc_dma_selection(&mut self, ccds: super::vals::Ccds) {
- Self::regs_gp16().cr2().modify(|w| w.set_ccds(ccds))
- }
-
- /// Get capture compare DMA enable state
- fn get_cc_dma_enable_state(&self, channel: Channel) -> bool {
- Self::regs_gp16().dier().read().ccde(channel.index())
- }
-
- /// Set capture compare DMA enable state
- fn set_cc_dma_enable_state(&mut self, channel: Channel, ccde: bool) {
- Self::regs_gp16().dier().modify(|w| w.set_ccde(channel.index(), ccde))
- }
- }
-
- /// Capture/Compare 16-bit timer instance with complementary pin support.
- pub trait ComplementaryCaptureCompare16bitInstance:
- CaptureCompare16bitInstance + GeneralPurpose1ChannelComplementaryInstance
- {
- /// Set complementary output polarity.
- fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- Self::regs_1ch_cmp()
- .ccer()
- .modify(|w| w.set_ccnp(channel.index(), polarity.into()));
- }
-
- /// Set clock divider for the dead time.
- fn set_dead_time_clock_division(&mut self, value: vals::Ckd) {
- Self::regs_1ch_cmp().cr1().modify(|w| w.set_ckd(value));
- }
-
- /// Set dead time, as a fraction of the max duty value.
- fn set_dead_time_value(&mut self, value: u8) {
- Self::regs_1ch_cmp().bdtr().modify(|w| w.set_dtg(value));
- }
-
- /// Enable/disable a complementary channel.
- fn enable_complementary_channel(&mut self, channel: Channel, enable: bool) {
- Self::regs_1ch_cmp()
- .ccer()
- .modify(|w| w.set_ccne(channel.index(), enable));
- }
- }
-
- /// Capture/Compare 32-bit timer instance.
- pub trait CaptureCompare32bitInstance: GeneralPurpose32bitInstance + CaptureCompare16bitInstance {
/// Set comapre value for a channel.
fn set_compare_value(&mut self, channel: Channel, value: u32) {
Self::regs_gp32().ccr(channel.index()).modify(|w| w.set_ccr(value));
@@ -470,6 +433,59 @@ pub(crate) mod sealed {
Self::regs_gp32().ccr(channel.index()).read().ccr()
}
}
+
+ /// Gneral-purpose 1 channel with one complementary 16-bit timer instance.
+ pub trait GeneralPurpose1ChannelComplementaryInstance: BasicNoCr2Instance + GeneralPurpose1ChannelInstance {
+ /// Get access to the general purpose 1 channel with one complementary 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_1ch_cmp() -> crate::pac::timer::Tim1chCmp;
+
+ /// Set clock divider for the dead time.
+ fn set_dead_time_clock_division(&mut self, value: vals::Ckd) {
+ Self::regs_1ch_cmp().cr1().modify(|w| w.set_ckd(value));
+ }
+
+ /// Set dead time, as a fraction of the max duty value.
+ fn set_dead_time_value(&mut self, value: u8) {
+ Self::regs_1ch_cmp().bdtr().modify(|w| w.set_dtg(value));
+ }
+
+ /// Enable timer outputs.
+ fn enable_outputs(&mut self) {
+ Self::regs_1ch_cmp().bdtr().modify(|w| w.set_moe(true));
+ }
+
+ add_complementary_capture_compare_methods!(regs_1ch_cmp);
+ }
+
+ /// Gneral-purpose 2 channel with one complementary 16-bit timer instance.
+ pub trait GeneralPurpose2ChannelComplementaryInstance:
+ BasicInstance + GeneralPurpose2ChannelInstance + GeneralPurpose1ChannelComplementaryInstance
+ {
+ /// Get access to the general purpose 2 channel with one complementary 16bit timer registers.
+ ///
+ /// Note: This works even if the timer is more capable, because registers
+ /// for the less capable timers are a subset. This allows writing a driver
+ /// for a given set of capabilities, and having it transparently work with
+ /// more capable timers.
+ fn regs_2ch_cmp() -> crate::pac::timer::Tim2chCmp;
+
+ add_complementary_capture_compare_methods!(regs_2ch_cmp);
+ }
+
+ /// Advanced control timer instance.
+ pub trait AdvancedControlInstance:
+ GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance
+ {
+ /// Get access to the advanced timer registers.
+ fn regs_advanced() -> crate::pac::timer::TimAdv;
+
+ add_complementary_capture_compare_methods!(regs_advanced);
+ }
}
/// Timer channel.
@@ -699,6 +715,7 @@ pub trait GeneralPurpose1ChannelComplementaryInstance:
pub trait GeneralPurpose2ChannelComplementaryInstance:
sealed::GeneralPurpose2ChannelComplementaryInstance
+ BasicInstance
+ + GeneralPurpose2ChannelInstance
+ GeneralPurpose1ChannelComplementaryInstance
+ 'static
{
@@ -710,42 +727,30 @@ pub trait AdvancedControlInstance:
{
}
-/// Capture/Compare 16-bit timer instance.
-pub trait CaptureCompare16bitInstance:
- sealed::CaptureCompare16bitInstance + GeneralPurpose1ChannelInstance + 'static
-{
-}
+pin_trait!(Channel1Pin, GeneralPurpose1ChannelInstance);
+pin_trait!(Channel2Pin, GeneralPurpose2ChannelInstance);
+pin_trait!(Channel3Pin, GeneralPurpose16bitInstance);
+pin_trait!(Channel4Pin, GeneralPurpose16bitInstance);
-/// Capture/Compare 16-bit timer instance with complementary pin support.
-pub trait ComplementaryCaptureCompare16bitInstance:
- sealed::ComplementaryCaptureCompare16bitInstance
- + CaptureCompare16bitInstance
- + GeneralPurpose1ChannelComplementaryInstance
- + 'static
-{
-}
+#[cfg(not(stm32l0))]
+pin_trait!(ExternalTriggerPin, GeneralPurpose16bitInstance);
-/// Capture/Compare 32-bit timer instance.
-pub trait CaptureCompare32bitInstance:
- sealed::CaptureCompare32bitInstance + CaptureCompare16bitInstance + GeneralPurpose32bitInstance + 'static
-{
-}
+#[cfg(stm32l0)]
+pin_trait!(ExternalTriggerPin, GeneralPurpose2ChannelInstance);
-pin_trait!(Channel1Pin, CaptureCompare16bitInstance);
-pin_trait!(Channel1ComplementaryPin, CaptureCompare16bitInstance);
-pin_trait!(Channel2Pin, CaptureCompare16bitInstance);
-pin_trait!(Channel2ComplementaryPin, CaptureCompare16bitInstance);
-pin_trait!(Channel3Pin, CaptureCompare16bitInstance);
-pin_trait!(Channel3ComplementaryPin, CaptureCompare16bitInstance);
-pin_trait!(Channel4Pin, CaptureCompare16bitInstance);
-pin_trait!(Channel4ComplementaryPin, CaptureCompare16bitInstance);
-pin_trait!(ExternalTriggerPin, CaptureCompare16bitInstance);
-pin_trait!(BreakInputPin, CaptureCompare16bitInstance);
-pin_trait!(BreakInputComparator1Pin, CaptureCompare16bitInstance);
-pin_trait!(BreakInputComparator2Pin, CaptureCompare16bitInstance);
-pin_trait!(BreakInput2Pin, CaptureCompare16bitInstance);
-pin_trait!(BreakInput2Comparator1Pin, CaptureCompare16bitInstance);
-pin_trait!(BreakInput2Comparator2Pin, CaptureCompare16bitInstance);
+pin_trait!(Channel1ComplementaryPin, GeneralPurpose1ChannelComplementaryInstance);
+pin_trait!(Channel2ComplementaryPin, GeneralPurpose2ChannelComplementaryInstance);
+pin_trait!(Channel3ComplementaryPin, AdvancedControlInstance);
+pin_trait!(Channel4ComplementaryPin, AdvancedControlInstance);
+
+pin_trait!(BreakInputPin, GeneralPurpose1ChannelComplementaryInstance);
+pin_trait!(BreakInput2Pin, GeneralPurpose2ChannelComplementaryInstance);
+
+pin_trait!(BreakInputComparator1Pin, GeneralPurpose1ChannelComplementaryInstance);
+pin_trait!(BreakInputComparator2Pin, AdvancedControlInstance);
+
+pin_trait!(BreakInput2Comparator1Pin, AdvancedControlInstance);
+pin_trait!(BreakInput2Comparator2Pin, AdvancedControlInstance);
#[allow(unused)]
macro_rules! impl_core_timer {
@@ -859,27 +864,6 @@ macro_rules! impl_adv_timer {
};
}
-#[allow(unused)]
-macro_rules! impl_compare_capable_16bit {
- ($inst:ident) => {
- impl sealed::CaptureCompare16bitInstance for crate::peripherals::$inst {}
- };
-}
-
-#[allow(unused)]
-macro_rules! impl_compare_capable_32bit {
- ($inst:ident) => {
- impl sealed::CaptureCompare32bitInstance for crate::peripherals::$inst {}
- };
-}
-
-#[allow(unused)]
-macro_rules! impl_compare_capable_complementary_16bit {
- ($inst:ident) => {
- impl sealed::ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
- };
-}
-
foreach_interrupt! {
($inst:ident, timer, TIM_BASIC, UP, $irq:ident) => {
@@ -894,21 +878,17 @@ foreach_interrupt! {
($inst:ident, timer, TIM_1CH, UP, $irq:ident) => {
impl_core_timer!($inst, $irq);
impl_1ch_timer!($inst);
- impl_compare_capable_16bit!($inst);
impl CoreInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
};
($inst:ident, timer, TIM_2CH, UP, $irq:ident) => {
impl_core_timer!($inst, $irq);
impl_1ch_timer!($inst);
- impl_compare_capable_16bit!($inst);
impl_2ch_timer!($inst);
impl CoreInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
};
@@ -917,14 +897,12 @@ foreach_interrupt! {
impl_basic_no_cr2_timer!($inst);
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
- impl_compare_capable_16bit!($inst);
impl_2ch_timer!($inst);
impl_gp_16bit_timer!($inst);
impl CoreInstance for crate::peripherals::$inst {}
impl BasicNoCr2Instance for crate::peripherals::$inst{}
impl BasicInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
};
@@ -934,8 +912,6 @@ foreach_interrupt! {
impl_basic_no_cr2_timer!($inst);
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
- impl_compare_capable_16bit!($inst);
- impl_compare_capable_32bit!($inst);
impl_2ch_timer!($inst);
impl_gp_16bit_timer!($inst);
impl_gp_32bit_timer!($inst);
@@ -943,8 +919,6 @@ foreach_interrupt! {
impl BasicNoCr2Instance for crate::peripherals::$inst{}
impl BasicInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
- impl CaptureCompare32bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose32bitInstance for crate::peripherals::$inst {}
@@ -954,15 +928,11 @@ foreach_interrupt! {
impl_core_timer!($inst, $irq);
impl_basic_no_cr2_timer!($inst);
impl_1ch_timer!($inst);
- impl_compare_capable_16bit!($inst);
impl_1ch_cmp_timer!($inst);
- impl_compare_capable_complementary_16bit!($inst);
impl CoreInstance for crate::peripherals::$inst {}
impl BasicNoCr2Instance for crate::peripherals::$inst{}
impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
- impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
@@ -971,17 +941,15 @@ foreach_interrupt! {
impl_basic_no_cr2_timer!($inst);
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
- impl_compare_capable_16bit!($inst);
+ impl_2ch_timer!($inst);
impl_1ch_cmp_timer!($inst);
- impl_compare_capable_complementary_16bit!($inst);
impl_2ch_cmp_timer!($inst);
impl CoreInstance for crate::peripherals::$inst {}
impl BasicNoCr2Instance for crate::peripherals::$inst{}
impl BasicInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
- impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose2ChannelComplementaryInstance for crate::peripherals::$inst {}
};
@@ -992,10 +960,8 @@ foreach_interrupt! {
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
impl_2ch_timer!($inst);
- impl_compare_capable_16bit!($inst);
impl_1ch_cmp_timer!($inst);
impl_gp_16bit_timer!($inst);
- impl_compare_capable_complementary_16bit!($inst);
impl_2ch_cmp_timer!($inst);
impl_adv_timer!($inst);
impl CoreInstance for crate::peripherals::$inst {}
@@ -1004,9 +970,7 @@ foreach_interrupt! {
impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
- impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
- impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
impl GeneralPurpose2ChannelComplementaryInstance for crate::peripherals::$inst {}
impl AdvancedControlInstance for crate::peripherals::$inst {}
};
@@ -1015,7 +979,7 @@ foreach_interrupt! {
// Update Event trigger DMA for every timer
dma_trait!(UpDma, BasicNoCr2Instance);
-dma_trait!(Ch1Dma, CaptureCompare16bitInstance);
-dma_trait!(Ch2Dma, CaptureCompare16bitInstance);
-dma_trait!(Ch3Dma, CaptureCompare16bitInstance);
-dma_trait!(Ch4Dma, CaptureCompare16bitInstance);
+dma_trait!(Ch1Dma, GeneralPurpose1ChannelInstance);
+dma_trait!(Ch2Dma, GeneralPurpose2ChannelInstance);
+dma_trait!(Ch3Dma, GeneralPurpose16bitInstance);
+dma_trait!(Ch4Dma, GeneralPurpose16bitInstance);
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index 75e5ab12a..7e56312bb 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -30,7 +30,7 @@ pub struct QeiPin<'d, T, Channel> {
macro_rules! channel_impl {
($new_chx:ident, $channel:ident, $pin_trait:ident) => {
- impl<'d, T: CaptureCompare16bitInstance> QeiPin<'d, T, $channel> {
+ impl<'d, T: GeneralPurpose16bitInstance> QeiPin<'d, T, $channel> {
#[doc = concat!("Create a new ", stringify!($channel), " QEI pin instance.")]
pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd) -> Self {
into_ref!(pin);
@@ -57,7 +57,7 @@ pub struct Qei<'d, T> {
_inner: PeripheralRef<'d, T>,
}
-impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> Qei<'d, T> {
+impl<'d, T: GeneralPurpose16bitInstance> Qei<'d, T> {
/// Create a new quadrature decoder driver.
pub fn new(tim: impl Peripheral<P = T> + 'd, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
Self::new_inner(tim)
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 1c665d456..088d02c97 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -1,6 +1,7 @@
//! Simple PWM driver.
use core::marker::PhantomData;
+use core::ops::{Deref, DerefMut};
use embassy_hal_internal::{into_ref, PeripheralRef};
@@ -30,7 +31,7 @@ pub struct PwmPin<'d, T, C> {
macro_rules! channel_impl {
($new_chx:ident, $channel:ident, $pin_trait:ident) => {
- impl<'d, T: CaptureCompare16bitInstance> PwmPin<'d, T, $channel> {
+ impl<'d, T: GeneralPurpose16bitInstance> PwmPin<'d, T, $channel> {
#[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
into_ref!(pin);
@@ -59,7 +60,7 @@ pub struct SimplePwm<'d, T> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> SimplePwm<'d, T> {
+impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
/// Create a new simple PWM driver.
pub fn new(
tim: impl Peripheral<P = T> + 'd,
@@ -87,8 +88,13 @@ impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> SimplePwm
[Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
.iter()
.for_each(|&channel| {
- this.inner.set_output_compare_mode(channel, OutputCompareMode::PwmMode1);
- this.inner.set_output_compare_preload(channel, true)
+ sealed::GeneralPurpose16bitInstance::set_output_compare_mode(
+ this.inner.deref_mut(),
+ channel,
+ OutputCompareMode::PwmMode1,
+ );
+
+ sealed::GeneralPurpose16bitInstance::set_output_compare_preload(this.inner.deref_mut(), channel, true);
});
this
@@ -96,17 +102,17 @@ impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> SimplePwm
/// Enable the given channel.
pub fn enable(&mut self, channel: Channel) {
- self.inner.enable_channel(channel, true);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
}
/// Disable the given channel.
pub fn disable(&mut self, channel: Channel) {
- self.inner.enable_channel(channel, false);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
}
/// Check whether given channel is enabled
pub fn is_enabled(&self, channel: Channel) -> bool {
- self.inner.get_channel_enable_state(channel)
+ sealed::GeneralPurpose16bitInstance::get_channel_enable_state(self.inner.deref(), channel)
}
/// Set PWM frequency.
@@ -134,24 +140,24 @@ impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> SimplePwm
/// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
pub fn set_duty(&mut self, channel: Channel, duty: u16) {
assert!(duty <= self.get_max_duty());
- self.inner.set_compare_value(channel, duty)
+ sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
}
/// Get the duty for a given channel.
///
/// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
pub fn get_duty(&self, channel: Channel) -> u16 {
- self.inner.get_compare_value(channel)
+ sealed::GeneralPurpose16bitInstance::get_compare_value(self.inner.deref(), channel)
}
/// Set the output polarity for a given channel.
pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- self.inner.set_output_polarity(channel, polarity);
+ sealed::GeneralPurpose16bitInstance::set_output_polarity(self.inner.deref_mut(), channel, polarity);
}
/// Set the output compare mode for a given channel.
pub fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
- self.inner.set_output_compare_mode(channel, mode);
+ sealed::GeneralPurpose16bitInstance::set_output_compare_mode(self.inner.deref_mut(), channel, mode);
}
/// Generate a sequence of PWM waveform
@@ -226,7 +232,7 @@ impl<'d, T: GeneralPurpose16bitInstance + CaptureCompare16bitInstance> SimplePwm
macro_rules! impl_waveform_chx {
($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
- impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
+ impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
/// Generate a sequence of PWM waveform
///
/// Note:
@@ -313,17 +319,17 @@ impl_waveform_chx!(waveform_ch2, Ch2Dma, Ch2);
impl_waveform_chx!(waveform_ch3, Ch3Dma, Ch3);
impl_waveform_chx!(waveform_ch4, Ch4Dma, Ch4);
-impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
+impl<'d, T: GeneralPurpose16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
type Channel = Channel;
type Time = Hertz;
type Duty = u16;
fn disable(&mut self, channel: Self::Channel) {
- self.inner.enable_channel(channel, false);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
}
fn enable(&mut self, channel: Self::Channel) {
- self.inner.enable_channel(channel, true);
+ sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
}
fn get_period(&self) -> Self::Time {
@@ -331,7 +337,7 @@ impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d,
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
- self.inner.get_compare_value(channel)
+ sealed::GeneralPurpose16bitInstance::get_compare_value(self.inner.deref(), channel)
}
fn get_max_duty(&self) -> Self::Duty {
@@ -340,7 +346,7 @@ impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d,
fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
assert!(duty <= self.get_max_duty());
- self.inner.set_compare_value(channel, duty)
+ sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
}
fn set_period<P>(&mut self, period: P)
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs
index cc508c3cf..0be3eccb7 100644
--- a/examples/stm32h7/src/bin/low_level_timer_api.rs
+++ b/examples/stm32h7/src/bin/low_level_timer_api.rs
@@ -56,11 +56,11 @@ async fn main(_spawner: Spawner) {
Timer::after_millis(300).await;
}
}
-pub struct SimplePwm32<'d, T: CaptureCompare32bitInstance> {
+pub struct SimplePwm32<'d, T: GeneralPurpose32bitInstance> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> {
+impl<'d, T: GeneralPurpose32bitInstance> SimplePwm32<'d, T> {
pub fn new(
tim: impl Peripheral<P = T> + 'd,
ch1: impl Peripheral<P = impl Channel1Pin<T>> + 'd,
From 5b646bc3bd0c4a2cd9acf6a59b3a76f2bbcb0bfb Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Thu, 1 Feb 2024 23:04:39 +0800
Subject: [PATCH 170/392] stm32-timer: L0 is special
---
embassy-stm32/src/timer/mod.rs | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 2f5d5770a..8be96b414 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -12,6 +12,7 @@
// | +--------------------------------------|-----------+
// +----------------------------------------------------+
+#[cfg(not(any(stm32l0, stm32l1)))]
pub mod complementary_pwm;
pub mod qei;
pub mod simple_pwm;
@@ -163,6 +164,7 @@ pub(crate) mod sealed {
};
}
+ #[cfg(not(any(stm32l0, stm32l1)))]
macro_rules! add_complementary_capture_compare_methods {
($regs:ident) => {
/// Set complementary output polarity.
@@ -374,6 +376,7 @@ pub(crate) mod sealed {
add_capture_compare_dma_methods!(regs_gp16);
}
+ #[cfg(not(any(stm32l0)))]
/// Gneral-purpose 32-bit timer instance.
pub trait GeneralPurpose32bitInstance: GeneralPurpose16bitInstance {
/// Get access to the general purpose 32bit timer registers.
@@ -434,6 +437,7 @@ pub(crate) mod sealed {
}
}
+ #[cfg(not(any(stm32l0, stm32l1)))]
/// Gneral-purpose 1 channel with one complementary 16-bit timer instance.
pub trait GeneralPurpose1ChannelComplementaryInstance: BasicNoCr2Instance + GeneralPurpose1ChannelInstance {
/// Get access to the general purpose 1 channel with one complementary 16bit timer registers.
@@ -462,6 +466,7 @@ pub(crate) mod sealed {
add_complementary_capture_compare_methods!(regs_1ch_cmp);
}
+ #[cfg(not(any(stm32l0, stm32l1)))]
/// Gneral-purpose 2 channel with one complementary 16-bit timer instance.
pub trait GeneralPurpose2ChannelComplementaryInstance:
BasicInstance + GeneralPurpose2ChannelInstance + GeneralPurpose1ChannelComplementaryInstance
@@ -477,6 +482,7 @@ pub(crate) mod sealed {
add_complementary_capture_compare_methods!(regs_2ch_cmp);
}
+ #[cfg(not(any(stm32l0, stm32l1)))]
/// Advanced control timer instance.
pub trait AdvancedControlInstance:
GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance
@@ -699,18 +705,21 @@ pub trait GeneralPurpose16bitInstance:
{
}
+#[cfg(not(stm32l0))]
/// Gneral-purpose 32-bit timer instance.
pub trait GeneralPurpose32bitInstance:
sealed::GeneralPurpose32bitInstance + GeneralPurpose16bitInstance + 'static
{
}
+#[cfg(not(any(stm32l0, stm32l1)))]
/// General-purpose 1 channel with one complementary 16-bit timer instance.
pub trait GeneralPurpose1ChannelComplementaryInstance:
sealed::GeneralPurpose1ChannelComplementaryInstance + GeneralPurpose1ChannelInstance + 'static
{
}
+#[cfg(not(any(stm32l0, stm32l1)))]
/// General-purpose 2 channel with one complementary 16-bit timer instance.
pub trait GeneralPurpose2ChannelComplementaryInstance:
sealed::GeneralPurpose2ChannelComplementaryInstance
@@ -721,6 +730,7 @@ pub trait GeneralPurpose2ChannelComplementaryInstance:
{
}
+#[cfg(not(any(stm32l0, stm32l1)))]
/// Advanced control timer instance.
pub trait AdvancedControlInstance:
sealed::AdvancedControlInstance + GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance + 'static
@@ -738,18 +748,28 @@ pin_trait!(ExternalTriggerPin, GeneralPurpose16bitInstance);
#[cfg(stm32l0)]
pin_trait!(ExternalTriggerPin, GeneralPurpose2ChannelInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(Channel1ComplementaryPin, GeneralPurpose1ChannelComplementaryInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(Channel2ComplementaryPin, GeneralPurpose2ChannelComplementaryInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(Channel3ComplementaryPin, AdvancedControlInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(Channel4ComplementaryPin, AdvancedControlInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(BreakInputPin, GeneralPurpose1ChannelComplementaryInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(BreakInput2Pin, GeneralPurpose2ChannelComplementaryInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(BreakInputComparator1Pin, GeneralPurpose1ChannelComplementaryInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(BreakInputComparator2Pin, AdvancedControlInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(BreakInput2Comparator1Pin, AdvancedControlInstance);
+#[cfg(not(any(stm32l0, stm32l1)))]
pin_trait!(BreakInput2Comparator2Pin, AdvancedControlInstance);
#[allow(unused)]
From 319f10da5daff415ad2dac17f4eed43313455167 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Thu, 1 Feb 2024 23:41:32 +0800
Subject: [PATCH 171/392] stm32-timer: filter out c0, f1 and f37x
---
embassy-stm32/src/timer/mod.rs | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 8be96b414..be5c6cf29 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -376,7 +376,7 @@ pub(crate) mod sealed {
add_capture_compare_dma_methods!(regs_gp16);
}
- #[cfg(not(any(stm32l0)))]
+ #[cfg(not(any(stm32f1, stm32l0, stm32c0)))]
/// Gneral-purpose 32-bit timer instance.
pub trait GeneralPurpose32bitInstance: GeneralPurpose16bitInstance {
/// Get access to the general purpose 32bit timer registers.
@@ -705,7 +705,7 @@ pub trait GeneralPurpose16bitInstance:
{
}
-#[cfg(not(stm32l0))]
+#[cfg(not(any(stm32f1, stm32l0, stm32c0)))]
/// Gneral-purpose 32-bit timer instance.
pub trait GeneralPurpose32bitInstance:
sealed::GeneralPurpose32bitInstance + GeneralPurpose16bitInstance + 'static
@@ -730,7 +730,7 @@ pub trait GeneralPurpose2ChannelComplementaryInstance:
{
}
-#[cfg(not(any(stm32l0, stm32l1)))]
+#[cfg(not(any(stm32f37, stm32l0, stm32l1)))]
/// Advanced control timer instance.
pub trait AdvancedControlInstance:
sealed::AdvancedControlInstance + GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance + 'static
From b3cdf3a040ae97923e84eca525505f7eff55e870 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Fri, 2 Feb 2024 14:52:54 +0800
Subject: [PATCH 172/392] bug fix
---
embassy-stm32/src/timer/mod.rs | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index be5c6cf29..3e303a6cf 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -90,9 +90,9 @@ pub(crate) mod sealed {
/// Set output compare mode.
fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
- let r = Self::$regs();
let raw_channel: usize = channel.index();
- r.ccmr_output(raw_channel / 2)
+ Self::$regs()
+ .ccmr_output(raw_channel / 2)
.modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
}
@@ -133,7 +133,7 @@ pub(crate) mod sealed {
/// Set output compare preload.
fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
let channel_index = channel.index();
- Self::regs_1ch()
+ Self::$regs()
.ccmr_output(channel_index / 2)
.modify(|w| w.set_ocpe(channel_index % 2, preload));
}
From 6c690ab259ed15eece329a53a7147e7780f53cf3 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Fri, 2 Feb 2024 17:45:51 +0800
Subject: [PATCH 173/392] restore original public API of timer, but keep new
PAC
---
embassy-stm32/src/timer/complementary_pwm.rs | 41 +-
embassy-stm32/src/timer/mod.rs | 525 ++++++++----------
embassy-stm32/src/timer/qei.rs | 4 +-
embassy-stm32/src/timer/simple_pwm.rs | 39 +-
.../stm32h7/src/bin/low_level_timer_api.rs | 4 +-
5 files changed, 274 insertions(+), 339 deletions(-)
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index b9cd044c9..72f1ec864 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -1,7 +1,6 @@
//! PWM driver with complementary output support.
use core::marker::PhantomData;
-use core::ops::{Deref, DerefMut};
use embassy_hal_internal::{into_ref, PeripheralRef};
use stm32_metapac::timer::vals::Ckd;
@@ -24,7 +23,7 @@ pub struct ComplementaryPwmPin<'d, T, C> {
macro_rules! complementary_channel_impl {
($new_chx:ident, $channel:ident, $pin_trait:ident) => {
- impl<'d, T: AdvancedControlInstance> ComplementaryPwmPin<'d, T, $channel> {
+ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwmPin<'d, T, $channel> {
#[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
into_ref!(pin);
@@ -53,7 +52,7 @@ pub struct ComplementaryPwm<'d, T> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: AdvancedControlInstance> ComplementaryPwm<'d, T> {
+impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
/// Create a new complementary PWM driver.
#[allow(clippy::too_many_arguments)]
pub fn new(
@@ -88,12 +87,8 @@ impl<'d, T: AdvancedControlInstance> ComplementaryPwm<'d, T> {
[Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
.iter()
.for_each(|&channel| {
- sealed::GeneralPurpose16bitInstance::set_output_compare_mode(
- this.inner.deref_mut(),
- channel,
- OutputCompareMode::PwmMode1,
- );
- sealed::GeneralPurpose16bitInstance::set_output_compare_preload(this.inner.deref_mut(), channel, true);
+ this.inner.set_output_compare_mode(channel, OutputCompareMode::PwmMode1);
+ this.inner.set_output_compare_preload(channel, true);
});
this
@@ -101,14 +96,14 @@ impl<'d, T: AdvancedControlInstance> ComplementaryPwm<'d, T> {
/// Enable the given channel.
pub fn enable(&mut self, channel: Channel) {
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
- sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, true);
+ self.inner.enable_channel(channel, true);
+ self.inner.enable_complementary_channel(channel, true);
}
/// Disable the given channel.
pub fn disable(&mut self, channel: Channel) {
- sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, false);
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
+ self.inner.enable_complementary_channel(channel, false);
+ self.inner.enable_channel(channel, false);
}
/// Set PWM frequency.
@@ -136,13 +131,13 @@ impl<'d, T: AdvancedControlInstance> ComplementaryPwm<'d, T> {
/// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
pub fn set_duty(&mut self, channel: Channel, duty: u16) {
assert!(duty <= self.get_max_duty());
- sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
+ self.inner.set_compare_value(channel, duty)
}
/// Set the output polarity for a given channel.
pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- sealed::GeneralPurpose16bitInstance::set_output_polarity(self.inner.deref_mut(), channel, polarity);
- sealed::AdvancedControlInstance::set_complementary_output_polarity(self.inner.deref_mut(), channel, polarity);
+ self.inner.set_output_polarity(channel, polarity);
+ self.inner.set_complementary_output_polarity(channel, polarity);
}
/// Set the dead time as a proportion of max_duty
@@ -154,19 +149,19 @@ impl<'d, T: AdvancedControlInstance> ComplementaryPwm<'d, T> {
}
}
-impl<'d, T: AdvancedControlInstance> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
+impl<'d, T: ComplementaryCaptureCompare16bitInstance> embedded_hal_02::Pwm for ComplementaryPwm<'d, T> {
type Channel = Channel;
type Time = Hertz;
type Duty = u16;
fn disable(&mut self, channel: Self::Channel) {
- sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, false);
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
+ self.inner.enable_complementary_channel(channel, false);
+ self.inner.enable_channel(channel, false);
}
fn enable(&mut self, channel: Self::Channel) {
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
- sealed::AdvancedControlInstance::enable_complementary_channel(self.inner.deref_mut(), channel, true);
+ self.inner.enable_channel(channel, true);
+ self.inner.enable_complementary_channel(channel, true);
}
fn get_period(&self) -> Self::Time {
@@ -174,7 +169,7 @@ impl<'d, T: AdvancedControlInstance> embedded_hal_02::Pwm for ComplementaryPwm<'
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
- sealed::GeneralPurpose16bitInstance::get_compare_value(self.inner.deref(), channel)
+ self.inner.get_compare_value(channel)
}
fn get_max_duty(&self) -> Self::Duty {
@@ -183,7 +178,7 @@ impl<'d, T: AdvancedControlInstance> embedded_hal_02::Pwm for ComplementaryPwm<'
fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
assert!(duty <= self.get_max_duty());
- sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
+ self.inner.set_compare_value(channel, duty)
}
fn set_period<P>(&mut self, period: P)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 3e303a6cf..5f40be957 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -1,6 +1,8 @@
//! Timers, PWM, quadrature decoder.
-// Timer inheritance
+//! Timer inheritance
+
+// sealed:
//
// Core -------------------------> 1CH -------------------------> 1CH_CMP
// | | ^ |
@@ -12,7 +14,18 @@
// | +--------------------------------------|-----------+
// +----------------------------------------------------+
-#[cfg(not(any(stm32l0, stm32l1)))]
+//! BasicInstance --> CaptureCompare16bitInstance --+--> ComplementaryCaptureCompare16bitInstance
+//! |
+//! +--> CaptureCompare32bitInstance
+//!
+//! mapping:
+//!
+//! Basic Timer --> BasicInstance
+//! 1-channel Timer, 2-channel Timer, General Purpose 16-bit Timer --> CaptureCompare16bitInstance
+//! General Purpose 32-bit Timer --> CaptureCompare32bitInstance
+//! 1-channel with one complentary Timer, 2-channel with one complentary Timer, Advance Control Timer --> ComplementaryCaptureCompare16bitInstance
+
+#[cfg(not(stm32l0))]
pub mod complementary_pwm;
pub mod qei;
pub mod simple_pwm;
@@ -32,157 +45,6 @@ pub mod low_level {
pub(crate) mod sealed {
use super::*;
- macro_rules! add_capture_compare_common_methods {
- ($regs:ident) => {
- /// Set input capture filter.
- fn set_input_capture_filter(&mut self, channel: Channel, icf: vals::FilterValue) {
- let raw_channel = channel.index();
- Self::$regs()
- .ccmr_input(raw_channel / 2)
- .modify(|r| r.set_icf(raw_channel % 2, icf));
- }
-
- /// Clear input interrupt.
- fn clear_input_interrupt(&mut self, channel: Channel) {
- Self::$regs().sr().modify(|r| r.set_ccif(channel.index(), false));
- }
-
- /// Enable input interrupt.
- fn enable_input_interrupt(&mut self, channel: Channel, enable: bool) {
- Self::$regs()
- .dier()
- .modify(|r| r.set_ccie(channel.index(), enable));
- }
-
- /// Set input capture prescaler.
- fn set_input_capture_prescaler(&mut self, channel: Channel, factor: u8) {
- let raw_channel = channel.index();
- Self::$regs()
- .ccmr_input(raw_channel / 2)
- .modify(|r| r.set_icpsc(raw_channel % 2, factor));
- }
-
- /// Set input TI selection.
- fn set_input_ti_selection(&mut self, channel: Channel, tisel: InputTISelection) {
- let raw_channel = channel.index();
- Self::$regs()
- .ccmr_input(raw_channel / 2)
- .modify(|r| r.set_ccs(raw_channel % 2, tisel.into()));
- }
-
- /// Set input capture mode.
- fn set_input_capture_mode(&mut self, channel: Channel, mode: InputCaptureMode) {
- Self::$regs().ccer().modify(|r| match mode {
- InputCaptureMode::Rising => {
- r.set_ccnp(channel.index(), false);
- r.set_ccp(channel.index(), false);
- }
- InputCaptureMode::Falling => {
- r.set_ccnp(channel.index(), false);
- r.set_ccp(channel.index(), true);
- }
- InputCaptureMode::BothEdges => {
- r.set_ccnp(channel.index(), true);
- r.set_ccp(channel.index(), true);
- }
- });
- }
-
- /// Set output compare mode.
- fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
- let raw_channel: usize = channel.index();
- Self::$regs()
- .ccmr_output(raw_channel / 2)
- .modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
- }
-
- /// Set output polarity.
- fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- Self::$regs()
- .ccer()
- .modify(|w| w.set_ccp(channel.index(), polarity.into()));
- }
-
- /// Enable/disable a channel.
- fn enable_channel(&mut self, channel: Channel, enable: bool) {
- Self::$regs()
- .ccer()
- .modify(|w| w.set_cce(channel.index(), enable));
- }
-
- /// Get enable/disable state of a channel
- fn get_channel_enable_state(&self, channel: Channel) -> bool {
- Self::$regs().ccer().read().cce(channel.index())
- }
-
- /// Set compare value for a channel.
- fn set_compare_value(&mut self, channel: Channel, value: u16) {
- Self::$regs().ccr(channel.index()).modify(|w| w.set_ccr(value));
- }
-
- /// Get capture value for a channel.
- fn get_capture_value(&mut self, channel: Channel) -> u16 {
- Self::$regs().ccr(channel.index()).read().ccr()
- }
-
- /// Get compare value for a channel.
- fn get_compare_value(&self, channel: Channel) -> u16 {
- Self::$regs().ccr(channel.index()).read().ccr()
- }
-
- /// Set output compare preload.
- fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
- let channel_index = channel.index();
- Self::$regs()
- .ccmr_output(channel_index / 2)
- .modify(|w| w.set_ocpe(channel_index % 2, preload));
- }
- };
- }
-
- macro_rules! add_capture_compare_dma_methods {
- ($regs:ident) => {
- /// Get capture compare DMA selection
- fn get_cc_dma_selection(&self) -> super::vals::Ccds {
- Self::$regs().cr2().read().ccds()
- }
-
- /// Set capture compare DMA selection
- fn set_cc_dma_selection(&mut self, ccds: super::vals::Ccds) {
- Self::$regs().cr2().modify(|w| w.set_ccds(ccds))
- }
-
- /// Get capture compare DMA enable state
- fn get_cc_dma_enable_state(&self, channel: Channel) -> bool {
- Self::$regs().dier().read().ccde(channel.index())
- }
-
- /// Set capture compare DMA enable state
- fn set_cc_dma_enable_state(&mut self, channel: Channel, ccde: bool) {
- Self::$regs().dier().modify(|w| w.set_ccde(channel.index(), ccde))
- }
- };
- }
-
- #[cfg(not(any(stm32l0, stm32l1)))]
- macro_rules! add_complementary_capture_compare_methods {
- ($regs:ident) => {
- /// Set complementary output polarity.
- fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- Self::$regs()
- .ccer()
- .modify(|w| w.set_ccnp(channel.index(), polarity.into()));
- }
-
- /// Enable/disable a complementary channel.
- fn enable_complementary_channel(&mut self, channel: Channel, enable: bool) {
- Self::$regs()
- .ccer()
- .modify(|w| w.set_ccne(channel.index(), enable));
- }
- };
- }
-
/// Virtual Core 16-bit timer instance.
pub trait CoreInstance: RccPeripheral {
/// Interrupt for this timer.
@@ -326,8 +188,6 @@ pub(crate) mod sealed {
fn get_max_compare_value(&self) -> u16 {
Self::regs_1ch().arr().read().arr()
}
-
- add_capture_compare_common_methods!(regs_1ch);
}
/// Gneral-purpose 1 channel 16-bit timer instance.
@@ -339,8 +199,6 @@ pub(crate) mod sealed {
/// for a given set of capabilities, and having it transparently work with
/// more capable timers.
fn regs_2ch() -> crate::pac::timer::Tim2ch;
-
- add_capture_compare_common_methods!(regs_2ch);
}
/// Gneral-purpose 16-bit timer instance.
@@ -372,11 +230,128 @@ pub(crate) mod sealed {
(cr1.cms(), cr1.dir()).into()
}
- add_capture_compare_common_methods!(regs_gp16);
- add_capture_compare_dma_methods!(regs_gp16);
+ /// Set input capture filter.
+ fn set_input_capture_filter(&mut self, channel: Channel, icf: vals::FilterValue) {
+ let raw_channel = channel.index();
+ Self::regs_gp16()
+ .ccmr_input(raw_channel / 2)
+ .modify(|r| r.set_icf(raw_channel % 2, icf));
+ }
+
+ /// Clear input interrupt.
+ fn clear_input_interrupt(&mut self, channel: Channel) {
+ Self::regs_gp16().sr().modify(|r| r.set_ccif(channel.index(), false));
+ }
+
+ /// Enable input interrupt.
+ fn enable_input_interrupt(&mut self, channel: Channel, enable: bool) {
+ Self::regs_gp16().dier().modify(|r| r.set_ccie(channel.index(), enable));
+ }
+
+ /// Set input capture prescaler.
+ fn set_input_capture_prescaler(&mut self, channel: Channel, factor: u8) {
+ let raw_channel = channel.index();
+ Self::regs_gp16()
+ .ccmr_input(raw_channel / 2)
+ .modify(|r| r.set_icpsc(raw_channel % 2, factor));
+ }
+
+ /// Set input TI selection.
+ fn set_input_ti_selection(&mut self, channel: Channel, tisel: InputTISelection) {
+ let raw_channel = channel.index();
+ Self::regs_gp16()
+ .ccmr_input(raw_channel / 2)
+ .modify(|r| r.set_ccs(raw_channel % 2, tisel.into()));
+ }
+
+ /// Set input capture mode.
+ fn set_input_capture_mode(&mut self, channel: Channel, mode: InputCaptureMode) {
+ Self::regs_gp16().ccer().modify(|r| match mode {
+ InputCaptureMode::Rising => {
+ r.set_ccnp(channel.index(), false);
+ r.set_ccp(channel.index(), false);
+ }
+ InputCaptureMode::Falling => {
+ r.set_ccnp(channel.index(), false);
+ r.set_ccp(channel.index(), true);
+ }
+ InputCaptureMode::BothEdges => {
+ r.set_ccnp(channel.index(), true);
+ r.set_ccp(channel.index(), true);
+ }
+ });
+ }
+
+ /// Set output compare mode.
+ fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
+ let raw_channel: usize = channel.index();
+ Self::regs_gp16()
+ .ccmr_output(raw_channel / 2)
+ .modify(|w| w.set_ocm(raw_channel % 2, mode.into()));
+ }
+
+ /// Set output polarity.
+ fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+ Self::regs_gp16()
+ .ccer()
+ .modify(|w| w.set_ccp(channel.index(), polarity.into()));
+ }
+
+ /// Enable/disable a channel.
+ fn enable_channel(&mut self, channel: Channel, enable: bool) {
+ Self::regs_gp16().ccer().modify(|w| w.set_cce(channel.index(), enable));
+ }
+
+ /// Get enable/disable state of a channel
+ fn get_channel_enable_state(&self, channel: Channel) -> bool {
+ Self::regs_gp16().ccer().read().cce(channel.index())
+ }
+
+ /// Set compare value for a channel.
+ fn set_compare_value(&mut self, channel: Channel, value: u16) {
+ Self::regs_gp16().ccr(channel.index()).modify(|w| w.set_ccr(value));
+ }
+
+ /// Get capture value for a channel.
+ fn get_capture_value(&mut self, channel: Channel) -> u16 {
+ Self::regs_gp16().ccr(channel.index()).read().ccr()
+ }
+
+ /// Get compare value for a channel.
+ fn get_compare_value(&self, channel: Channel) -> u16 {
+ Self::regs_gp16().ccr(channel.index()).read().ccr()
+ }
+
+ /// Set output compare preload.
+ fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
+ let channel_index = channel.index();
+ Self::regs_gp16()
+ .ccmr_output(channel_index / 2)
+ .modify(|w| w.set_ocpe(channel_index % 2, preload));
+ }
+
+ /// Get capture compare DMA selection
+ fn get_cc_dma_selection(&self) -> super::vals::Ccds {
+ Self::regs_gp16().cr2().read().ccds()
+ }
+
+ /// Set capture compare DMA selection
+ fn set_cc_dma_selection(&mut self, ccds: super::vals::Ccds) {
+ Self::regs_gp16().cr2().modify(|w| w.set_ccds(ccds))
+ }
+
+ /// Get capture compare DMA enable state
+ fn get_cc_dma_enable_state(&self, channel: Channel) -> bool {
+ Self::regs_gp16().dier().read().ccde(channel.index())
+ }
+
+ /// Set capture compare DMA enable state
+ fn set_cc_dma_enable_state(&mut self, channel: Channel, ccde: bool) {
+ Self::regs_gp16().dier().modify(|w| w.set_ccde(channel.index(), ccde))
+ }
}
- #[cfg(not(any(stm32f1, stm32l0, stm32c0)))]
+ #[cfg(not(stm32l0))]
/// Gneral-purpose 32-bit timer instance.
pub trait GeneralPurpose32bitInstance: GeneralPurpose16bitInstance {
/// Get access to the general purpose 32bit timer registers.
@@ -437,7 +412,7 @@ pub(crate) mod sealed {
}
}
- #[cfg(not(any(stm32l0, stm32l1)))]
+ #[cfg(not(stm32l0))]
/// Gneral-purpose 1 channel with one complementary 16-bit timer instance.
pub trait GeneralPurpose1ChannelComplementaryInstance: BasicNoCr2Instance + GeneralPurpose1ChannelInstance {
/// Get access to the general purpose 1 channel with one complementary 16bit timer registers.
@@ -462,11 +437,9 @@ pub(crate) mod sealed {
fn enable_outputs(&mut self) {
Self::regs_1ch_cmp().bdtr().modify(|w| w.set_moe(true));
}
-
- add_complementary_capture_compare_methods!(regs_1ch_cmp);
}
- #[cfg(not(any(stm32l0, stm32l1)))]
+ #[cfg(not(stm32l0))]
/// Gneral-purpose 2 channel with one complementary 16-bit timer instance.
pub trait GeneralPurpose2ChannelComplementaryInstance:
BasicInstance + GeneralPurpose2ChannelInstance + GeneralPurpose1ChannelComplementaryInstance
@@ -478,11 +451,9 @@ pub(crate) mod sealed {
/// for a given set of capabilities, and having it transparently work with
/// more capable timers.
fn regs_2ch_cmp() -> crate::pac::timer::Tim2chCmp;
-
- add_complementary_capture_compare_methods!(regs_2ch_cmp);
}
- #[cfg(not(any(stm32l0, stm32l1)))]
+ #[cfg(not(stm32l0))]
/// Advanced control timer instance.
pub trait AdvancedControlInstance:
GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance
@@ -490,7 +461,19 @@ pub(crate) mod sealed {
/// Get access to the advanced timer registers.
fn regs_advanced() -> crate::pac::timer::TimAdv;
- add_complementary_capture_compare_methods!(regs_advanced);
+ /// Set complementary output polarity.
+ fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+ Self::regs_advanced()
+ .ccer()
+ .modify(|w| w.set_ccnp(channel.index(), polarity.into()));
+ }
+
+ /// Enable/disable a complementary channel.
+ fn enable_complementary_channel(&mut self, channel: Channel, enable: bool) {
+ Self::regs_advanced()
+ .ccer()
+ .modify(|w| w.set_ccne(channel.index(), enable));
+ }
}
}
@@ -681,96 +664,66 @@ impl From<OutputPolarity> for bool {
}
}
-/// Virtual Core 16-bit timer instance.
-pub trait CoreInstance: sealed::CoreInstance + 'static {}
-
-/// Virtual Basic 16-bit timer without CR2 register instance.
-pub trait BasicNoCr2Instance: sealed::BasicNoCr2Instance + CoreInstance + 'static {}
-
/// Basic 16-bit timer instance.
-pub trait BasicInstance: sealed::BasicInstance + BasicNoCr2Instance + 'static {}
-
-/// 1 channel 16-bit instance.
-pub trait GeneralPurpose1ChannelInstance: sealed::GeneralPurpose1ChannelInstance + CoreInstance + 'static {}
-
-/// 2 channel 16-bit instance.
-pub trait GeneralPurpose2ChannelInstance:
- sealed::GeneralPurpose2ChannelInstance + GeneralPurpose1ChannelInstance + 'static
-{
-}
+pub trait BasicInstance: sealed::BasicInstance + sealed::BasicNoCr2Instance + sealed::CoreInstance + 'static {}
/// General-purpose 16-bit timer instance.
-pub trait GeneralPurpose16bitInstance:
- sealed::GeneralPurpose16bitInstance + BasicInstance + GeneralPurpose2ChannelInstance + 'static
-{
-}
-
-#[cfg(not(any(stm32f1, stm32l0, stm32c0)))]
-/// Gneral-purpose 32-bit timer instance.
-pub trait GeneralPurpose32bitInstance:
- sealed::GeneralPurpose32bitInstance + GeneralPurpose16bitInstance + 'static
-{
-}
-
-#[cfg(not(any(stm32l0, stm32l1)))]
-/// General-purpose 1 channel with one complementary 16-bit timer instance.
-pub trait GeneralPurpose1ChannelComplementaryInstance:
- sealed::GeneralPurpose1ChannelComplementaryInstance + GeneralPurpose1ChannelInstance + 'static
-{
-}
-
-#[cfg(not(any(stm32l0, stm32l1)))]
-/// General-purpose 2 channel with one complementary 16-bit timer instance.
-pub trait GeneralPurpose2ChannelComplementaryInstance:
- sealed::GeneralPurpose2ChannelComplementaryInstance
- + BasicInstance
- + GeneralPurpose2ChannelInstance
- + GeneralPurpose1ChannelComplementaryInstance
+pub trait CaptureCompare16bitInstance:
+ BasicInstance
+ + sealed::GeneralPurpose2ChannelInstance
+ + sealed::GeneralPurpose1ChannelInstance
+ + sealed::GeneralPurpose16bitInstance
+ 'static
{
}
-#[cfg(not(any(stm32f37, stm32l0, stm32l1)))]
-/// Advanced control timer instance.
-pub trait AdvancedControlInstance:
- sealed::AdvancedControlInstance + GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance + 'static
+#[cfg(not(stm32l0))]
+/// Gneral-purpose 32-bit timer instance.
+pub trait CaptureCompare32bitInstance:
+ sealed::GeneralPurpose32bitInstance + CaptureCompare16bitInstance + 'static
{
}
-pin_trait!(Channel1Pin, GeneralPurpose1ChannelInstance);
-pin_trait!(Channel2Pin, GeneralPurpose2ChannelInstance);
-pin_trait!(Channel3Pin, GeneralPurpose16bitInstance);
-pin_trait!(Channel4Pin, GeneralPurpose16bitInstance);
+#[cfg(not(stm32l0))]
+/// Advanced control timer instance.
+pub trait ComplementaryCaptureCompare16bitInstance:
+ CaptureCompare16bitInstance
+ + sealed::GeneralPurpose1ChannelComplementaryInstance
+ + sealed::GeneralPurpose2ChannelComplementaryInstance
+ + sealed::AdvancedControlInstance
+ + 'static
+{
+}
+
+pin_trait!(Channel1Pin, CaptureCompare16bitInstance);
+pin_trait!(Channel2Pin, CaptureCompare16bitInstance);
+pin_trait!(Channel3Pin, CaptureCompare16bitInstance);
+pin_trait!(Channel4Pin, CaptureCompare16bitInstance);
+pin_trait!(ExternalTriggerPin, CaptureCompare16bitInstance);
#[cfg(not(stm32l0))]
-pin_trait!(ExternalTriggerPin, GeneralPurpose16bitInstance);
+pin_trait!(Channel1ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(Channel2ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(Channel3ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(Channel4ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(stm32l0)]
-pin_trait!(ExternalTriggerPin, GeneralPurpose2ChannelInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(BreakInputPin, ComplementaryCaptureCompare16bitInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(BreakInput2Pin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(Channel1ComplementaryPin, GeneralPurpose1ChannelComplementaryInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(Channel2ComplementaryPin, GeneralPurpose2ChannelComplementaryInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(Channel3ComplementaryPin, AdvancedControlInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(Channel4ComplementaryPin, AdvancedControlInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(BreakInputComparator1Pin, ComplementaryCaptureCompare16bitInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(BreakInputComparator2Pin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(BreakInputPin, GeneralPurpose1ChannelComplementaryInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(BreakInput2Pin, GeneralPurpose2ChannelComplementaryInstance);
-
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(BreakInputComparator1Pin, GeneralPurpose1ChannelComplementaryInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(BreakInputComparator2Pin, AdvancedControlInstance);
-
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(BreakInput2Comparator1Pin, AdvancedControlInstance);
-#[cfg(not(any(stm32l0, stm32l1)))]
-pin_trait!(BreakInput2Comparator2Pin, AdvancedControlInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(BreakInput2Comparator1Pin, ComplementaryCaptureCompare16bitInstance);
+#[cfg(not(stm32l0))]
+pin_trait!(BreakInput2Comparator2Pin, ComplementaryCaptureCompare16bitInstance);
#[allow(unused)]
macro_rules! impl_core_timer {
@@ -830,7 +783,7 @@ macro_rules! impl_2ch_timer {
}
#[allow(unused)]
-macro_rules! impl_gp_16bit_timer {
+macro_rules! impl_gp16_timer {
($inst:ident) => {
impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst {
fn regs_gp16() -> crate::pac::timer::TimGp16 {
@@ -841,7 +794,7 @@ macro_rules! impl_gp_16bit_timer {
}
#[allow(unused)]
-macro_rules! impl_gp_32bit_timer {
+macro_rules! impl_gp32_timer {
($inst:ident) => {
impl sealed::GeneralPurpose32bitInstance for crate::peripherals::$inst {
fn regs_gp32() -> crate::pac::timer::TimGp32 {
@@ -890,26 +843,30 @@ foreach_interrupt! {
impl_core_timer!($inst, $irq);
impl_basic_no_cr2_timer!($inst);
impl_basic_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl BasicNoCr2Instance for crate::peripherals::$inst{}
impl BasicInstance for crate::peripherals::$inst {}
};
($inst:ident, timer, TIM_1CH, UP, $irq:ident) => {
impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
impl_1ch_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
+ impl_2ch_timer!($inst);
+ impl_gp16_timer!($inst);
+ impl BasicInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
};
($inst:ident, timer, TIM_2CH, UP, $irq:ident) => {
impl_core_timer!($inst, $irq);
+ impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
impl_1ch_timer!($inst);
impl_2ch_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
+ impl_gp16_timer!($inst);
+ impl BasicInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
};
($inst:ident, timer, TIM_GP16, UP, $irq:ident) => {
@@ -918,13 +875,9 @@ foreach_interrupt! {
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
impl_2ch_timer!($inst);
- impl_gp_16bit_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl_gp16_timer!($inst);
impl BasicInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
};
($inst:ident, timer, TIM_GP32, UP, $irq:ident) => {
@@ -933,26 +886,26 @@ foreach_interrupt! {
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
impl_2ch_timer!($inst);
- impl_gp_16bit_timer!($inst);
- impl_gp_32bit_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl_gp16_timer!($inst);
+ impl_gp32_timer!($inst);
impl BasicInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
- impl GeneralPurpose32bitInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl CaptureCompare32bitInstance for crate::peripherals::$inst {}
};
($inst:ident, timer, TIM_1CH_CMP, UP, $irq:ident) => {
impl_core_timer!($inst, $irq);
impl_basic_no_cr2_timer!($inst);
+ impl_basic_timer!($inst);
impl_1ch_timer!($inst);
+ impl_2ch_timer!($inst);
+ impl_gp16_timer!($inst);
impl_1ch_cmp_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl BasicNoCr2Instance for crate::peripherals::$inst{}
- impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
+ impl_2ch_cmp_timer!($inst);
+ impl_adv_timer!($inst);
+ impl BasicInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
@@ -962,15 +915,13 @@ foreach_interrupt! {
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
impl_2ch_timer!($inst);
+ impl_gp16_timer!($inst);
impl_1ch_cmp_timer!($inst);
impl_2ch_cmp_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl BasicNoCr2Instance for crate::peripherals::$inst{}
+ impl_adv_timer!($inst);
impl BasicInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
- impl GeneralPurpose2ChannelComplementaryInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
@@ -980,26 +931,20 @@ foreach_interrupt! {
impl_basic_timer!($inst);
impl_1ch_timer!($inst);
impl_2ch_timer!($inst);
+ impl_gp16_timer!($inst);
impl_1ch_cmp_timer!($inst);
- impl_gp_16bit_timer!($inst);
impl_2ch_cmp_timer!($inst);
impl_adv_timer!($inst);
- impl CoreInstance for crate::peripherals::$inst {}
- impl BasicNoCr2Instance for crate::peripherals::$inst{}
impl BasicInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose2ChannelInstance for crate::peripherals::$inst {}
- impl GeneralPurpose16bitInstance for crate::peripherals::$inst {}
- impl GeneralPurpose1ChannelComplementaryInstance for crate::peripherals::$inst {}
- impl GeneralPurpose2ChannelComplementaryInstance for crate::peripherals::$inst {}
- impl AdvancedControlInstance for crate::peripherals::$inst {}
+ impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
+ impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
}
// Update Event trigger DMA for every timer
-dma_trait!(UpDma, BasicNoCr2Instance);
+dma_trait!(UpDma, BasicInstance);
-dma_trait!(Ch1Dma, GeneralPurpose1ChannelInstance);
-dma_trait!(Ch2Dma, GeneralPurpose2ChannelInstance);
-dma_trait!(Ch3Dma, GeneralPurpose16bitInstance);
-dma_trait!(Ch4Dma, GeneralPurpose16bitInstance);
+dma_trait!(Ch1Dma, CaptureCompare16bitInstance);
+dma_trait!(Ch2Dma, CaptureCompare16bitInstance);
+dma_trait!(Ch3Dma, CaptureCompare16bitInstance);
+dma_trait!(Ch4Dma, CaptureCompare16bitInstance);
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index 7e56312bb..59efb72ba 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -30,7 +30,7 @@ pub struct QeiPin<'d, T, Channel> {
macro_rules! channel_impl {
($new_chx:ident, $channel:ident, $pin_trait:ident) => {
- impl<'d, T: GeneralPurpose16bitInstance> QeiPin<'d, T, $channel> {
+ impl<'d, T: CaptureCompare16bitInstance> QeiPin<'d, T, $channel> {
#[doc = concat!("Create a new ", stringify!($channel), " QEI pin instance.")]
pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd) -> Self {
into_ref!(pin);
@@ -57,7 +57,7 @@ pub struct Qei<'d, T> {
_inner: PeripheralRef<'d, T>,
}
-impl<'d, T: GeneralPurpose16bitInstance> Qei<'d, T> {
+impl<'d, T: CaptureCompare16bitInstance> Qei<'d, T> {
/// Create a new quadrature decoder driver.
pub fn new(tim: impl Peripheral<P = T> + 'd, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
Self::new_inner(tim)
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 088d02c97..1acba504e 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -1,7 +1,6 @@
//! Simple PWM driver.
use core::marker::PhantomData;
-use core::ops::{Deref, DerefMut};
use embassy_hal_internal::{into_ref, PeripheralRef};
@@ -31,7 +30,7 @@ pub struct PwmPin<'d, T, C> {
macro_rules! channel_impl {
($new_chx:ident, $channel:ident, $pin_trait:ident) => {
- impl<'d, T: GeneralPurpose16bitInstance> PwmPin<'d, T, $channel> {
+ impl<'d, T: CaptureCompare16bitInstance> PwmPin<'d, T, $channel> {
#[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
into_ref!(pin);
@@ -60,7 +59,7 @@ pub struct SimplePwm<'d, T> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
+impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
/// Create a new simple PWM driver.
pub fn new(
tim: impl Peripheral<P = T> + 'd,
@@ -88,13 +87,9 @@ impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
[Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
.iter()
.for_each(|&channel| {
- sealed::GeneralPurpose16bitInstance::set_output_compare_mode(
- this.inner.deref_mut(),
- channel,
- OutputCompareMode::PwmMode1,
- );
+ this.inner.set_output_compare_mode(channel, OutputCompareMode::PwmMode1);
- sealed::GeneralPurpose16bitInstance::set_output_compare_preload(this.inner.deref_mut(), channel, true);
+ this.inner.set_output_compare_preload(channel, true);
});
this
@@ -102,17 +97,17 @@ impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
/// Enable the given channel.
pub fn enable(&mut self, channel: Channel) {
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
+ self.inner.enable_channel(channel, true);
}
/// Disable the given channel.
pub fn disable(&mut self, channel: Channel) {
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
+ self.inner.enable_channel(channel, false);
}
/// Check whether given channel is enabled
pub fn is_enabled(&self, channel: Channel) -> bool {
- sealed::GeneralPurpose16bitInstance::get_channel_enable_state(self.inner.deref(), channel)
+ self.inner.get_channel_enable_state(channel)
}
/// Set PWM frequency.
@@ -140,24 +135,24 @@ impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
/// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
pub fn set_duty(&mut self, channel: Channel, duty: u16) {
assert!(duty <= self.get_max_duty());
- sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
+ self.inner.set_compare_value(channel, duty)
}
/// Get the duty for a given channel.
///
/// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
pub fn get_duty(&self, channel: Channel) -> u16 {
- sealed::GeneralPurpose16bitInstance::get_compare_value(self.inner.deref(), channel)
+ self.inner.get_compare_value(channel)
}
/// Set the output polarity for a given channel.
pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
- sealed::GeneralPurpose16bitInstance::set_output_polarity(self.inner.deref_mut(), channel, polarity);
+ self.inner.set_output_polarity(channel, polarity);
}
/// Set the output compare mode for a given channel.
pub fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
- sealed::GeneralPurpose16bitInstance::set_output_compare_mode(self.inner.deref_mut(), channel, mode);
+ self.inner.set_output_compare_mode(channel, mode);
}
/// Generate a sequence of PWM waveform
@@ -232,7 +227,7 @@ impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
macro_rules! impl_waveform_chx {
($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
- impl<'d, T: GeneralPurpose16bitInstance> SimplePwm<'d, T> {
+ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
/// Generate a sequence of PWM waveform
///
/// Note:
@@ -319,17 +314,17 @@ impl_waveform_chx!(waveform_ch2, Ch2Dma, Ch2);
impl_waveform_chx!(waveform_ch3, Ch3Dma, Ch3);
impl_waveform_chx!(waveform_ch4, Ch4Dma, Ch4);
-impl<'d, T: GeneralPurpose16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
+impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
type Channel = Channel;
type Time = Hertz;
type Duty = u16;
fn disable(&mut self, channel: Self::Channel) {
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, false);
+ self.inner.enable_channel(channel, false);
}
fn enable(&mut self, channel: Self::Channel) {
- sealed::GeneralPurpose16bitInstance::enable_channel(self.inner.deref_mut(), channel, true);
+ self.inner.enable_channel(channel, true);
}
fn get_period(&self) -> Self::Time {
@@ -337,7 +332,7 @@ impl<'d, T: GeneralPurpose16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d,
}
fn get_duty(&self, channel: Self::Channel) -> Self::Duty {
- sealed::GeneralPurpose16bitInstance::get_compare_value(self.inner.deref(), channel)
+ self.inner.get_compare_value(channel)
}
fn get_max_duty(&self) -> Self::Duty {
@@ -346,7 +341,7 @@ impl<'d, T: GeneralPurpose16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d,
fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
assert!(duty <= self.get_max_duty());
- sealed::GeneralPurpose16bitInstance::set_compare_value(self.inner.deref_mut(), channel, duty)
+ self.inner.set_compare_value(channel, duty)
}
fn set_period<P>(&mut self, period: P)
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs
index 0be3eccb7..cc508c3cf 100644
--- a/examples/stm32h7/src/bin/low_level_timer_api.rs
+++ b/examples/stm32h7/src/bin/low_level_timer_api.rs
@@ -56,11 +56,11 @@ async fn main(_spawner: Spawner) {
Timer::after_millis(300).await;
}
}
-pub struct SimplePwm32<'d, T: GeneralPurpose32bitInstance> {
+pub struct SimplePwm32<'d, T: CaptureCompare32bitInstance> {
inner: PeripheralRef<'d, T>,
}
-impl<'d, T: GeneralPurpose32bitInstance> SimplePwm32<'d, T> {
+impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> {
pub fn new(
tim: impl Peripheral<P = T> + 'd,
ch1: impl Peripheral<P = impl Channel1Pin<T>> + 'd,
From 0f94006be3aa099d0a6039d51834562e51f91580 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Sat, 3 Feb 2024 17:30:00 +0800
Subject: [PATCH 174/392] doc fix
---
embassy-stm32/src/timer/mod.rs | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 5f40be957..9780c005c 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -20,10 +20,10 @@
//!
//! mapping:
//!
-//! Basic Timer --> BasicInstance
-//! 1-channel Timer, 2-channel Timer, General Purpose 16-bit Timer --> CaptureCompare16bitInstance
-//! General Purpose 32-bit Timer --> CaptureCompare32bitInstance
-//! 1-channel with one complentary Timer, 2-channel with one complentary Timer, Advance Control Timer --> ComplementaryCaptureCompare16bitInstance
+//! BasicInstance --> Basic Timer
+//! CaptureCompare16bitInstance --> 1-channel Timer, 2-channel Timer, General Purpose 16-bit Timer
+//! CaptureCompare32bitInstance --> General Purpose 32-bit Timer
+//! ComplementaryCaptureCompare16bitInstance --> 1-channel with one complentary Timer, 2-channel with one complentary Timer, Advance Control Timer
#[cfg(not(stm32l0))]
pub mod complementary_pwm;
@@ -667,7 +667,8 @@ impl From<OutputPolarity> for bool {
/// Basic 16-bit timer instance.
pub trait BasicInstance: sealed::BasicInstance + sealed::BasicNoCr2Instance + sealed::CoreInstance + 'static {}
-/// General-purpose 16-bit timer instance.
+// It's just a General-purpose 16-bit timer instance.
+/// Capture Compare timer instance.
pub trait CaptureCompare16bitInstance:
BasicInstance
+ sealed::GeneralPurpose2ChannelInstance
@@ -678,14 +679,16 @@ pub trait CaptureCompare16bitInstance:
}
#[cfg(not(stm32l0))]
-/// Gneral-purpose 32-bit timer instance.
+// It's just a General-purpose 32-bit timer instance.
+/// Capture Compare 32-bit timer instance.
pub trait CaptureCompare32bitInstance:
- sealed::GeneralPurpose32bitInstance + CaptureCompare16bitInstance + 'static
+ CaptureCompare16bitInstance + sealed::GeneralPurpose32bitInstance + 'static
{
}
#[cfg(not(stm32l0))]
-/// Advanced control timer instance.
+// It's just a Advanced Control timer instance.
+/// Complementary Capture Compare 32-bit timer instance.
pub trait ComplementaryCaptureCompare16bitInstance:
CaptureCompare16bitInstance
+ sealed::GeneralPurpose1ChannelComplementaryInstance
From 8fd803a5fe0af8cc9d648ba2efba755b502f08e9 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Sun, 4 Feb 2024 15:14:02 +0800
Subject: [PATCH 175/392] use cfg_if to reduce macro condition
---
embassy-stm32/src/timer/mod.rs | 34 ++++++++++++++--------------------
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 9780c005c..0118395a7 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -704,29 +704,23 @@ pin_trait!(Channel3Pin, CaptureCompare16bitInstance);
pin_trait!(Channel4Pin, CaptureCompare16bitInstance);
pin_trait!(ExternalTriggerPin, CaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(Channel1ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(Channel2ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(Channel3ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(Channel4ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
+cfg_if::cfg_if! {
+ if #[cfg(not(stm32l0))] {
+ pin_trait!(Channel1ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(Channel2ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(Channel3ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(Channel4ComplementaryPin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(BreakInputPin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(BreakInput2Pin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(BreakInputPin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(BreakInput2Pin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(BreakInputComparator1Pin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(BreakInputComparator2Pin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(BreakInputComparator1Pin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(BreakInputComparator2Pin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(BreakInput2Comparator1Pin, ComplementaryCaptureCompare16bitInstance);
-#[cfg(not(stm32l0))]
-pin_trait!(BreakInput2Comparator2Pin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(BreakInput2Comparator1Pin, ComplementaryCaptureCompare16bitInstance);
+ pin_trait!(BreakInput2Comparator2Pin, ComplementaryCaptureCompare16bitInstance);
+ }
+}
#[allow(unused)]
macro_rules! impl_core_timer {
From 832776d2c72a1fa9f6dcc89ea535e1023c368456 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 10 Feb 2024 02:50:35 +0100
Subject: [PATCH 176/392] stm32: update metapac.
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/rcc/h.rs | 1 +
embassy-stm32/src/rcc/u5.rs | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index eb67404d3..3f5f12f06 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-028efe4e6e0719b661cbdf8ffda3341e4d63d0df" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5bf4bec597bdf0d85402789b40c3a37b0f5a8e76" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-028efe4e6e0719b661cbdf8ffda3341e4d63d0df", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5bf4bec597bdf0d85402789b40c3a37b0f5a8e76", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 352e10816..474c44115 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -658,6 +658,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h5)]
audioclk: None,
per: None,
+ i2s_ckin: None,
);
}
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 9cec6c96c..20cc3112a 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -477,6 +477,7 @@ pub(crate) unsafe fn init(config: Config) {
pll3_p: None,
pll3_q: None,
pll3_r: None,
+ iclk: None,
);
}
From 802bdd1af86829482d6b847f73f02e6973bb68ea Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Sat, 10 Feb 2024 08:09:08 +0100
Subject: [PATCH 177/392] remove first person comments and assert disable state
when it's necessary
---
embassy-nrf/src/radio/ble.rs | 201 ++++++++++++++++++-----------------
1 file changed, 106 insertions(+), 95 deletions(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index 369b49c55..b0d374579 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -64,13 +64,13 @@ impl<'d, T: Instance> Radio<'d, T> {
// that if the packet payload length defined by PCNF1.STATLEN and the LENGTH field in the packet specifies a
// packet larger than MAXLEN, the payload will be truncated at MAXLEN
//
- // To simplify the implementation, I'm setting the max length to the maximum value
- // and I'm using only the length field to truncate the payload
+ // To simplify the implementation, It is setted as the maximum value
+ // and the length of the packet is controlled only by the LENGTH field in the packet
.maxlen()
.bits(255)
// Configure the length of the address field in the packet
// The prefix after the address fields is always appended, so is always 1 byte less than the size of the address
- // The base address is truncated from the least significant byte if the BALEN is less than 4
+ // The base address is truncated from the least significant byte if the BALEN is less than 4
//
// BLE address is always 4 bytes long
.balen()
@@ -92,14 +92,14 @@ impl<'d, T: Instance> Radio<'d, T> {
// Before whitening or de-whitening, the shift register should be
// initialized based on the channel index.
.whiteen()
- .set_bit() // Enable whitening
+ .set_bit()
});
// Configure CRC
r.crccnf.write(|w| {
// In BLE the CRC shall be calculated on the PDU of all Link Layer
// packets (even if the packet is encrypted).
- // So here we skip the address field
+ // It skips the address field
w.skipaddr()
.skip()
// In BLE 24-bit CRC = 3 bytes
@@ -125,11 +125,18 @@ impl<'d, T: Instance> Radio<'d, T> {
Self { _p: radio }
}
+ fn state(&self) -> RadioState {
+ match T::regs().state.read().state().variant() {
+ Ok(s) => s,
+ None => unreachable!(),
+ }
+ }
+
#[allow(dead_code)]
fn trace_state(&self) {
let r = T::regs();
- match r.state.read().state().variant().unwrap() {
+ match self.state() {
RadioState::DISABLED => trace!("radio:state:DISABLED"),
RadioState::RX_RU => trace!("radio:state:RX_RU"),
RadioState::RX_IDLE => trace!("radio:state:RX_IDLE"),
@@ -142,86 +149,12 @@ impl<'d, T: Instance> Radio<'d, T> {
}
}
- async fn trigger_and_wait_end(&mut self, trigger: impl FnOnce() -> ()) {
- //self.trace_state();
-
- let r = T::regs();
- let s = T::state();
-
- // If the Future is dropped before the end of the transmission
- // we need to disable the interrupt and stop the transmission
- // to keep the state consistent
- let drop = OnDrop::new(|| {
- trace!("radio drop: stopping");
-
- r.intenclr.write(|w| w.end().clear());
- r.events_end.reset();
-
- r.tasks_stop.write(|w| w.tasks_stop().set_bit());
-
- // The docs don't explicitly mention any event to acknowledge the stop task
- // So I guess it's the same as end
- while r.events_end.read().events_end().bit_is_clear() {}
-
- trace!("radio drop: stopped");
- });
-
- // trace!("radio:enable interrupt");
- // Clear some remnant side-effects (I'm unsure if this is needed)
- r.events_end.reset();
-
- // Enable interrupt
- r.intenset.write(|w| w.end().set());
-
- compiler_fence(Ordering::SeqCst);
-
- // Trigger the transmission
- trigger();
- // self.trace_state();
-
- // On poll check if interrupt happen
- poll_fn(|cx| {
- s.end_waker.register(cx.waker());
- if r.events_end.read().events_end().bit_is_set() {
- // trace!("radio:end");
- return core::task::Poll::Ready(());
- }
- Poll::Pending
- })
- .await;
-
- compiler_fence(Ordering::SeqCst);
- r.events_disabled.reset(); // ACK
-
- // Everthing ends fine, so we can disable the drop
- drop.defuse();
- }
-
- /// Disable the radio.
- fn disable(&mut self) {
- let r = T::regs();
-
- compiler_fence(Ordering::SeqCst);
- // If is already disabled, do nothing
- if !r.state.read().state().is_disabled() {
- trace!("radio:disable");
- // Trigger the disable task
- r.tasks_disable.write(|w| w.tasks_disable().set_bit());
-
- // Wait until the radio is disabled
- while r.events_disabled.read().events_disabled().bit_is_clear() {}
-
- compiler_fence(Ordering::SeqCst);
-
- // Acknowledge it
- r.events_disabled.reset();
- }
- }
-
/// Set the radio mode
///
/// The radio must be disabled before calling this function
pub fn set_mode(&mut self, mode: Mode) {
+ assert!(self.state() == RadioState::DISABLED);
+
let r = T::regs();
r.mode.write(|w| w.mode().variant(mode));
@@ -235,10 +168,12 @@ impl<'d, T: Instance> Radio<'d, T> {
});
}
- /// Set the header size changing the S1 field
+ /// Set the header size changing the S1's len field
///
/// The radio must be disabled before calling this function
pub fn set_header_expansion(&mut self, use_s1_field: bool) {
+ assert!(self.state() == RadioState::DISABLED);
+
let r = T::regs();
// s1 len in bits
@@ -268,6 +203,8 @@ impl<'d, T: Instance> Radio<'d, T> {
///
/// The radio must be disabled before calling this function
pub fn set_whitening_init(&mut self, whitening_init: u8) {
+ assert!(self.state() == RadioState::DISABLED);
+
let r = T::regs();
r.datawhiteiv.write(|w| unsafe { w.datawhiteiv().bits(whitening_init) });
@@ -276,9 +213,11 @@ impl<'d, T: Instance> Radio<'d, T> {
/// Set the central frequency to be used
/// It should be in the range 2400..2500
///
- /// The radio must be disabled before calling this function
+ /// [The radio must be disabled before calling this function](https://devzone.nordicsemi.com/f/nordic-q-a/15829/radio-frequency-change)
pub fn set_frequency(&mut self, frequency: u32) {
+ assert!(self.state() == RadioState::DISABLED);
assert!(2400 <= frequency && frequency <= 2500);
+
let r = T::regs();
r.frequency
@@ -292,6 +231,8 @@ impl<'d, T: Instance> Radio<'d, T> {
///
/// The radio must be disabled before calling this function
pub fn set_access_address(&mut self, access_address: u32) {
+ assert!(self.state() == RadioState::DISABLED);
+
let r = T::regs();
// Configure logical address
@@ -309,9 +250,9 @@ impl<'d, T: Instance> Radio<'d, T> {
r.txaddress.write(|w| unsafe { w.txaddress().bits(0) });
// Match on logical address
- // For what I understand, this config only filter the packets
- // by the address, so only packages send to the previous address
- // will finish the reception
+ // This config only filter the packets by the address,
+ // so only packages send to the previous address
+ // will finish the reception (TODO: check the explanation)
r.rxaddresses.write(|w| {
w.addr0()
.enabled()
@@ -331,6 +272,8 @@ impl<'d, T: Instance> Radio<'d, T> {
///
/// The radio must be disabled before calling this function
pub fn set_crc_poly(&mut self, crc_poly: u32) {
+ assert!(self.state() == RadioState::DISABLED);
+
let r = T::regs();
r.crcpoly.write(|w| unsafe {
@@ -351,6 +294,8 @@ impl<'d, T: Instance> Radio<'d, T> {
///
/// The radio must be disabled before calling this function
pub fn set_crc_init(&mut self, crc_init: u32) {
+ assert!(self.state() == RadioState::DISABLED);
+
let r = T::regs();
r.crcinit.write(|w| unsafe { w.crcinit().bits(crc_init & 0xFFFFFF) });
@@ -360,6 +305,8 @@ impl<'d, T: Instance> Radio<'d, T> {
///
/// The radio must be disabled before calling this function
pub fn set_tx_power(&mut self, tx_power: TxPower) {
+ assert!(self.state() == RadioState::DISABLED);
+
let r = T::regs();
r.txpower.write(|w| w.txpower().variant(tx_power));
@@ -408,19 +355,83 @@ impl<'d, T: Instance> Radio<'d, T> {
// Initialize the transmission
// trace!("rxen");
r.tasks_rxen.write(|w| w.tasks_rxen().set_bit());
+ })
+ .await;
+ }
- // Await until ready
- while r.events_ready.read().events_ready().bit_is_clear() {}
+ async fn trigger_and_wait_end(&mut self, trigger: impl FnOnce()) {
+ //self.trace_state();
+
+ let r = T::regs();
+ let s = T::state();
+
+ // If the Future is dropped before the end of the transmission
+ // we need to disable the interrupt and stop the transmission
+ // to keep the state consistent
+ let drop = OnDrop::new(|| {
+ trace!("radio drop: stopping");
+
+ r.intenclr.write(|w| w.end().clear());
+ r.events_end.reset();
+
+ r.tasks_stop.write(|w| w.tasks_stop().set_bit());
+
+ // The docs don't explicitly mention any event to acknowledge the stop task
+ while r.events_end.read().events_end().bit_is_clear() {}
+
+ trace!("radio drop: stopped");
+ });
+
+ // trace!("radio:enable interrupt");
+ // Clear some remnant side-effects (TODO: check if this is necessary)
+ r.events_end.reset();
+
+ // Enable interrupt
+ r.intenset.write(|w| w.end().set());
+
+ compiler_fence(Ordering::SeqCst);
+
+ // Trigger the transmission
+ trigger();
+ // self.trace_state();
+
+ // On poll check if interrupt happen
+ poll_fn(|cx| {
+ s.end_waker.register(cx.waker());
+ if r.events_end.read().events_end().bit_is_set() {
+ // trace!("radio:end");
+ return core::task::Poll::Ready(());
+ }
+ Poll::Pending
+ })
+ .await;
+
+ compiler_fence(Ordering::SeqCst);
+ r.events_disabled.reset(); // ACK
+
+ // Everthing ends fine, so we can disable the drop
+ drop.defuse();
+ }
+
+ /// Disable the radio
+ fn disable(&mut self) {
+ let r = T::regs();
+
+ compiler_fence(Ordering::SeqCst);
+ // If it is already disabled, do nothing
+ if self.state() != RadioState::DISABLED {
+ trace!("radio:disable");
+ // Trigger the disable task
+ r.tasks_disable.write(|w| w.tasks_disable().set_bit());
+
+ // Wait until the radio is disabled
+ while r.events_disabled.read().events_disabled().bit_is_clear() {}
compiler_fence(Ordering::SeqCst);
// Acknowledge it
- r.events_ready.reset();
-
- // trace!("radio:start");
- r.tasks_start.write(|w| w.tasks_start().set_bit());
- })
- .await;
+ r.events_disabled.reset();
+ }
}
}
From 37739284253699d3f087fd8e1f9282090e6aaf95 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Sat, 10 Feb 2024 08:18:32 +0100
Subject: [PATCH 178/392] apply clippy sugestions
---
embassy-nrf/src/radio/ble.rs | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index b0d374579..c74676f58 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -127,15 +127,13 @@ impl<'d, T: Instance> Radio<'d, T> {
fn state(&self) -> RadioState {
match T::regs().state.read().state().variant() {
- Ok(s) => s,
+ Some(s) => s,
None => unreachable!(),
}
}
#[allow(dead_code)]
fn trace_state(&self) {
- let r = T::regs();
-
match self.state() {
RadioState::DISABLED => trace!("radio:state:DISABLED"),
RadioState::RX_RU => trace!("radio:state:RX_RU"),
@@ -216,7 +214,7 @@ impl<'d, T: Instance> Radio<'d, T> {
/// [The radio must be disabled before calling this function](https://devzone.nordicsemi.com/f/nordic-q-a/15829/radio-frequency-change)
pub fn set_frequency(&mut self, frequency: u32) {
assert!(self.state() == RadioState::DISABLED);
- assert!(2400 <= frequency && frequency <= 2500);
+ assert!((2400..=2500).contains(&frequency));
let r = T::regs();
From 40282c2666f8b8bda5785b30a62ab352ff8e7498 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Sat, 10 Feb 2024 08:49:14 +0100
Subject: [PATCH 179/392] add buffer input on transmit/receive
---
embassy-nrf/src/radio/ble.rs | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index c74676f58..7718cfe14 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -316,7 +316,7 @@ impl<'d, T: Instance> Radio<'d, T> {
/// for the life time of the transmission or if the buffer will be modified.
/// Also if the buffer is smaller than the packet length, the radio will
/// read/write memory out of the buffer bounds.
- pub fn set_buffer(&mut self, buffer: &[u8]) -> Result<(), Error> {
+ fn set_buffer(&mut self, buffer: &[u8]) -> Result<(), Error> {
// Because we are serializing the buffer, we should always have the buffer in RAM
slice_in_ram_or(buffer, Error::BufferNotInRAM)?;
@@ -334,27 +334,33 @@ impl<'d, T: Instance> Radio<'d, T> {
}
/// Send packet
- pub async fn transmit(&mut self) {
- let r = T::regs();
+ pub async fn transmit(&mut self, buffer: &[u8]) -> Result<(), Error> {
+ self.set_buffer(buffer)?;
+ let r = T::regs();
self.trigger_and_wait_end(move || {
// Initialize the transmission
// trace!("txen");
r.tasks_txen.write(|w| w.tasks_txen().set_bit());
})
.await;
+
+ Ok(())
}
/// Receive packet
- pub async fn receive(&mut self) {
- let r = T::regs();
+ pub async fn receive(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
+ self.set_buffer(buffer)?;
+ let r = T::regs();
self.trigger_and_wait_end(move || {
// Initialize the transmission
// trace!("rxen");
r.tasks_rxen.write(|w| w.tasks_rxen().set_bit());
})
.await;
+
+ Ok(())
}
async fn trigger_and_wait_end(&mut self, trigger: impl FnOnce()) {
From fdb15b205424e71107f18b43553d43691f3d8fb7 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Sat, 10 Feb 2024 08:58:31 +0100
Subject: [PATCH 180/392] add comments about buffer unsound
---
embassy-nrf/src/radio/ble.rs | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index 7718cfe14..ba9ac5f2e 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -334,6 +334,8 @@ impl<'d, T: Instance> Radio<'d, T> {
}
/// Send packet
+ /// If the length byte in the package is greater than the buffer length
+ /// the radio will read memory out of the buffer bounds
pub async fn transmit(&mut self, buffer: &[u8]) -> Result<(), Error> {
self.set_buffer(buffer)?;
@@ -349,6 +351,8 @@ impl<'d, T: Instance> Radio<'d, T> {
}
/// Receive packet
+ /// If the length byte in the received package is greater than the buffer length
+ /// the radio will write memory out of the buffer bounds
pub async fn receive(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
self.set_buffer(buffer)?;
From b4399a1bf56403a8a3204e440fb1b9295bb2a137 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Sat, 10 Feb 2024 15:58:56 +0800
Subject: [PATCH 181/392] timer-doc-fix
---
embassy-stm32/src/timer/mod.rs | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 0118395a7..9480d6972 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -1,6 +1,8 @@
//! Timers, PWM, quadrature decoder.
+//!
//! Timer inheritance
+//!
// sealed:
//
@@ -14,16 +16,20 @@
// | +--------------------------------------|-----------+
// +----------------------------------------------------+
-//! BasicInstance --> CaptureCompare16bitInstance --+--> ComplementaryCaptureCompare16bitInstance
-//! |
-//! +--> CaptureCompare32bitInstance
+//! ```text
+//! BasicInstance --> CaptureCompare16bitInstance --+--> ComplementaryCaptureCompare16bitInstance
+//! |
+//! +--> CaptureCompare32bitInstance
+//! ```
//!
-//! mapping:
+//! Mapping:
//!
-//! BasicInstance --> Basic Timer
-//! CaptureCompare16bitInstance --> 1-channel Timer, 2-channel Timer, General Purpose 16-bit Timer
-//! CaptureCompare32bitInstance --> General Purpose 32-bit Timer
-//! ComplementaryCaptureCompare16bitInstance --> 1-channel with one complentary Timer, 2-channel with one complentary Timer, Advance Control Timer
+//! | trait | timer |
+//! | :----------------------------------------: | ------------------------------------------------------------------------------------------------- |
+//! | [BasicInstance] | Basic Timer |
+//! | [CaptureCompare16bitInstance] | 1-channel Timer, 2-channel Timer, General Purpose 16-bit Timer |
+//! | [CaptureCompare32bitInstance] | General Purpose 32-bit Timer |
+//! | [ComplementaryCaptureCompare16bitInstance] | 1-channel with one complentary Timer, 2-channel with one complentary Timer, Advance Control Timer |
#[cfg(not(stm32l0))]
pub mod complementary_pwm;
From d77b6a60d21568b8470957441b07a4974751c288 Mon Sep 17 00:00:00 2001
From: Han Cen <hi@chamburr.com>
Date: Sat, 10 Feb 2024 20:44:14 +0800
Subject: [PATCH 182/392] Fix unaligned buffer in async updater
---
embassy-boot/src/firmware_updater/asynch.rs | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/embassy-boot/src/firmware_updater/asynch.rs b/embassy-boot/src/firmware_updater/asynch.rs
index 668f16f16..a7c360a35 100644
--- a/embassy-boot/src/firmware_updater/asynch.rs
+++ b/embassy-boot/src/firmware_updater/asynch.rs
@@ -276,16 +276,25 @@ impl<'d, STATE: NorFlash> FirmwareState<'d, STATE> {
async fn set_magic(&mut self, magic: u8) -> Result<(), FirmwareUpdaterError> {
self.state.read(0, &mut self.aligned).await?;
- if self.aligned.iter().any(|&b| b != magic) {
+ if self.aligned[..STATE::WRITE_SIZE].iter().any(|&b| b != magic) {
// Read progress validity
- self.state.read(STATE::WRITE_SIZE as u32, &mut self.aligned).await?;
+ if STATE::READ_SIZE <= 2 * STATE::WRITE_SIZE {
+ self.state.read(STATE::WRITE_SIZE as u32, &mut self.aligned).await?;
+ } else {
+ self.aligned.rotate_left(STATE::WRITE_SIZE);
+ }
- if self.aligned.iter().any(|&b| b != STATE_ERASE_VALUE) {
+ if self.aligned[..STATE::WRITE_SIZE]
+ .iter()
+ .any(|&b| b != STATE_ERASE_VALUE)
+ {
// The current progress validity marker is invalid
} else {
// Invalidate progress
self.aligned.fill(!STATE_ERASE_VALUE);
- self.state.write(STATE::WRITE_SIZE as u32, &self.aligned).await?;
+ self.state
+ .write(STATE::WRITE_SIZE as u32, &self.aligned[..STATE::WRITE_SIZE])
+ .await?;
}
// Clear magic and progress
@@ -293,7 +302,7 @@ impl<'d, STATE: NorFlash> FirmwareState<'d, STATE> {
// Set magic
self.aligned.fill(magic);
- self.state.write(0, &self.aligned).await?;
+ self.state.write(0, &self.aligned[..STATE::WRITE_SIZE]).await?;
}
Ok(())
}
From c873dcbb20f06e00659ab1c984ce7a753aaea7dc Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Sat, 10 Feb 2024 16:55:32 -0500
Subject: [PATCH 183/392] Add explicit reset time to ws2812 write fn.
---
examples/rp/src/bin/pio_ws2812.rs | 2 ++
1 file changed, 2 insertions(+)
diff --git a/examples/rp/src/bin/pio_ws2812.rs b/examples/rp/src/bin/pio_ws2812.rs
index 9a97cb8a7..e9a3d0e41 100644
--- a/examples/rp/src/bin/pio_ws2812.rs
+++ b/examples/rp/src/bin/pio_ws2812.rs
@@ -107,6 +107,8 @@ impl<'d, P: Instance, const S: usize, const N: usize> Ws2812<'d, P, S, N> {
// DMA transfer
self.sm.tx().dma_push(self.dma.reborrow(), &words).await;
+
+ Timer::after_micros(55).await;
}
}
From b4dc406e199a7e4aafcdd601aaef999c6b7ba590 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Sat, 10 Feb 2024 17:00:10 -0500
Subject: [PATCH 184/392] Switch to ticker
---
examples/rp/src/bin/pio_ws2812.rs | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/examples/rp/src/bin/pio_ws2812.rs b/examples/rp/src/bin/pio_ws2812.rs
index e9a3d0e41..ac145933c 100644
--- a/examples/rp/src/bin/pio_ws2812.rs
+++ b/examples/rp/src/bin/pio_ws2812.rs
@@ -12,7 +12,7 @@ use embassy_rp::pio::{
Common, Config, FifoJoin, Instance, InterruptHandler, Pio, PioPin, ShiftConfig, ShiftDirection, StateMachine,
};
use embassy_rp::{bind_interrupts, clocks, into_ref, Peripheral, PeripheralRef};
-use embassy_time::Timer;
+use embassy_time::{Duration, Ticker, Timer};
use fixed::types::U24F8;
use fixed_macro::fixed;
use smart_leds::RGB8;
@@ -145,6 +145,7 @@ async fn main(_spawner: Spawner) {
let mut ws2812 = Ws2812::new(&mut common, sm0, p.DMA_CH0, p.PIN_16);
// Loop forever making RGB values and pushing them out to the WS2812.
+ let mut ticker = Ticker::every(Duration::from_millis(10));
loop {
for j in 0..(256 * 5) {
debug!("New Colors:");
@@ -154,7 +155,7 @@ async fn main(_spawner: Spawner) {
}
ws2812.write(&data).await;
- Timer::after_millis(10).await;
+ ticker.next().await;
}
}
}
From eb64d71247dd7c217c7ead98635610fdd8a104e3 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 11 Feb 2024 11:32:29 -0500
Subject: [PATCH 185/392] Consolidated hash drivers.
---
embassy-stm32/src/hash/mod.rs | 551 ++++++++++++++++++++++++++++++-
embassy-stm32/src/hash/v1v3v4.rs | 399 ----------------------
embassy-stm32/src/hash/v2.rs | 389 ----------------------
examples/stm32f7/src/bin/hash.rs | 10 +-
tests/stm32/Cargo.toml | 2 +-
tests/stm32/src/bin/hash.rs | 30 +-
tests/stm32/src/common.rs | 7 -
7 files changed, 565 insertions(+), 823 deletions(-)
delete mode 100644 embassy-stm32/src/hash/v1v3v4.rs
delete mode 100644 embassy-stm32/src/hash/v2.rs
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 64c1a0a8c..f0c2c839a 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -1,8 +1,545 @@
-//! Hash Accelerator (HASH)
-#[cfg_attr(hash_v1, path = "v1v3v4.rs")]
-#[cfg_attr(hash_v2, path = "v2.rs")]
-#[cfg_attr(hash_v3, path = "v1v3v4.rs")]
-#[cfg_attr(hash_v4, path = "v1v3v4.rs")]
-mod _version;
+//! Hash generator (HASH)
+use core::cmp::min;
+#[cfg(hash_v2)]
+use core::future::poll_fn;
+use core::marker::PhantomData;
+#[cfg(hash_v2)]
+use core::ptr;
+#[cfg(hash_v2)]
+use core::task::Poll;
-pub use _version::*;
+use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_sync::waitqueue::AtomicWaker;
+use stm32_metapac::hash::regs::*;
+
+use crate::dma::NoDma;
+#[cfg(hash_v2)]
+use crate::dma::Transfer;
+use crate::interrupt::typelevel::Interrupt;
+use crate::peripherals::HASH;
+use crate::rcc::sealed::RccPeripheral;
+use crate::{interrupt, pac, peripherals, Peripheral};
+
+#[cfg(hash_v1)]
+const NUM_CONTEXT_REGS: usize = 51;
+#[cfg(hash_v3)]
+const NUM_CONTEXT_REGS: usize = 103;
+#[cfg(any(hash_v2, hash_v4))]
+const NUM_CONTEXT_REGS: usize = 54;
+
+const HASH_BUFFER_LEN: usize = 132;
+const DIGEST_BLOCK_SIZE: usize = 128;
+
+static HASH_WAKER: AtomicWaker = AtomicWaker::new();
+
+/// HASH interrupt handler.
+pub struct InterruptHandler<T: Instance> {
+ _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
+ unsafe fn on_interrupt() {
+ let bits = T::regs().sr().read();
+ if bits.dinis() {
+ T::regs().imr().modify(|reg| reg.set_dinie(false));
+ HASH_WAKER.wake();
+ }
+ if bits.dcis() {
+ T::regs().imr().modify(|reg| reg.set_dcie(false));
+ HASH_WAKER.wake();
+ }
+ }
+}
+
+///Hash algorithm selection
+#[derive(Clone, Copy, PartialEq)]
+pub enum Algorithm {
+ /// SHA-1 Algorithm
+ SHA1 = 0,
+
+ #[cfg(any(hash_v1, hash_v2, hash_v4))]
+ /// MD5 Algorithm
+ MD5 = 1,
+
+ /// SHA-224 Algorithm
+ SHA224 = 2,
+
+ /// SHA-256 Algorithm
+ SHA256 = 3,
+
+ #[cfg(hash_v3)]
+ /// SHA-384 Algorithm
+ SHA384 = 12,
+
+ #[cfg(hash_v3)]
+ /// SHA-512/224 Algorithm
+ SHA512_224 = 13,
+
+ #[cfg(hash_v3)]
+ /// SHA-512/256 Algorithm
+ SHA512_256 = 14,
+
+ #[cfg(hash_v3)]
+ /// SHA-256 Algorithm
+ SHA512 = 15,
+}
+
+/// Input data width selection
+#[repr(u8)]
+#[derive(Clone, Copy)]
+pub enum DataType {
+ ///32-bit data, no data is swapped.
+ Width32 = 0,
+ ///16-bit data, each half-word is swapped.
+ Width16 = 1,
+ ///8-bit data, all bytes are swapped.
+ Width8 = 2,
+ ///1-bit data, all bits are swapped.
+ Width1 = 3,
+}
+
+/// Stores the state of the HASH peripheral for suspending/resuming
+/// digest calculation.
+pub struct Context {
+ first_word_sent: bool,
+ buffer: [u8; HASH_BUFFER_LEN],
+ buflen: usize,
+ algo: Algorithm,
+ format: DataType,
+ imr: u32,
+ str: u32,
+ cr: u32,
+ csr: [u32; NUM_CONTEXT_REGS],
+}
+
+/// HASH driver.
+pub struct Hash<'d, T: Instance, D = NoDma> {
+ _peripheral: PeripheralRef<'d, T>,
+ #[allow(dead_code)]
+ dma: PeripheralRef<'d, D>,
+}
+
+impl<'d, T: Instance, D> Hash<'d, T, D> {
+ /// Instantiates, resets, and enables the HASH peripheral.
+ pub fn new(
+ peripheral: impl Peripheral<P = T> + 'd,
+ dma: impl Peripheral<P = D> + 'd,
+ _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+ ) -> Self {
+ HASH::enable_and_reset();
+ into_ref!(peripheral, dma);
+ let instance = Self {
+ _peripheral: peripheral,
+ dma: dma,
+ };
+
+ T::Interrupt::unpend();
+ unsafe { T::Interrupt::enable() };
+
+ instance
+ }
+
+ /// Starts computation of a new hash and returns the saved peripheral state.
+ pub fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
+ // Define a context for this new computation.
+ let mut ctx = Context {
+ first_word_sent: false,
+ buffer: [0; HASH_BUFFER_LEN],
+ buflen: 0,
+ algo: algorithm,
+ format: format,
+ imr: 0,
+ str: 0,
+ cr: 0,
+ csr: [0; NUM_CONTEXT_REGS],
+ };
+
+ // Set the data type in the peripheral.
+ T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
+
+ // Select the algorithm.
+ #[cfg(hash_v1)]
+ if ctx.algo == Algorithm::MD5 {
+ T::regs().cr().modify(|w| w.set_algo(true));
+ }
+
+ #[cfg(hash_v2)]
+ {
+ // Select the algorithm.
+ let mut algo0 = false;
+ let mut algo1 = false;
+ if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
+ algo0 = true;
+ }
+ if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
+ algo1 = true;
+ }
+ T::regs().cr().modify(|w| w.set_algo0(algo0));
+ T::regs().cr().modify(|w| w.set_algo1(algo1));
+ }
+
+ #[cfg(any(hash_v3, hash_v4))]
+ T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
+
+ T::regs().cr().modify(|w| w.set_init(true));
+
+ // Store and return the state of the peripheral.
+ self.store_context(&mut ctx);
+ ctx
+ }
+
+ /// Restores the peripheral state using the given context,
+ /// then updates the state with the provided data.
+ /// Peripheral state is saved upon return.
+ pub fn update_blocking(&mut self, ctx: &mut Context, input: &[u8]) {
+ let mut data_waiting = input.len() + ctx.buflen;
+ if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
+ // There isn't enough data to digest a block, so append it to the buffer.
+ ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
+ ctx.buflen += input.len();
+ return;
+ }
+
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ let mut ilen_remaining = input.len();
+ let mut input_start = 0;
+
+ // Handle first block.
+ if !ctx.first_word_sent {
+ let empty_len = ctx.buffer.len() - ctx.buflen;
+ let copy_len = min(empty_len, ilen_remaining);
+ // Fill the buffer.
+ if copy_len > 0 {
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[0..copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ self.accumulate_blocking(ctx.buffer.as_slice());
+ data_waiting -= ctx.buflen;
+ ctx.buflen = 0;
+ ctx.first_word_sent = true;
+ }
+
+ if data_waiting < DIGEST_BLOCK_SIZE {
+ // There isn't enough data remaining to process another block, so store it.
+ ctx.buffer[0..ilen_remaining].copy_from_slice(&input[input_start..input_start + ilen_remaining]);
+ ctx.buflen += ilen_remaining;
+ } else {
+ // First ingest the data in the buffer.
+ let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
+ if empty_len > 0 {
+ let copy_len = min(empty_len, ilen_remaining);
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len]
+ .copy_from_slice(&input[input_start..input_start + copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ self.accumulate_blocking(&ctx.buffer[0..DIGEST_BLOCK_SIZE]);
+ ctx.buflen = 0;
+
+ // Move any extra data to the now-empty buffer.
+ let leftovers = ilen_remaining % 64;
+ if leftovers > 0 {
+ ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
+ ctx.buflen += leftovers;
+ ilen_remaining -= leftovers;
+ }
+
+ // Hash the remaining data.
+ self.accumulate_blocking(&input[input_start..input_start + ilen_remaining]);
+ }
+
+ // Save the peripheral context.
+ self.store_context(ctx);
+ }
+
+ /// Restores the peripheral state using the given context,
+ /// then updates the state with the provided data.
+ /// Peripheral state is saved upon return.
+ #[cfg(hash_v2)]
+ pub async fn update(&mut self, ctx: &mut Context, input: &[u8])
+ where
+ D: crate::hash::Dma<T>,
+ {
+ let data_waiting = input.len() + ctx.buflen;
+ if data_waiting < DIGEST_BLOCK_SIZE {
+ // There isn't enough data to digest a block, so append it to the buffer.
+ ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
+ ctx.buflen += input.len();
+ return;
+ }
+
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ // Enable multiple DMA transfers.
+ T::regs().cr().modify(|w| w.set_mdmat(true));
+
+ let mut ilen_remaining = input.len();
+ let mut input_start = 0;
+
+ // First ingest the data in the buffer.
+ let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
+ if empty_len > 0 {
+ let copy_len = min(empty_len, ilen_remaining);
+ ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[input_start..input_start + copy_len]);
+ ctx.buflen += copy_len;
+ ilen_remaining -= copy_len;
+ input_start += copy_len;
+ }
+ self.accumulate(&ctx.buffer[..DIGEST_BLOCK_SIZE]).await;
+ ctx.buflen = 0;
+
+ // Move any extra data to the now-empty buffer.
+ let leftovers = ilen_remaining % DIGEST_BLOCK_SIZE;
+ if leftovers > 0 {
+ assert!(ilen_remaining >= leftovers);
+ ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
+ ctx.buflen += leftovers;
+ ilen_remaining -= leftovers;
+ } else {
+ ctx.buffer
+ .copy_from_slice(&input[input.len() - DIGEST_BLOCK_SIZE..input.len()]);
+ ctx.buflen += DIGEST_BLOCK_SIZE;
+ ilen_remaining -= DIGEST_BLOCK_SIZE;
+ }
+
+ // Hash the remaining data.
+ self.accumulate(&input[input_start..input_start + ilen_remaining]).await;
+
+ // Save the peripheral context.
+ self.store_context(ctx);
+ }
+
+ /// Computes a digest for the given context.
+ /// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
+ /// The largest returned digest size is 128 bytes for SHA-512.
+ /// Panics if the supplied digest buffer is too short.
+ pub fn finish_blocking(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize {
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ // Hash the leftover bytes, if any.
+ self.accumulate_blocking(&ctx.buffer[0..ctx.buflen]);
+ ctx.buflen = 0;
+
+ //Start the digest calculation.
+ T::regs().str().write(|w| w.set_dcal(true));
+
+ // Block waiting for digest.
+ while !T::regs().sr().read().dcis() {}
+
+ // Return the digest.
+ let digest_words = match ctx.algo {
+ Algorithm::SHA1 => 5,
+ #[cfg(any(hash_v1, hash_v2, hash_v4))]
+ Algorithm::MD5 => 4,
+ Algorithm::SHA224 => 7,
+ Algorithm::SHA256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA384 => 12,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_224 => 7,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512 => 16,
+ };
+
+ let digest_len_bytes = digest_words * 4;
+ // Panics if the supplied digest buffer is too short.
+ if digest.len() < digest_len_bytes {
+ panic!("Digest buffer must be at least {} bytes long.", digest_words * 4);
+ }
+
+ let mut i = 0;
+ while i < digest_words {
+ let word = T::regs().hr(i).read();
+ digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
+ i += 1;
+ }
+ digest_len_bytes
+ }
+
+ /// Computes a digest for the given context.
+ /// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
+ /// The largest returned digest size is 128 bytes for SHA-512.
+ /// Panics if the supplied digest buffer is too short.
+ #[cfg(hash_v2)]
+ pub async fn finish(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize
+ where
+ D: crate::hash::Dma<T>,
+ {
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ // Must be cleared prior to the last DMA transfer.
+ T::regs().cr().modify(|w| w.set_mdmat(false));
+
+ // Hash the leftover bytes, if any.
+ self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
+ ctx.buflen = 0;
+
+ // Wait for completion.
+ poll_fn(|cx| {
+ // Check if already done.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ return Poll::Ready(());
+ }
+ // Register waker, then enable interrupts.
+ HASH_WAKER.register(cx.waker());
+ T::regs().imr().modify(|reg| reg.set_dcie(true));
+ // Check for completion.
+ let bits = T::regs().sr().read();
+ if bits.dcis() {
+ Poll::Ready(())
+ } else {
+ Poll::Pending
+ }
+ })
+ .await;
+
+ // Return the digest.
+ let digest_words = match ctx.algo {
+ Algorithm::SHA1 => 5,
+ #[cfg(any(hash_v1, hash_v2, hash_v4))]
+ Algorithm::MD5 => 4,
+ Algorithm::SHA224 => 7,
+ Algorithm::SHA256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA384 => 12,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_224 => 7,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512_256 => 8,
+ #[cfg(hash_v3)]
+ Algorithm::SHA512 => 16,
+ };
+
+ let digest_len_bytes = digest_words * 4;
+ // Panics if the supplied digest buffer is too short.
+ if digest.len() < digest_len_bytes {
+ panic!("Digest buffer must be at least {} bytes long.", digest_words * 4);
+ }
+
+ let mut i = 0;
+ while i < digest_words {
+ let word = T::regs().hr(i).read();
+ digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
+ i += 1;
+ }
+ digest_len_bytes
+ }
+
+ /// Push data into the hash core.
+ fn accumulate_blocking(&mut self, input: &[u8]) {
+ // Set the number of valid bits.
+ let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
+ T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
+
+ let mut i = 0;
+ while i < input.len() {
+ let mut word: [u8; 4] = [0; 4];
+ let copy_idx = min(i + 4, input.len());
+ word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
+ T::regs().din().write_value(u32::from_ne_bytes(word));
+ i += 4;
+ }
+ }
+
+ /// Push data into the hash core.
+ #[cfg(hash_v2)]
+ async fn accumulate(&mut self, input: &[u8])
+ where
+ D: crate::hash::Dma<T>,
+ {
+ // Ignore an input length of 0.
+ if input.len() == 0 {
+ return;
+ }
+
+ // Set the number of valid bits.
+ let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
+ T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
+
+ // Configure DMA to transfer input to hash core.
+ let dma_request = self.dma.request();
+ let dst_ptr = T::regs().din().as_ptr();
+ let mut num_words = input.len() / 4;
+ if input.len() % 4 > 0 {
+ num_words += 1;
+ }
+ let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
+ let dma_transfer =
+ unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) };
+ T::regs().cr().modify(|w| w.set_dmae(true));
+
+ // Wait for the transfer to complete.
+ dma_transfer.await;
+ }
+
+ /// Save the peripheral state to a context.
+ fn store_context(&mut self, ctx: &mut Context) {
+ // Block waiting for data in ready.
+ while !T::regs().sr().read().dinis() {}
+
+ // Store peripheral context.
+ ctx.imr = T::regs().imr().read().0;
+ ctx.str = T::regs().str().read().0;
+ ctx.cr = T::regs().cr().read().0;
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ ctx.csr[i] = T::regs().csr(i).read();
+ i += 1;
+ }
+ }
+
+ /// Restore the peripheral state from a context.
+ fn load_context(&mut self, ctx: &Context) {
+ // Restore the peripheral state from the context.
+ T::regs().imr().write_value(Imr { 0: ctx.imr });
+ T::regs().str().write_value(Str { 0: ctx.str });
+ T::regs().cr().write_value(Cr { 0: ctx.cr });
+ T::regs().cr().modify(|w| w.set_init(true));
+ let mut i = 0;
+ while i < NUM_CONTEXT_REGS {
+ T::regs().csr(i).write_value(ctx.csr[i]);
+ i += 1;
+ }
+ }
+}
+
+pub(crate) mod sealed {
+ use super::*;
+
+ pub trait Instance {
+ fn regs() -> pac::hash::Hash;
+ }
+}
+
+/// HASH instance trait.
+pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+ /// Interrupt for this HASH instance.
+ type Interrupt: interrupt::typelevel::Interrupt;
+}
+
+foreach_interrupt!(
+ ($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
+ impl Instance for peripherals::$inst {
+ type Interrupt = crate::interrupt::typelevel::$irq;
+ }
+
+ impl sealed::Instance for peripherals::$inst {
+ fn regs() -> crate::pac::hash::Hash {
+ crate::pac::$inst
+ }
+ }
+ };
+);
+
+dma_trait!(Dma, Instance);
diff --git a/embassy-stm32/src/hash/v1v3v4.rs b/embassy-stm32/src/hash/v1v3v4.rs
deleted file mode 100644
index 771144b11..000000000
--- a/embassy-stm32/src/hash/v1v3v4.rs
+++ /dev/null
@@ -1,399 +0,0 @@
-//! Hash generator (HASH)
-use core::cmp::min;
-use core::future::poll_fn;
-use core::marker::PhantomData;
-use core::task::Poll;
-
-use embassy_hal_internal::{into_ref, PeripheralRef};
-use embassy_sync::waitqueue::AtomicWaker;
-use stm32_metapac::hash::regs::*;
-
-use crate::interrupt::typelevel::Interrupt;
-use crate::peripherals::HASH;
-use crate::rcc::sealed::RccPeripheral;
-use crate::{interrupt, pac, peripherals, Peripheral};
-
-#[cfg(hash_v1)]
-const NUM_CONTEXT_REGS: usize = 51;
-#[cfg(hash_v3)]
-const NUM_CONTEXT_REGS: usize = 103;
-#[cfg(hash_v4)]
-const NUM_CONTEXT_REGS: usize = 54;
-
-const HASH_BUFFER_LEN: usize = 132;
-const DIGEST_BLOCK_SIZE: usize = 128;
-const MAX_DIGEST_SIZE: usize = 128;
-
-static HASH_WAKER: AtomicWaker = AtomicWaker::new();
-
-/// HASH interrupt handler.
-pub struct InterruptHandler<T: Instance> {
- _phantom: PhantomData<T>,
-}
-
-impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
- unsafe fn on_interrupt() {
- let bits = T::regs().sr().read();
- if bits.dinis() {
- T::regs().imr().modify(|reg| reg.set_dinie(false));
- HASH_WAKER.wake();
- }
- if bits.dcis() {
- T::regs().imr().modify(|reg| reg.set_dcie(false));
- HASH_WAKER.wake();
- }
- }
-}
-
-///Hash algorithm selection
-#[derive(Clone, Copy, PartialEq)]
-pub enum Algorithm {
- /// SHA-1 Algorithm
- SHA1 = 0,
-
- #[cfg(any(hash_v1, hash_v4))]
- /// MD5 Algorithm
- MD5 = 1,
-
- /// SHA-224 Algorithm
- SHA224 = 2,
-
- /// SHA-256 Algorithm
- SHA256 = 3,
-
- #[cfg(hash_v3)]
- /// SHA-384 Algorithm
- SHA384 = 12,
-
- #[cfg(hash_v3)]
- /// SHA-512/224 Algorithm
- SHA512_224 = 13,
-
- #[cfg(hash_v3)]
- /// SHA-512/256 Algorithm
- SHA512_256 = 14,
-
- #[cfg(hash_v3)]
- /// SHA-256 Algorithm
- SHA512 = 15,
-}
-
-/// Input data width selection
-#[repr(u8)]
-#[derive(Clone, Copy)]
-pub enum DataType {
- ///32-bit data, no data is swapped.
- Width32 = 0,
- ///16-bit data, each half-word is swapped.
- Width16 = 1,
- ///8-bit data, all bytes are swapped.
- Width8 = 2,
- ///1-bit data, all bits are swapped.
- Width1 = 3,
-}
-
-/// Stores the state of the HASH peripheral for suspending/resuming
-/// digest calculation.
-pub struct Context {
- first_word_sent: bool,
- buffer: [u8; HASH_BUFFER_LEN],
- buflen: usize,
- algo: Algorithm,
- format: DataType,
- imr: u32,
- str: u32,
- cr: u32,
- csr: [u32; NUM_CONTEXT_REGS],
-}
-
-/// HASH driver.
-pub struct Hash<'d, T: Instance> {
- _peripheral: PeripheralRef<'d, T>,
-}
-
-impl<'d, T: Instance> Hash<'d, T> {
- /// Instantiates, resets, and enables the HASH peripheral.
- pub fn new(
- peripheral: impl Peripheral<P = T> + 'd,
- _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
- ) -> Self {
- HASH::enable_and_reset();
- into_ref!(peripheral);
- let instance = Self {
- _peripheral: peripheral,
- };
-
- T::Interrupt::unpend();
- unsafe { T::Interrupt::enable() };
-
- instance
- }
-
- /// Starts computation of a new hash and returns the saved peripheral state.
- pub async fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
- // Define a context for this new computation.
- let mut ctx = Context {
- first_word_sent: false,
- buffer: [0; HASH_BUFFER_LEN],
- buflen: 0,
- algo: algorithm,
- format: format,
- imr: 0,
- str: 0,
- cr: 0,
- csr: [0; NUM_CONTEXT_REGS],
- };
-
- // Set the data type in the peripheral.
- T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
-
- // Select the algorithm.
- #[cfg(hash_v1)]
- if ctx.algo == Algorithm::MD5 {
- T::regs().cr().modify(|w| w.set_algo(true));
- }
-
- #[cfg(hash_v2)]
- {
- // Select the algorithm.
- let mut algo0 = false;
- let mut algo1 = false;
- if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
- algo0 = true;
- }
- if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
- algo1 = true;
- }
- T::regs().cr().modify(|w| w.set_algo0(algo0));
- T::regs().cr().modify(|w| w.set_algo1(algo1));
- }
-
- #[cfg(any(hash_v3, hash_v4))]
- T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
-
- T::regs().cr().modify(|w| w.set_init(true));
-
- // Store and return the state of the peripheral.
- self.store_context(&mut ctx).await;
- ctx
- }
-
- /// Restores the peripheral state using the given context,
- /// then updates the state with the provided data.
- /// Peripheral state is saved upon return.
- pub async fn update(&mut self, ctx: &mut Context, input: &[u8]) {
- let mut data_waiting = input.len() + ctx.buflen;
- if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
- // There isn't enough data to digest a block, so append it to the buffer.
- ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
- ctx.buflen += input.len();
- return;
- }
-
- // Restore the peripheral state.
- self.load_context(&ctx);
-
- let mut ilen_remaining = input.len();
- let mut input_start = 0;
-
- // Handle first block.
- if !ctx.first_word_sent {
- let empty_len = ctx.buffer.len() - ctx.buflen;
- let copy_len = min(empty_len, ilen_remaining);
- // Fill the buffer.
- if copy_len > 0 {
- ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[0..copy_len]);
- ctx.buflen += copy_len;
- ilen_remaining -= copy_len;
- input_start += copy_len;
- }
- self.accumulate(ctx.buffer.as_slice());
- data_waiting -= ctx.buflen;
- ctx.buflen = 0;
- ctx.first_word_sent = true;
- }
-
- if data_waiting < DIGEST_BLOCK_SIZE {
- // There isn't enough data remaining to process another block, so store it.
- ctx.buffer[0..ilen_remaining].copy_from_slice(&input[input_start..input_start + ilen_remaining]);
- ctx.buflen += ilen_remaining;
- } else {
- // First ingest the data in the buffer.
- let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
- if empty_len > 0 {
- let copy_len = min(empty_len, ilen_remaining);
- ctx.buffer[ctx.buflen..ctx.buflen + copy_len]
- .copy_from_slice(&input[input_start..input_start + copy_len]);
- ctx.buflen += copy_len;
- ilen_remaining -= copy_len;
- input_start += copy_len;
- }
- self.accumulate(&ctx.buffer[0..DIGEST_BLOCK_SIZE]);
- ctx.buflen = 0;
-
- // Move any extra data to the now-empty buffer.
- let leftovers = ilen_remaining % 64;
- if leftovers > 0 {
- ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
- ctx.buflen += leftovers;
- ilen_remaining -= leftovers;
- }
-
- // Hash the remaining data.
- self.accumulate(&input[input_start..input_start + ilen_remaining]);
- }
-
- // Save the peripheral context.
- self.store_context(ctx).await;
- }
-
- /// Computes a digest for the given context. A slice of the provided digest buffer is returned.
- /// The length of the returned slice is dependent on the digest length of the selected algorithm.
- pub async fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; MAX_DIGEST_SIZE]) -> &'a [u8] {
- // Restore the peripheral state.
- self.load_context(&ctx);
-
- // Hash the leftover bytes, if any.
- self.accumulate(&ctx.buffer[0..ctx.buflen]);
- ctx.buflen = 0;
-
- //Start the digest calculation.
- T::regs().str().write(|w| w.set_dcal(true));
-
- // Wait for completion.
- poll_fn(|cx| {
- // Check if already done.
- let bits = T::regs().sr().read();
- if bits.dcis() {
- return Poll::Ready(());
- }
- // Register waker, then enable interrupts.
- HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dcie(true));
- // Check for completion.
- let bits = T::regs().sr().read();
- if bits.dcis() {
- Poll::Ready(())
- } else {
- Poll::Pending
- }
- })
- .await;
-
- // Return the digest.
- let digest_words = match ctx.algo {
- Algorithm::SHA1 => 5,
- #[cfg(any(hash_v1, hash_v4))]
- Algorithm::MD5 => 4,
- Algorithm::SHA224 => 7,
- Algorithm::SHA256 => 8,
- #[cfg(hash_v3)]
- Algorithm::SHA384 => 12,
- #[cfg(hash_v3)]
- Algorithm::SHA512_224 => 7,
- #[cfg(hash_v3)]
- Algorithm::SHA512_256 => 8,
- #[cfg(hash_v3)]
- Algorithm::SHA512 => 16,
- };
- let mut i = 0;
- while i < digest_words {
- let word = T::regs().hr(i).read();
- digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
- i += 1;
- }
- &digest[0..digest_words * 4]
- }
-
- /// Push data into the hash core.
- fn accumulate(&mut self, input: &[u8]) {
- // Set the number of valid bits.
- let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
- T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
-
- let mut i = 0;
- while i < input.len() {
- let mut word: [u8; 4] = [0; 4];
- let copy_idx = min(i + 4, input.len());
- word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
- T::regs().din().write_value(u32::from_ne_bytes(word));
- i += 4;
- }
- }
-
- /// Save the peripheral state to a context.
- async fn store_context(&mut self, ctx: &mut Context) {
- // Wait for interrupt.
- poll_fn(|cx| {
- // Check if already done.
- let bits = T::regs().sr().read();
- if bits.dinis() {
- return Poll::Ready(());
- }
- // Register waker, then enable interrupts.
- HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dinie(true));
- // Check for completion.
- let bits = T::regs().sr().read();
- if bits.dinis() {
- Poll::Ready(())
- } else {
- Poll::Pending
- }
- })
- .await;
-
- ctx.imr = T::regs().imr().read().0;
- ctx.str = T::regs().str().read().0;
- ctx.cr = T::regs().cr().read().0;
- let mut i = 0;
- while i < NUM_CONTEXT_REGS {
- ctx.csr[i] = T::regs().csr(i).read();
- i += 1;
- }
- }
-
- /// Restore the peripheral state from a context.
- fn load_context(&mut self, ctx: &Context) {
- // Restore the peripheral state from the context.
- T::regs().imr().write_value(Imr { 0: ctx.imr });
- T::regs().str().write_value(Str { 0: ctx.str });
- T::regs().cr().write_value(Cr { 0: ctx.cr });
- T::regs().cr().modify(|w| w.set_init(true));
- let mut i = 0;
- while i < NUM_CONTEXT_REGS {
- T::regs().csr(i).write_value(ctx.csr[i]);
- i += 1;
- }
- }
-}
-
-pub(crate) mod sealed {
- use super::*;
-
- pub trait Instance {
- fn regs() -> pac::hash::Hash;
- }
-}
-
-/// HASH instance trait.
-pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
- /// Interrupt for this HASH instance.
- type Interrupt: interrupt::typelevel::Interrupt;
-}
-
-foreach_interrupt!(
- ($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
- impl Instance for peripherals::$inst {
- type Interrupt = crate::interrupt::typelevel::$irq;
- }
-
- impl sealed::Instance for peripherals::$inst {
- fn regs() -> crate::pac::hash::Hash {
- crate::pac::$inst
- }
- }
- };
-);
-
-dma_trait!(Dma, Instance);
diff --git a/embassy-stm32/src/hash/v2.rs b/embassy-stm32/src/hash/v2.rs
deleted file mode 100644
index b8104c825..000000000
--- a/embassy-stm32/src/hash/v2.rs
+++ /dev/null
@@ -1,389 +0,0 @@
-//! Hash generator (HASH)
-use core::cmp::min;
-use core::future::poll_fn;
-use core::marker::PhantomData;
-use core::ptr;
-use core::task::Poll;
-
-use embassy_hal_internal::{into_ref, PeripheralRef};
-use embassy_sync::waitqueue::AtomicWaker;
-use stm32_metapac::hash::regs::*;
-
-use crate::dma::Transfer;
-use crate::interrupt::typelevel::Interrupt;
-use crate::peripherals::HASH;
-use crate::rcc::sealed::RccPeripheral;
-use crate::{interrupt, pac, peripherals, Peripheral};
-
-#[cfg(hash_v2)]
-const NUM_CONTEXT_REGS: usize = 54;
-#[cfg(hash_v3)]
-const NUM_CONTEXT_REGS: usize = 103;
-const DIGEST_BLOCK_SIZE: usize = 64;
-const MAX_DIGEST_SIZE: usize = 64;
-
-static HASH_WAKER: AtomicWaker = AtomicWaker::new();
-
-/// HASH interrupt handler.
-pub struct InterruptHandler<T: Instance> {
- _phantom: PhantomData<T>,
-}
-
-impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
- unsafe fn on_interrupt() {
- let bits = T::regs().sr().read();
- if bits.dinis() {
- T::regs().imr().modify(|reg| reg.set_dinie(false));
- HASH_WAKER.wake();
- }
- if bits.dcis() {
- T::regs().imr().modify(|reg| reg.set_dcie(false));
- HASH_WAKER.wake();
- }
- }
-}
-
-///Hash algorithm selection
-#[derive(Clone, Copy, PartialEq)]
-pub enum Algorithm {
- /// SHA-1 Algorithm
- SHA1 = 0,
-
- #[cfg(hash_v2)]
- /// MD5 Algorithm
- MD5 = 1,
-
- /// SHA-224 Algorithm
- SHA224 = 2,
-
- /// SHA-256 Algorithm
- SHA256 = 3,
-
- #[cfg(hash_v3)]
- /// SHA-384 Algorithm
- SHA384 = 12,
-
- #[cfg(hash_v3)]
- /// SHA-512/224 Algorithm
- SHA512_224 = 13,
-
- #[cfg(hash_v3)]
- /// SHA-512/256 Algorithm
- SHA512_256 = 14,
-
- #[cfg(hash_v3)]
- /// SHA-256 Algorithm
- SHA512 = 15,
-}
-
-/// Input data width selection
-#[repr(u8)]
-#[derive(Clone, Copy)]
-pub enum DataType {
- ///32-bit data, no data is swapped.
- Width32 = 0,
- ///16-bit data, each half-word is swapped.
- Width16 = 1,
- ///8-bit data, all bytes are swapped.
- Width8 = 2,
- ///1-bit data, all bits are swapped.
- Width1 = 3,
-}
-
-/// Stores the state of the HASH peripheral for suspending/resuming
-/// digest calculation.
-pub struct Context {
- buffer: [u8; DIGEST_BLOCK_SIZE],
- buflen: usize,
- algo: Algorithm,
- format: DataType,
- imr: u32,
- str: u32,
- cr: u32,
- csr: [u32; NUM_CONTEXT_REGS],
-}
-
-/// HASH driver.
-pub struct Hash<'d, T: Instance, D: Dma<T>> {
- _peripheral: PeripheralRef<'d, T>,
- dma: PeripheralRef<'d, D>,
-}
-
-impl<'d, T: Instance, D: Dma<T>> Hash<'d, T, D> {
- /// Instantiates, resets, and enables the HASH peripheral.
- pub fn new(
- peripheral: impl Peripheral<P = T> + 'd,
- dma: impl Peripheral<P = D> + 'd,
- _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
- ) -> Self {
- HASH::enable_and_reset();
- into_ref!(peripheral, dma);
- let instance = Self {
- _peripheral: peripheral,
- dma: dma,
- };
-
- T::Interrupt::unpend();
- unsafe { T::Interrupt::enable() };
-
- instance
- }
-
- /// Starts computation of a new hash and returns the saved peripheral state.
- pub async fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
- // Define a context for this new computation.
- let mut ctx = Context {
- buffer: [0; DIGEST_BLOCK_SIZE],
- buflen: 0,
- algo: algorithm,
- format: format,
- imr: 0,
- str: 0,
- cr: 0,
- csr: [0; NUM_CONTEXT_REGS],
- };
-
- // Set the data type in the peripheral.
- T::regs().cr().modify(|w| w.set_datatype(ctx.format as u8));
-
- #[cfg(hash_v2)]
- {
- // Select the algorithm.
- let mut algo0 = false;
- let mut algo1 = false;
- if ctx.algo == Algorithm::MD5 || ctx.algo == Algorithm::SHA256 {
- algo0 = true;
- }
- if ctx.algo == Algorithm::SHA224 || ctx.algo == Algorithm::SHA256 {
- algo1 = true;
- }
- T::regs().cr().modify(|w| w.set_algo0(algo0));
- T::regs().cr().modify(|w| w.set_algo1(algo1));
- }
-
- #[cfg(hash_v3)]
- T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
-
- // Enable multiple DMA transfers.
- T::regs().cr().modify(|w| w.set_mdmat(true));
-
- // Set init to load the context registers. Necessary before storing context.
- T::regs().cr().modify(|w| w.set_init(true));
-
- // Store and return the state of the peripheral.
- self.store_context(&mut ctx).await;
- ctx
- }
-
- /// Restores the peripheral state using the given context,
- /// then updates the state with the provided data.
- /// Peripheral state is saved upon return.
- pub async fn update(&mut self, ctx: &mut Context, input: &[u8]) {
- let data_waiting = input.len() + ctx.buflen;
- if data_waiting < DIGEST_BLOCK_SIZE {
- // There isn't enough data to digest a block, so append it to the buffer.
- ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
- ctx.buflen += input.len();
- return;
- }
-
- // Restore the peripheral state.
- self.load_context(&ctx);
-
- let mut ilen_remaining = input.len();
- let mut input_start = 0;
-
- // First ingest the data in the buffer.
- let empty_len = DIGEST_BLOCK_SIZE - ctx.buflen;
- if empty_len > 0 {
- let copy_len = min(empty_len, ilen_remaining);
- ctx.buffer[ctx.buflen..ctx.buflen + copy_len].copy_from_slice(&input[input_start..input_start + copy_len]);
- ctx.buflen += copy_len;
- ilen_remaining -= copy_len;
- input_start += copy_len;
- }
- self.accumulate(&ctx.buffer).await;
- ctx.buflen = 0;
-
- // Move any extra data to the now-empty buffer.
- let leftovers = ilen_remaining % DIGEST_BLOCK_SIZE;
- if leftovers > 0 {
- assert!(ilen_remaining >= leftovers);
- ctx.buffer[0..leftovers].copy_from_slice(&input[input.len() - leftovers..input.len()]);
- ctx.buflen += leftovers;
- ilen_remaining -= leftovers;
- } else {
- ctx.buffer
- .copy_from_slice(&input[input.len() - DIGEST_BLOCK_SIZE..input.len()]);
- ctx.buflen += DIGEST_BLOCK_SIZE;
- ilen_remaining -= DIGEST_BLOCK_SIZE;
- }
-
- // Hash the remaining data.
- self.accumulate(&input[input_start..input_start + ilen_remaining]).await;
-
- // Save the peripheral context.
- self.store_context(ctx).await;
- }
-
- /// Computes a digest for the given context. A slice of the provided digest buffer is returned.
- /// The length of the returned slice is dependent on the digest length of the selected algorithm.
- pub async fn finish<'a>(&mut self, mut ctx: Context, digest: &'a mut [u8; MAX_DIGEST_SIZE]) -> &'a [u8] {
- // Restore the peripheral state.
- self.load_context(&ctx);
-
- // Must be cleared prior to the last DMA transfer.
- T::regs().cr().modify(|w| w.set_mdmat(false));
-
- // Hash the leftover bytes, if any.
- self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
- ctx.buflen = 0;
-
- // Wait for completion.
- poll_fn(|cx| {
- // Check if already done.
- let bits = T::regs().sr().read();
- if bits.dcis() {
- return Poll::Ready(());
- }
- // Register waker, then enable interrupts.
- HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dcie(true));
- // Check for completion.
- let bits = T::regs().sr().read();
- if bits.dcis() {
- Poll::Ready(())
- } else {
- Poll::Pending
- }
- })
- .await;
-
- // Return the digest.
- let digest_words = match ctx.algo {
- Algorithm::SHA1 => 5,
- #[cfg(hash_v2)]
- Algorithm::MD5 => 4,
- Algorithm::SHA224 => 7,
- Algorithm::SHA256 => 8,
- #[cfg(hash_v3)]
- Algorithm::SHA384 => 12,
- #[cfg(hash_v3)]
- Algorithm::SHA512_224 => 7,
- #[cfg(hash_v3)]
- Algorithm::SHA512_256 => 8,
- #[cfg(hash_v3)]
- Algorithm::SHA512 => 16,
- };
- let mut i = 0;
- while i < digest_words {
- let word = T::regs().hr(i).read();
- digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
- i += 1;
- }
- &digest[0..digest_words * 4]
- }
-
- /// Push data into the hash core.
- async fn accumulate(&mut self, input: &[u8]) {
- // Ignore an input length of 0.
- if input.len() == 0 {
- return;
- }
-
- // Set the number of valid bits.
- let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
- T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
-
- // Configure DMA to transfer input to hash core.
- let dma_request = self.dma.request();
- let dst_ptr = T::regs().din().as_ptr();
- let mut num_words = input.len() / 4;
- if input.len() % 4 > 0 {
- num_words += 1;
- }
- let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
- let dma_transfer =
- unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) };
- T::regs().cr().modify(|w| w.set_dmae(true));
-
- // Wait for the transfer to complete.
- dma_transfer.await;
- }
-
- /// Save the peripheral state to a context.
- async fn store_context(&mut self, ctx: &mut Context) {
- // Wait for interrupt.
- poll_fn(|cx| {
- // Check if already done.
- let bits = T::regs().sr().read();
- if bits.dinis() {
- return Poll::Ready(());
- }
- // Register waker, then enable interrupts.
- HASH_WAKER.register(cx.waker());
- T::regs().imr().modify(|reg| reg.set_dinie(true));
- // Check for completion.
- let bits = T::regs().sr().read();
- if bits.dinis() {
- Poll::Ready(())
- } else {
- Poll::Pending
- }
- })
- .await;
-
- ctx.imr = T::regs().imr().read().0;
- ctx.str = T::regs().str().read().0;
- ctx.cr = T::regs().cr().read().0;
- let mut i = 0;
- while i < NUM_CONTEXT_REGS {
- ctx.csr[i] = T::regs().csr(i).read();
- i += 1;
- }
- }
-
- /// Restore the peripheral state from a context.
- fn load_context(&mut self, ctx: &Context) {
- // Restore the peripheral state from the context.
- T::regs().imr().write_value(Imr { 0: ctx.imr });
- T::regs().str().write_value(Str { 0: ctx.str });
- T::regs().cr().write_value(Cr { 0: ctx.cr });
- T::regs().cr().modify(|w| w.set_init(true));
- let mut i = 0;
- while i < NUM_CONTEXT_REGS {
- T::regs().csr(i).write_value(ctx.csr[i]);
- i += 1;
- }
- }
-}
-
-pub(crate) mod sealed {
- use super::*;
-
- pub trait Instance {
- fn regs() -> pac::hash::Hash;
- }
-}
-
-/// HASH instance trait.
-pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
- /// Interrupt for this HASH instance.
- type Interrupt: interrupt::typelevel::Interrupt;
-}
-
-foreach_interrupt!(
- ($inst:ident, hash, HASH, GLOBAL, $irq:ident) => {
- impl Instance for peripherals::$inst {
- type Interrupt = crate::interrupt::typelevel::$irq;
- }
-
- impl sealed::Instance for peripherals::$inst {
- fn regs() -> crate::pac::hash::Hash {
- crate::pac::$inst
- }
- }
- };
-);
-
-dma_trait!(Dma, Instance);
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index 7d96bd49c..31f8d32a7 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -3,7 +3,7 @@
use defmt::info;
use embassy_executor::Spawner;
-use embassy_stm32::{bind_interrupts, Config, hash, hash::*, peripherals};
+use embassy_stm32::{bind_interrupts, hash, hash::*, peripherals, Config};
use embassy_time::Instant;
use sha2::{Digest, Sha256};
use {defmt_rtt as _, panic_probe as _};
@@ -25,11 +25,11 @@ async fn main(_spawner: Spawner) -> ! {
let hw_start_time = Instant::now();
// Compute a digest in hardware.
- let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
+ let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
hw_hasher.update(&mut context, test_1).await;
hw_hasher.update(&mut context, test_2).await;
- let mut buffer: [u8; 64] = [0; 64];
- let hw_digest = hw_hasher.finish(context, &mut buffer).await;
+ let mut hw_digest: [u8; 32] = [0; 32];
+ hw_hasher.finish(context, &mut hw_digest).await;
let hw_end_time = Instant::now();
let hw_execution_time = hw_end_time - hw_start_time;
@@ -49,7 +49,7 @@ async fn main(_spawner: Spawner) -> ! {
info!("Software Digest: {:?}", sw_digest[..]);
info!("Hardware Execution Time: {:?}", hw_execution_time);
info!("Software Execution Time: {:?}", sw_execution_time);
- assert_eq!(*hw_digest, sw_digest[..]);
+ assert_eq!(hw_digest, sw_digest[..]);
loop {}
}
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index d02f1a253..fc4420687 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -26,7 +26,7 @@ stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng", "hash"
stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"]
stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash"]
stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng", "hash"]
-stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng", "hash"]
+stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"]
stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 2867115dc..cfcf3d976 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -6,6 +6,7 @@
mod common;
use common::*;
use embassy_executor::Spawner;
+use embassy_stm32::dma::NoDma;
use embassy_stm32::hash::*;
use embassy_stm32::{bind_interrupts, hash, peripherals};
use sha2::{Digest, Sha224, Sha256};
@@ -30,27 +31,26 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
- let dma = peri!(p, HASH_DMA);
- let mut hw_hasher = Hash::new(p.HASH, dma);
+ let mut hw_hasher = Hash::new(p.HASH, NoDma, Irqs);
let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
// Start an SHA-256 digest.
- let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
- hw_hasher.update(&mut sha256context, test_1).await;
+ let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
+ hw_hasher.update_blocking(&mut sha256context, test_1);
// Interrupt the SHA-256 digest to compute an SHA-224 digest.
- let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8).await;
- hw_hasher.update(&mut sha224context, test_3).await;
- let mut sha224_digest_buffer: [u8; 64] = [0; 64];
- let sha224_digest = hw_hasher.finish(sha224context, &mut sha224_digest_buffer).await;
+ let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8);
+ hw_hasher.update_blocking(&mut sha224context, test_3);
+ let mut sha224_digest_buffer: [u8; 28] = [0; 28];
+ let _ = hw_hasher.finish_blocking(sha224context, &mut sha224_digest_buffer);
// Finish the SHA-256 digest.
- hw_hasher.update(&mut sha256context, test_2).await;
- let mut sha_256_digest_buffer: [u8; 64] = [0; 64];
- let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await;
+ hw_hasher.update_blocking(&mut sha256context, test_2);
+ let mut sha256_digest_buffer: [u8; 32] = [0; 32];
+ let _ = hw_hasher.finish_blocking(sha256context, &mut sha256_digest_buffer);
// Compute the SHA-256 digest in software.
let mut sw_sha256_hasher = Sha256::new();
@@ -64,14 +64,14 @@ async fn main(_spawner: Spawner) {
let sw_sha224_digest = sw_sha224_hasher.finalize();
// Compare the SHA-256 digests.
- info!("Hardware SHA-256 Digest: {:?}", sha256_digest);
+ info!("Hardware SHA-256 Digest: {:?}", sha256_digest_buffer);
info!("Software SHA-256 Digest: {:?}", sw_sha256_digest[..]);
- defmt::assert!(*sha256_digest == sw_sha256_digest[..]);
+ defmt::assert!(sha256_digest_buffer == sw_sha256_digest[..]);
// Compare the SHA-224 digests.
- info!("Hardware SHA-256 Digest: {:?}", sha224_digest);
+ info!("Hardware SHA-256 Digest: {:?}", sha224_digest_buffer);
info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
- defmt::assert!(*sha224_digest == sw_sha224_digest[..]);
+ defmt::assert!(sha224_digest_buffer == sw_sha224_digest[..]);
info!("Test OK");
cortex_m::asm::bkpt();
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 14d5b6d7b..fefe72c86 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -128,7 +128,6 @@ define_peris!(
);
#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
define_peris!(
- HASH_DMA = DMA1_CH0,
UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
@@ -142,21 +141,18 @@ define_peris!(
);
#[cfg(feature = "stm32u585ai")]
define_peris!(
- HASH_DMA = GPDMA1_CH0,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
);
#[cfg(feature = "stm32u5a5zj")]
define_peris!(
- HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PG7, UART_RX = PG8, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
);
#[cfg(feature = "stm32h563zi")]
define_peris!(
- HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
@@ -175,7 +171,6 @@ define_peris!(
);
#[cfg(feature = "stm32l4a6zg")]
define_peris!(
- HASH_DMA = DMA2_CH7,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -201,7 +196,6 @@ define_peris!(
);
#[cfg(feature = "stm32l552ze")]
define_peris!(
- HASH_DMA = DMA1_CH1,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -232,7 +226,6 @@ define_peris!(
);
#[cfg(feature = "stm32wba52cg")]
define_peris!(
- HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
From 7bf044278e8c85b5ea6dbe3de6b3cdea884c995a Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 11 Feb 2024 11:47:38 -0500
Subject: [PATCH 186/392] fmt
---
examples/stm32f7/src/bin/hash.rs | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index 31f8d32a7..96e50f84b 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -3,7 +3,8 @@
use defmt::info;
use embassy_executor::Spawner;
-use embassy_stm32::{bind_interrupts, hash, hash::*, peripherals, Config};
+use embassy_stm32::hash::*;
+use embassy_stm32::{bind_interrupts, hash, peripherals, Config};
use embassy_time::Instant;
use sha2::{Digest, Sha256};
use {defmt_rtt as _, panic_probe as _};
From 8f7d80f9f71e55ffe97b72dbb361409aee003ea4 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Sun, 11 Feb 2024 19:37:48 +0100
Subject: [PATCH 187/392] Revert "feat(boot): introduce non-erase flash write
method "
This reverts commit 2e8b7d259057a0cf345396b250cacfc04a0e64a0.
---
embassy-boot/src/firmware_updater/blocking.rs | 35 -------------------
1 file changed, 35 deletions(-)
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index 3e83366af..4044871f0 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -225,41 +225,6 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
Ok(())
}
- /// Write data directly to a flash page without erasing it first.
- ///
- /// This function writes the provided data to the specified offset in the flash memory,
- /// without performing an erase operation beforehand. It is crucial that the area being
- /// written to is either already erased.
- /// This method is intended to be used in conjunction with the `prepare_update` method.
- ///
- /// The buffer must follow the alignment requirements of the target flash and be a multiple of
- /// the page size. This is essential to ensure data integrity and prevent corruption.
- ///
- /// # Safety
- ///
- /// This function requires careful management of the memory being written to. Writing to a
- /// non-erased page or not adhering to alignment and size requirements may result in a panic.
- ///
- /// Ensure that the data being written is compatible with the current contents of the flash
- /// memory, as no erase operation will be performed to reset the page content to a default state.
- ///
- /// # Parameters
- ///
- /// - `offset`: The offset within the DFU partition where the data will be written. Must be
- /// aligned according to the flash's requirements and within the writable memory range.
- /// - `data`: A reference to the slice of bytes to be written. The length of the data must not
- /// exceed the partition size and must follow the flash's alignment requirements.
- ///
- /// # Returns
- ///
- /// A result indicating the success or failure of the write operation. On success, returns `Ok(())`.
- /// On failure, returns an `Err` with a `FirmwareUpdaterError` detailing the cause of the failure.
- pub fn write_firmware_without_erase(&mut self, offset: usize, data: &[u8]) -> Result<(), FirmwareUpdaterError> {
- self.dfu.write(offset as u32, data)?;
-
- Ok(())
- }
-
/// Prepare for an incoming DFU update by erasing the entire DFU area and
/// returning its `Partition`.
///
From 72ab04c45335ceb725076a38a252749e781a8cf6 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Sun, 11 Feb 2024 19:38:01 +0100
Subject: [PATCH 188/392] Revert "feat(usb-dfu): change usb dfu chunks write
mechanism "
This reverts commit c95bf6895adfcd33b5238c02620e83c6713205ce.
---
embassy-usb-dfu/src/dfu.rs | 17 +----------------
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/embassy-usb-dfu/src/dfu.rs b/embassy-usb-dfu/src/dfu.rs
index 5f2c98684..e99aa70c3 100644
--- a/embassy-usb-dfu/src/dfu.rs
+++ b/embassy-usb-dfu/src/dfu.rs
@@ -60,21 +60,6 @@ impl<'d, DFU: NorFlash, STATE: NorFlash, RST: Reset, const BLOCK_SIZE: usize> Ha
}
Ok(Request::Dnload) if self.attrs.contains(DfuAttributes::CAN_DOWNLOAD) => {
if req.value == 0 {
- match self.updater.prepare_update() {
- Ok(_) => {
- self.status = Status::Ok;
- }
- Err(e) => {
- self.state = State::Error;
- match e {
- embassy_boot::FirmwareUpdaterError::Flash(e) => match e {
- NorFlashErrorKind::NotAligned => self.status = Status::ErrErase,
- _ => self.status = Status::ErrUnknown,
- },
- _ => self.status = Status::ErrUnknown,
- }
- }
- }
self.state = State::Download;
self.offset = 0;
}
@@ -108,7 +93,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash, RST: Reset, const BLOCK_SIZE: usize> Ha
self.state = State::Error;
return Some(OutResponse::Rejected);
}
- match self.updater.write_firmware_without_erase(self.offset, buf.as_ref()) {
+ match self.updater.write_firmware(self.offset, buf.as_ref()) {
Ok(_) => {
self.status = Status::Ok;
self.state = State::DlSync;
From eb3bd39b068ae34892520ec38f111704ea357355 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Sun, 11 Feb 2024 20:02:28 +0100
Subject: [PATCH 189/392] feat(boot): enhance firmware write functionality
---
embassy-boot/src/firmware_updater/asynch.rs | 71 ++++++++++++++++---
embassy-boot/src/firmware_updater/blocking.rs | 70 +++++++++++++++---
2 files changed, 124 insertions(+), 17 deletions(-)
diff --git a/embassy-boot/src/firmware_updater/asynch.rs b/embassy-boot/src/firmware_updater/asynch.rs
index 668f16f16..99a3aa246 100644
--- a/embassy-boot/src/firmware_updater/asynch.rs
+++ b/embassy-boot/src/firmware_updater/asynch.rs
@@ -172,21 +172,69 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
self.state.mark_booted().await
}
- /// Write data to a flash page.
+ /// Writes firmware data to the device.
///
- /// The buffer must follow alignment requirements of the target flash and a multiple of page size big.
+ /// This function writes the given data to the firmware area starting at the specified offset.
+ /// It handles sector erasures and data writes while verifying the device is in a proper state
+ /// for firmware updates. The function ensures that only unerased sectors are erased before
+ /// writing and efficiently handles the writing process across sector boundaries and in
+ /// various configurations (data size, page size, etc.).
///
- /// # Safety
+ /// # Arguments
///
- /// Failing to meet alignment and size requirements may result in a panic.
+ /// * `offset` - The starting offset within the firmware area where data writing should begin.
+ /// * `data` - A slice of bytes representing the firmware data to be written. It must be a
+ /// multiple of NorFlash WRITE_SIZE.
+ ///
+ /// # Returns
+ ///
+ /// A `Result<(), FirmwareUpdaterError>` indicating the success or failure of the write operation.
+ ///
+ /// # Errors
+ ///
+ /// This function will return an error if:
+ ///
+ /// - The device is not in a proper state to receive firmware updates (e.g., not booted).
+ /// - There is a failure erasing a sector before writing.
+ /// - There is a failure writing data to the device.
pub async fn write_firmware(&mut self, offset: usize, data: &[u8]) -> Result<(), FirmwareUpdaterError> {
- assert!(data.len() >= DFU::ERASE_SIZE);
-
+ // Make sure we are running a booted firmware to avoid reverting to a bad state.
self.state.verify_booted().await?;
- self.dfu.erase(offset as u32, (offset + data.len()) as u32).await?;
+ // Initialize variables to keep track of the remaining data and the current offset.
+ let mut remaining_data = data;
+ let mut offset = offset;
- self.dfu.write(offset as u32, data).await?;
+ // Continue writing as long as there is data left to write.
+ while !remaining_data.is_empty() {
+ // Compute the current sector and its boundaries.
+ let current_sector = offset / DFU::ERASE_SIZE;
+ let sector_start = current_sector * DFU::ERASE_SIZE;
+ let sector_end = sector_start + DFU::ERASE_SIZE;
+ // Determine if the current sector needs to be erased before writing.
+ let need_erase = self
+ .state
+ .last_erased_dfu_page_index
+ .map_or(true, |last_erased_sector| current_sector != last_erased_sector);
+
+ // If the sector needs to be erased, erase it and update the last erased sector index.
+ if need_erase {
+ self.dfu.erase(sector_start as u32, sector_end as u32).await?;
+ self.state.last_erased_dfu_page_index = Some(current_sector);
+ }
+
+ // Calculate the size of the data chunk that can be written in the current iteration.
+ let write_size = core::cmp::min(remaining_data.len(), sector_end - offset);
+ // Split the data to get the current chunk to be written and the remaining data.
+ let (data_chunk, rest) = remaining_data.split_at(write_size);
+
+ // Write the current data chunk.
+ self.dfu.write(offset as u32, data_chunk).await?;
+
+ // Update the offset and remaining data for the next iteration.
+ remaining_data = rest;
+ offset += write_size;
+ }
Ok(())
}
@@ -210,6 +258,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
pub struct FirmwareState<'d, STATE> {
state: STATE,
aligned: &'d mut [u8],
+ last_erased_dfu_page_index: Option<usize>,
}
impl<'d, STATE: NorFlash> FirmwareState<'d, STATE> {
@@ -231,7 +280,11 @@ impl<'d, STATE: NorFlash> FirmwareState<'d, STATE> {
/// and follow the alignment rules for the flash being read from and written to.
pub fn new(state: STATE, aligned: &'d mut [u8]) -> Self {
assert_eq!(aligned.len(), STATE::WRITE_SIZE.max(STATE::READ_SIZE));
- Self { state, aligned }
+ Self {
+ state,
+ aligned,
+ last_erased_dfu_page_index: None,
+ }
}
// Make sure we are running a booted firmware to avoid reverting to a bad state.
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index 4044871f0..45ae966f3 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -207,20 +207,69 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
self.state.mark_booted()
}
- /// Write data to a flash page.
+ /// Writes firmware data to the device.
///
- /// The buffer must follow alignment requirements of the target flash and a multiple of page size big.
+ /// This function writes the given data to the firmware area starting at the specified offset.
+ /// It handles sector erasures and data writes while verifying the device is in a proper state
+ /// for firmware updates. The function ensures that only unerased sectors are erased before
+ /// writing and efficiently handles the writing process across sector boundaries and in
+ /// various configurations (data size, page size, etc.).
///
- /// # Safety
+ /// # Arguments
///
- /// Failing to meet alignment and size requirements may result in a panic.
+ /// * `offset` - The starting offset within the firmware area where data writing should begin.
+ /// * `data` - A slice of bytes representing the firmware data to be written. It must be a
+ /// multiple of NorFlash WRITE_SIZE.
+ ///
+ /// # Returns
+ ///
+ /// A `Result<(), FirmwareUpdaterError>` indicating the success or failure of the write operation.
+ ///
+ /// # Errors
+ ///
+ /// This function will return an error if:
+ ///
+ /// - The device is not in a proper state to receive firmware updates (e.g., not booted).
+ /// - There is a failure erasing a sector before writing.
+ /// - There is a failure writing data to the device.
pub fn write_firmware(&mut self, offset: usize, data: &[u8]) -> Result<(), FirmwareUpdaterError> {
- assert!(data.len() >= DFU::ERASE_SIZE);
+ // Make sure we are running a booted firmware to avoid reverting to a bad state.
self.state.verify_booted()?;
- self.dfu.erase(offset as u32, (offset + data.len()) as u32)?;
+ // Initialize variables to keep track of the remaining data and the current offset.
+ let mut remaining_data = data;
+ let mut offset = offset;
- self.dfu.write(offset as u32, data)?;
+ // Continue writing as long as there is data left to write.
+ while !remaining_data.is_empty() {
+ // Compute the current sector and its boundaries.
+ let current_sector = offset / DFU::ERASE_SIZE;
+ let sector_start = current_sector * DFU::ERASE_SIZE;
+ let sector_end = sector_start + DFU::ERASE_SIZE;
+ // Determine if the current sector needs to be erased before writing.
+ let need_erase = self
+ .state
+ .last_erased_dfu_page_index
+ .map_or(true, |last_erased_sector| current_sector != last_erased_sector);
+
+ // If the sector needs to be erased, erase it and update the last erased sector index.
+ if need_erase {
+ self.dfu.erase(sector_start as u32, sector_end as u32)?;
+ self.state.last_erased_dfu_page_index = Some(current_sector);
+ }
+
+ // Calculate the size of the data chunk that can be written in the current iteration.
+ let write_size = core::cmp::min(remaining_data.len(), sector_end - offset);
+ // Split the data to get the current chunk to be written and the remaining data.
+ let (data_chunk, rest) = remaining_data.split_at(write_size);
+
+ // Write the current data chunk.
+ self.dfu.write(offset as u32, data_chunk)?;
+
+ // Update the offset and remaining data for the next iteration.
+ remaining_data = rest;
+ offset += write_size;
+ }
Ok(())
}
@@ -244,6 +293,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
pub struct BlockingFirmwareState<'d, STATE> {
state: STATE,
aligned: &'d mut [u8],
+ last_erased_dfu_page_index: Option<usize>,
}
impl<'d, STATE: NorFlash> BlockingFirmwareState<'d, STATE> {
@@ -265,7 +315,11 @@ impl<'d, STATE: NorFlash> BlockingFirmwareState<'d, STATE> {
/// and written to.
pub fn new(state: STATE, aligned: &'d mut [u8]) -> Self {
assert_eq!(aligned.len(), STATE::WRITE_SIZE);
- Self { state, aligned }
+ Self {
+ state,
+ aligned,
+ last_erased_dfu_page_index: None,
+ }
}
// Make sure we are running a booted firmware to avoid reverting to a bad state.
From 333b2afe6d5319317b2679e634c3cf242bab0e73 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Sun, 11 Feb 2024 20:17:15 +0100
Subject: [PATCH 190/392] test(boot): add various write firmware test
configurations
---
embassy-boot/src/firmware_updater/asynch.rs | 72 +++++++++++++++++
embassy-boot/src/firmware_updater/blocking.rs | 78 +++++++++++++++++++
2 files changed, 150 insertions(+)
diff --git a/embassy-boot/src/firmware_updater/asynch.rs b/embassy-boot/src/firmware_updater/asynch.rs
index 99a3aa246..d31eff005 100644
--- a/embassy-boot/src/firmware_updater/asynch.rs
+++ b/embassy-boot/src/firmware_updater/asynch.rs
@@ -382,4 +382,76 @@ mod tests {
assert_eq!(Sha1::digest(update).as_slice(), hash);
}
+
+ #[test]
+ fn can_verify_sha1_page_bigger_than_chunk() {
+ let flash = Mutex::<NoopRawMutex, _>::new(MemFlash::<131072, 4096, 8>::default());
+ let state = Partition::new(&flash, 0, 4096);
+ let dfu = Partition::new(&flash, 65536, 65536);
+ let mut aligned = [0; 8];
+
+ let update = [0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66];
+ let mut to_write = [0; 4096];
+ to_write[..7].copy_from_slice(update.as_slice());
+
+ let mut updater = FirmwareUpdater::new(FirmwareUpdaterConfig { dfu, state }, &mut aligned);
+ let mut offset = 0;
+ for chunk in to_write.chunks(1024) {
+ block_on(updater.write_firmware(offset, chunk)).unwrap();
+ offset += chunk.len();
+ }
+ let mut chunk_buf = [0; 2];
+ let mut hash = [0; 20];
+ block_on(updater.hash::<Sha1>(update.len() as u32, &mut chunk_buf, &mut hash)).unwrap();
+
+ assert_eq!(Sha1::digest(update).as_slice(), hash);
+ }
+
+ #[test]
+ fn can_verify_sha1_page_smaller_than_chunk() {
+ let flash = Mutex::<NoopRawMutex, _>::new(MemFlash::<131072, 1024, 8>::default());
+ let state = Partition::new(&flash, 0, 4096);
+ let dfu = Partition::new(&flash, 65536, 65536);
+ let mut aligned = [0; 8];
+
+ let update = [0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66];
+ let mut to_write = [0; 4096];
+ to_write[..7].copy_from_slice(update.as_slice());
+
+ let mut updater = FirmwareUpdater::new(FirmwareUpdaterConfig { dfu, state }, &mut aligned);
+ let mut offset = 0;
+ for chunk in to_write.chunks(2048) {
+ block_on(updater.write_firmware(offset, chunk)).unwrap();
+ offset += chunk.len();
+ }
+ let mut chunk_buf = [0; 2];
+ let mut hash = [0; 20];
+ block_on(updater.hash::<Sha1>(update.len() as u32, &mut chunk_buf, &mut hash)).unwrap();
+
+ assert_eq!(Sha1::digest(update).as_slice(), hash);
+ }
+
+ #[test]
+ fn can_verify_sha1_cross_page_boundary() {
+ let flash = Mutex::<NoopRawMutex, _>::new(MemFlash::<131072, 1024, 8>::default());
+ let state = Partition::new(&flash, 0, 4096);
+ let dfu = Partition::new(&flash, 65536, 65536);
+ let mut aligned = [0; 8];
+
+ let update = [0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66];
+ let mut to_write = [0; 4096];
+ to_write[..7].copy_from_slice(update.as_slice());
+
+ let mut updater = FirmwareUpdater::new(FirmwareUpdaterConfig { dfu, state }, &mut aligned);
+ let mut offset = 0;
+ for chunk in to_write.chunks(896) {
+ block_on(updater.write_firmware(offset, chunk)).unwrap();
+ offset += chunk.len();
+ }
+ let mut chunk_buf = [0; 2];
+ let mut hash = [0; 20];
+ block_on(updater.hash::<Sha1>(update.len() as u32, &mut chunk_buf, &mut hash)).unwrap();
+
+ assert_eq!(Sha1::digest(update).as_slice(), hash);
+ }
}
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index 45ae966f3..5b8076f81 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -422,4 +422,82 @@ mod tests {
assert_eq!(Sha1::digest(update).as_slice(), hash);
}
+
+ #[test]
+ fn can_verify_sha1_page_bigger_than_chunk() {
+ let flash = Mutex::<NoopRawMutex, _>::new(RefCell::new(MemFlash::<131072, 4096, 8>::default()));
+ let state = BlockingPartition::new(&flash, 0, 4096);
+ let dfu = BlockingPartition::new(&flash, 65536, 65536);
+ let mut aligned = [0; 8];
+
+ let update = [0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66];
+ let mut to_write = [0; 4096];
+ to_write[..7].copy_from_slice(update.as_slice());
+
+ let mut updater = BlockingFirmwareUpdater::new(FirmwareUpdaterConfig { dfu, state }, &mut aligned);
+ let mut offset = 0;
+ for chunk in to_write.chunks(1024) {
+ updater.write_firmware(offset, chunk).unwrap();
+ offset += chunk.len();
+ }
+ let mut chunk_buf = [0; 2];
+ let mut hash = [0; 20];
+ updater
+ .hash::<Sha1>(update.len() as u32, &mut chunk_buf, &mut hash)
+ .unwrap();
+
+ assert_eq!(Sha1::digest(update).as_slice(), hash);
+ }
+
+ #[test]
+ fn can_verify_sha1_page_smaller_than_chunk() {
+ let flash = Mutex::<NoopRawMutex, _>::new(RefCell::new(MemFlash::<131072, 1024, 8>::default()));
+ let state = BlockingPartition::new(&flash, 0, 4096);
+ let dfu = BlockingPartition::new(&flash, 65536, 65536);
+ let mut aligned = [0; 8];
+
+ let update = [0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66];
+ let mut to_write = [0; 4096];
+ to_write[..7].copy_from_slice(update.as_slice());
+
+ let mut updater = BlockingFirmwareUpdater::new(FirmwareUpdaterConfig { dfu, state }, &mut aligned);
+ let mut offset = 0;
+ for chunk in to_write.chunks(2048) {
+ updater.write_firmware(offset, chunk).unwrap();
+ offset += chunk.len();
+ }
+ let mut chunk_buf = [0; 2];
+ let mut hash = [0; 20];
+ updater
+ .hash::<Sha1>(update.len() as u32, &mut chunk_buf, &mut hash)
+ .unwrap();
+
+ assert_eq!(Sha1::digest(update).as_slice(), hash);
+ }
+
+ #[test]
+ fn can_verify_sha1_cross_page_boundary() {
+ let flash = Mutex::<NoopRawMutex, _>::new(RefCell::new(MemFlash::<131072, 1024, 8>::default()));
+ let state = BlockingPartition::new(&flash, 0, 4096);
+ let dfu = BlockingPartition::new(&flash, 65536, 65536);
+ let mut aligned = [0; 8];
+
+ let update = [0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66];
+ let mut to_write = [0; 4096];
+ to_write[..7].copy_from_slice(update.as_slice());
+
+ let mut updater = BlockingFirmwareUpdater::new(FirmwareUpdaterConfig { dfu, state }, &mut aligned);
+ let mut offset = 0;
+ for chunk in to_write.chunks(896) {
+ updater.write_firmware(offset, chunk).unwrap();
+ offset += chunk.len();
+ }
+ let mut chunk_buf = [0; 2];
+ let mut hash = [0; 20];
+ updater
+ .hash::<Sha1>(update.len() as u32, &mut chunk_buf, &mut hash)
+ .unwrap();
+
+ assert_eq!(Sha1::digest(update).as_slice(), hash);
+ }
}
From 58fa5e57b67935d2a81f4fd708d6829afb8112b0 Mon Sep 17 00:00:00 2001
From: Mick Chanthaseth <mchant@users.noreply.github.com>
Date: Sun, 11 Feb 2024 16:04:06 -0800
Subject: [PATCH 191/392] added usb_hid_mouse example for rp
---
examples/rp/src/bin/usb_hid_mouse.rs | 183 +++++++++++++++++++++++++++
1 file changed, 183 insertions(+)
create mode 100644 examples/rp/src/bin/usb_hid_mouse.rs
diff --git a/examples/rp/src/bin/usb_hid_mouse.rs b/examples/rp/src/bin/usb_hid_mouse.rs
new file mode 100644
index 000000000..ec125a47e
--- /dev/null
+++ b/examples/rp/src/bin/usb_hid_mouse.rs
@@ -0,0 +1,183 @@
+#![no_std]
+#![no_main]
+
+use core::sync::atomic::{AtomicBool, Ordering};
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_futures::join::join;
+use embassy_rp::bind_interrupts;
+use embassy_rp::clocks::RoscRng;
+use embassy_rp::gpio::{Input, Pull};
+use embassy_rp::peripherals::USB;
+use embassy_time::Timer;
+use embassy_rp::usb::{Driver, InterruptHandler};
+use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
+use embassy_usb::control::OutResponse;
+use embassy_usb::{Builder, Config, Handler};
+use rand::{Rng, RngCore};
+use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ USBCTRL_IRQ => InterruptHandler<USB>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p = embassy_rp::init(Default::default());
+ // Create the driver, from the HAL.
+ let driver = Driver::new(p.USB, Irqs);
+
+ // Create embassy-usb Config
+ let mut config = Config::new(0xc0de, 0xcafe);
+ config.manufacturer = Some("Embassy");
+ config.product = Some("HID keyboard example");
+ config.serial_number = Some("12345678");
+ config.max_power = 100;
+ config.max_packet_size_0 = 64;
+
+ // Create embassy-usb DeviceBuilder using the driver and config.
+ // It needs some buffers for building the descriptors.
+ let mut device_descriptor = [0; 256];
+ let mut config_descriptor = [0; 256];
+ let mut bos_descriptor = [0; 256];
+ // You can also add a Microsoft OS descriptor.
+ let mut msos_descriptor = [0; 256];
+ let mut control_buf = [0; 64];
+ let request_handler = MyRequestHandler {};
+ let mut device_handler = MyDeviceHandler::new();
+
+ let mut state = State::new();
+
+ let mut builder = Builder::new(
+ driver,
+ config,
+ &mut device_descriptor,
+ &mut config_descriptor,
+ &mut bos_descriptor,
+ &mut msos_descriptor,
+ &mut control_buf,
+ );
+
+ builder.handler(&mut device_handler);
+
+ // Create classes on the builder.
+ let config = embassy_usb::class::hid::Config {
+ report_descriptor: MouseReport::desc(),
+ request_handler: Some(&request_handler),
+ poll_ms: 60,
+ max_packet_size: 64,
+ };
+ let hid = HidReaderWriter::<_, 1, 8>::new(&mut builder, &mut state, config);
+
+ // Build the builder.
+ let mut usb = builder.build();
+
+ // Run the USB device.
+ let usb_fut = usb.run();
+
+ // Set up the signal pin that will be used to trigger the keyboard.
+ let mut signal_pin = Input::new(p.PIN_16, Pull::None);
+
+ // Enable the schmitt trigger to slightly debounce.
+ signal_pin.set_schmitt(true);
+
+ let (reader, mut writer) = hid.split();
+
+ // Do stuff with the class!
+ let in_fut = async {
+ let mut rng = RoscRng;
+
+ loop {
+ // every 1 second
+ _ = Timer::after_secs(1).await;
+ let report = MouseReport{
+ buttons: 0,
+ x: rng.gen_range(-100..100), // random small x movement
+ y: rng.gen_range(-100..100), // random small y movement
+ wheel: 0,
+ pan: 0,
+ };
+ match writer.write_serialize(&report).await{
+ Ok(())=>{},
+ Err(e)=>{
+ warn!("Failed to send report: {:?}", e);
+ },
+ }
+ }
+ };
+
+ let out_fut = async {
+ reader.run(false, &request_handler).await;
+ };
+
+ // Run everything concurrently.
+ // If we had made everything `'static` above instead, we could do this using separate tasks instead.
+ join(usb_fut, join(in_fut, out_fut)).await;
+}
+
+struct MyRequestHandler {}
+
+impl RequestHandler for MyRequestHandler {
+ fn get_report(&self, id: ReportId, _buf: &mut [u8]) -> Option<usize> {
+ info!("Get report for {:?}", id);
+ None
+ }
+
+ fn set_report(&self, id: ReportId, data: &[u8]) -> OutResponse {
+ info!("Set report for {:?}: {=[u8]}", id, data);
+ OutResponse::Accepted
+ }
+
+ fn set_idle_ms(&self, id: Option<ReportId>, dur: u32) {
+ info!("Set idle rate for {:?} to {:?}", id, dur);
+ }
+
+ fn get_idle_ms(&self, id: Option<ReportId>) -> Option<u32> {
+ info!("Get idle rate for {:?}", id);
+ None
+ }
+}
+
+struct MyDeviceHandler {
+ configured: AtomicBool,
+}
+
+impl MyDeviceHandler {
+ fn new() -> Self {
+ MyDeviceHandler {
+ configured: AtomicBool::new(false),
+ }
+ }
+}
+
+impl Handler for MyDeviceHandler {
+ fn enabled(&mut self, enabled: bool) {
+ self.configured.store(false, Ordering::Relaxed);
+ if enabled {
+ info!("Device enabled");
+ } else {
+ info!("Device disabled");
+ }
+ }
+
+ fn reset(&mut self) {
+ self.configured.store(false, Ordering::Relaxed);
+ info!("Bus reset, the Vbus current limit is 100mA");
+ }
+
+ fn addressed(&mut self, addr: u8) {
+ self.configured.store(false, Ordering::Relaxed);
+ info!("USB address set to: {}", addr);
+ }
+
+ fn configured(&mut self, configured: bool) {
+ self.configured.store(configured, Ordering::Relaxed);
+ if configured {
+ info!("Device configured, it may now draw up to the configured current limit from Vbus.")
+ } else {
+ info!("Device is no longer configured, the Vbus current limit is 100mA.");
+ }
+ }
+}
From 0dc5e6d3e4646fd8f67840f32a756d55ac36569a Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 12 Feb 2024 02:17:33 +0100
Subject: [PATCH 192/392] stm32/rcc: port F3 RCC to new API
See #2515
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/rcc/f3.rs | 611 ++++++++++---------------
embassy-stm32/src/rcc/mco.rs | 24 +-
examples/stm32f3/src/bin/hello.rs | 5 +-
examples/stm32f3/src/bin/usb_serial.rs | 21 +-
examples/stm32f334/src/bin/adc.rs | 24 +-
examples/stm32f334/src/bin/hello.rs | 5 +-
examples/stm32f334/src/bin/opamp.rs | 24 +-
examples/stm32f334/src/bin/pwm.rs | 27 +-
tests/stm32/src/common.rs | 18 +
10 files changed, 351 insertions(+), 412 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 3f5f12f06..24af17327 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5bf4bec597bdf0d85402789b40c3a37b0f5a8e76" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8ae5bb5fe696a7e61fb41b8b797372aed8103a82" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5bf4bec597bdf0d85402789b40c3a37b0f5a8e76", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8ae5bb5fe696a7e61fb41b8b797372aed8103a82", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f3.rs
index 25866e446..0a5e67b4a 100644
--- a/embassy-stm32/src/rcc/f3.rs
+++ b/embassy-stm32/src/rcc/f3.rs
@@ -1,208 +1,230 @@
-#[cfg(rcc_f3)]
-use crate::pac::adccommon::vals::Ckmode;
use crate::pac::flash::vals::Latency;
-pub use crate::pac::rcc::vals::Adcpres;
-use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
+pub use crate::pac::rcc::vals::{
+ Adcpres as AdcPllPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv,
+ Sw as Sysclk,
+};
+use crate::pac::rcc::vals::{Pllsrc, Usbpre};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
-#[cfg(rcc_f3)]
-impl From<AdcClockSource> for Ckmode {
- fn from(value: AdcClockSource) -> Self {
- match value {
- AdcClockSource::BusDiv1 => Ckmode::SYNCDIV1,
- AdcClockSource::BusDiv2 => Ckmode::SYNCDIV2,
- AdcClockSource::BusDiv4 => Ckmode::SYNCDIV4,
- _ => unreachable!(),
- }
- }
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+ /// crystal/ceramic oscillator (HSEBYP=0)
+ Oscillator,
+ /// external analog clock (low swing) (HSEBYP=1)
+ Bypass,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+ /// HSE frequency.
+ pub freq: Hertz,
+ /// HSE mode.
+ pub mode: HseMode,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum PllSource {
+ HSE,
+ HSI,
+}
+
+#[derive(Clone, Copy)]
+pub struct Pll {
+ pub src: PllSource,
+
+ /// PLL pre-divider.
+ ///
+ /// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
+ pub prediv: PllPreDiv,
+
+ /// PLL multiplication factor.
+ pub mul: PllMul,
}
#[derive(Clone, Copy)]
pub enum AdcClockSource {
- Pll(Adcpres),
- BusDiv1,
- BusDiv2,
- BusDiv4,
+ Pll(AdcPllPrescaler),
+ Hclk(AdcHclkPrescaler),
}
-impl AdcClockSource {
- pub fn bus_div(&self) -> u32 {
- match self {
- Self::BusDiv1 => 1,
- Self::BusDiv2 => 2,
- Self::BusDiv4 => 4,
- _ => unreachable!(),
- }
- }
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub enum AdcHclkPrescaler {
+ Div1,
+ Div2,
+ Div4,
}
-#[derive(Default)]
+#[derive(Clone, Copy, PartialEq, Eq)]
pub enum HrtimClockSource {
- #[default]
BusClk,
PllClk,
}
/// Clocks configutation
#[non_exhaustive]
-#[derive(Default)]
pub struct Config {
- /// Frequency of HSE oscillator
- /// 4MHz to 32MHz
- pub hse: Option<Hertz>,
- /// Bypass HSE for an external clock
- pub bypass_hse: bool,
- /// Frequency of the System Clock
- pub sysclk: Option<Hertz>,
- /// Frequency of AHB bus
- pub hclk: Option<Hertz>,
- /// Frequency of APB1 bus
- /// - Max frequency 36MHz
- pub pclk1: Option<Hertz>,
- /// Frequency of APB2 bus
- /// - Max frequency with HSE is 72MHz
- /// - Max frequency without HSE is 64MHz
- pub pclk2: Option<Hertz>,
- /// USB clock setup
- /// It is valid only when,
- /// - HSE is enabled,
- /// - The System clock frequency is either 48MHz or 72MHz
- /// - APB1 clock has a minimum frequency of 10MHz
- pub pll48: bool,
- #[cfg(rcc_f3)]
- /// ADC clock setup
- /// - For AHB, a psc of 4 or less must be used
- pub adc: Option<AdcClockSource>,
- #[cfg(rcc_f3)]
- /// ADC clock setup
- /// - For AHB, a psc of 4 or less must be used
- pub adc34: Option<AdcClockSource>,
+ pub hsi: bool,
+ pub hse: Option<Hse>,
+ pub sys: Sysclk,
+
+ pub pll: Option<Pll>,
+
+ pub ahb_pre: AHBPrescaler,
+ pub apb1_pre: APBPrescaler,
+ pub apb2_pre: APBPrescaler,
+
+ #[cfg(not(rcc_f37))]
+ pub adc: AdcClockSource,
+ #[cfg(all(not(rcc_f37), adc3_common))]
+ pub adc34: AdcClockSource,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
+
pub ls: super::LsConfig,
}
-// Information required to setup the PLL clock
-#[derive(Clone, Copy)]
-struct PllConfig {
- pll_src: Pllsrc,
- pll_mul: Pllmul,
- pll_div: Option<Prediv>,
+impl Default for Config {
+ fn default() -> Self {
+ Self {
+ hsi: true,
+ hse: None,
+ sys: Sysclk::HSI,
+ pll: None,
+ ahb_pre: AHBPrescaler::DIV1,
+ apb1_pre: APBPrescaler::DIV1,
+ apb2_pre: APBPrescaler::DIV1,
+ ls: Default::default(),
+
+ #[cfg(not(rcc_f37))]
+ adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
+ #[cfg(all(not(rcc_f37), adc3_common))]
+ adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
+ #[cfg(stm32f334)]
+ hrtim: HrtimClockSource::BusClk,
+ }
+ }
}
/// Initialize and Set the clock frequencies
pub(crate) unsafe fn init(config: Config) {
- // Calculate the real System clock, and PLL configuration if applicable
- let (sysclk, pll_config) = get_sysclk(&config);
- assert!(sysclk.0 <= 72_000_000);
-
- // Calculate real AHB clock
- let hclk = config.hclk.map(|h| h).unwrap_or(sysclk);
- let hpre = match sysclk.0 / hclk.0 {
- 0 => unreachable!(),
- 1 => Hpre::DIV1,
- 2 => Hpre::DIV2,
- 3..=5 => Hpre::DIV4,
- 6..=11 => Hpre::DIV8,
- 12..=39 => Hpre::DIV16,
- 40..=95 => Hpre::DIV64,
- 96..=191 => Hpre::DIV128,
- 192..=383 => Hpre::DIV256,
- _ => Hpre::DIV512,
+ // Configure HSI
+ let hsi = match config.hsi {
+ false => {
+ RCC.cr().modify(|w| w.set_hsion(false));
+ None
+ }
+ true => {
+ RCC.cr().modify(|w| w.set_hsion(true));
+ while !RCC.cr().read().hsirdy() {}
+ Some(HSI_FREQ)
+ }
};
- let hclk = sysclk / hpre;
- assert!(hclk <= Hertz(72_000_000));
- // Calculate real APB1 clock
- let pclk1 = config.pclk1.unwrap_or(hclk);
- let ppre1 = match hclk / pclk1 {
- 0 => unreachable!(),
- 1 => Ppre::DIV1,
- 2 => Ppre::DIV2,
- 3..=5 => Ppre::DIV4,
- 6..=11 => Ppre::DIV8,
- _ => Ppre::DIV16,
- };
- let timer_mul1 = if ppre1 == Ppre::DIV1 { 1u32 } else { 2 };
- let pclk1 = hclk / ppre1;
- assert!(pclk1 <= Hertz(36_000_000));
+ // Configure HSE
+ let hse = match config.hse {
+ None => {
+ RCC.cr().modify(|w| w.set_hseon(false));
+ None
+ }
+ Some(hse) => {
+ match hse.mode {
+ HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+ HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+ }
- // Calculate real APB2 clock
- let pclk2 = config.pclk2.unwrap_or(hclk);
- let ppre2 = match hclk / pclk2 {
- 0 => unreachable!(),
- 1 => Ppre::DIV1,
- 2 => Ppre::DIV2,
- 3..=5 => Ppre::DIV4,
- 6..=11 => Ppre::DIV8,
- _ => Ppre::DIV16,
+ RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+ RCC.cr().modify(|w| w.set_hseon(true));
+ while !RCC.cr().read().hserdy() {}
+ Some(hse.freq)
+ }
};
- let timer_mul2 = if ppre2 == Ppre::DIV1 { 1u32 } else { 2 };
- let pclk2 = hclk / ppre2;
- assert!(pclk2 <= Hertz(72_000_000));
+
+ // Enable PLL
+ // RM0316: "Reserved, must be kept at reset value."
+ let pll = config.pll.map(|pll| {
+ let (src_val, src_freq) = match pll.src {
+ #[cfg(rcc_f3v3)]
+ PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
+ #[cfg(not(rcc_f3v3))]
+ PllSource::HSI => {
+ if pll.prediv != PllPreDiv::DIV2 {
+ panic!("if PLL source is HSI, PLL prediv must be 2.");
+ }
+ (Pllsrc::HSI_DIV2, unwrap!(hsi))
+ }
+ PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
+ };
+ let in_freq = src_freq / pll.prediv;
+ assert!(max::PLL_IN.contains(&in_freq));
+ let out_freq = in_freq * pll.mul;
+ assert!(max::PLL_OUT.contains(&out_freq));
+
+ RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
+ RCC.cfgr().modify(|w| {
+ w.set_pllmul(pll.mul);
+ w.set_pllsrc(src_val);
+ });
+ RCC.cr().modify(|w| w.set_pllon(true));
+ while !RCC.cr().read().pllrdy() {}
+
+ out_freq
+ });
+
+ let usb = match pll {
+ Some(Hertz(72_000_000)) => {
+ RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
+ Some(Hertz(48_000_000))
+ }
+ Some(Hertz(48_000_000)) => {
+ RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
+ Some(Hertz(48_000_000))
+ }
+ _ => None,
+ };
+
+ // Configure sysclk
+ let sys = match config.sys {
+ Sysclk::HSI => unwrap!(hsi),
+ Sysclk::HSE => unwrap!(hse),
+ Sysclk::PLL1_P => unwrap!(pll),
+ _ => unreachable!(),
+ };
+
+ let hclk = sys / config.ahb_pre;
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+ let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
+
+ assert!(max::HCLK.contains(&hclk));
+ assert!(max::PCLK1.contains(&pclk1));
+ assert!(max::PCLK2.contains(&pclk2));
// Set latency based on HCLK frquency
- // RM0316: "The prefetch buffer must be kept on when using a prescaler
- // different from 1 on the AHB clock.", "Half-cycle access cannot be
- // used when there is a prescaler different from 1 on the AHB clock"
+ let latency = match hclk.0 {
+ ..=24_000_000 => Latency::WS0,
+ ..=48_000_000 => Latency::WS1,
+ _ => Latency::WS2,
+ };
FLASH.acr().modify(|w| {
- w.set_latency(if hclk <= Hertz(24_000_000) {
- Latency::WS0
- } else if hclk <= Hertz(48_000_000) {
- Latency::WS1
- } else {
- Latency::WS2
- });
- if hpre != Hpre::DIV1 {
+ w.set_latency(latency);
+ // RM0316: "The prefetch buffer must be kept on when using a prescaler
+ // different from 1 on the AHB clock.", "Half-cycle access cannot be
+ // used when there is a prescaler different from 1 on the AHB clock"
+ if config.ahb_pre != AHBPrescaler::DIV1 {
w.set_hlfcya(false);
w.set_prftbe(true);
}
});
- // Enable HSE
- // RM0316: "Bits 31:26 Reserved, must be kept at reset value."
- if config.hse.is_some() {
- RCC.cr().modify(|w| {
- w.set_hsebyp(config.bypass_hse);
- // We turn on clock security to switch to HSI when HSE fails
- w.set_csson(true);
- w.set_hseon(true);
- });
- while !RCC.cr().read().hserdy() {}
- }
-
- // Enable PLL
- // RM0316: "Reserved, must be kept at reset value."
- if let Some(ref pll_config) = pll_config {
- RCC.cfgr().modify(|w| {
- w.set_pllmul(pll_config.pll_mul);
- w.set_pllsrc(pll_config.pll_src);
- });
- if let Some(pll_div) = pll_config.pll_div {
- RCC.cfgr2().modify(|w| w.set_prediv(pll_div));
- }
- RCC.cr().modify(|w| w.set_pllon(true));
- while !RCC.cr().read().pllrdy() {}
- }
-
- // CFGR has been written before (PLL) don't overwrite these settings
- if config.pll48 {
- let usb_pre = get_usb_pre(&config, sysclk, pclk1, &pll_config);
- RCC.cfgr().modify(|w| {
- w.set_usbpre(usb_pre);
- });
- }
-
// Set prescalers
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
RCC.cfgr().modify(|w| {
- w.set_ppre2(ppre2);
- w.set_ppre1(ppre1);
- w.set_hpre(hpre);
+ w.set_ppre2(config.apb1_pre);
+ w.set_ppre1(config.apb2_pre);
+ w.set_hpre(config.ahb_pre);
});
// Wait for the new prescalers to kick in
@@ -211,53 +233,60 @@ pub(crate) unsafe fn init(config: Config) {
cortex_m::asm::delay(16);
// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
- RCC.cfgr().modify(|w| {
- w.set_sw(match (pll_config, config.hse) {
- (Some(_), _) => Sw::PLL1_P,
- (None, Some(_)) => Sw::HSE,
- (None, None) => Sw::HSI,
- })
- });
+ RCC.cfgr().modify(|w| w.set_sw(config.sys));
- #[cfg(rcc_f3)]
- let adc = config.adc.map(|adc| match adc {
+ let rtc = config.ls.init();
+
+ #[cfg(not(rcc_f37))]
+ use crate::pac::adccommon::vals::Ckmode;
+
+ #[cfg(not(rcc_f37))]
+ let adc = match config.adc {
AdcClockSource::Pll(adcpres) => {
- RCC.cfgr2().modify(|w| {
- // Make sure that we're using the PLL
- pll_config.unwrap();
- w.set_adc12pres(adcpres);
+ RCC.cfgr2().modify(|w| w.set_adc12pres(adcpres));
+ crate::pac::ADC_COMMON
+ .ccr()
+ .modify(|w| w.set_ckmode(Ckmode::ASYNCHRONOUS));
- sysclk / adcpres
- })
+ unwrap!(pll) / adcpres
}
- _ => crate::pac::ADC_COMMON.ccr().modify(|w| {
- assert!(!(adc.bus_div() == 1 && hpre != Hpre::DIV1));
+ AdcClockSource::Hclk(adcpres) => {
+ assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
- w.set_ckmode(adc.into());
+ let (div, ckmode) = match adcpres {
+ AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
+ AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
+ AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
+ };
+ crate::pac::ADC_COMMON.ccr().modify(|w| w.set_ckmode(ckmode));
- sysclk / adc.bus_div()
- }),
- });
+ hclk / div
+ }
+ };
- #[cfg(all(rcc_f3, adc3_common))]
- let adc34 = config.adc34.map(|adc| match adc {
+ #[cfg(all(not(rcc_f37), adc3_common))]
+ let adc34 = match config.adc34 {
AdcClockSource::Pll(adcpres) => {
- RCC.cfgr2().modify(|w| {
- // Make sure that we're using the PLL
- pll_config.unwrap();
- w.set_adc34pres(adcpres);
+ RCC.cfgr2().modify(|w| w.set_adc34pres(adcpres));
+ crate::pac::ADC3_COMMON
+ .ccr()
+ .modify(|w| w.set_ckmode(Ckmode::ASYNCHRONOUS));
- sysclk / adcpres
- })
+ unwrap!(pll) / adcpres
}
- _ => crate::pac::ADC_COMMON.ccr().modify(|w| {
- assert!(!(adc.bus_div() == 1 && hpre != Hpre::DIV1));
+ AdcClockSource::Hclk(adcpres) => {
+ assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
- w.set_ckmode(adc.into());
+ let (div, ckmode) = match adcpres {
+ AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
+ AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
+ AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
+ };
+ crate::pac::ADC3_COMMON.ccr().modify(|w| w.set_ckmode(ckmode));
- sysclk / adc.bus_div()
- }),
- });
+ hclk / div
+ }
+ };
#[cfg(stm32f334)]
let hrtim = match config.hrtim {
@@ -267,195 +296,49 @@ pub(crate) unsafe fn init(config: Config) {
use crate::pac::rcc::vals::Timsw;
// Make sure that we're using the PLL
- pll_config.unwrap();
- assert!((pclk2 == sysclk) || (pclk2 * 2u32 == sysclk));
+ let pll = unwrap!(pll);
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
RCC.cfgr3().modify(|w| w.set_hrtim1sw(Timsw::PLL1_P));
- Some(sysclk * 2u32)
+ Some(pll * 2u32)
}
};
- let rtc = config.ls.init();
-
set_clocks!(
- hsi: None,
- lse: None,
- pll1_p: None,
- sys: Some(sysclk),
+ hsi: hsi,
+ hse: hse,
+ pll1_p: pll,
+ sys: Some(sys),
pclk1: Some(pclk1),
pclk2: Some(pclk2),
- pclk1_tim: Some(pclk1 * timer_mul1),
- pclk2_tim: Some(pclk2 * timer_mul2),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2_tim: Some(pclk2_tim),
hclk1: Some(hclk),
- #[cfg(rcc_f3)]
- adc: adc,
- #[cfg(all(rcc_f3, adc3_common))]
- adc34: adc34,
- #[cfg(all(rcc_f3, not(adc3_common)))]
- adc34: None,
+ #[cfg(not(rcc_f37))]
+ adc: Some(adc),
+ #[cfg(all(not(rcc_f37), adc3_common))]
+ adc34: Some(adc34),
#[cfg(stm32f334)]
hrtim: hrtim,
rtc: rtc,
+ usb: usb,
+ lse: None,
);
}
-#[inline]
-fn get_sysclk(config: &Config) -> (Hertz, Option<PllConfig>) {
- match (config.sysclk, config.hse) {
- (Some(sysclk), Some(hse)) if sysclk == hse => (hse, None),
- (Some(sysclk), None) if sysclk == HSI_FREQ => (HSI_FREQ, None),
- // If the user selected System clock is different from HSI or HSE
- // we will have to setup PLL clock source
- (Some(sysclk), _) => {
- let (sysclk, pll_config) = calc_pll(config, sysclk);
- (sysclk, Some(pll_config))
- }
- (None, Some(hse)) => (hse, None),
- (None, None) => (HSI_FREQ, None),
- }
-}
+mod max {
+ use core::ops::RangeInclusive;
-#[inline]
-fn calc_pll(config: &Config, Hertz(sysclk): Hertz) -> (Hertz, PllConfig) {
- // Calculates the Multiplier and the Divisor to arrive at
- // the required System clock from PLL source frequency
- let get_mul_div = |sysclk, pllsrcclk| {
- let bus_div = gcd(sysclk, pllsrcclk);
- let mut multiplier = sysclk / bus_div;
- let mut divisor = pllsrcclk / bus_div;
- // Minimum PLL multiplier is two
- if multiplier == 1 {
- multiplier *= 2;
- divisor *= 2;
- }
- assert!(multiplier <= 16);
- assert!(divisor <= 16);
- (multiplier, divisor)
- };
- // Based on the source of Pll, we calculate the actual system clock
- // frequency, PLL's source identifier, multiplier and divisor
- let (act_sysclk, pll_src, pll_mul, pll_div) = match config.hse {
- Some(Hertz(hse)) => {
- let (multiplier, divisor) = get_mul_div(sysclk, hse);
- (
- Hertz((hse / divisor) * multiplier),
- Pllsrc::HSE_DIV_PREDIV,
- into_pll_mul(multiplier),
- Some(into_pre_div(divisor)),
- )
- }
- None => {
- cfg_if::cfg_if! {
- // For some chips PREDIV is always two, and cannot be changed
- if #[cfg(any(flashsize_d, flashsize_e))] {
- let (multiplier, divisor) = get_mul_div(sysclk, HSI_FREQ.0);
- (
- Hertz((HSI_FREQ.0 / divisor) * multiplier),
- Pllsrc::HSI_DIV_PREDIV,
- into_pll_mul(multiplier),
- Some(into_pre_div(divisor)),
- )
- } else {
- let pllsrcclk = HSI_FREQ.0 / 2;
- let multiplier = sysclk / pllsrcclk;
- assert!(multiplier <= 16);
- (
- Hertz(pllsrcclk * multiplier),
- Pllsrc::HSI_DIV2,
- into_pll_mul(multiplier),
- None,
- )
- }
- }
- }
- };
- (
- act_sysclk,
- PllConfig {
- pll_src,
- pll_mul,
- pll_div,
- },
- )
-}
+ use crate::time::Hertz;
-#[inline]
-#[allow(unused_variables)]
-fn get_usb_pre(config: &Config, sysclk: Hertz, pclk1: Hertz, pll_config: &Option<PllConfig>) -> Usbpre {
- cfg_if::cfg_if! {
- // Some chips do not have USB
- if #[cfg(any(stm32f301, stm32f318, stm32f334))] {
- panic!("USB clock not supported by the chip");
- } else {
- let usb_ok = config.hse.is_some() && pll_config.is_some() && (pclk1 >= Hertz(10_000_000));
- match (usb_ok, sysclk) {
- (true, Hertz(72_000_000)) => Usbpre::DIV1_5,
- (true, Hertz(48_000_000)) => Usbpre::DIV1,
- _ => panic!(
- "USB clock is only valid if the PLL output frequency is either 48MHz or 72MHz"
- ),
- }
- }
- }
-}
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
-// This function assumes cases when multiplier is one and it
-// being greater than 16 is made impossible
-#[inline]
-fn into_pll_mul(multiplier: u32) -> Pllmul {
- match multiplier {
- 2 => Pllmul::MUL2,
- 3 => Pllmul::MUL3,
- 4 => Pllmul::MUL4,
- 5 => Pllmul::MUL5,
- 6 => Pllmul::MUL6,
- 7 => Pllmul::MUL7,
- 8 => Pllmul::MUL8,
- 9 => Pllmul::MUL9,
- 10 => Pllmul::MUL10,
- 11 => Pllmul::MUL11,
- 12 => Pllmul::MUL12,
- 13 => Pllmul::MUL13,
- 14 => Pllmul::MUL14,
- 15 => Pllmul::MUL15,
- 16 => Pllmul::MUL16,
- _ => unreachable!(),
- }
-}
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
+ pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
+ pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
-// This function assumes the incoming divisor cannot be greater
-// than 16
-#[inline]
-fn into_pre_div(divisor: u32) -> Prediv {
- match divisor {
- 1 => Prediv::DIV1,
- 2 => Prediv::DIV2,
- 3 => Prediv::DIV3,
- 4 => Prediv::DIV4,
- 5 => Prediv::DIV5,
- 6 => Prediv::DIV6,
- 7 => Prediv::DIV7,
- 8 => Prediv::DIV8,
- 9 => Prediv::DIV9,
- 10 => Prediv::DIV10,
- 11 => Prediv::DIV11,
- 12 => Prediv::DIV12,
- 13 => Prediv::DIV13,
- 14 => Prediv::DIV14,
- 15 => Prediv::DIV15,
- 16 => Prediv::DIV16,
- _ => unreachable!(),
- }
-}
-
-// Determine GCD using Euclidean algorithm
-#[inline]
-fn gcd(mut a: u32, mut b: u32) -> u32 {
- while b != 0 {
- let r = a % b;
- a = b;
- b = r;
- }
- a
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
+ pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
}
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index eaaf8071c..db0df9fac 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -4,7 +4,7 @@ use embassy_hal_internal::into_ref;
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
-#[cfg(not(stm32f1))]
+#[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
#[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
pub use crate::pac::rcc::vals::Mcosel as McoSource;
@@ -13,10 +13,16 @@ pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
use crate::pac::RCC;
use crate::{peripherals, Peripheral};
+#[cfg(any(stm32f1, rcc_f3v1, rcc_f37))]
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
+pub enum McoPrescaler {
+ DIV1,
+}
+
pub(crate) mod sealed {
pub trait McoInstance {
type Source;
- unsafe fn apply_clock_settings(source: Self::Source, #[cfg(not(stm32f1))] prescaler: super::McoPrescaler);
+ unsafe fn apply_clock_settings(source: Self::Source, prescaler: super::McoPrescaler);
}
}
@@ -29,7 +35,7 @@ macro_rules! impl_peri {
impl sealed::McoInstance for peripherals::$peri {
type Source = $source;
- unsafe fn apply_clock_settings(source: Self::Source, #[cfg(not(stm32f1))] prescaler: McoPrescaler) {
+ unsafe fn apply_clock_settings(source: Self::Source, _prescaler: McoPrescaler) {
#[cfg(not(any(stm32u5, stm32wba)))]
let r = RCC.cfgr();
#[cfg(any(stm32u5, stm32wba))]
@@ -37,8 +43,8 @@ macro_rules! impl_peri {
r.modify(|w| {
w.$set_source(source);
- #[cfg(not(stm32f1))]
- w.$set_prescaler(prescaler);
+ #[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
+ w.$set_prescaler(_prescaler);
});
}
}
@@ -68,16 +74,12 @@ impl<'d, T: McoInstance> Mco<'d, T> {
_peri: impl Peripheral<P = T> + 'd,
pin: impl Peripheral<P = impl McoPin<T>> + 'd,
source: T::Source,
- #[cfg(not(stm32f1))] prescaler: McoPrescaler,
+ prescaler: McoPrescaler,
) -> Self {
into_ref!(pin);
critical_section::with(|_| unsafe {
- T::apply_clock_settings(
- source,
- #[cfg(not(stm32f1))]
- prescaler,
- );
+ T::apply_clock_settings(source, prescaler);
pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
pin.set_speed(Speed::VeryHigh);
});
diff --git a/examples/stm32f3/src/bin/hello.rs b/examples/stm32f3/src/bin/hello.rs
index fd54da53d..3c295612c 100644
--- a/examples/stm32f3/src/bin/hello.rs
+++ b/examples/stm32f3/src/bin/hello.rs
@@ -3,16 +3,13 @@
use defmt::info;
use embassy_executor::Spawner;
-use embassy_stm32::time::Hertz;
use embassy_stm32::Config;
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
- let mut config = Config::default();
- config.rcc.hse = Some(Hertz(8_000_000));
- config.rcc.sysclk = Some(Hertz(16_000_000));
+ let config = Config::default();
let _p = embassy_stm32::init(config);
loop {
diff --git a/examples/stm32f3/src/bin/usb_serial.rs b/examples/stm32f3/src/bin/usb_serial.rs
index cf9ecedfa..ee1c43afd 100644
--- a/examples/stm32f3/src/bin/usb_serial.rs
+++ b/examples/stm32f3/src/bin/usb_serial.rs
@@ -21,11 +21,22 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
- config.rcc.hse = Some(mhz(8));
- config.rcc.sysclk = Some(mhz(48));
- config.rcc.pclk1 = Some(mhz(24));
- config.rcc.pclk2 = Some(mhz(24));
- config.rcc.pll48 = true;
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: mhz(8),
+ mode: HseMode::Bypass,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL9,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV2;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ }
let p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/examples/stm32f334/src/bin/adc.rs b/examples/stm32f334/src/bin/adc.rs
index 063ee9dac..a9fb7f1a6 100644
--- a/examples/stm32f334/src/bin/adc.rs
+++ b/examples/stm32f334/src/bin/adc.rs
@@ -5,7 +5,6 @@ use defmt::info;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
use embassy_stm32::peripherals::ADC1;
-use embassy_stm32::rcc::{AdcClockSource, Adcpres};
use embassy_stm32::time::mhz;
use embassy_stm32::{adc, bind_interrupts, Config};
use embassy_time::{Delay, Timer};
@@ -18,12 +17,23 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
let mut config = Config::default();
- config.rcc.sysclk = Some(mhz(64));
- config.rcc.hclk = Some(mhz(64));
- config.rcc.pclk1 = Some(mhz(32));
- config.rcc.pclk2 = Some(mhz(64));
- config.rcc.adc = Some(AdcClockSource::Pll(Adcpres::DIV1));
-
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: mhz(8),
+ mode: HseMode::Bypass,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL9,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV2;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ config.rcc.adc = AdcClockSource::Pll(AdcPllPrescaler::DIV1);
+ }
let mut p = embassy_stm32::init(config);
info!("create adc...");
diff --git a/examples/stm32f334/src/bin/hello.rs b/examples/stm32f334/src/bin/hello.rs
index fd54da53d..3c295612c 100644
--- a/examples/stm32f334/src/bin/hello.rs
+++ b/examples/stm32f334/src/bin/hello.rs
@@ -3,16 +3,13 @@
use defmt::info;
use embassy_executor::Spawner;
-use embassy_stm32::time::Hertz;
use embassy_stm32::Config;
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
- let mut config = Config::default();
- config.rcc.hse = Some(Hertz(8_000_000));
- config.rcc.sysclk = Some(Hertz(16_000_000));
+ let config = Config::default();
let _p = embassy_stm32::init(config);
loop {
diff --git a/examples/stm32f334/src/bin/opamp.rs b/examples/stm32f334/src/bin/opamp.rs
index 850a0e335..6f25191be 100644
--- a/examples/stm32f334/src/bin/opamp.rs
+++ b/examples/stm32f334/src/bin/opamp.rs
@@ -6,7 +6,6 @@ use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
use embassy_stm32::opamp::{OpAmp, OpAmpGain};
use embassy_stm32::peripherals::ADC2;
-use embassy_stm32::rcc::{AdcClockSource, Adcpres};
use embassy_stm32::time::mhz;
use embassy_stm32::{adc, bind_interrupts, Config};
use embassy_time::{Delay, Timer};
@@ -19,12 +18,23 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
let mut config = Config::default();
- config.rcc.sysclk = Some(mhz(64));
- config.rcc.hclk = Some(mhz(64));
- config.rcc.pclk1 = Some(mhz(32));
- config.rcc.pclk2 = Some(mhz(64));
- config.rcc.adc = Some(AdcClockSource::Pll(Adcpres::DIV1));
-
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: mhz(8),
+ mode: HseMode::Bypass,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL9,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV2;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ config.rcc.adc = AdcClockSource::Pll(AdcPllPrescaler::DIV1);
+ }
let mut p = embassy_stm32::init(config);
info!("create adc...");
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index c149cad92..7fc1ea926 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -4,7 +4,6 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::hrtim::*;
-use embassy_stm32::rcc::HrtimClockSource;
use embassy_stm32::time::{khz, mhz};
use embassy_stm32::Config;
use embassy_time::Timer;
@@ -12,14 +11,26 @@ use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
- let mut config: Config = Default::default();
- config.rcc.sysclk = Some(mhz(64));
- config.rcc.hclk = Some(mhz(64));
- config.rcc.pclk1 = Some(mhz(32));
- config.rcc.pclk2 = Some(mhz(64));
- config.rcc.hrtim = HrtimClockSource::PllClk;
-
+ let mut config = Config::default();
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: mhz(8),
+ mode: HseMode::Bypass,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL9,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV2;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ config.rcc.hrtim = HrtimClockSource::PllClk;
+ }
let p = embassy_stm32::init(config);
+
info!("Hello World!");
let ch1 = PwmPin::new_cha(p.PA8);
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index fefe72c86..36fe8a235 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -276,6 +276,24 @@ pub fn config() -> Config {
config.rcc.apb2_pre = APBPrescaler::DIV2;
}
+ #[cfg(feature = "stm32f303ze")]
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(8_000_000),
+ mode: HseMode::Bypass,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL9,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV2;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ }
+
#[cfg(feature = "stm32f429zi")]
{
use embassy_stm32::rcc::*;
From b4f0f575388df405e4e7330f2e8cdac30c4d60d9 Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Mon, 12 Feb 2024 13:21:01 +0100
Subject: [PATCH 193/392] remove first person comments
---
embassy-nrf/src/lib.rs | 3 ++-
embassy-nrf/src/radio/ble.rs | 22 +++++-----------------
2 files changed, 7 insertions(+), 18 deletions(-)
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 5dba6f975..04a6293a4 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -46,7 +46,8 @@ pub mod gpio;
#[cfg(feature = "gpiote")]
pub mod gpiote;
-#[cfg(any(feature = "nrf52840"))] // needs to be tested on other chips
+// TODO: tested on other chips
+#[cfg(any(feature = "nrf52840"))]
pub mod radio;
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index ba9ac5f2e..81ef96b65 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -1,15 +1,4 @@
//! Radio driver implementation focused on Bluetooth Low-Energy transmission.
-//!
-//! The radio can calculate the CRC, perform data whitening,
-//! automatically send the right preamble.
-//! Most of the configuration is done automatically when you choose the mode and this driver.
-//!
-//! Some configuration can just be done when de device is disabled,
-//! and the configuration varies depending if is a transmitter or a receiver.
-//! Because of that we have a state machine to keep track of the state of the radio.
-//! The Radio is the disable radio which configure the common parameters between
-//! the bluetooth protocols, like the package format, the CRC and the whitening.
-//! The TxRadio radio enable and configured as a transmitter with the specific parameters.
use core::future::poll_fn;
use core::sync::atomic::{compiler_fence, Ordering};
@@ -241,7 +230,7 @@ impl<'d, T: Instance> Radio<'d, T> {
.write(|w| unsafe { w.ap0().bits((access_address >> 24) as u8) });
// The base address is truncated from the least significant byte (because the BALEN is less than 4)
- // So we need to shift the address to the right
+ // So it shifts the address to the right
r.base0.write(|w| unsafe { w.bits(access_address << 8) });
// Don't match tx address
@@ -317,13 +306,12 @@ impl<'d, T: Instance> Radio<'d, T> {
/// Also if the buffer is smaller than the packet length, the radio will
/// read/write memory out of the buffer bounds.
fn set_buffer(&mut self, buffer: &[u8]) -> Result<(), Error> {
- // Because we are serializing the buffer, we should always have the buffer in RAM
slice_in_ram_or(buffer, Error::BufferNotInRAM)?;
let r = T::regs();
- // Here we are considering that the length of the packet is
- // correctly set in the buffer, otherwise we will sending
+ // Here it consider that the length of the packet is
+ // correctly set in the buffer, otherwise it will send
// unowned regions of memory
let ptr = buffer.as_ptr();
@@ -374,7 +362,7 @@ impl<'d, T: Instance> Radio<'d, T> {
let s = T::state();
// If the Future is dropped before the end of the transmission
- // we need to disable the interrupt and stop the transmission
+ // it disable the interrupt and stop the transmission
// to keep the state consistent
let drop = OnDrop::new(|| {
trace!("radio drop: stopping");
@@ -417,7 +405,7 @@ impl<'d, T: Instance> Radio<'d, T> {
compiler_fence(Ordering::SeqCst);
r.events_disabled.reset(); // ACK
- // Everthing ends fine, so we can disable the drop
+ // Everthing ends fine, so it disable the drop
drop.defuse();
}
From 16ed0b1e37a6106596efb2f3fa26344d550fc1ff Mon Sep 17 00:00:00 2001
From: "Jomer.Dev" <Jomer.Dev@posteo.de>
Date: Mon, 12 Feb 2024 19:01:22 +0100
Subject: [PATCH 194/392] Move usb clas loop to private function Move const to
the outside of the logger
---
embassy-usb-logger/src/lib.rs | 75 +++++++++++++++--------------------
1 file changed, 33 insertions(+), 42 deletions(-)
diff --git a/embassy-usb-logger/src/lib.rs b/embassy-usb-logger/src/lib.rs
index a057fcf32..da5ff0f36 100644
--- a/embassy-usb-logger/src/lib.rs
+++ b/embassy-usb-logger/src/lib.rs
@@ -6,7 +6,7 @@ use core::fmt::Write as _;
use embassy_futures::join::join;
use embassy_sync::pipe::Pipe;
-use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
+use embassy_usb::class::cdc_acm::{CdcAcmClass, Receiver, Sender, State};
use embassy_usb::driver::Driver;
use embassy_usb::{Builder, Config};
use log::{Metadata, Record};
@@ -37,6 +37,9 @@ impl<'d> LoggerState<'d> {
}
}
+/// The packet size used in the usb logger, to be used with `create_future_from_class`
+pub const MAX_PACKET_SIZE: u8 = 64;
+
/// The logger handle, which contains a pipe with configurable size for buffering log messages.
pub struct UsbLogger<const N: usize> {
buffer: Pipe<CS, N>,
@@ -54,7 +57,6 @@ impl<const N: usize> UsbLogger<N> {
D: Driver<'d>,
Self: 'd,
{
- const MAX_PACKET_SIZE: u8 = 64;
let mut config = Config::new(0xc0de, 0xcafe);
config.manufacturer = Some("Embassy");
config.product = Some("USB-serial logger");
@@ -87,57 +89,46 @@ impl<const N: usize> UsbLogger<N> {
let mut device = builder.build();
loop {
let run_fut = device.run();
- let log_fut = async {
- let mut rx: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
- sender.wait_connection().await;
- loop {
- let len = self.buffer.read(&mut rx[..]).await;
- let _ = sender.write_packet(&rx[..len]).await;
- if len as u8 == MAX_PACKET_SIZE {
- let _ = sender.write_packet(&[]).await;
- }
- }
- };
- let discard_fut = async {
- let mut discard_buf: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
- receiver.wait_connection().await;
- loop {
- let _ = receiver.read_packet(&mut discard_buf).await;
- }
- };
- join(run_fut, join(log_fut, discard_fut)).await;
+ let class_fut = self.run_logger_class(&mut sender, &mut receiver);
+ join(run_fut, class_fut).await;
}
}
+ async fn run_logger_class<'d, D>(&self, sender: &mut Sender<'d, D>, receiver: &mut Receiver<'d, D>)
+ where
+ D: Driver<'d>,
+ {
+ let log_fut = async {
+ let mut rx: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
+ sender.wait_connection().await;
+ loop {
+ let len = self.buffer.read(&mut rx[..]).await;
+ let _ = sender.write_packet(&rx[..len]).await;
+ if len as u8 == MAX_PACKET_SIZE {
+ let _ = sender.write_packet(&[]).await;
+ }
+ }
+ };
+ let discard_fut = async {
+ let mut discard_buf: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
+ receiver.wait_connection().await;
+ loop {
+ let _ = receiver.read_packet(&mut discard_buf).await;
+ }
+ };
+
+ join(log_fut, discard_fut).await;
+ }
+
/// Creates the futures needed for the logger from a given class
/// This can be used in cases where the usb device is already in use for another connection
pub async fn create_future_from_class<'d, D>(&'d self, class: CdcAcmClass<'d, D>)
where
D: Driver<'d>,
{
- const MAX_PACKET_SIZE: u8 = 64;
let (mut sender, mut receiver) = class.split();
-
loop {
- let log_fut = async {
- let mut rx: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
- sender.wait_connection().await;
- loop {
- let len = self.buffer.read(&mut rx[..]).await;
- let _ = sender.write_packet(&rx[..len]).await;
- if len as u8 == MAX_PACKET_SIZE {
- let _ = sender.write_packet(&[]).await;
- }
- }
- };
- let discard_fut = async {
- let mut discard_buf: [u8; MAX_PACKET_SIZE as usize] = [0; MAX_PACKET_SIZE as usize];
- receiver.wait_connection().await;
- loop {
- let _ = receiver.read_packet(&mut discard_buf).await;
- }
- };
- join(log_fut, discard_fut).await;
+ self.run_logger_class(&mut sender, &mut receiver).await;
}
}
}
From affaf2be1f7e351312e3e34e32c6707b43a23843 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 12 Feb 2024 20:50:06 +0100
Subject: [PATCH 195/392] net: enable dhcpv4-hostname feature in docs.
---
embassy-net/Cargo.toml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-net/Cargo.toml b/embassy-net/Cargo.toml
index 44bd2e8f3..be9f1d784 100644
--- a/embassy-net/Cargo.toml
+++ b/embassy-net/Cargo.toml
@@ -16,11 +16,11 @@ categories = [
[package.metadata.embassy_docs]
src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-v$VERSION/embassy-net/src/"
src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-net/src/"
-features = ["defmt", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6", "medium-ethernet", "medium-ip", "medium-ieee802154", "igmp"]
+features = ["defmt", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6", "medium-ethernet", "medium-ip", "medium-ieee802154", "igmp", "dhcpv4-hostname"]
target = "thumbv7em-none-eabi"
[package.metadata.docs.rs]
-features = ["defmt", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6", "medium-ethernet", "medium-ip", "medium-ieee802154", "igmp"]
+features = ["defmt", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6", "medium-ethernet", "medium-ip", "medium-ieee802154", "igmp", "dhcpv4-hostname"]
[features]
default = []
From 937a9e7955210b5e5467ba4e049d4fa86ec0c42b Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 12 Feb 2024 20:58:04 +0100
Subject: [PATCH 196/392] stm32/rcc: use h7 sdlevel enum from pac.
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/rcc/h.rs | 27 ++++++---------------------
2 files changed, 8 insertions(+), 23 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 24af17327..cc76408f3 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8ae5bb5fe696a7e61fb41b8b797372aed8103a82" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8ae5bb5fe696a7e61fb41b8b797372aed8103a82", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 474c44115..c2a71eaf1 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -170,22 +170,7 @@ pub enum SupplyConfig {
/// This is only used in certain power supply configurations:
/// SMPSLDO, SMPSExternalLDO, SMPSExternalLDOBypass.
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
-#[derive(PartialEq)]
-pub enum SMPSSupplyVoltage {
- V1_8,
- V2_5,
-}
-
-#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
-impl SMPSSupplyVoltage {
- /// Convert SMPSSupplyVoltage to u8 representation.
- fn to_u8(&self) -> u8 {
- match self {
- SMPSSupplyVoltage::V1_8 => 0b01,
- SMPSSupplyVoltage::V2_5 => 0b10,
- }
- }
-}
+pub use pac::pwr::vals::Sdlevel as SMPSSupplyVoltage;
/// Configuration of the core clocks
#[non_exhaustive]
@@ -279,7 +264,7 @@ pub(crate) unsafe fn init(config: Config) {
match config.supply_config {
SupplyConfig::Default => {
PWR.cr3().modify(|w| {
- w.set_sdlevel(0b00);
+ w.set_sdlevel(SMPSSupplyVoltage::RESET);
w.set_sdexthp(false);
w.set_sden(true);
w.set_ldoen(true);
@@ -301,11 +286,11 @@ pub(crate) unsafe fn init(config: Config) {
w.set_bypass(false);
});
}
- SupplyConfig::SMPSLDO(ref smps_supply_voltage)
- | SupplyConfig::SMPSExternalLDO(ref smps_supply_voltage)
- | SupplyConfig::SMPSExternalLDOBypass(ref smps_supply_voltage) => {
+ SupplyConfig::SMPSLDO(smps_supply_voltage)
+ | SupplyConfig::SMPSExternalLDO(smps_supply_voltage)
+ | SupplyConfig::SMPSExternalLDOBypass(smps_supply_voltage) => {
PWR.cr3().modify(|w| {
- w.set_sdlevel(smps_supply_voltage.to_u8());
+ w.set_sdlevel(smps_supply_voltage);
w.set_sdexthp(matches!(
config.supply_config,
SupplyConfig::SMPSExternalLDO(_) | SupplyConfig::SMPSExternalLDOBypass(_)
From 6e24f0562d4dc3aae66d7fa16366e7b7a5aabcb9 Mon Sep 17 00:00:00 2001
From: Nils Bars <nils_bars@t-online.de>
Date: Mon, 12 Feb 2024 21:18:50 +0100
Subject: [PATCH 197/392] Print panics via defmt per default for the stm32f0
example
---
examples/stm32f0/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/stm32f0/Cargo.toml b/examples/stm32f0/Cargo.toml
index 71b0eb683..c74980dc4 100644
--- a/examples/stm32f0/Cargo.toml
+++ b/examples/stm32f0/Cargo.toml
@@ -13,7 +13,7 @@ cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-sing
cortex-m-rt = "0.7.0"
defmt = "0.3"
defmt-rtt = "0.4"
-panic-probe = "0.3"
+panic-probe = { version = "0.3", features = ["print-defmt"] }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
From 56e6b6bee6bd6087b35857e8aa1a011f6e83f703 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Mon, 12 Feb 2024 23:24:21 +0100
Subject: [PATCH 198/392] refactor(boot): move page erase index out of state
---
embassy-boot/src/firmware_updater/asynch.rs | 14 +++++---------
embassy-boot/src/firmware_updater/blocking.rs | 14 +++++---------
2 files changed, 10 insertions(+), 18 deletions(-)
diff --git a/embassy-boot/src/firmware_updater/asynch.rs b/embassy-boot/src/firmware_updater/asynch.rs
index d31eff005..b76668136 100644
--- a/embassy-boot/src/firmware_updater/asynch.rs
+++ b/embassy-boot/src/firmware_updater/asynch.rs
@@ -13,6 +13,7 @@ use crate::{FirmwareUpdaterError, State, BOOT_MAGIC, DFU_DETACH_MAGIC, STATE_ERA
pub struct FirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
dfu: DFU,
state: FirmwareState<'d, STATE>,
+ last_erased_dfu_page_index: Option<usize>,
}
#[cfg(target_os = "none")]
@@ -56,6 +57,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
Self {
dfu: config.dfu,
state: FirmwareState::new(config.state, aligned),
+ last_erased_dfu_page_index: None,
}
}
@@ -72,7 +74,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
/// proceed with updating the firmware as it must be signed with a
/// corresponding private key (otherwise it could be malicious firmware).
///
- /// Mark to trigger firmware swap on next boot if verify suceeds.
+ /// Mark to trigger firmware swap on next boot if verify succeeds.
///
/// If the "ed25519-salty" feature is set (or another similar feature) then the signature is expected to have
/// been generated from a SHA-512 digest of the firmware bytes.
@@ -213,14 +215,13 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
let sector_end = sector_start + DFU::ERASE_SIZE;
// Determine if the current sector needs to be erased before writing.
let need_erase = self
- .state
.last_erased_dfu_page_index
.map_or(true, |last_erased_sector| current_sector != last_erased_sector);
// If the sector needs to be erased, erase it and update the last erased sector index.
if need_erase {
self.dfu.erase(sector_start as u32, sector_end as u32).await?;
- self.state.last_erased_dfu_page_index = Some(current_sector);
+ self.last_erased_dfu_page_index = Some(current_sector);
}
// Calculate the size of the data chunk that can be written in the current iteration.
@@ -258,7 +259,6 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
pub struct FirmwareState<'d, STATE> {
state: STATE,
aligned: &'d mut [u8],
- last_erased_dfu_page_index: Option<usize>,
}
impl<'d, STATE: NorFlash> FirmwareState<'d, STATE> {
@@ -280,11 +280,7 @@ impl<'d, STATE: NorFlash> FirmwareState<'d, STATE> {
/// and follow the alignment rules for the flash being read from and written to.
pub fn new(state: STATE, aligned: &'d mut [u8]) -> Self {
assert_eq!(aligned.len(), STATE::WRITE_SIZE.max(STATE::READ_SIZE));
- Self {
- state,
- aligned,
- last_erased_dfu_page_index: None,
- }
+ Self { state, aligned }
}
// Make sure we are running a booted firmware to avoid reverting to a bad state.
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index 5b8076f81..eb96a9523 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -13,6 +13,7 @@ use crate::{FirmwareUpdaterError, State, BOOT_MAGIC, DFU_DETACH_MAGIC, STATE_ERA
pub struct BlockingFirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
dfu: DFU,
state: BlockingFirmwareState<'d, STATE>,
+ last_erased_dfu_page_index: Option<usize>,
}
#[cfg(target_os = "none")]
@@ -91,6 +92,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
Self {
dfu: config.dfu,
state: BlockingFirmwareState::new(config.state, aligned),
+ last_erased_dfu_page_index: None,
}
}
@@ -107,7 +109,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
/// proceed with updating the firmware as it must be signed with a
/// corresponding private key (otherwise it could be malicious firmware).
///
- /// Mark to trigger firmware swap on next boot if verify suceeds.
+ /// Mark to trigger firmware swap on next boot if verify succeeds.
///
/// If the "ed25519-salty" feature is set (or another similar feature) then the signature is expected to have
/// been generated from a SHA-512 digest of the firmware bytes.
@@ -248,14 +250,13 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
let sector_end = sector_start + DFU::ERASE_SIZE;
// Determine if the current sector needs to be erased before writing.
let need_erase = self
- .state
.last_erased_dfu_page_index
.map_or(true, |last_erased_sector| current_sector != last_erased_sector);
// If the sector needs to be erased, erase it and update the last erased sector index.
if need_erase {
self.dfu.erase(sector_start as u32, sector_end as u32)?;
- self.state.last_erased_dfu_page_index = Some(current_sector);
+ self.last_erased_dfu_page_index = Some(current_sector);
}
// Calculate the size of the data chunk that can be written in the current iteration.
@@ -293,7 +294,6 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
pub struct BlockingFirmwareState<'d, STATE> {
state: STATE,
aligned: &'d mut [u8],
- last_erased_dfu_page_index: Option<usize>,
}
impl<'d, STATE: NorFlash> BlockingFirmwareState<'d, STATE> {
@@ -315,11 +315,7 @@ impl<'d, STATE: NorFlash> BlockingFirmwareState<'d, STATE> {
/// and written to.
pub fn new(state: STATE, aligned: &'d mut [u8]) -> Self {
assert_eq!(aligned.len(), STATE::WRITE_SIZE);
- Self {
- state,
- aligned,
- last_erased_dfu_page_index: None,
- }
+ Self { state, aligned }
}
// Make sure we are running a booted firmware to avoid reverting to a bad state.
From 7dd974aa0dd88ad319971b81083f63a190d278bf Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Mon, 12 Feb 2024 23:28:04 +0100
Subject: [PATCH 199/392] refactor(boot): use sector instead of page for
consistency
---
embassy-boot/src/firmware_updater/asynch.rs | 16 ++++++++--------
embassy-boot/src/firmware_updater/blocking.rs | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/embassy-boot/src/firmware_updater/asynch.rs b/embassy-boot/src/firmware_updater/asynch.rs
index b76668136..3d211be65 100644
--- a/embassy-boot/src/firmware_updater/asynch.rs
+++ b/embassy-boot/src/firmware_updater/asynch.rs
@@ -13,7 +13,7 @@ use crate::{FirmwareUpdaterError, State, BOOT_MAGIC, DFU_DETACH_MAGIC, STATE_ERA
pub struct FirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
dfu: DFU,
state: FirmwareState<'d, STATE>,
- last_erased_dfu_page_index: Option<usize>,
+ last_erased_dfu_sector_index: Option<usize>,
}
#[cfg(target_os = "none")]
@@ -57,7 +57,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
Self {
dfu: config.dfu,
state: FirmwareState::new(config.state, aligned),
- last_erased_dfu_page_index: None,
+ last_erased_dfu_sector_index: None,
}
}
@@ -180,7 +180,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
/// It handles sector erasures and data writes while verifying the device is in a proper state
/// for firmware updates. The function ensures that only unerased sectors are erased before
/// writing and efficiently handles the writing process across sector boundaries and in
- /// various configurations (data size, page size, etc.).
+ /// various configurations (data size, sector size, etc.).
///
/// # Arguments
///
@@ -215,13 +215,13 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> FirmwareUpdater<'d, DFU, STATE> {
let sector_end = sector_start + DFU::ERASE_SIZE;
// Determine if the current sector needs to be erased before writing.
let need_erase = self
- .last_erased_dfu_page_index
+ .last_erased_dfu_sector_index
.map_or(true, |last_erased_sector| current_sector != last_erased_sector);
// If the sector needs to be erased, erase it and update the last erased sector index.
if need_erase {
self.dfu.erase(sector_start as u32, sector_end as u32).await?;
- self.last_erased_dfu_page_index = Some(current_sector);
+ self.last_erased_dfu_sector_index = Some(current_sector);
}
// Calculate the size of the data chunk that can be written in the current iteration.
@@ -380,7 +380,7 @@ mod tests {
}
#[test]
- fn can_verify_sha1_page_bigger_than_chunk() {
+ fn can_verify_sha1_sector_bigger_than_chunk() {
let flash = Mutex::<NoopRawMutex, _>::new(MemFlash::<131072, 4096, 8>::default());
let state = Partition::new(&flash, 0, 4096);
let dfu = Partition::new(&flash, 65536, 65536);
@@ -404,7 +404,7 @@ mod tests {
}
#[test]
- fn can_verify_sha1_page_smaller_than_chunk() {
+ fn can_verify_sha1_sector_smaller_than_chunk() {
let flash = Mutex::<NoopRawMutex, _>::new(MemFlash::<131072, 1024, 8>::default());
let state = Partition::new(&flash, 0, 4096);
let dfu = Partition::new(&flash, 65536, 65536);
@@ -428,7 +428,7 @@ mod tests {
}
#[test]
- fn can_verify_sha1_cross_page_boundary() {
+ fn can_verify_sha1_cross_sector_boundary() {
let flash = Mutex::<NoopRawMutex, _>::new(MemFlash::<131072, 1024, 8>::default());
let state = Partition::new(&flash, 0, 4096);
let dfu = Partition::new(&flash, 65536, 65536);
diff --git a/embassy-boot/src/firmware_updater/blocking.rs b/embassy-boot/src/firmware_updater/blocking.rs
index eb96a9523..35772a856 100644
--- a/embassy-boot/src/firmware_updater/blocking.rs
+++ b/embassy-boot/src/firmware_updater/blocking.rs
@@ -13,7 +13,7 @@ use crate::{FirmwareUpdaterError, State, BOOT_MAGIC, DFU_DETACH_MAGIC, STATE_ERA
pub struct BlockingFirmwareUpdater<'d, DFU: NorFlash, STATE: NorFlash> {
dfu: DFU,
state: BlockingFirmwareState<'d, STATE>,
- last_erased_dfu_page_index: Option<usize>,
+ last_erased_dfu_sector_index: Option<usize>,
}
#[cfg(target_os = "none")]
@@ -92,7 +92,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
Self {
dfu: config.dfu,
state: BlockingFirmwareState::new(config.state, aligned),
- last_erased_dfu_page_index: None,
+ last_erased_dfu_sector_index: None,
}
}
@@ -215,7 +215,7 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
/// It handles sector erasures and data writes while verifying the device is in a proper state
/// for firmware updates. The function ensures that only unerased sectors are erased before
/// writing and efficiently handles the writing process across sector boundaries and in
- /// various configurations (data size, page size, etc.).
+ /// various configurations (data size, sector size, etc.).
///
/// # Arguments
///
@@ -250,13 +250,13 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
let sector_end = sector_start + DFU::ERASE_SIZE;
// Determine if the current sector needs to be erased before writing.
let need_erase = self
- .last_erased_dfu_page_index
+ .last_erased_dfu_sector_index
.map_or(true, |last_erased_sector| current_sector != last_erased_sector);
// If the sector needs to be erased, erase it and update the last erased sector index.
if need_erase {
self.dfu.erase(sector_start as u32, sector_end as u32)?;
- self.last_erased_dfu_page_index = Some(current_sector);
+ self.last_erased_dfu_sector_index = Some(current_sector);
}
// Calculate the size of the data chunk that can be written in the current iteration.
@@ -420,7 +420,7 @@ mod tests {
}
#[test]
- fn can_verify_sha1_page_bigger_than_chunk() {
+ fn can_verify_sha1_sector_bigger_than_chunk() {
let flash = Mutex::<NoopRawMutex, _>::new(RefCell::new(MemFlash::<131072, 4096, 8>::default()));
let state = BlockingPartition::new(&flash, 0, 4096);
let dfu = BlockingPartition::new(&flash, 65536, 65536);
@@ -446,7 +446,7 @@ mod tests {
}
#[test]
- fn can_verify_sha1_page_smaller_than_chunk() {
+ fn can_verify_sha1_sector_smaller_than_chunk() {
let flash = Mutex::<NoopRawMutex, _>::new(RefCell::new(MemFlash::<131072, 1024, 8>::default()));
let state = BlockingPartition::new(&flash, 0, 4096);
let dfu = BlockingPartition::new(&flash, 65536, 65536);
@@ -472,7 +472,7 @@ mod tests {
}
#[test]
- fn can_verify_sha1_cross_page_boundary() {
+ fn can_verify_sha1_cross_sector_boundary() {
let flash = Mutex::<NoopRawMutex, _>::new(RefCell::new(MemFlash::<131072, 1024, 8>::default()));
let state = BlockingPartition::new(&flash, 0, 4096);
let dfu = BlockingPartition::new(&flash, 65536, 65536);
From 739c69bd637baf471585648db4d253089301d6c8 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Tue, 13 Feb 2024 00:58:18 +0100
Subject: [PATCH 200/392] stm32/rcc: some f3 fixes.
---
embassy-stm32/src/rcc/f3.rs | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f3.rs
index 0a5e67b4a..580aa389f 100644
--- a/embassy-stm32/src/rcc/f3.rs
+++ b/embassy-stm32/src/rcc/f3.rs
@@ -222,8 +222,8 @@ pub(crate) unsafe fn init(config: Config) {
// Set prescalers
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
RCC.cfgr().modify(|w| {
- w.set_ppre2(config.apb1_pre);
- w.set_ppre1(config.apb2_pre);
+ w.set_ppre1(config.apb1_pre);
+ w.set_ppre2(config.apb2_pre);
w.set_hpre(config.ahb_pre);
});
@@ -234,6 +234,7 @@ pub(crate) unsafe fn init(config: Config) {
// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
RCC.cfgr().modify(|w| w.set_sw(config.sys));
+ while RCC.cfgr().read().sws() != config.sys {}
let rtc = config.ls.init();
From b7c147445a98ced9557ca6c0950f6083d0cf09af Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 12 Feb 2024 21:54:53 +0100
Subject: [PATCH 201/392] stm32/rcc: port F1 to new API.
---
embassy-stm32/src/rcc/f1.rs | 390 +++++++++++++++----------
examples/stm32f1/src/bin/hello.rs | 4 +-
examples/stm32f1/src/bin/usb_serial.rs | 20 +-
tests/stm32/.cargo/config.toml | 4 +-
tests/stm32/src/common.rs | 18 ++
5 files changed, 266 insertions(+), 170 deletions(-)
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index 7f0adab27..9fdd4c11c 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -1,191 +1,257 @@
-use core::convert::TryFrom;
-
use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::*;
+use crate::pac::rcc::vals::Pllsrc;
+#[cfg(any(rcc_f1, rcc_f1cl))]
+use crate::pac::rcc::vals::Usbpre;
+pub use crate::pac::rcc::vals::{
+ Adcpre as ADCPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Pllxtpre as PllPreDiv, Ppre as APBPrescaler,
+ Sw as Sysclk,
+};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
-/// Configuration of the clocks
-///
-#[non_exhaustive]
-#[derive(Default)]
-pub struct Config {
- pub hse: Option<Hertz>,
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+ /// crystal/ceramic oscillator (HSEBYP=0)
+ Oscillator,
+ /// external analog clock (low swing) (HSEBYP=1)
+ Bypass,
+}
- pub sys_ck: Option<Hertz>,
- pub hclk: Option<Hertz>,
- pub pclk1: Option<Hertz>,
- pub pclk2: Option<Hertz>,
- pub adcclk: Option<Hertz>,
- pub pllxtpre: bool,
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+ /// HSE frequency.
+ pub freq: Hertz,
+ /// HSE mode.
+ pub mode: HseMode,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum PllSource {
+ HSE,
+ HSI,
+}
+
+#[derive(Clone, Copy)]
+pub struct Pll {
+ pub src: PllSource,
+
+ /// PLL pre-divider.
+ ///
+ /// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
+ pub prediv: PllPreDiv,
+
+ /// PLL multiplication factor.
+ pub mul: PllMul,
+}
+
+/// Clocks configutation
+#[non_exhaustive]
+pub struct Config {
+ pub hsi: bool,
+ pub hse: Option<Hse>,
+ pub sys: Sysclk,
+
+ pub pll: Option<Pll>,
+
+ pub ahb_pre: AHBPrescaler,
+ pub apb1_pre: APBPrescaler,
+ pub apb2_pre: APBPrescaler,
+
+ pub adc_pre: ADCPrescaler,
pub ls: super::LsConfig,
}
-pub(crate) unsafe fn init(config: Config) {
- let pllxtpre_div = if config.pllxtpre { 2 } else { 1 };
- let pllsrcclk = config.hse.map(|hse| hse.0 / pllxtpre_div).unwrap_or(HSI_FREQ.0 / 2);
+impl Default for Config {
+ fn default() -> Self {
+ Self {
+ hsi: true,
+ hse: None,
+ sys: Sysclk::HSI,
+ pll: None,
+ ahb_pre: AHBPrescaler::DIV1,
+ apb1_pre: APBPrescaler::DIV1,
+ apb2_pre: APBPrescaler::DIV1,
+ ls: Default::default(),
- let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
- let pllmul = sysclk / pllsrcclk;
-
- let (pllmul_bits, real_sysclk) = if pllmul == 1 {
- (None, config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0))
- } else {
- let pllmul = core::cmp::min(core::cmp::max(pllmul, 1), 16);
- (Some(pllmul as u8 - 2), pllsrcclk * pllmul)
- };
-
- assert!(real_sysclk <= 72_000_000);
-
- let hpre_bits = config
- .hclk
- .map(|hclk| match real_sysclk / hclk.0 {
- 0 => unreachable!(),
- 1 => 0b0111,
- 2 => 0b1000,
- 3..=5 => 0b1001,
- 6..=11 => 0b1010,
- 12..=39 => 0b1011,
- 40..=95 => 0b1100,
- 96..=191 => 0b1101,
- 192..=383 => 0b1110,
- _ => 0b1111,
- })
- .unwrap_or(0b0111);
-
- let hclk = if hpre_bits >= 0b1100 {
- real_sysclk / (1 << (hpre_bits - 0b0110))
- } else {
- real_sysclk / (1 << (hpre_bits - 0b0111))
- };
-
- assert!(hclk <= 72_000_000);
-
- let ppre1_bits = config
- .pclk1
- .map(|pclk1| match hclk / pclk1.0 {
- 0 => unreachable!(),
- 1 => 0b011,
- 2 => 0b100,
- 3..=5 => 0b101,
- 6..=11 => 0b110,
- _ => 0b111,
- })
- .unwrap_or(0b011);
-
- let ppre1 = 1 << (ppre1_bits - 0b011);
- let pclk1 = hclk / u32::try_from(ppre1).unwrap();
- let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
-
- assert!(pclk1 <= 36_000_000);
-
- let ppre2_bits = config
- .pclk2
- .map(|pclk2| match hclk / pclk2.0 {
- 0 => unreachable!(),
- 1 => 0b011,
- 2 => 0b100,
- 3..=5 => 0b101,
- 6..=11 => 0b110,
- _ => 0b111,
- })
- .unwrap_or(0b011);
-
- let ppre2 = 1 << (ppre2_bits - 0b011);
- let pclk2 = hclk / u32::try_from(ppre2).unwrap();
- let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
-
- assert!(pclk2 <= 72_000_000);
-
- FLASH.acr().write(|w| {
- w.set_latency(if real_sysclk <= 24_000_000 {
- Latency::WS0
- } else if real_sysclk <= 48_000_000 {
- Latency::WS1
- } else {
- Latency::WS2
- });
- // the prefetch buffer is enabled by default, let's keep it enabled
- w.set_prftbe(true);
- });
-
- // the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
- // PLL output frequency is a supported one.
- // usbpre == false: divide clock by 1.5, otherwise no division
- #[cfg(not(rcc_f100))]
- let (usbpre, _usbclk_valid) = match (config.hse, pllmul_bits, real_sysclk) {
- (Some(_), Some(_), 72_000_000) => (false, true),
- (Some(_), Some(_), 48_000_000) => (true, true),
- _ => (true, false),
- };
-
- let apre_bits: u8 = config
- .adcclk
- .map(|adcclk| match pclk2 / adcclk.0 {
- 0..=2 => 0b00,
- 3..=4 => 0b01,
- 5..=7 => 0b10,
- _ => 0b11,
- })
- .unwrap_or(0b11);
-
- let apre = (apre_bits + 1) << 1;
- let adcclk = pclk2 / unwrap!(u32::try_from(apre));
-
- assert!(adcclk <= 14_000_000);
-
- if config.hse.is_some() {
- // enable HSE and wait for it to be ready
- RCC.cr().modify(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
+ // ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
+ adc_pre: ADCPrescaler::DIV6,
+ }
}
+}
- if let Some(pllmul_bits) = pllmul_bits {
- let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
- RCC.cfgr()
- .modify(|w| w.set_pllxtpre(Pllxtpre::from_bits(pllctpre_flag)));
+/// Initialize and Set the clock frequencies
+pub(crate) unsafe fn init(config: Config) {
+ // Configure HSI
+ let hsi = match config.hsi {
+ false => {
+ RCC.cr().modify(|w| w.set_hsion(false));
+ None
+ }
+ true => {
+ RCC.cr().modify(|w| w.set_hsion(true));
+ while !RCC.cr().read().hsirdy() {}
+ Some(HSI_FREQ)
+ }
+ };
+
+ // Configure HSE
+ let hse = match config.hse {
+ None => {
+ RCC.cr().modify(|w| w.set_hseon(false));
+ None
+ }
+ Some(hse) => {
+ match hse.mode {
+ HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+ HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+ }
+
+ RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+ RCC.cr().modify(|w| w.set_hseon(true));
+ while !RCC.cr().read().hserdy() {}
+ Some(hse.freq)
+ }
+ };
+
+ // Enable PLL
+ let pll = config.pll.map(|pll| {
+ let (src_val, src_freq) = match pll.src {
+ PllSource::HSI => {
+ if pll.prediv != PllPreDiv::DIV2 {
+ panic!("if PLL source is HSI, PLL prediv must be 2.");
+ }
+ (Pllsrc::HSI_DIV2, unwrap!(hsi))
+ }
+ PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
+ };
+ let in_freq = src_freq / pll.prediv;
+ assert!(max::PLL_IN.contains(&in_freq));
+ let out_freq = in_freq * pll.mul;
+ assert!(max::PLL_OUT.contains(&out_freq));
- // enable PLL and wait for it to be ready
RCC.cfgr().modify(|w| {
- w.set_pllmul(Pllmul::from_bits(pllmul_bits));
- w.set_pllsrc(Pllsrc::from_bits(config.hse.is_some() as u8));
+ w.set_pllmul(pll.mul);
+ w.set_pllsrc(src_val);
+ w.set_pllxtpre(pll.prediv);
});
-
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
- }
- // Only needed for stm32f103?
- RCC.cfgr().modify(|w| {
- w.set_adcpre(Adcpre::from_bits(apre_bits));
- w.set_ppre2(Ppre::from_bits(ppre2_bits));
- w.set_ppre1(Ppre::from_bits(ppre1_bits));
- w.set_hpre(Hpre::from_bits(hpre_bits));
- #[cfg(not(rcc_f100))]
- w.set_usbpre(Usbpre::from_bits(usbpre as u8));
- w.set_sw(if pllmul_bits.is_some() {
- Sw::PLL1_P
- } else if config.hse.is_some() {
- Sw::HSE
- } else {
- Sw::HSI
- });
+ out_freq
});
+ #[cfg(any(rcc_f1, rcc_f1cl))]
+ let usb = match pll {
+ Some(Hertz(72_000_000)) => {
+ RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
+ Some(Hertz(48_000_000))
+ }
+ Some(Hertz(48_000_000)) => {
+ RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
+ Some(Hertz(48_000_000))
+ }
+ _ => None,
+ };
+
+ // Configure sysclk
+ let sys = match config.sys {
+ Sysclk::HSI => unwrap!(hsi),
+ Sysclk::HSE => unwrap!(hse),
+ Sysclk::PLL1_P => unwrap!(pll),
+ _ => unreachable!(),
+ };
+
+ let hclk = sys / config.ahb_pre;
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+ let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
+
+ assert!(max::HCLK.contains(&hclk));
+ assert!(max::PCLK1.contains(&pclk1));
+ assert!(max::PCLK2.contains(&pclk2));
+
+ let adc = pclk2 / config.adc_pre;
+ assert!(max::ADC.contains(&adc));
+
+ // Set latency based on HCLK frquency
+ let latency = match hclk.0 {
+ ..=24_000_000 => Latency::WS0,
+ ..=48_000_000 => Latency::WS1,
+ _ => Latency::WS2,
+ };
+ FLASH.acr().modify(|w| {
+ w.set_latency(latency);
+ // RM0316: "The prefetch buffer must be kept on when using a prescaler
+ // different from 1 on the AHB clock.", "Half-cycle access cannot be
+ // used when there is a prescaler different from 1 on the AHB clock"
+ if config.ahb_pre != AHBPrescaler::DIV1 {
+ w.set_hlfcya(false);
+ w.set_prftbe(true);
+ }
+ });
+
+ // Set prescalers
+ // CFGR has been written before (PLL, PLL48) don't overwrite these settings
+ RCC.cfgr().modify(|w| {
+ w.set_ppre1(config.apb1_pre);
+ w.set_ppre2(config.apb2_pre);
+ w.set_hpre(config.ahb_pre);
+ w.set_adcpre(config.adc_pre);
+ });
+
+ // Wait for the new prescalers to kick in
+ // "The clocks are divided with the new prescaler factor from
+ // 1 to 16 AHB cycles after write"
+ cortex_m::asm::delay(16);
+
+ // CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
+ RCC.cfgr().modify(|w| w.set_sw(config.sys));
+ while RCC.cfgr().read().sws() != config.sys {}
+
let rtc = config.ls.init();
set_clocks!(
- sys: Some(Hertz(real_sysclk)),
- pclk1: Some(Hertz(pclk1)),
- pclk2: Some(Hertz(pclk2)),
- pclk1_tim: Some(Hertz(pclk1 * timer_mul1)),
- pclk2_tim: Some(Hertz(pclk2 * timer_mul2)),
- hclk1: Some(Hertz(hclk)),
- adc: Some(Hertz(adcclk)),
+ hsi: hsi,
+ hse: hse,
+ pll1_p: pll,
+ sys: Some(sys),
+ pclk1: Some(pclk1),
+ pclk2: Some(pclk2),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2_tim: Some(pclk2_tim),
+ hclk1: Some(hclk),
+ adc: Some(adc),
rtc: rtc,
+ #[cfg(any(rcc_f1, rcc_f1cl))]
+ usb: usb,
+ lse: None,
);
}
+
+mod max {
+ use core::ops::RangeInclusive;
+
+ use crate::time::Hertz;
+
+ #[cfg(not(rcc_f1cl))]
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(16_000_000);
+ #[cfg(not(rcc_f1cl))]
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
+
+ #[cfg(rcc_f1cl)]
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(3_000_000)..=Hertz(25_000_000);
+ #[cfg(rcc_f1cl)]
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
+
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
+ pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
+ pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
+
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
+ pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
+
+ pub(crate) const ADC: RangeInclusive<Hertz> = Hertz(0)..=Hertz(14_000_000);
+}
diff --git a/examples/stm32f1/src/bin/hello.rs b/examples/stm32f1/src/bin/hello.rs
index 7b761ecc1..3c295612c 100644
--- a/examples/stm32f1/src/bin/hello.rs
+++ b/examples/stm32f1/src/bin/hello.rs
@@ -3,15 +3,13 @@
use defmt::info;
use embassy_executor::Spawner;
-use embassy_stm32::time::Hertz;
use embassy_stm32::Config;
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) -> ! {
- let mut config = Config::default();
- config.rcc.sys_ck = Some(Hertz(36_000_000));
+ let config = Config::default();
let _p = embassy_stm32::init(config);
loop {
diff --git a/examples/stm32f1/src/bin/usb_serial.rs b/examples/stm32f1/src/bin/usb_serial.rs
index e28381893..1ae6c1dee 100644
--- a/examples/stm32f1/src/bin/usb_serial.rs
+++ b/examples/stm32f1/src/bin/usb_serial.rs
@@ -21,9 +21,23 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
- config.rcc.hse = Some(Hertz(8_000_000));
- config.rcc.sys_ck = Some(Hertz(48_000_000));
- config.rcc.pclk1 = Some(Hertz(24_000_000));
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(8_000_000),
+ // Oscillator for bluepill, Bypass for nucleos.
+ mode: HseMode::Oscillator,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL9,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV2;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ }
let mut p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/tests/stm32/.cargo/config.toml b/tests/stm32/.cargo/config.toml
index 8e32b4cee..528bd3451 100644
--- a/tests/stm32/.cargo/config.toml
+++ b/tests/stm32/.cargo/config.toml
@@ -14,9 +14,9 @@ rustflags = [
]
[build]
-target = "thumbv6m-none-eabi"
+#target = "thumbv6m-none-eabi"
#target = "thumbv7m-none-eabi"
-#target = "thumbv7em-none-eabi"
+target = "thumbv7em-none-eabi"
#target = "thumbv8m.main-none-eabihf"
[env]
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 36fe8a235..182ad6298 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -247,6 +247,24 @@ pub fn config() -> Config {
config.rcc = embassy_stm32::rcc::WPAN_DEFAULT;
}
+ #[cfg(feature = "stm32f103c8")]
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(8_000_000),
+ mode: HseMode::Oscillator,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL9,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV2;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ }
+
#[cfg(feature = "stm32f207zg")]
{
use embassy_stm32::rcc::*;
From ccd2c574c37d26d09f67d6410d79e7e3e16e6119 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Tue, 13 Feb 2024 01:15:20 +0100
Subject: [PATCH 202/392] stm32/rcc: port F0 to new API.
---
ci.sh | 7 +
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/rcc/f0.rs | 338 +++++++++++++++++++----------------
embassy-stm32/src/rcc/mco.rs | 6 +-
embassy-stm32/src/rcc/mod.rs | 16 +-
5 files changed, 207 insertions(+), 164 deletions(-)
diff --git a/ci.sh b/ci.sh
index 58a288441..7ecca92af 100755
--- a/ci.sh
+++ b/ci.sh
@@ -88,6 +88,13 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030r8,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f031k6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030rc,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f070f6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f078vb,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index cc76408f3..4c27164ce 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-8a3ad0b738292ae40af201d79b28db60fe876e11", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
index 1042a1cb2..d6f995e45 100644
--- a/embassy-stm32/src/rcc/f0.rs
+++ b/embassy-stm32/src/rcc/f0.rs
@@ -1,27 +1,64 @@
-use stm32_metapac::flash::vals::Latency;
-
-use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Sw, Usbsw};
+use crate::pac::flash::vals::Latency;
+use crate::pac::rcc::vals::Pllsrc;
+pub use crate::pac::rcc::vals::{
+ Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv, Sw as Sysclk,
+};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(8_000_000);
-/// Configuration of the clocks
-///
-/// hse takes precedence over hsi48 if both are enabled
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+ /// crystal/ceramic oscillator (HSEBYP=0)
+ Oscillator,
+ /// external analog clock (low swing) (HSEBYP=1)
+ Bypass,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+ /// HSE frequency.
+ pub freq: Hertz,
+ /// HSE mode.
+ pub mode: HseMode,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum PllSource {
+ HSE,
+ HSI,
+ #[cfg(rcc_f0v4)]
+ HSI48,
+}
+
+#[derive(Clone, Copy)]
+pub struct Pll {
+ pub src: PllSource,
+
+ /// PLL pre-divider.
+ ///
+ /// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
+ pub prediv: PllPreDiv,
+
+ /// PLL multiplication factor.
+ pub mul: PllMul,
+}
+
+/// Clocks configutation
#[non_exhaustive]
pub struct Config {
- pub hse: Option<Hertz>,
- pub bypass_hse: bool,
- pub usb_pll: bool,
-
+ pub hsi: bool,
+ pub hse: Option<Hse>,
#[cfg(crs)]
pub hsi48: Option<super::Hsi48Config>,
+ pub sys: Sysclk,
- pub sys_ck: Option<Hertz>,
- pub hclk: Option<Hertz>,
- pub pclk: Option<Hertz>,
+ pub pll: Option<Pll>,
+
+ pub ahb_pre: AHBPrescaler,
+ pub apb1_pre: APBPrescaler,
pub ls: super::LsConfig,
}
@@ -29,168 +66,167 @@ pub struct Config {
impl Default for Config {
fn default() -> Self {
Self {
- hse: Default::default(),
- bypass_hse: Default::default(),
- usb_pll: Default::default(),
+ hsi: true,
+ hse: None,
#[cfg(crs)]
hsi48: Some(Default::default()),
- sys_ck: Default::default(),
- hclk: Default::default(),
- pclk: Default::default(),
+ sys: Sysclk::HSI,
+ pll: None,
+ ahb_pre: AHBPrescaler::DIV1,
+ apb1_pre: APBPrescaler::DIV1,
ls: Default::default(),
}
}
}
+/// Initialize and Set the clock frequencies
pub(crate) unsafe fn init(config: Config) {
- let sysclk = config.sys_ck.map(|v| v.0).unwrap_or(HSI_FREQ.0);
+ // Configure HSI
+ let hsi = match config.hsi {
+ false => {
+ RCC.cr().modify(|w| w.set_hsion(false));
+ None
+ }
+ true => {
+ RCC.cr().modify(|w| w.set_hsion(true));
+ while !RCC.cr().read().hsirdy() {}
+ Some(HSI_FREQ)
+ }
+ };
+ // Configure HSE
+ let hse = match config.hse {
+ None => {
+ RCC.cr().modify(|w| w.set_hseon(false));
+ None
+ }
+ Some(hse) => {
+ match hse.mode {
+ HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+ HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+ }
+
+ RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+ RCC.cr().modify(|w| w.set_hseon(true));
+ while !RCC.cr().read().hserdy() {}
+ Some(hse.freq)
+ }
+ };
+
+ // configure HSI48
#[cfg(crs)]
let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
#[cfg(not(crs))]
let hsi48: Option<Hertz> = None;
- let (src_clk, use_hsi48) = config.hse.map(|v| (v.0, false)).unwrap_or_else(|| {
- if hsi48.is_some() {
- return (48_000_000, true);
- }
- (HSI_FREQ.0, false)
- });
+ // Enable PLL
+ let pll = config.pll.map(|pll| {
+ let (src_val, src_freq) = match pll.src {
+ #[cfg(not(any(rcc_f0v1, rcc_f0v2)))]
+ PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
+ #[cfg(any(rcc_f0v1, rcc_f0v2))]
+ PllSource::HSI => {
+ if pll.prediv != PllPreDiv::DIV2 {
+ panic!("if PLL source is HSI, PLL prediv must be 2.");
+ }
+ (Pllsrc::HSI_DIV2, unwrap!(hsi))
+ }
+ PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
+ #[cfg(rcc_f0v4)]
+ PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
+ };
+ let in_freq = src_freq / pll.prediv;
+ assert!(max::PLL_IN.contains(&in_freq));
+ let out_freq = in_freq * pll.mul;
+ assert!(max::PLL_OUT.contains(&out_freq));
- let (pllmul_bits, real_sysclk) = if sysclk == src_clk {
- (None, sysclk)
- } else {
- let prediv = if config.hse.is_some() { 1 } else { 2 };
- let pllmul = (2 * prediv * sysclk + src_clk) / src_clk / 2;
- let pllmul = pllmul.max(2).min(16);
-
- let pllmul_bits = pllmul as u8 - 2;
- let real_sysclk = pllmul * src_clk / prediv;
- (Some(pllmul_bits), real_sysclk)
- };
-
- let hpre_bits = config
- .hclk
- .map(|hclk| match real_sysclk / hclk.0 {
- 0 => unreachable!(),
- 1 => 0b0111,
- 2 => 0b1000,
- 3..=5 => 0b1001,
- 6..=11 => 0b1010,
- 12..=39 => 0b1011,
- 40..=95 => 0b1100,
- 96..=191 => 0b1101,
- 192..=383 => 0b1110,
- _ => 0b1111,
- })
- .unwrap_or(0b0111);
- let hclk = real_sysclk / (1 << (hpre_bits - 0b0111));
-
- let ppre_bits = config
- .pclk
- .map(|pclk| match hclk / pclk.0 {
- 0 => unreachable!(),
- 1 => 0b011,
- 2 => 0b100,
- 3..=5 => 0b101,
- 6..=11 => 0b110,
- _ => 0b111,
- })
- .unwrap_or(0b011);
-
- let ppre: u8 = 1 << (ppre_bits - 0b011);
- let pclk = hclk / u32::from(ppre);
-
- let timer_mul = if ppre == 1 { 1 } else { 2 };
-
- FLASH.acr().write(|w| {
- w.set_latency(if real_sysclk <= 24_000_000 {
- Latency::WS0
- } else {
- Latency::WS1
+ RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
+ RCC.cfgr().modify(|w| {
+ w.set_pllmul(pll.mul);
+ w.set_pllsrc(src_val);
});
- });
-
- match (config.hse.is_some(), use_hsi48) {
- (true, _) => {
- RCC.cr().modify(|w| {
- w.set_csson(true);
- w.set_hseon(true);
- w.set_hsebyp(config.bypass_hse);
- });
- while !RCC.cr().read().hserdy() {}
-
- if pllmul_bits.is_some() {
- RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSE_DIV_PREDIV))
- }
- }
- // use_hsi48 will always be false for stm32f0x0
- #[cfg(not(stm32f0x0))]
- (false, true) => {
- RCC.cr2().modify(|w| w.set_hsi48on(true));
- while !RCC.cr2().read().hsi48rdy() {}
-
- if pllmul_bits.is_some() {
- RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI48_DIV_PREDIV))
- }
- }
- _ => {
- RCC.cr().modify(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
-
- if pllmul_bits.is_some() {
- RCC.cfgr().modify(|w| w.set_pllsrc(Pllsrc::HSI_DIV2))
- }
- }
- }
-
- if config.usb_pll {
- RCC.cfgr3().modify(|w| w.set_usbsw(Usbsw::PLL1_P));
- }
- // TODO: Option to use CRS (Clock Recovery)
-
- if let Some(pllmul_bits) = pllmul_bits {
- RCC.cfgr().modify(|w| w.set_pllmul(Pllmul::from_bits(pllmul_bits)));
-
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
- RCC.cfgr().modify(|w| {
- w.set_ppre(Ppre::from_bits(ppre_bits));
- w.set_hpre(Hpre::from_bits(hpre_bits));
- w.set_sw(Sw::PLL1_P)
- });
- } else {
- RCC.cfgr().modify(|w| {
- w.set_ppre(Ppre::from_bits(ppre_bits));
- w.set_hpre(Hpre::from_bits(hpre_bits));
+ out_freq
+ });
- if config.hse.is_some() {
- w.set_sw(Sw::HSE);
- } else if use_hsi48 {
- #[cfg(not(stm32f0x0))]
- w.set_sw(Sw::HSI48);
- } else {
- w.set_sw(Sw::HSI)
- }
- })
- }
+ // Configure sysclk
+ let sys = match config.sys {
+ Sysclk::HSI => unwrap!(hsi),
+ Sysclk::HSE => unwrap!(hse),
+ Sysclk::PLL1_P => unwrap!(pll),
+ #[cfg(rcc_f0v4)]
+ Sysclk::HSI48 => unwrap!(hsi48),
+ #[allow(unreachable_patterns)]
+ _ => unreachable!(),
+ };
+
+ let hclk = sys / config.ahb_pre;
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+
+ assert!(max::HCLK.contains(&hclk));
+ assert!(max::PCLK1.contains(&pclk1));
+
+ // Set latency based on HCLK frquency
+ let latency = match hclk.0 {
+ ..=24_000_000 => Latency::WS0,
+ _ => Latency::WS1,
+ };
+ FLASH.acr().modify(|w| {
+ w.set_latency(latency);
+ w.set_prftbe(true);
+ });
+
+ // Set prescalers
+ // CFGR has been written before (PLL, PLL48) don't overwrite these settings
+ RCC.cfgr().modify(|w| {
+ w.set_ppre(config.apb1_pre);
+ w.set_hpre(config.ahb_pre);
+ });
+
+ // Wait for the new prescalers to kick in
+ // "The clocks are divided with the new prescaler factor from
+ // 1 to 16 AHB cycles after write"
+ cortex_m::asm::delay(16);
+
+ // CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
+ RCC.cfgr().modify(|w| w.set_sw(config.sys));
+ while RCC.cfgr().read().sws() != config.sys {}
let rtc = config.ls.init();
set_clocks!(
- hsi: None,
- lse: None,
- sys: Some(Hertz(real_sysclk)),
- pclk1: Some(Hertz(pclk)),
- pclk2: Some(Hertz(pclk)),
- pclk1_tim: Some(Hertz(pclk * timer_mul)),
- pclk2_tim: Some(Hertz(pclk * timer_mul)),
- hclk1: Some(Hertz(hclk)),
- rtc: rtc,
+ hsi: hsi,
+ hse: hse,
+ pll1_p: pll,
+ sys: Some(sys),
+ pclk1: Some(pclk1),
+ pclk2: Some(pclk1),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2_tim: Some(pclk1_tim),
+ hclk1: Some(hclk),
+ #[cfg(all(not(rcc_f37), adc3_common))]
+ adc34: Some(adc34),
+ #[cfg(stm32f334)]
+ hrtim: hrtim,
hsi48: hsi48,
-
- // TODO:
- pll1_p: None,
+ rtc: rtc,
+ lse: None,
);
}
+
+mod max {
+ use core::ops::RangeInclusive;
+
+ use crate::time::Hertz;
+
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
+
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+ pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
+ pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
+}
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index db0df9fac..654943bc1 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -4,7 +4,7 @@ use embassy_hal_internal::into_ref;
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
-#[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
+#[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
#[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
pub use crate::pac::rcc::vals::Mcosel as McoSource;
@@ -13,7 +13,7 @@ pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
use crate::pac::RCC;
use crate::{peripherals, Peripheral};
-#[cfg(any(stm32f1, rcc_f3v1, rcc_f37))]
+#[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
pub enum McoPrescaler {
DIV1,
@@ -43,7 +43,7 @@ macro_rules! impl_peri {
r.modify(|w| {
w.$set_source(source);
- #[cfg(not(any(stm32f1, rcc_f3v1, rcc_f37)))]
+ #[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
w.$set_prescaler(_prescaler);
});
}
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 05937cc5d..b7eca0615 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -18,17 +18,17 @@ mod hsi48;
#[cfg(crs)]
pub use hsi48::*;
-#[cfg_attr(rcc_f0, path = "f0.rs")]
-#[cfg_attr(any(stm32f1), path = "f1.rs")]
-#[cfg_attr(any(stm32f3), path = "f3.rs")]
+#[cfg_attr(stm32f0, path = "f0.rs")]
+#[cfg_attr(stm32f1, path = "f1.rs")]
+#[cfg_attr(stm32f3, path = "f3.rs")]
#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f.rs")]
-#[cfg_attr(rcc_c0, path = "c0.rs")]
-#[cfg_attr(rcc_g0, path = "g0.rs")]
-#[cfg_attr(rcc_g4, path = "g4.rs")]
+#[cfg_attr(stm32c0, path = "c0.rs")]
+#[cfg_attr(stm32g0, path = "g0.rs")]
+#[cfg_attr(stm32g4, path = "g4.rs")]
#[cfg_attr(any(stm32h5, stm32h7), path = "h.rs")]
#[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl), path = "l.rs")]
-#[cfg_attr(rcc_u5, path = "u5.rs")]
-#[cfg_attr(rcc_wba, path = "wba.rs")]
+#[cfg_attr(stm32u5, path = "u5.rs")]
+#[cfg_attr(stm32wba, path = "wba.rs")]
mod _version;
pub use _version::*;
From d8b4922b3ced8645a6225dcb0e8b873364bc8337 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Mon, 12 Feb 2024 20:33:04 -0500
Subject: [PATCH 203/392] Add STM32 HMAC function.
---
embassy-stm32/src/hash/mod.rs | 73 ++++++++++++++++++++++++++------
examples/stm32f7/src/bin/hash.rs | 2 +-
2 files changed, 61 insertions(+), 14 deletions(-)
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index f0c2c839a..bae538b5f 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -100,8 +100,9 @@ pub enum DataType {
/// Stores the state of the HASH peripheral for suspending/resuming
/// digest calculation.
-pub struct Context {
+pub struct Context<'c> {
first_word_sent: bool,
+ key_sent: bool,
buffer: [u8; HASH_BUFFER_LEN],
buflen: usize,
algo: Algorithm,
@@ -110,8 +111,11 @@ pub struct Context {
str: u32,
cr: u32,
csr: [u32; NUM_CONTEXT_REGS],
+ key: HmacKey<'c>,
}
+type HmacKey<'k> = Option<&'k [u8]>;
+
/// HASH driver.
pub struct Hash<'d, T: Instance, D = NoDma> {
_peripheral: PeripheralRef<'d, T>,
@@ -140,10 +144,11 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
}
/// Starts computation of a new hash and returns the saved peripheral state.
- pub fn start(&mut self, algorithm: Algorithm, format: DataType) -> Context {
+ pub fn start<'c>(&mut self, algorithm: Algorithm, format: DataType, key: HmacKey<'c>) -> Context<'c> {
// Define a context for this new computation.
let mut ctx = Context {
first_word_sent: false,
+ key_sent: false,
buffer: [0; HASH_BUFFER_LEN],
buflen: 0,
algo: algorithm,
@@ -152,6 +157,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
str: 0,
cr: 0,
csr: [0; NUM_CONTEXT_REGS],
+ key,
};
// Set the data type in the peripheral.
@@ -181,6 +187,14 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
#[cfg(any(hash_v3, hash_v4))]
T::regs().cr().modify(|w| w.set_algo(ctx.algo as u8));
+ // Configure HMAC mode if a key is provided.
+ if let Some(key) = ctx.key {
+ T::regs().cr().modify(|w| w.set_mode(true));
+ if key.len() > 64 {
+ T::regs().cr().modify(|w| w.set_lkey(true));
+ }
+ }
+
T::regs().cr().modify(|w| w.set_init(true));
// Store and return the state of the peripheral.
@@ -191,18 +205,30 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
/// Restores the peripheral state using the given context,
/// then updates the state with the provided data.
/// Peripheral state is saved upon return.
- pub fn update_blocking(&mut self, ctx: &mut Context, input: &[u8]) {
+ pub fn update_blocking<'c>(&mut self, ctx: &mut Context<'c>, input: &[u8]) {
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ // Load the HMAC key if provided.
+ if !ctx.key_sent {
+ if let Some(key) = ctx.key {
+ self.accumulate_blocking(key);
+ T::regs().str().write(|w| w.set_dcal(true));
+ // Block waiting for digest.
+ while !T::regs().sr().read().dcis() {}
+ }
+ ctx.key_sent = true;
+ }
+
let mut data_waiting = input.len() + ctx.buflen;
if data_waiting < DIGEST_BLOCK_SIZE || (data_waiting < ctx.buffer.len() && !ctx.first_word_sent) {
// There isn't enough data to digest a block, so append it to the buffer.
ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
ctx.buflen += input.len();
+ self.store_context(ctx);
return;
}
- // Restore the peripheral state.
- self.load_context(&ctx);
-
let mut ilen_remaining = input.len();
let mut input_start = 0;
@@ -261,21 +287,30 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
/// then updates the state with the provided data.
/// Peripheral state is saved upon return.
#[cfg(hash_v2)]
- pub async fn update(&mut self, ctx: &mut Context, input: &[u8])
+ pub async fn update<'c>(&mut self, ctx: &mut Context<'c>, input: &[u8])
where
D: crate::hash::Dma<T>,
{
+ // Restore the peripheral state.
+ self.load_context(&ctx);
+
+ // Load the HMAC key if provided.
+ if !ctx.key_sent {
+ if let Some(key) = ctx.key {
+ self.accumulate(key).await;
+ }
+ ctx.key_sent = true;
+ }
+
let data_waiting = input.len() + ctx.buflen;
if data_waiting < DIGEST_BLOCK_SIZE {
// There isn't enough data to digest a block, so append it to the buffer.
ctx.buffer[ctx.buflen..ctx.buflen + input.len()].copy_from_slice(input);
ctx.buflen += input.len();
+ self.store_context(ctx);
return;
}
- // Restore the peripheral state.
- self.load_context(&ctx);
-
// Enable multiple DMA transfers.
T::regs().cr().modify(|w| w.set_mdmat(true));
@@ -319,7 +354,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
/// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
/// The largest returned digest size is 128 bytes for SHA-512.
/// Panics if the supplied digest buffer is too short.
- pub fn finish_blocking(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize {
+ pub fn finish_blocking<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize {
// Restore the peripheral state.
self.load_context(&ctx);
@@ -333,6 +368,13 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
// Block waiting for digest.
while !T::regs().sr().read().dcis() {}
+ // Load the HMAC key if provided.
+ if let Some(key) = ctx.key {
+ self.accumulate_blocking(key);
+ T::regs().str().write(|w| w.set_dcal(true));
+ while !T::regs().sr().read().dcis() {}
+ }
+
// Return the digest.
let digest_words = match ctx.algo {
Algorithm::SHA1 => 5,
@@ -370,7 +412,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
/// The largest returned digest size is 128 bytes for SHA-512.
/// Panics if the supplied digest buffer is too short.
#[cfg(hash_v2)]
- pub async fn finish(&mut self, mut ctx: Context, digest: &mut [u8]) -> usize
+ pub async fn finish<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize
where
D: crate::hash::Dma<T>,
{
@@ -384,6 +426,11 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
self.accumulate(&ctx.buffer[0..ctx.buflen]).await;
ctx.buflen = 0;
+ // Load the HMAC key if provided.
+ if let Some(key) = ctx.key {
+ self.accumulate(key).await;
+ }
+
// Wait for completion.
poll_fn(|cx| {
// Check if already done.
@@ -484,7 +531,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
}
/// Save the peripheral state to a context.
- fn store_context(&mut self, ctx: &mut Context) {
+ fn store_context<'c>(&mut self, ctx: &mut Context<'c>) {
// Block waiting for data in ready.
while !T::regs().sr().read().dinis() {}
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index 96e50f84b..cbb880353 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -26,7 +26,7 @@ async fn main(_spawner: Spawner) -> ! {
let hw_start_time = Instant::now();
// Compute a digest in hardware.
- let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
+ let mut context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, None);
hw_hasher.update(&mut context, test_1).await;
hw_hasher.update(&mut context, test_2).await;
let mut hw_digest: [u8; 32] = [0; 32];
From 37c869827e96fb17838f89a082f12c08f3177fff Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Mon, 12 Feb 2024 20:33:04 -0500
Subject: [PATCH 204/392] Update STM32 hash test.
---
tests/stm32/src/bin/hash.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index cfcf3d976..1b89f46e8 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -38,11 +38,11 @@ async fn main(_spawner: Spawner) {
let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
// Start an SHA-256 digest.
- let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
+ let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, None);
hw_hasher.update_blocking(&mut sha256context, test_1);
// Interrupt the SHA-256 digest to compute an SHA-224 digest.
- let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8);
+ let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8, None);
hw_hasher.update_blocking(&mut sha224context, test_3);
let mut sha224_digest_buffer: [u8; 28] = [0; 28];
let _ = hw_hasher.finish_blocking(sha224context, &mut sha224_digest_buffer);
From f0f1f2d14c6cb82ee1a4f452bdece2f98479c39f Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Mon, 12 Feb 2024 20:33:04 -0500
Subject: [PATCH 205/392] Added HMAC example.
---
examples/stm32f7/Cargo.toml | 1 +
examples/stm32f7/src/bin/hash.rs | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/examples/stm32f7/Cargo.toml b/examples/stm32f7/Cargo.toml
index a612c2554..736e81723 100644
--- a/examples/stm32f7/Cargo.toml
+++ b/examples/stm32f7/Cargo.toml
@@ -29,6 +29,7 @@ critical-section = "1.1"
embedded-storage = "0.3.1"
static_cell = "2"
sha2 = { version = "0.10.8", default-features = false }
+hmac = "0.12.1"
[profile.release]
debug = 2
diff --git a/examples/stm32f7/src/bin/hash.rs b/examples/stm32f7/src/bin/hash.rs
index cbb880353..c2d1a7158 100644
--- a/examples/stm32f7/src/bin/hash.rs
+++ b/examples/stm32f7/src/bin/hash.rs
@@ -6,9 +6,12 @@ use embassy_executor::Spawner;
use embassy_stm32::hash::*;
use embassy_stm32::{bind_interrupts, hash, peripherals, Config};
use embassy_time::Instant;
+use hmac::{Hmac, Mac};
use sha2::{Digest, Sha256};
use {defmt_rtt as _, panic_probe as _};
+type HmacSha256 = Hmac<Sha256>;
+
bind_interrupts!(struct Irqs {
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
});
@@ -52,5 +55,24 @@ async fn main(_spawner: Spawner) -> ! {
info!("Software Execution Time: {:?}", sw_execution_time);
assert_eq!(hw_digest, sw_digest[..]);
+ let hmac_key: [u8; 64] = [0x55; 64];
+
+ // Compute HMAC in hardware.
+ let mut sha256hmac_context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, Some(&hmac_key));
+ hw_hasher.update(&mut sha256hmac_context, test_1).await;
+ hw_hasher.update(&mut sha256hmac_context, test_2).await;
+ let mut hw_hmac: [u8; 32] = [0; 32];
+ hw_hasher.finish(sha256hmac_context, &mut hw_hmac).await;
+
+ // Compute HMAC in software.
+ let mut sw_mac = HmacSha256::new_from_slice(&hmac_key).unwrap();
+ sw_mac.update(test_1);
+ sw_mac.update(test_2);
+ let sw_hmac = sw_mac.finalize().into_bytes();
+
+ info!("Hardware HMAC: {:?}", hw_hmac);
+ info!("Software HMAC: {:?}", sw_hmac[..]);
+ assert_eq!(hw_hmac, sw_hmac[..]);
+
loop {}
}
From 14a678fe4542d7c400d0d68b2859c54f2246abe4 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Mon, 12 Feb 2024 20:33:04 -0500
Subject: [PATCH 206/392] Fixed HMAC blocking mode.
---
embassy-stm32/src/hash/mod.rs | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index bae538b5f..b47814f8b 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -215,7 +215,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
self.accumulate_blocking(key);
T::regs().str().write(|w| w.set_dcal(true));
// Block waiting for digest.
- while !T::regs().sr().read().dcis() {}
+ while !T::regs().sr().read().dinis() {}
}
ctx.key_sent = true;
}
@@ -365,16 +365,16 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
//Start the digest calculation.
T::regs().str().write(|w| w.set_dcal(true));
- // Block waiting for digest.
- while !T::regs().sr().read().dcis() {}
-
// Load the HMAC key if provided.
if let Some(key) = ctx.key {
+ while !T::regs().sr().read().dinis() {}
self.accumulate_blocking(key);
T::regs().str().write(|w| w.set_dcal(true));
- while !T::regs().sr().read().dcis() {}
}
+ // Block until digest computation is complete.
+ while !T::regs().sr().read().dcis() {}
+
// Return the digest.
let digest_words = match ctx.algo {
Algorithm::SHA1 => 5,
From f9af0096bd6cd74853b8e5406d6135de2f5c8274 Mon Sep 17 00:00:00 2001
From: Ralf <jr-oss@gmx.net>
Date: Mon, 12 Feb 2024 19:29:29 +0100
Subject: [PATCH 207/392] FAQ add hint to embassy-time linker error to include
HAL in linking
---
docs/modules/ROOT/pages/faq.adoc | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/docs/modules/ROOT/pages/faq.adoc b/docs/modules/ROOT/pages/faq.adoc
index 7fb81e2ca..d55e63130 100644
--- a/docs/modules/ROOT/pages/faq.adoc
+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -118,6 +118,13 @@ features = [
]
----
+If you are in the early project setup phase and not using anything from the HAL, make sure the HAL is passed to the linker by adding this line to your source:
+
+[source,rust]
+----
+use embassy_stm32 as _;
+----
+
== Error: `Only one package in the dependency graph may specify the same links value.`
You have multiple versions of the same crate in your dependency tree. This means that some of your
From 4a0b1cbadb252f186ef41c465936bb3ac4dfcf3f Mon Sep 17 00:00:00 2001
From: James Munns <james@onevariable.com>
Date: Tue, 13 Feb 2024 15:23:50 +0100
Subject: [PATCH 208/392] Update docs/modules/ROOT/pages/faq.adoc
---
docs/modules/ROOT/pages/faq.adoc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/modules/ROOT/pages/faq.adoc b/docs/modules/ROOT/pages/faq.adoc
index d55e63130..6b5e6d009 100644
--- a/docs/modules/ROOT/pages/faq.adoc
+++ b/docs/modules/ROOT/pages/faq.adoc
@@ -118,7 +118,7 @@ features = [
]
----
-If you are in the early project setup phase and not using anything from the HAL, make sure the HAL is passed to the linker by adding this line to your source:
+If you are in the early project setup phase and not using anything from the HAL, make sure the HAL is explicitly used to prevent the linker removing it as dead code by adding this line to your source:
[source,rust]
----
From f0045b92173a46e45be1724d28e1a59045c9c3f6 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 13 Feb 2024 10:17:19 -0500
Subject: [PATCH 209/392] Added HMAC to STM32 hash test.
---
tests/stm32/Cargo.toml | 1 +
tests/stm32/src/bin/hash.rs | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index fc4420687..d94045737 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -76,6 +76,7 @@ portable-atomic = { version = "1.5", features = [] }
chrono = { version = "^0.4", default-features = false, optional = true}
sha2 = { version = "0.10.8", default-features = false }
+hmac = "0.12.1"
# BEGIN TESTS
# Generated by gen_test.py. DO NOT EDIT.
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index 1b89f46e8..d1cfac5ce 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -9,9 +9,12 @@ use embassy_executor::Spawner;
use embassy_stm32::dma::NoDma;
use embassy_stm32::hash::*;
use embassy_stm32::{bind_interrupts, hash, peripherals};
+use hmac::{Hmac, Mac};
use sha2::{Digest, Sha224, Sha256};
use {defmt_rtt as _, panic_probe as _};
+type HmacSha256 = Hmac<Sha256>;
+
#[cfg(any(feature = "stm32l4a6zg", feature = "stm32h755zi", feature = "stm32h753zi"))]
bind_interrupts!(struct Irqs {
HASH_RNG => hash::InterruptHandler<peripherals::HASH>;
@@ -73,6 +76,25 @@ async fn main(_spawner: Spawner) {
info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
defmt::assert!(sha224_digest_buffer == sw_sha224_digest[..]);
+ let hmac_key: [u8; 64] = [0x55; 64];
+
+ // Compute HMAC in hardware.
+ let mut sha256hmac_context = hw_hasher.start(Algorithm::SHA256, DataType::Width8, Some(&hmac_key));
+ hw_hasher.update_blocking(&mut sha256hmac_context, test_1);
+ hw_hasher.update_blocking(&mut sha256hmac_context, test_2);
+ let mut hw_hmac: [u8; 32] = [0; 32];
+ hw_hasher.finish_blocking(sha256hmac_context, &mut hw_hmac);
+
+ // Compute HMAC in software.
+ let mut sw_mac = HmacSha256::new_from_slice(&hmac_key).unwrap();
+ sw_mac.update(test_1);
+ sw_mac.update(test_2);
+ let sw_hmac = sw_mac.finalize().into_bytes();
+
+ info!("Hardware HMAC: {:?}", hw_hmac);
+ info!("Software HMAC: {:?}", sw_hmac[..]);
+ defmt::assert!(hw_hmac == sw_hmac[..]);
+
info!("Test OK");
cortex_m::asm::bkpt();
}
From 0ceb313b6f0827c1b9544f8b87e721c616de8cc2 Mon Sep 17 00:00:00 2001
From: Michael de Silva <michael@mwdesilva.com>
Date: Wed, 14 Feb 2024 07:22:52 +0530
Subject: [PATCH 210/392] FIX: Correct typo in stm32 gpio
---
embassy-stm32/src/gpio.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 1051a13c8..00e3e1727 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -249,7 +249,7 @@ impl From<Pull> for vals::Pupdr {
/// Speed settings
///
-/// These vary dpeending on the chip, ceck the reference manual or datasheet for details.
+/// These vary depending on the chip, check the reference manual or datasheet for details.
#[allow(missing_docs)]
#[derive(Debug, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
From bbe1eebc534f57c74f1735e5d99ed3c4136636bd Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Wed, 14 Feb 2024 17:17:27 +0800
Subject: [PATCH 211/392] Add missing TIM for time-driver; reorder time-driver
selection when use "time-drvier-any".
---
embassy-stm32/build.rs | 41 ++++++++------------
embassy-stm32/src/time_driver.rs | 66 +++++++++++++++++++++++++++-----
2 files changed, 73 insertions(+), 34 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 35023bf1f..5241dbb27 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -183,40 +183,33 @@ fn main() {
let time_driver_singleton = match time_driver.as_ref().map(|x| x.as_ref()) {
None => "",
+ Some("tim1") => "TIM1",
Some("tim2") => "TIM2",
Some("tim3") => "TIM3",
Some("tim4") => "TIM4",
Some("tim5") => "TIM5",
+ Some("tim8") => "TIM8",
Some("tim9") => "TIM9",
- Some("tim11") => "TIM11",
Some("tim12") => "TIM12",
Some("tim15") => "TIM15",
+ Some("tim20") => "TIM20",
Some("tim21") => "TIM21",
Some("tim22") => "TIM22",
+ Some("tim23") => "TIM23",
+ Some("tim24") => "TIM24",
Some("any") => {
- if singletons.contains(&"TIM2".to_string()) {
- "TIM2"
- } else if singletons.contains(&"TIM3".to_string()) {
- "TIM3"
- } else if singletons.contains(&"TIM4".to_string()) {
- "TIM4"
- } else if singletons.contains(&"TIM5".to_string()) {
- "TIM5"
- } else if singletons.contains(&"TIM9".to_string()) {
- "TIM9"
- } else if singletons.contains(&"TIM11".to_string()) {
- "TIM11"
- } else if singletons.contains(&"TIM12".to_string()) {
- "TIM12"
- } else if singletons.contains(&"TIM15".to_string()) {
- "TIM15"
- } else if singletons.contains(&"TIM21".to_string()) {
- "TIM21"
- } else if singletons.contains(&"TIM22".to_string()) {
- "TIM22"
- } else {
- panic!("time-driver-any requested, but the chip doesn't have TIM2, TIM3, TIM4, TIM5, TIM9, TIM11, TIM12 or TIM15.")
- }
+ // Order of TIM candidators:
+ // 1. 2CH -> 2CH_CMP -> GP16 -> GP32 -> ADV
+ // 2. In same catagory: larger TIM number first
+ [
+ "TIM22", "TIM21", "TIM12", "TIM9", // 2CH
+ "TIM15", // 2CH_CMP
+ "TIM19", "TIM4", "TIM3", // GP16
+ "TIM24", "TIM23", "TIM5", "TIM2", // GP32
+ "TIM20", "TIM8", "TIM1", //ADV
+ ]
+ .iter()
+ .find(|tim| singletons.contains(&tim.to_string())).expect("time-driver-any requested, but the chip doesn't have TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM12, TIM15, TIM20, TIM21, TIM22, TIM23 or TIM24.")
}
_ => panic!("unknown time_driver {:?}", time_driver),
};
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 29ff4a736..a1f54307d 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -1,3 +1,5 @@
+#![allow(non_snake_case)]
+
use core::cell::Cell;
use core::convert::TryInto;
use core::sync::atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
@@ -22,18 +24,22 @@ use crate::{interrupt, peripherals};
// As of 2023-12-04, this driver is implemented using CC1 as the halfway rollover interrupt, and any
// additional CC capabilities to provide timer alarms to embassy-time. embassy-time requires AT LEAST
// one alarm to be allocatable, which means timers that only have CC1, such as TIM16/TIM17, are not
-// candidates for use as an embassy-time driver provider.
+// candidates for use as an embassy-time driver provider. (a.k.a 1CH and 1CH_CMP are not, others are good.)
//
// The values of ALARM_COUNT below are not the TOTAL CC registers available, but rather the number
// available after reserving CC1 for regular time keeping. For example, TIM2 has four CC registers:
// CC1, CC2, CC3, and CC4, so it can provide ALARM_COUNT = 3.
-#[cfg(not(any(time_driver_tim12, time_driver_tim15, time_driver_tim21, time_driver_tim22)))]
-const ALARM_COUNT: usize = 3;
-
-#[cfg(any(time_driver_tim12, time_driver_tim15, time_driver_tim21, time_driver_tim22))]
-const ALARM_COUNT: usize = 1;
+cfg_if::cfg_if! {
+ if #[cfg(any(time_driver_tim9, time_driver_tim12, time_driver_tim15, time_driver_tim21, time_driver_tim22))] {
+ const ALARM_COUNT: usize = 1;
+ } else {
+ const ALARM_COUNT: usize = 3;
+ }
+}
+#[cfg(time_drvier_tim1)]
+type T = peripherals::TIM1;
#[cfg(time_driver_tim2)]
type T = peripherals::TIM2;
#[cfg(time_driver_tim3)]
@@ -42,6 +48,8 @@ type T = peripherals::TIM3;
type T = peripherals::TIM4;
#[cfg(time_driver_tim5)]
type T = peripherals::TIM5;
+#[cfg(time_driver_tim8)]
+type T = peripherals::TIM8;
#[cfg(time_driver_tim9)]
type T = peripherals::TIM9;
#[cfg(time_driver_tim11)]
@@ -50,12 +58,26 @@ type T = peripherals::TIM11;
type T = peripherals::TIM12;
#[cfg(time_driver_tim15)]
type T = peripherals::TIM15;
+#[cfg(time_driver_tim20)]
+type T = peripherals::TIM20;
#[cfg(time_driver_tim21)]
type T = peripherals::TIM21;
#[cfg(time_driver_tim22)]
type T = peripherals::TIM22;
+#[cfg(time_driver_tim23)]
+type T = peripherals::TIM23;
+#[cfg(time_driver_tim24)]
+type T = peripherals::TIM24;
foreach_interrupt! {
+ (TIM1, timer, $block:ident, UP, $irq:ident) => {
+ #[cfg(time_driver_tim1)]
+ #[cfg(feature = "rt")]
+ #[interrupt]
+ fn $irq() {
+ DRIVER.on_interrupt()
+ }
+ };
(TIM2, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim2)]
#[cfg(feature = "rt")]
@@ -88,16 +110,16 @@ foreach_interrupt! {
DRIVER.on_interrupt()
}
};
- (TIM9, timer, $block:ident, UP, $irq:ident) => {
- #[cfg(time_driver_tim9)]
+ (TIM8, timer, $block:ident, UP, $irq:ident) => {
+ #[cfg(time_driver_tim8)]
#[cfg(feature = "rt")]
#[interrupt]
fn $irq() {
DRIVER.on_interrupt()
}
};
- (TIM11, timer, $block:ident, UP, $irq:ident) => {
- #[cfg(time_driver_tim11)]
+ (TIM9, timer, $block:ident, UP, $irq:ident) => {
+ #[cfg(time_driver_tim9)]
#[cfg(feature = "rt")]
#[interrupt]
fn $irq() {
@@ -120,6 +142,14 @@ foreach_interrupt! {
DRIVER.on_interrupt()
}
};
+ (TIM20, timer, $block:ident, UP, $irq:ident) => {
+ #[cfg(time_driver_tim20)]
+ #[cfg(feature = "rt")]
+ #[interrupt]
+ fn $irq() {
+ DRIVER.on_interrupt()
+ }
+ };
(TIM21, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim21)]
#[cfg(feature = "rt")]
@@ -136,6 +166,22 @@ foreach_interrupt! {
DRIVER.on_interrupt()
}
};
+ (TIM23, timer, $block:ident, UP, $irq:ident) => {
+ #[cfg(time_driver_tim23)]
+ #[cfg(feature = "rt")]
+ #[interrupt]
+ fn $irq() {
+ DRIVER.on_interrupt()
+ }
+ };
+ (TIM24, timer, $block:ident, UP, $irq:ident) => {
+ #[cfg(time_driver_tim24)]
+ #[cfg(feature = "rt")]
+ #[interrupt]
+ fn $irq() {
+ DRIVER.on_interrupt()
+ }
+ };
}
// Clock timekeeping works with something we call "periods", which are time intervals
From 1860e2269311df018a47a9a52f9f942c0285c97b Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 14 Feb 2024 00:10:59 +0100
Subject: [PATCH 212/392] stm32/rcc: unify f0, f1, f3.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/rcc/f0.rs | 232 --------------------
embassy-stm32/src/rcc/{f3.rs => f013.rs} | 163 +++++++++++---
embassy-stm32/src/rcc/f1.rs | 257 -----------------------
embassy-stm32/src/rcc/{f.rs => f247.rs} | 0
embassy-stm32/src/rcc/mod.rs | 6 +-
6 files changed, 137 insertions(+), 525 deletions(-)
delete mode 100644 embassy-stm32/src/rcc/f0.rs
rename embassy-stm32/src/rcc/{f3.rs => f013.rs} (65%)
delete mode 100644 embassy-stm32/src/rcc/f1.rs
rename embassy-stm32/src/rcc/{f.rs => f247.rs} (100%)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 4c27164ce..c384f14f1 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7734584b2007766b1c5a6a7f2654fdb442fa211a", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/f0.rs b/embassy-stm32/src/rcc/f0.rs
deleted file mode 100644
index d6f995e45..000000000
--- a/embassy-stm32/src/rcc/f0.rs
+++ /dev/null
@@ -1,232 +0,0 @@
-use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::Pllsrc;
-pub use crate::pac::rcc::vals::{
- Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv, Sw as Sysclk,
-};
-use crate::pac::{FLASH, RCC};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(8_000_000);
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum HseMode {
- /// crystal/ceramic oscillator (HSEBYP=0)
- Oscillator,
- /// external analog clock (low swing) (HSEBYP=1)
- Bypass,
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub struct Hse {
- /// HSE frequency.
- pub freq: Hertz,
- /// HSE mode.
- pub mode: HseMode,
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum PllSource {
- HSE,
- HSI,
- #[cfg(rcc_f0v4)]
- HSI48,
-}
-
-#[derive(Clone, Copy)]
-pub struct Pll {
- pub src: PllSource,
-
- /// PLL pre-divider.
- ///
- /// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
- pub prediv: PllPreDiv,
-
- /// PLL multiplication factor.
- pub mul: PllMul,
-}
-
-/// Clocks configutation
-#[non_exhaustive]
-pub struct Config {
- pub hsi: bool,
- pub hse: Option<Hse>,
- #[cfg(crs)]
- pub hsi48: Option<super::Hsi48Config>,
- pub sys: Sysclk,
-
- pub pll: Option<Pll>,
-
- pub ahb_pre: AHBPrescaler,
- pub apb1_pre: APBPrescaler,
-
- pub ls: super::LsConfig,
-}
-
-impl Default for Config {
- fn default() -> Self {
- Self {
- hsi: true,
- hse: None,
- #[cfg(crs)]
- hsi48: Some(Default::default()),
- sys: Sysclk::HSI,
- pll: None,
- ahb_pre: AHBPrescaler::DIV1,
- apb1_pre: APBPrescaler::DIV1,
- ls: Default::default(),
- }
- }
-}
-
-/// Initialize and Set the clock frequencies
-pub(crate) unsafe fn init(config: Config) {
- // Configure HSI
- let hsi = match config.hsi {
- false => {
- RCC.cr().modify(|w| w.set_hsion(false));
- None
- }
- true => {
- RCC.cr().modify(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
- Some(HSI_FREQ)
- }
- };
-
- // Configure HSE
- let hse = match config.hse {
- None => {
- RCC.cr().modify(|w| w.set_hseon(false));
- None
- }
- Some(hse) => {
- match hse.mode {
- HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
- HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
- }
-
- RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
- RCC.cr().modify(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
- Some(hse.freq)
- }
- };
-
- // configure HSI48
- #[cfg(crs)]
- let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
- #[cfg(not(crs))]
- let hsi48: Option<Hertz> = None;
-
- // Enable PLL
- let pll = config.pll.map(|pll| {
- let (src_val, src_freq) = match pll.src {
- #[cfg(not(any(rcc_f0v1, rcc_f0v2)))]
- PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
- #[cfg(any(rcc_f0v1, rcc_f0v2))]
- PllSource::HSI => {
- if pll.prediv != PllPreDiv::DIV2 {
- panic!("if PLL source is HSI, PLL prediv must be 2.");
- }
- (Pllsrc::HSI_DIV2, unwrap!(hsi))
- }
- PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
- #[cfg(rcc_f0v4)]
- PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
- };
- let in_freq = src_freq / pll.prediv;
- assert!(max::PLL_IN.contains(&in_freq));
- let out_freq = in_freq * pll.mul;
- assert!(max::PLL_OUT.contains(&out_freq));
-
- RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
- RCC.cfgr().modify(|w| {
- w.set_pllmul(pll.mul);
- w.set_pllsrc(src_val);
- });
- RCC.cr().modify(|w| w.set_pllon(true));
- while !RCC.cr().read().pllrdy() {}
-
- out_freq
- });
-
- // Configure sysclk
- let sys = match config.sys {
- Sysclk::HSI => unwrap!(hsi),
- Sysclk::HSE => unwrap!(hse),
- Sysclk::PLL1_P => unwrap!(pll),
- #[cfg(rcc_f0v4)]
- Sysclk::HSI48 => unwrap!(hsi48),
- #[allow(unreachable_patterns)]
- _ => unreachable!(),
- };
-
- let hclk = sys / config.ahb_pre;
- let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
-
- assert!(max::HCLK.contains(&hclk));
- assert!(max::PCLK1.contains(&pclk1));
-
- // Set latency based on HCLK frquency
- let latency = match hclk.0 {
- ..=24_000_000 => Latency::WS0,
- _ => Latency::WS1,
- };
- FLASH.acr().modify(|w| {
- w.set_latency(latency);
- w.set_prftbe(true);
- });
-
- // Set prescalers
- // CFGR has been written before (PLL, PLL48) don't overwrite these settings
- RCC.cfgr().modify(|w| {
- w.set_ppre(config.apb1_pre);
- w.set_hpre(config.ahb_pre);
- });
-
- // Wait for the new prescalers to kick in
- // "The clocks are divided with the new prescaler factor from
- // 1 to 16 AHB cycles after write"
- cortex_m::asm::delay(16);
-
- // CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
- RCC.cfgr().modify(|w| w.set_sw(config.sys));
- while RCC.cfgr().read().sws() != config.sys {}
-
- let rtc = config.ls.init();
-
- set_clocks!(
- hsi: hsi,
- hse: hse,
- pll1_p: pll,
- sys: Some(sys),
- pclk1: Some(pclk1),
- pclk2: Some(pclk1),
- pclk1_tim: Some(pclk1_tim),
- pclk2_tim: Some(pclk1_tim),
- hclk1: Some(hclk),
- #[cfg(all(not(rcc_f37), adc3_common))]
- adc34: Some(adc34),
- #[cfg(stm32f334)]
- hrtim: hrtim,
- hsi48: hsi48,
- rtc: rtc,
- lse: None,
- );
-}
-
-mod max {
- use core::ops::RangeInclusive;
-
- use crate::time::Hertz;
-
- pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
- pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
-
- pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
- pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
-
- pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
- pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
-}
diff --git a/embassy-stm32/src/rcc/f3.rs b/embassy-stm32/src/rcc/f013.rs
similarity index 65%
rename from embassy-stm32/src/rcc/f3.rs
rename to embassy-stm32/src/rcc/f013.rs
index 580aa389f..c2933186c 100644
--- a/embassy-stm32/src/rcc/f3.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -1,9 +1,14 @@
use crate::pac::flash::vals::Latency;
-pub use crate::pac::rcc::vals::{
- Adcpres as AdcPllPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Prediv as PllPreDiv,
- Sw as Sysclk,
-};
-use crate::pac::rcc::vals::{Pllsrc, Usbpre};
+#[cfg(stm32f1)]
+pub use crate::pac::rcc::vals::Adcpre as ADCPrescaler;
+#[cfg(stm32f3)]
+pub use crate::pac::rcc::vals::Adcpres as AdcPllPrescaler;
+use crate::pac::rcc::vals::Pllsrc;
+#[cfg(stm32f1)]
+pub use crate::pac::rcc::vals::Pllxtpre as PllPreDiv;
+#[cfg(any(stm32f0, stm32f3))]
+pub use crate::pac::rcc::vals::Prediv as PllPreDiv;
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Sw as Sysclk};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
@@ -30,6 +35,8 @@ pub struct Hse {
pub enum PllSource {
HSE,
HSI,
+ #[cfg(rcc_f0v4)]
+ HSI48,
}
#[derive(Clone, Copy)]
@@ -38,19 +45,21 @@ pub struct Pll {
/// PLL pre-divider.
///
- /// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
+ /// On some chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
pub prediv: PllPreDiv,
/// PLL multiplication factor.
pub mul: PllMul,
}
+#[cfg(all(stm32f3, not(rcc_f37)))]
#[derive(Clone, Copy)]
pub enum AdcClockSource {
Pll(AdcPllPrescaler),
Hclk(AdcHclkPrescaler),
}
+#[cfg(all(stm32f3, not(rcc_f37)))]
#[derive(Clone, Copy, PartialEq, Eq)]
pub enum AdcHclkPrescaler {
Div1,
@@ -58,6 +67,7 @@ pub enum AdcHclkPrescaler {
Div4,
}
+#[cfg(stm32f334)]
#[derive(Clone, Copy, PartialEq, Eq)]
pub enum HrtimClockSource {
BusClk,
@@ -69,17 +79,23 @@ pub enum HrtimClockSource {
pub struct Config {
pub hsi: bool,
pub hse: Option<Hse>,
+ #[cfg(crs)]
+ pub hsi48: Option<super::Hsi48Config>,
pub sys: Sysclk,
pub pll: Option<Pll>,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
+ #[cfg(not(stm32f0))]
pub apb2_pre: APBPrescaler,
- #[cfg(not(rcc_f37))]
+ #[cfg(stm32f1)]
+ pub adc_pre: ADCPrescaler,
+
+ #[cfg(all(stm32f3, not(rcc_f37)))]
pub adc: AdcClockSource,
- #[cfg(all(not(rcc_f37), adc3_common))]
+ #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
pub adc34: AdcClockSource,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
@@ -92,16 +108,24 @@ impl Default for Config {
Self {
hsi: true,
hse: None,
+ #[cfg(crs)]
+ hsi48: Some(Default::default()),
sys: Sysclk::HSI,
pll: None,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
+ #[cfg(not(stm32f0))]
apb2_pre: APBPrescaler::DIV1,
ls: Default::default(),
- #[cfg(not(rcc_f37))]
+ #[cfg(stm32f1)]
+ // ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
+ adc_pre: ADCPrescaler::DIV6,
+
+
+ #[cfg(all(stm32f3, not(rcc_f37)))]
adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
- #[cfg(all(not(rcc_f37), adc3_common))]
+ #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(stm32f334)]
hrtim: HrtimClockSource::BusClk,
@@ -143,13 +167,18 @@ pub(crate) unsafe fn init(config: Config) {
}
};
+ // configure HSI48
+ #[cfg(crs)]
+ let hsi48 = config.hsi48.map(|config| super::init_hsi48(config));
+ #[cfg(not(crs))]
+ let hsi48: Option<Hertz> = None;
+
// Enable PLL
- // RM0316: "Reserved, must be kept at reset value."
let pll = config.pll.map(|pll| {
let (src_val, src_freq) = match pll.src {
- #[cfg(rcc_f3v3)]
+ #[cfg(any(rcc_f0v3, rcc_f0v4, rcc_f3v3))]
PllSource::HSI => (Pllsrc::HSI_DIV_PREDIV, unwrap!(hsi)),
- #[cfg(not(rcc_f3v3))]
+ #[cfg(not(any(rcc_f0v3, rcc_f0v4, rcc_f3v3)))]
PllSource::HSI => {
if pll.prediv != PllPreDiv::DIV2 {
panic!("if PLL source is HSI, PLL prediv must be 2.");
@@ -157,16 +186,21 @@ pub(crate) unsafe fn init(config: Config) {
(Pllsrc::HSI_DIV2, unwrap!(hsi))
}
PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
+ #[cfg(rcc_f0v4)]
+ PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
};
let in_freq = src_freq / pll.prediv;
assert!(max::PLL_IN.contains(&in_freq));
let out_freq = in_freq * pll.mul;
assert!(max::PLL_OUT.contains(&out_freq));
+ #[cfg(not(stm32f1))]
RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
RCC.cfgr().modify(|w| {
w.set_pllmul(pll.mul);
w.set_pllsrc(src_val);
+ #[cfg(stm32f1)]
+ w.set_pllxtpre(pll.prediv);
});
RCC.cr().modify(|w| w.set_pllon(true));
while !RCC.cr().read().pllrdy() {}
@@ -174,17 +208,16 @@ pub(crate) unsafe fn init(config: Config) {
out_freq
});
+ #[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
let usb = match pll {
- Some(Hertz(72_000_000)) => {
- RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
- Some(Hertz(48_000_000))
- }
- Some(Hertz(48_000_000)) => {
- RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
- Some(Hertz(48_000_000))
- }
+ Some(Hertz(72_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1_5),
+ Some(Hertz(48_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1),
_ => None,
- };
+ }
+ .map(|usbpre| {
+ RCC.cfgr().modify(|w| w.set_usbpre(usbpre));
+ Hertz(48_000_000)
+ });
// Configure sysclk
let sys = match config.sys {
@@ -196,13 +229,28 @@ pub(crate) unsafe fn init(config: Config) {
let hclk = sys / config.ahb_pre;
let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+ #[cfg(not(stm32f0))]
let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
+ #[cfg(stm32f0)]
+ let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);
assert!(max::HCLK.contains(&hclk));
assert!(max::PCLK1.contains(&pclk1));
+ #[cfg(not(stm32f0))]
assert!(max::PCLK2.contains(&pclk2));
+ #[cfg(stm32f1)]
+ let adc = pclk2 / config.adc_pre;
+ #[cfg(stm32f1)]
+ assert!(max::ADC.contains(&adc));
+
// Set latency based on HCLK frquency
+ #[cfg(stm32f0)]
+ let latency = match hclk.0 {
+ ..=24_000_000 => Latency::WS0,
+ _ => Latency::WS1,
+ };
+ #[cfg(any(stm32f1, stm32f3))]
let latency = match hclk.0 {
..=24_000_000 => Latency::WS0,
..=48_000_000 => Latency::WS1,
@@ -213,18 +261,28 @@ pub(crate) unsafe fn init(config: Config) {
// RM0316: "The prefetch buffer must be kept on when using a prescaler
// different from 1 on the AHB clock.", "Half-cycle access cannot be
// used when there is a prescaler different from 1 on the AHB clock"
+ #[cfg(stm32f3)]
if config.ahb_pre != AHBPrescaler::DIV1 {
w.set_hlfcya(false);
w.set_prftbe(true);
}
+ #[cfg(not(stm32f3))]
+ w.set_prftbe(true);
});
// Set prescalers
// CFGR has been written before (PLL, PLL48) don't overwrite these settings
- RCC.cfgr().modify(|w| {
- w.set_ppre1(config.apb1_pre);
- w.set_ppre2(config.apb2_pre);
+ RCC.cfgr().modify(|w: &mut stm32_metapac::rcc::regs::Cfgr| {
+ #[cfg(not(stm32f0))]
+ {
+ w.set_ppre1(config.apb1_pre);
+ w.set_ppre2(config.apb2_pre);
+ }
+ #[cfg(stm32f0)]
+ w.set_ppre(config.apb1_pre);
w.set_hpre(config.ahb_pre);
+ #[cfg(stm32f1)]
+ w.set_adcpre(config.adc_pre);
});
// Wait for the new prescalers to kick in
@@ -238,10 +296,10 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
- #[cfg(not(rcc_f37))]
+ #[cfg(all(stm32f3, not(rcc_f37)))]
use crate::pac::adccommon::vals::Ckmode;
- #[cfg(not(rcc_f37))]
+ #[cfg(all(stm32f3, not(rcc_f37)))]
let adc = match config.adc {
AdcClockSource::Pll(adcpres) => {
RCC.cfgr2().modify(|w| w.set_adc12pres(adcpres));
@@ -265,7 +323,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(all(not(rcc_f37), adc3_common))]
+ #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
let adc34 = match config.adc34 {
AdcClockSource::Pll(adcpres) => {
RCC.cfgr2().modify(|w| w.set_adc34pres(adcpres));
@@ -316,18 +374,63 @@ pub(crate) unsafe fn init(config: Config) {
pclk1_tim: Some(pclk1_tim),
pclk2_tim: Some(pclk2_tim),
hclk1: Some(hclk),
- #[cfg(not(rcc_f37))]
+ #[cfg(all(stm32f3, not(rcc_f37)))]
adc: Some(adc),
- #[cfg(all(not(rcc_f37), adc3_common))]
+ #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
adc34: Some(adc34),
#[cfg(stm32f334)]
hrtim: hrtim,
rtc: rtc,
+ hsi48: hsi48,
+ #[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
usb: usb,
lse: None,
);
}
+#[cfg(stm32f0)]
+mod max {
+ use core::ops::RangeInclusive;
+
+ use crate::time::Hertz;
+
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(32_000_000);
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(32_000_000);
+
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+ pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(24_000_000);
+ pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(48_000_000);
+}
+
+#[cfg(stm32f1)]
+mod max {
+ use core::ops::RangeInclusive;
+
+ use crate::time::Hertz;
+
+ #[cfg(not(rcc_f1cl))]
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(16_000_000);
+ #[cfg(not(rcc_f1cl))]
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
+
+ #[cfg(rcc_f1cl)]
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(3_000_000)..=Hertz(25_000_000);
+ #[cfg(rcc_f1cl)]
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
+
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
+ pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
+ pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
+
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
+ pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
+
+ pub(crate) const ADC: RangeInclusive<Hertz> = Hertz(0)..=Hertz(14_000_000);
+}
+
+#[cfg(stm32f3)]
mod max {
use core::ops::RangeInclusive;
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
deleted file mode 100644
index 9fdd4c11c..000000000
--- a/embassy-stm32/src/rcc/f1.rs
+++ /dev/null
@@ -1,257 +0,0 @@
-use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::Pllsrc;
-#[cfg(any(rcc_f1, rcc_f1cl))]
-use crate::pac::rcc::vals::Usbpre;
-pub use crate::pac::rcc::vals::{
- Adcpre as ADCPrescaler, Hpre as AHBPrescaler, Pllmul as PllMul, Pllxtpre as PllPreDiv, Ppre as APBPrescaler,
- Sw as Sysclk,
-};
-use crate::pac::{FLASH, RCC};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(8_000_000);
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum HseMode {
- /// crystal/ceramic oscillator (HSEBYP=0)
- Oscillator,
- /// external analog clock (low swing) (HSEBYP=1)
- Bypass,
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub struct Hse {
- /// HSE frequency.
- pub freq: Hertz,
- /// HSE mode.
- pub mode: HseMode,
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum PllSource {
- HSE,
- HSI,
-}
-
-#[derive(Clone, Copy)]
-pub struct Pll {
- pub src: PllSource,
-
- /// PLL pre-divider.
- ///
- /// On some F3 chips, this must be 2 if `src == HSI`. Init will panic if this is not the case.
- pub prediv: PllPreDiv,
-
- /// PLL multiplication factor.
- pub mul: PllMul,
-}
-
-/// Clocks configutation
-#[non_exhaustive]
-pub struct Config {
- pub hsi: bool,
- pub hse: Option<Hse>,
- pub sys: Sysclk,
-
- pub pll: Option<Pll>,
-
- pub ahb_pre: AHBPrescaler,
- pub apb1_pre: APBPrescaler,
- pub apb2_pre: APBPrescaler,
-
- pub adc_pre: ADCPrescaler,
-
- pub ls: super::LsConfig,
-}
-
-impl Default for Config {
- fn default() -> Self {
- Self {
- hsi: true,
- hse: None,
- sys: Sysclk::HSI,
- pll: None,
- ahb_pre: AHBPrescaler::DIV1,
- apb1_pre: APBPrescaler::DIV1,
- apb2_pre: APBPrescaler::DIV1,
- ls: Default::default(),
-
- // ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
- adc_pre: ADCPrescaler::DIV6,
- }
- }
-}
-
-/// Initialize and Set the clock frequencies
-pub(crate) unsafe fn init(config: Config) {
- // Configure HSI
- let hsi = match config.hsi {
- false => {
- RCC.cr().modify(|w| w.set_hsion(false));
- None
- }
- true => {
- RCC.cr().modify(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
- Some(HSI_FREQ)
- }
- };
-
- // Configure HSE
- let hse = match config.hse {
- None => {
- RCC.cr().modify(|w| w.set_hseon(false));
- None
- }
- Some(hse) => {
- match hse.mode {
- HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
- HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
- }
-
- RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
- RCC.cr().modify(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
- Some(hse.freq)
- }
- };
-
- // Enable PLL
- let pll = config.pll.map(|pll| {
- let (src_val, src_freq) = match pll.src {
- PllSource::HSI => {
- if pll.prediv != PllPreDiv::DIV2 {
- panic!("if PLL source is HSI, PLL prediv must be 2.");
- }
- (Pllsrc::HSI_DIV2, unwrap!(hsi))
- }
- PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
- };
- let in_freq = src_freq / pll.prediv;
- assert!(max::PLL_IN.contains(&in_freq));
- let out_freq = in_freq * pll.mul;
- assert!(max::PLL_OUT.contains(&out_freq));
-
- RCC.cfgr().modify(|w| {
- w.set_pllmul(pll.mul);
- w.set_pllsrc(src_val);
- w.set_pllxtpre(pll.prediv);
- });
- RCC.cr().modify(|w| w.set_pllon(true));
- while !RCC.cr().read().pllrdy() {}
-
- out_freq
- });
-
- #[cfg(any(rcc_f1, rcc_f1cl))]
- let usb = match pll {
- Some(Hertz(72_000_000)) => {
- RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1_5));
- Some(Hertz(48_000_000))
- }
- Some(Hertz(48_000_000)) => {
- RCC.cfgr().modify(|w| w.set_usbpre(Usbpre::DIV1));
- Some(Hertz(48_000_000))
- }
- _ => None,
- };
-
- // Configure sysclk
- let sys = match config.sys {
- Sysclk::HSI => unwrap!(hsi),
- Sysclk::HSE => unwrap!(hse),
- Sysclk::PLL1_P => unwrap!(pll),
- _ => unreachable!(),
- };
-
- let hclk = sys / config.ahb_pre;
- let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
- let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
-
- assert!(max::HCLK.contains(&hclk));
- assert!(max::PCLK1.contains(&pclk1));
- assert!(max::PCLK2.contains(&pclk2));
-
- let adc = pclk2 / config.adc_pre;
- assert!(max::ADC.contains(&adc));
-
- // Set latency based on HCLK frquency
- let latency = match hclk.0 {
- ..=24_000_000 => Latency::WS0,
- ..=48_000_000 => Latency::WS1,
- _ => Latency::WS2,
- };
- FLASH.acr().modify(|w| {
- w.set_latency(latency);
- // RM0316: "The prefetch buffer must be kept on when using a prescaler
- // different from 1 on the AHB clock.", "Half-cycle access cannot be
- // used when there is a prescaler different from 1 on the AHB clock"
- if config.ahb_pre != AHBPrescaler::DIV1 {
- w.set_hlfcya(false);
- w.set_prftbe(true);
- }
- });
-
- // Set prescalers
- // CFGR has been written before (PLL, PLL48) don't overwrite these settings
- RCC.cfgr().modify(|w| {
- w.set_ppre1(config.apb1_pre);
- w.set_ppre2(config.apb2_pre);
- w.set_hpre(config.ahb_pre);
- w.set_adcpre(config.adc_pre);
- });
-
- // Wait for the new prescalers to kick in
- // "The clocks are divided with the new prescaler factor from
- // 1 to 16 AHB cycles after write"
- cortex_m::asm::delay(16);
-
- // CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
- RCC.cfgr().modify(|w| w.set_sw(config.sys));
- while RCC.cfgr().read().sws() != config.sys {}
-
- let rtc = config.ls.init();
-
- set_clocks!(
- hsi: hsi,
- hse: hse,
- pll1_p: pll,
- sys: Some(sys),
- pclk1: Some(pclk1),
- pclk2: Some(pclk2),
- pclk1_tim: Some(pclk1_tim),
- pclk2_tim: Some(pclk2_tim),
- hclk1: Some(hclk),
- adc: Some(adc),
- rtc: rtc,
- #[cfg(any(rcc_f1, rcc_f1cl))]
- usb: usb,
- lse: None,
- );
-}
-
-mod max {
- use core::ops::RangeInclusive;
-
- use crate::time::Hertz;
-
- #[cfg(not(rcc_f1cl))]
- pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(16_000_000);
- #[cfg(not(rcc_f1cl))]
- pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
-
- #[cfg(rcc_f1cl)]
- pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(3_000_000)..=Hertz(25_000_000);
- #[cfg(rcc_f1cl)]
- pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(50_000_000);
-
- pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
- pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(36_000_000);
- pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(72_000_000);
-
- pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(25_000_000);
- pub(crate) const PLL_OUT: RangeInclusive<Hertz> = Hertz(16_000_000)..=Hertz(72_000_000);
-
- pub(crate) const ADC: RangeInclusive<Hertz> = Hertz(0)..=Hertz(14_000_000);
-}
diff --git a/embassy-stm32/src/rcc/f.rs b/embassy-stm32/src/rcc/f247.rs
similarity index 100%
rename from embassy-stm32/src/rcc/f.rs
rename to embassy-stm32/src/rcc/f247.rs
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index b7eca0615..0f3467151 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -18,10 +18,8 @@ mod hsi48;
#[cfg(crs)]
pub use hsi48::*;
-#[cfg_attr(stm32f0, path = "f0.rs")]
-#[cfg_attr(stm32f1, path = "f1.rs")]
-#[cfg_attr(stm32f3, path = "f3.rs")]
-#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f.rs")]
+#[cfg_attr(any(stm32f0, stm32f1, stm32f3), path = "f013.rs")]
+#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f247.rs")]
#[cfg_attr(stm32c0, path = "c0.rs")]
#[cfg_attr(stm32g0, path = "g0.rs")]
#[cfg_attr(stm32g4, path = "g4.rs")]
From 50b8100fd30fd13ac706889b0951e6ec25c77821 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Thu, 15 Feb 2024 12:34:51 +0200
Subject: [PATCH 213/392] nrf: Implement chunked DMA transfers for SPIM
peripheral
On some chips (notably nrf52832), the maximum DMA transfer is 255
bytes, which has caused subtle issues while interfacing with various
devices over SPI bus.
---
embassy-nrf/src/spim.rs | 112 ++++++++++++++++++++++++----------------
embassy-nrf/src/util.rs | 13 +++++
2 files changed, 81 insertions(+), 44 deletions(-)
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index 8937159df..2d70732a8 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -17,7 +17,7 @@ use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::typelevel::Interrupt;
-use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
+use crate::util::{slice_in_ram_or, slice_ptr_len, slice_ptr_parts, slice_ptr_parts_mut};
use crate::{interrupt, pac, Peripheral};
/// SPIM error
@@ -25,10 +25,6 @@ use crate::{interrupt, pac, Peripheral};
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
pub enum Error {
- /// Supplied TX buffer overflows EasyDMA transmit buffer
- TxBufferTooLong,
- /// Supplied RX buffer overflows EasyDMA receive buffer
- RxBufferTooLong,
/// EasyDMA can only read from data memory, read only buffers in flash will fail.
BufferNotInRAM,
}
@@ -74,9 +70,13 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
let s = T::state();
#[cfg(feature = "_nrf52832_anomaly_109")]
- if r.events_started.read().bits() != 0 {
- s.waker.wake();
- r.intenclr.write(|w| w.started().clear());
+ {
+ // Ideally we should call this only during the first chunk transfer,
+ // but so far calling this every time doesn't seem to be causing any issues.
+ if r.events_started.read().bits() != 0 {
+ s.waker.wake();
+ r.intenclr.write(|w| w.started().clear());
+ }
}
if r.events_end.read().bits() != 0 {
@@ -209,35 +209,39 @@ impl<'d, T: Instance> Spim<'d, T> {
spim
}
- fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
- slice_in_ram_or(tx, Error::BufferNotInRAM)?;
- // NOTE: RAM slice check for rx is not necessary, as a mutable
- // slice can only be built from data located in RAM.
-
+ fn prepare_dma_transfer(&mut self, rx: *mut [u8], tx: *const [u8], offset: usize, length: usize) {
compiler_fence(Ordering::SeqCst);
let r = T::regs();
- // Set up the DMA write.
- let (ptr, tx_len) = slice_ptr_parts(tx);
- if tx_len > EASY_DMA_SIZE {
- return Err(Error::TxBufferTooLong);
+ fn xfer_params(ptr: u32, total: usize, offset: usize, length: usize) -> (u32, usize) {
+ if total > offset {
+ (ptr.wrapping_add(offset as _), core::cmp::min(total - offset, length))
+ } else {
+ (ptr, 0)
+ }
}
- r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
- r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(tx_len as _) });
-
// Set up the DMA read.
- let (ptr, rx_len) = slice_ptr_parts_mut(rx);
- if rx_len > EASY_DMA_SIZE {
- return Err(Error::RxBufferTooLong);
- }
-
- r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
+ let (ptr, len) = slice_ptr_parts_mut(rx);
+ let (rx_ptr, rx_len) = xfer_params(ptr as _, len as _, offset, length);
+ r.rxd.ptr.write(|w| unsafe { w.ptr().bits(rx_ptr) });
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(rx_len as _) });
+ // Set up the DMA write.
+ let (ptr, len) = slice_ptr_parts(tx);
+ let (tx_ptr, tx_len) = xfer_params(ptr as _, len as _, offset, length);
+ r.txd.ptr.write(|w| unsafe { w.ptr().bits(tx_ptr) });
+ r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(tx_len as _) });
+
+ /*
+ trace!("XFER: offset: {}, length: {}", offset, length);
+ trace!("RX(len: {}, ptr: {=u32:02x})", rx_len, rx_ptr as u32);
+ trace!("TX(len: {}, ptr: {=u32:02x})", tx_len, tx_ptr as u32);
+ */
+
#[cfg(feature = "_nrf52832_anomaly_109")]
- {
+ if offset == 0 {
let s = T::state();
r.events_started.reset();
@@ -260,21 +264,32 @@ impl<'d, T: Instance> Spim<'d, T> {
// Start SPI transaction.
r.tasks_start.write(|w| unsafe { w.bits(1) });
-
- Ok(())
}
- fn blocking_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
- self.prepare(rx, tx)?;
+ fn blocking_inner_from_ram_chunk(&mut self, rx: *mut [u8], tx: *const [u8], offset: usize, length: usize) {
+ self.prepare_dma_transfer(rx, tx, offset, length);
#[cfg(feature = "_nrf52832_anomaly_109")]
- while let Poll::Pending = self.nrf52832_dma_workaround_status() {}
+ if offset == 0 {
+ while self.nrf52832_dma_workaround_status().is_pending() {}
+ }
// Wait for 'end' event.
while T::regs().events_end.read().bits() == 0 {}
compiler_fence(Ordering::SeqCst);
+ }
+ fn blocking_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
+ slice_in_ram_or(tx, Error::BufferNotInRAM)?;
+ // NOTE: RAM slice check for rx is not necessary, as a mutable
+ // slice can only be built from data located in RAM.
+
+ let xfer_len = core::cmp::max(slice_ptr_len(rx), slice_ptr_len(tx));
+ for offset in (0..xfer_len).step_by(EASY_DMA_SIZE) {
+ let length = core::cmp::min(xfer_len - offset, EASY_DMA_SIZE);
+ self.blocking_inner_from_ram_chunk(rx, tx, offset, length);
+ }
Ok(())
}
@@ -287,22 +302,23 @@ impl<'d, T: Instance> Spim<'d, T> {
tx_ram_buf.copy_from_slice(tx);
self.blocking_inner_from_ram(rx, tx_ram_buf)
}
- Err(error) => Err(error),
}
}
- async fn async_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
- self.prepare(rx, tx)?;
+ async fn async_inner_from_ram_chunk(&mut self, rx: *mut [u8], tx: *const [u8], offset: usize, length: usize) {
+ self.prepare_dma_transfer(rx, tx, offset, length);
#[cfg(feature = "_nrf52832_anomaly_109")]
- poll_fn(|cx| {
- let s = T::state();
+ if offset == 0 {
+ poll_fn(|cx| {
+ let s = T::state();
- s.waker.register(cx.waker());
+ s.waker.register(cx.waker());
- self.nrf52832_dma_workaround_status()
- })
- .await;
+ self.nrf52832_dma_workaround_status()
+ })
+ .await;
+ }
// Wait for 'end' event.
poll_fn(|cx| {
@@ -316,7 +332,18 @@ impl<'d, T: Instance> Spim<'d, T> {
.await;
compiler_fence(Ordering::SeqCst);
+ }
+ async fn async_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
+ slice_in_ram_or(tx, Error::BufferNotInRAM)?;
+ // NOTE: RAM slice check for rx is not necessary, as a mutable
+ // slice can only be built from data located in RAM.
+
+ let xfer_len = core::cmp::max(slice_ptr_len(rx), slice_ptr_len(tx));
+ for offset in (0..xfer_len).step_by(EASY_DMA_SIZE) {
+ let length = core::cmp::min(xfer_len - offset, EASY_DMA_SIZE);
+ self.async_inner_from_ram_chunk(rx, tx, offset, length).await;
+ }
Ok(())
}
@@ -329,7 +356,6 @@ impl<'d, T: Instance> Spim<'d, T> {
tx_ram_buf.copy_from_slice(tx);
self.async_inner_from_ram(rx, tx_ram_buf).await
}
- Err(error) => Err(error),
}
}
@@ -528,8 +554,6 @@ mod eh02 {
impl embedded_hal_1::spi::Error for Error {
fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
match *self {
- Self::TxBufferTooLong => embedded_hal_1::spi::ErrorKind::Other,
- Self::RxBufferTooLong => embedded_hal_1::spi::ErrorKind::Other,
Self::BufferNotInRAM => embedded_hal_1::spi::ErrorKind::Other,
}
}
diff --git a/embassy-nrf/src/util.rs b/embassy-nrf/src/util.rs
index b408c517b..6cdb97f08 100644
--- a/embassy-nrf/src/util.rs
+++ b/embassy-nrf/src/util.rs
@@ -4,6 +4,19 @@ use core::mem;
const SRAM_LOWER: usize = 0x2000_0000;
const SRAM_UPPER: usize = 0x3000_0000;
+// #![feature(const_slice_ptr_len)]
+// https://github.com/rust-lang/rust/issues/71146
+pub(crate) fn slice_ptr_len<T>(ptr: *const [T]) -> usize {
+ use core::ptr::NonNull;
+ let ptr = ptr.cast_mut();
+ if let Some(ptr) = NonNull::new(ptr) {
+ ptr.len()
+ } else {
+ // We know ptr is null, so we know ptr.wrapping_byte_add(1) is not null.
+ NonNull::new(ptr.wrapping_byte_add(1)).unwrap().len()
+ }
+}
+
// TODO: replace transmutes with core::ptr::metadata once it's stable
pub(crate) fn slice_ptr_parts<T>(slice: *const [T]) -> (*const T, usize) {
unsafe { mem::transmute(slice) }
From 5b7eff65417e491fa7908dfd8b62013efb55d30b Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Thu, 15 Feb 2024 23:56:26 +0100
Subject: [PATCH 214/392] [embassy-stm32]: started stm32g4 RCC refactor
* Copied API from f.rs where applicable
* HSE and HSI independantly configurable
* Boost mode set by user rather
* Added HSE, pll1_q and pll1_p frequencies to set_clocks call
* Stubbed max module based on f.rs, needs cleanup
---
embassy-stm32/src/rcc/g4.rs | 204 +++++++++++++++----------
examples/stm32g4/src/bin/adc.rs | 16 +-
examples/stm32g4/src/bin/pll.rs | 16 +-
examples/stm32g4/src/bin/usb_serial.rs | 33 ++--
4 files changed, 160 insertions(+), 109 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 3e20bf6af..edd14ab23 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -1,10 +1,10 @@
use stm32_metapac::flash::vals::Latency;
-use stm32_metapac::rcc::vals::{Adcsel, Pllsrc, Sw};
+use stm32_metapac::rcc::vals::{Adcsel, Sw};
use stm32_metapac::FLASH;
pub use crate::pac::rcc::vals::{
- Adcsel as AdcClockSource, Fdcansel as FdCanClockSource, Hpre as AHBPrescaler, Pllm as PllM, Plln as PllN,
- Pllp as PllP, Pllq as PllQ, Pllr as PllR, Ppre as APBPrescaler,
+ Adcsel as AdcClockSource, Clk48sel, Fdcansel as FdCanClockSource, Hpre as AHBPrescaler, Pllm as PllPreDiv,
+ Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc, Ppre as APBPrescaler, Sw as Sysclk,
};
use crate::pac::{PWR, RCC};
use crate::time::Hertz;
@@ -12,28 +12,20 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum ClockSrc {
- HSE(Hertz),
- HSI,
- PLL,
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+ /// crystal/ceramic oscillator (HSEBYP=0)
+ Oscillator,
+ /// external analog clock (low swing) (HSEBYP=1)
+ Bypass,
}
-/// PLL clock input source
-#[derive(Clone, Copy, Debug)]
-pub enum PllSource {
- HSI,
- HSE(Hertz),
-}
-
-impl Into<Pllsrc> for PllSource {
- fn into(self) -> Pllsrc {
- match self {
- PllSource::HSE(..) => Pllsrc::HSE,
- PllSource::HSI => Pllsrc::HSI,
- }
- }
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+ /// HSE frequency.
+ pub freq: Hertz,
+ /// HSE mode.
+ pub mode: HseMode,
}
/// PLL Configuration
@@ -43,22 +35,22 @@ impl Into<Pllsrc> for PllSource {
/// frequency ranges for each of these settings.
pub struct Pll {
/// PLL Source clock selection.
- pub source: PllSource,
+ pub source: Pllsrc,
/// PLL pre-divider
- pub prediv_m: PllM,
+ pub prediv: PllPreDiv,
/// PLL multiplication factor for VCO
- pub mul_n: PllN,
+ pub mul: PllMul,
/// PLL division factor for P clock (ADC Clock)
- pub div_p: Option<PllP>,
+ pub divp: Option<PllPDiv>,
/// PLL division factor for Q clock (USB, I2S23, SAI1, FDCAN, QSPI)
- pub div_q: Option<PllQ>,
+ pub divq: Option<PllQDiv>,
/// PLL division factor for R clock (SYSCLK)
- pub div_r: Option<PllR>,
+ pub divr: Option<PllRDiv>,
}
/// Sets the source for the 48MHz clock to the USB and RNG peripherals.
@@ -73,39 +65,53 @@ pub enum Clock48MhzSrc {
}
/// Clocks configutation
+#[non_exhaustive]
pub struct Config {
- pub mux: ClockSrc,
+ pub hsi: bool,
+ pub hse: Option<Hse>,
+ pub sys: Sysclk,
+ pub hsi48: Option<super::Hsi48Config>,
+
+ pub pll: Option<Pll>,
+
+ /// Iff PLL is requested as the main clock source in the `mux` field then the PLL configuration
+ /// MUST turn on the PLLR output.
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub low_power_run: bool,
- /// Iff PLL is requested as the main clock source in the `mux` field then the PLL configuration
- /// MUST turn on the PLLR output.
- pub pll: Option<Pll>,
+
/// Sets the clock source for the 48MHz clock used by the USB and RNG peripherals.
- pub clock_48mhz_src: Option<Clock48MhzSrc>,
+ pub clk48_src: Option<Clock48MhzSrc>,
+
+ pub ls: super::LsConfig,
+
pub adc12_clock_source: AdcClockSource,
pub adc345_clock_source: AdcClockSource,
pub fdcan_clock_source: FdCanClockSource,
- pub ls: super::LsConfig,
+ pub boost: bool,
}
impl Default for Config {
#[inline]
fn default() -> Config {
Config {
- mux: ClockSrc::HSI,
+ hsi: true,
+ hse: None,
+ sys: Sysclk::HSI,
+ hsi48: Some(Default::default()),
+ pll: None,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
low_power_run: false,
- pll: None,
- clock_48mhz_src: Some(Clock48MhzSrc::Hsi48(Default::default())),
+ clk48_src: Some(Clock48MhzSrc::Hsi48(Default::default())),
+ ls: Default::default(),
adc12_clock_source: Adcsel::DISABLE,
adc345_clock_source: Adcsel::DISABLE,
fdcan_clock_source: FdCanClockSource::PCLK1,
- ls: Default::default(),
+ boost: false,
}
}
}
@@ -117,34 +123,60 @@ pub struct PllFreq {
}
pub(crate) unsafe fn init(config: Config) {
+ // Configure HSI
+ let hsi = match config.hsi {
+ false => {
+ RCC.cr().modify(|w| w.set_hsion(false));
+ None
+ }
+ true => {
+ RCC.cr().modify(|w| w.set_hsion(true));
+ while !RCC.cr().read().hsirdy() {}
+ Some(HSI_FREQ)
+ }
+ };
+
+ // Configure HSE
+ let hse = match config.hse {
+ None => {
+ RCC.cr().modify(|w| w.set_hseon(false));
+ None
+ }
+ Some(hse) => {
+ match hse.mode {
+ HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+ HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+ }
+
+ RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+ RCC.cr().modify(|w| w.set_hseon(true));
+ while !RCC.cr().read().hserdy() {}
+ Some(hse.freq)
+ }
+ };
+
let pll_freq = config.pll.map(|pll_config| {
let src_freq = match pll_config.source {
- PllSource::HSI => {
- RCC.cr().write(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
-
- HSI_FREQ
- }
- PllSource::HSE(freq) => {
- RCC.cr().write(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
- freq
- }
+ Pllsrc::HSI => unwrap!(hsi),
+ Pllsrc::HSE => unwrap!(hse),
+ _ => unreachable!(),
};
+ // TODO: check PLL input, internal and output frequencies for validity
+
// Disable PLL before configuration
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
- let internal_freq = src_freq / pll_config.prediv_m * pll_config.mul_n;
+ let internal_freq = src_freq / pll_config.prediv * pll_config.mul;
RCC.pllcfgr().write(|w| {
- w.set_plln(pll_config.mul_n);
- w.set_pllm(pll_config.prediv_m);
+ w.set_plln(pll_config.mul);
+ w.set_pllm(pll_config.prediv);
w.set_pllsrc(pll_config.source.into());
});
- let pll_p_freq = pll_config.div_p.map(|div_p| {
+ let pll_p_freq = pll_config.divp.map(|div_p| {
RCC.pllcfgr().modify(|w| {
w.set_pllp(div_p);
w.set_pllpen(true);
@@ -152,7 +184,7 @@ pub(crate) unsafe fn init(config: Config) {
internal_freq / div_p
});
- let pll_q_freq = pll_config.div_q.map(|div_q| {
+ let pll_q_freq = pll_config.divq.map(|div_q| {
RCC.pllcfgr().modify(|w| {
w.set_pllq(div_q);
w.set_pllqen(true);
@@ -160,7 +192,7 @@ pub(crate) unsafe fn init(config: Config) {
internal_freq / div_q
});
- let pll_r_freq = pll_config.div_r.map(|div_r| {
+ let pll_r_freq = pll_config.divr.map(|div_r| {
RCC.pllcfgr().modify(|w| {
w.set_pllr(div_r);
w.set_pllren(true);
@@ -179,22 +211,10 @@ pub(crate) unsafe fn init(config: Config) {
}
});
- let (sys_clk, sw) = match config.mux {
- ClockSrc::HSI => {
- // Enable HSI
- RCC.cr().write(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
-
- (HSI_FREQ, Sw::HSI)
- }
- ClockSrc::HSE(freq) => {
- // Enable HSE
- RCC.cr().write(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
-
- (freq, Sw::HSE)
- }
- ClockSrc::PLL => {
+ let (sys_clk, sw) = match config.sys {
+ Sysclk::HSI => (HSI_FREQ, Sw::HSI),
+ Sysclk::HSE => (unwrap!(hse), Sw::HSE),
+ Sysclk::PLL1_R => {
assert!(pll_freq.is_some());
assert!(pll_freq.as_ref().unwrap().pll_r.is_some());
@@ -202,10 +222,9 @@ pub(crate) unsafe fn init(config: Config) {
assert!(freq <= 170_000_000);
- if freq >= 150_000_000 {
- // Enable Core Boost mode on freq >= 150Mhz ([RM0440] p234)
+ if config.boost {
+ // Enable Core Boost mode ([RM0440] p234)
PWR.cr5().modify(|w| w.set_r1mode(false));
- // Set flash wait state in boost mode based on frequency ([RM0440] p191)
if freq <= 36_000_000 {
FLASH.acr().modify(|w| w.set_latency(Latency::WS0));
} else if freq <= 68_000_000 {
@@ -218,8 +237,8 @@ pub(crate) unsafe fn init(config: Config) {
FLASH.acr().modify(|w| w.set_latency(Latency::WS4));
}
} else {
+ // Enable Core Boost mode ([RM0440] p234)
PWR.cr5().modify(|w| w.set_r1mode(true));
- // Set flash wait state in normal mode based on frequency ([RM0440] p191)
if freq <= 30_000_000 {
FLASH.acr().modify(|w| w.set_latency(Latency::WS0));
} else if freq <= 60_000_000 {
@@ -235,6 +254,7 @@ pub(crate) unsafe fn init(config: Config) {
(Hertz(freq), Sw::PLL1_R)
}
+ _ => unreachable!(),
};
RCC.cfgr().modify(|w| {
@@ -263,7 +283,7 @@ pub(crate) unsafe fn init(config: Config) {
};
// Setup the 48 MHz clock if needed
- if let Some(clock_48mhz_src) = config.clock_48mhz_src {
+ if let Some(clock_48mhz_src) = config.clk48_src {
let source = match clock_48mhz_src {
Clock48MhzSrc::PllQ => {
// Make sure the PLLQ is enabled and running at 48Mhz
@@ -317,9 +337,33 @@ pub(crate) unsafe fn init(config: Config) {
pclk2_tim: Some(apb2_tim_freq),
adc: adc12_ck,
adc34: adc345_ck,
- pll1_p: None,
- pll1_q: None, // TODO
- hse: None, // TODO
+ pll1_p: pll_freq.as_ref().and_then(|pll| pll.pll_p),
+ pll1_q: pll_freq.as_ref().and_then(|pll| pll.pll_p),
+ hse: hse,
rtc: rtc,
);
}
+
+// TODO: if necessary, make more of these gated behind cfg attrs
+mod max {
+ use core::ops::RangeInclusive;
+
+ use crate::time::Hertz;
+
+ /// HSE 4-48MHz (RM0440 p280)
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(48_000_000);
+
+ /// External Clock ?-48MHz (RM0440 p280)
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+
+ /// SYSCLK ?-170MHz (RM0440 p282)
+ pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
+
+ /// PLL Output frequency ?-170MHz (RM0440 p281)
+ pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
+
+ // Left over from f.rs, remove if not necessary
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
+ pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
+}
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index 35324d931..99e3ef63b 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -4,7 +4,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
-use embassy_stm32::rcc::{AdcClockSource, ClockSrc, Pll, PllM, PllN, PllR, PllSource};
+use embassy_stm32::rcc::{AdcClockSource, Pll, PllMul, PllPreDiv, PllRDiv, Pllsrc, Sysclk};
use embassy_stm32::Config;
use embassy_time::{Delay, Timer};
use {defmt_rtt as _, panic_probe as _};
@@ -14,17 +14,17 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.pll = Some(Pll {
- source: PllSource::HSI,
- prediv_m: PllM::DIV4,
- mul_n: PllN::MUL85,
- div_p: None,
- div_q: None,
+ source: Pllsrc::HSI,
+ prediv: PllPreDiv::DIV4,
+ mul: PllMul::MUL85,
+ divp: None,
+ divq: None,
// Main system clock at 170 MHz
- div_r: Some(PllR::DIV2),
+ divr: Some(PllRDiv::DIV2),
});
config.rcc.adc12_clock_source = AdcClockSource::SYS;
- config.rcc.mux = ClockSrc::PLL;
+ config.rcc.sys = Sysclk::PLL1_R;
let mut p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/examples/stm32g4/src/bin/pll.rs b/examples/stm32g4/src/bin/pll.rs
index 46ebe0b0d..5274de79d 100644
--- a/examples/stm32g4/src/bin/pll.rs
+++ b/examples/stm32g4/src/bin/pll.rs
@@ -3,7 +3,7 @@
use defmt::*;
use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, Pll, PllM, PllN, PllR, PllSource};
+use embassy_stm32::rcc::{Pll, PllMul, PllPreDiv, PllRDiv, Pllsrc, Sysclk};
use embassy_stm32::Config;
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
@@ -13,16 +13,16 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.pll = Some(Pll {
- source: PllSource::HSI,
- prediv_m: PllM::DIV4,
- mul_n: PllN::MUL85,
- div_p: None,
- div_q: None,
+ source: Pllsrc::HSI,
+ prediv: PllPreDiv::DIV4,
+ mul: PllMul::MUL85,
+ divp: None,
+ divq: None,
// Main system clock at 170 MHz
- div_r: Some(PllR::DIV2),
+ divr: Some(PllRDiv::DIV2),
});
- config.rcc.mux = ClockSrc::PLL;
+ config.rcc.sys = Sysclk::PLL1_R;
let _p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index c26fa76b7..d9207e4cd 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -3,7 +3,9 @@
use defmt::{panic, *};
use embassy_executor::Spawner;
-use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSource};
+use embassy_stm32::rcc::{
+ Clock48MhzSrc, Hse, HseMode, Hsi48Config, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, Pllsrc, Sysclk,
+};
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{self, Driver, Instance};
use embassy_stm32::{bind_interrupts, peripherals, Config};
@@ -24,25 +26,30 @@ async fn main(_spawner: Spawner) {
// Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
const USE_HSI48: bool = true;
- let plldivq = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
+ let plldivq = if USE_HSI48 { None } else { Some(PllQDiv::DIV6) };
- config.rcc.pll = Some(Pll {
- source: PllSource::HSE(Hertz(8_000_000)),
- prediv_m: PllM::DIV2,
- mul_n: PllN::MUL72,
- div_p: None,
- div_q: plldivq,
- // Main system clock at 144 MHz
- div_r: Some(PllR::DIV2),
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(8_000_000),
+ mode: HseMode::Oscillator,
});
- config.rcc.mux = ClockSrc::PLL;
+ config.rcc.pll = Some(Pll {
+ source: Pllsrc::HSE,
+ prediv: PllPreDiv::DIV2,
+ mul: PllMul::MUL72,
+ divp: None,
+ divq: plldivq,
+ // Main system clock at 144 MHz
+ divr: Some(PllRDiv::DIV2),
+ });
+
+ config.rcc.sys = Sysclk::PLL1_R;
if USE_HSI48 {
// Sets up the Clock Recovery System (CRS) to use the USB SOF to trim the HSI48 oscillator.
- config.rcc.clock_48mhz_src = Some(Clock48MhzSrc::Hsi48(Hsi48Config { sync_from_usb: true }));
+ config.rcc.clk48_src = Some(Clock48MhzSrc::Hsi48(Hsi48Config { sync_from_usb: true }));
} else {
- config.rcc.clock_48mhz_src = Some(Clock48MhzSrc::PllQ);
+ config.rcc.clk48_src = Some(Clock48MhzSrc::PllQ);
}
let p = embassy_stm32::init(config);
From bd0b450ca4ff36b2b1fe0b3b422cd478f9201ad0 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Thu, 15 Feb 2024 17:43:20 -0500
Subject: [PATCH 215/392] Improve rp2040 i2c slave
This commit takes the fixes and error reporting improvements from
jcdickinson's work and applies them without overlaying a software state
machine on top of the hardware state machine.
Also allows configuration of response to 'general call' writes.
---
embassy-rp/src/i2c_slave.rs | 234 +++++++++++++++++++------------
examples/rp/src/bin/i2c_slave.rs | 2 +-
2 files changed, 147 insertions(+), 89 deletions(-)
diff --git a/embassy-rp/src/i2c_slave.rs b/embassy-rp/src/i2c_slave.rs
index 721b7a1f6..d3cc20f39 100644
--- a/embassy-rp/src/i2c_slave.rs
+++ b/embassy-rp/src/i2c_slave.rs
@@ -4,6 +4,7 @@ use core::marker::PhantomData;
use core::task::Poll;
use embassy_hal_internal::into_ref;
+use embassy_time::{block_for, Duration};
use pac::i2c;
use crate::i2c::{
@@ -21,6 +22,16 @@ pub enum Error {
Abort(AbortReason),
/// User passed in a response buffer that was 0 length
InvalidResponseBufferLength,
+ /// The response buffer length was too short to contain the message
+ ///
+ /// The length parameter will always be the length of the buffer, and is
+ /// provided as a convenience for matching alongside `Command::Write`.
+ PartialWrite(usize),
+ /// The response buffer length was too short to contain the message
+ ///
+ /// The length parameter will always be the length of the buffer, and is
+ /// provided as a convenience for matching alongside `Command::GeneralCall`.
+ PartialGeneralCall(usize),
}
/// Received command
@@ -56,17 +67,23 @@ pub enum ReadStatus {
pub struct Config {
/// Target Address
pub addr: u16,
+ /// Control if the peripheral should ack to and report general calls.
+ pub general_call: bool,
}
impl Default for Config {
fn default() -> Self {
- Self { addr: 0x55 }
+ Self {
+ addr: 0x55,
+ general_call: true,
+ }
}
}
/// I2CSlave driver.
pub struct I2cSlave<'d, T: Instance> {
phantom: PhantomData<&'d mut T>,
+ pending_byte: Option<u8>,
}
impl<'d, T: Instance> I2cSlave<'d, T> {
@@ -96,7 +113,19 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
w.set_master_mode(false);
w.set_ic_slave_disable(false);
w.set_tx_empty_ctrl(true);
+ w.set_rx_fifo_full_hld_ctrl(true);
+
+ // This typically makes no sense for a slave, but it is used to
+ // tune spike suppression, according to the datasheet.
+ w.set_speed(pac::i2c::vals::Speed::FAST);
+
+ // Generate stop interrupts for general calls
+ // This also causes stop interrupts for other devices on the bus but those will not be
+ // propagated up to the application.
+ w.set_stop_det_ifaddressed(!config.general_call);
});
+ p.ic_ack_general_call()
+ .write(|w| w.set_ack_gen_call(config.general_call));
// Set FIFO watermarks to 1 to make things simpler. This is encoded
// by a register value of 0. Rx watermark should never change, but Tx watermark will be
@@ -119,7 +148,10 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
- Self { phantom: PhantomData }
+ Self {
+ phantom: PhantomData,
+ pending_byte: None,
+ }
}
/// Calls `f` to check if we are ready or not.
@@ -133,8 +165,6 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
future::poll_fn(|cx| {
let r = f(self);
- trace!("intr p: {:013b}", T::regs().ic_raw_intr_stat().read().0);
-
if r.is_pending() {
T::waker().register(cx.waker());
g(self);
@@ -146,14 +176,36 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
}
#[inline(always)]
- fn drain_fifo(&mut self, buffer: &mut [u8], offset: usize) -> usize {
+ fn drain_fifo(&mut self, buffer: &mut [u8], offset: &mut usize) {
let p = T::regs();
- let len = p.ic_rxflr().read().rxflr() as usize;
- let end = offset + len;
- for i in offset..end {
- buffer[i] = p.ic_data_cmd().read().dat();
+
+ for b in &mut buffer[*offset..] {
+ if let Some(pending) = self.pending_byte.take() {
+ *b = pending;
+ *offset += 1;
+ continue;
+ }
+
+ let status = p.ic_status().read();
+ if !status.rfne() {
+ break;
+ }
+
+ let dat = p.ic_data_cmd().read();
+ if *offset != 0 && dat.first_data_byte() {
+ // The RP2040 state machine will keep placing bytes into the
+ // FIFO, even if they are part of a subsequent write transaction.
+ //
+ // Unfortunately merely reading ic_data_cmd will consume that
+ // byte, the first byte of the next transaction, so we need
+ // to store it elsewhere
+ self.pending_byte = Some(dat.dat());
+ break;
+ }
+
+ *b = dat.dat();
+ *offset += 1;
}
- end
}
#[inline(always)]
@@ -165,52 +217,62 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
}
/// Wait asynchronously for commands from an I2C master.
- /// `buffer` is provided in case master does a 'write' and is unused for 'read'.
+ /// `buffer` is provided in case master does a 'write', 'write read', or 'general call' and is unused for 'read'.
pub async fn listen(&mut self, buffer: &mut [u8]) -> Result<Command, Error> {
let p = T::regs();
- p.ic_clr_intr().read();
// set rx fifo watermark to 1 byte
p.ic_rx_tl().write(|w| w.set_rx_tl(0));
let mut len = 0;
- let ret = self
- .wait_on(
- |me| {
- let stat = p.ic_raw_intr_stat().read();
- if p.ic_rxflr().read().rxflr() > 0 {
- len = me.drain_fifo(buffer, len);
- // we're recieving data, set rx fifo watermark to 12 bytes to reduce interrupt noise
- p.ic_rx_tl().write(|w| w.set_rx_tl(11));
- }
+ self.wait_on(
+ |me| {
+ let stat = p.ic_raw_intr_stat().read();
- if stat.restart_det() && stat.rd_req() {
- Poll::Ready(Ok(Command::WriteRead(len)))
- } else if stat.gen_call() && stat.stop_det() && len > 0 {
- Poll::Ready(Ok(Command::GeneralCall(len)))
- } else if stat.stop_det() {
- Poll::Ready(Ok(Command::Write(len)))
- } else if stat.rd_req() {
- Poll::Ready(Ok(Command::Read))
+ if p.ic_rxflr().read().rxflr() > 0 {
+ me.drain_fifo(buffer, &mut len);
+ // we're recieving data, set rx fifo watermark to 12 bytes (3/4 full) to reduce interrupt noise
+ p.ic_rx_tl().write(|w| w.set_rx_tl(11));
+ }
+
+ if buffer.len() == len {
+ if stat.gen_call() {
+ return Poll::Ready(Err(Error::PartialGeneralCall(buffer.len())));
} else {
- Poll::Pending
+ return Poll::Ready(Err(Error::PartialWrite(buffer.len())));
}
- },
- |_me| {
- p.ic_intr_mask().modify(|w| {
- w.set_m_stop_det(true);
- w.set_m_restart_det(true);
- w.set_m_gen_call(true);
- w.set_m_rd_req(true);
- w.set_m_rx_full(true);
- });
- },
- )
- .await;
+ }
- p.ic_clr_intr().read();
-
- ret
+ if stat.restart_det() && stat.rd_req() {
+ p.ic_clr_restart_det().read();
+ Poll::Ready(Ok(Command::WriteRead(len)))
+ } else if stat.gen_call() && stat.stop_det() && len > 0 {
+ p.ic_clr_gen_call().read();
+ p.ic_clr_stop_det().read();
+ Poll::Ready(Ok(Command::GeneralCall(len)))
+ } else if stat.stop_det() && len > 0 {
+ p.ic_clr_stop_det().read();
+ Poll::Ready(Ok(Command::Write(len)))
+ } else if stat.rd_req() {
+ p.ic_clr_stop_det().read();
+ p.ic_clr_restart_det().read();
+ p.ic_clr_gen_call().read();
+ Poll::Ready(Ok(Command::Read))
+ } else {
+ Poll::Pending
+ }
+ },
+ |_me| {
+ p.ic_intr_mask().modify(|w| {
+ w.set_m_stop_det(true);
+ w.set_m_restart_det(true);
+ w.set_m_gen_call(true);
+ w.set_m_rd_req(true);
+ w.set_m_rx_full(true);
+ });
+ },
+ )
+ .await
}
/// Respond to an I2C master READ command, asynchronously.
@@ -223,47 +285,47 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
let mut chunks = buffer.chunks(FIFO_SIZE as usize);
- let ret = self
- .wait_on(
- |me| {
- if let Err(abort_reason) = me.read_and_clear_abort_reason() {
- if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
- return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
- } else {
- return Poll::Ready(Err(abort_reason));
- }
- }
-
- if let Some(chunk) = chunks.next() {
- me.write_to_fifo(chunk);
-
- Poll::Pending
+ self.wait_on(
+ |me| {
+ if let Err(abort_reason) = me.read_and_clear_abort_reason() {
+ if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
+ p.ic_clr_intr().read();
+ return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
} else {
- let stat = p.ic_raw_intr_stat().read();
-
- if stat.rx_done() && stat.stop_det() {
- Poll::Ready(Ok(ReadStatus::Done))
- } else if stat.rd_req() {
- Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
- } else {
- Poll::Pending
- }
+ return Poll::Ready(Err(abort_reason));
}
- },
- |_me| {
- p.ic_intr_mask().modify(|w| {
- w.set_m_stop_det(true);
- w.set_m_rx_done(true);
- w.set_m_tx_empty(true);
- w.set_m_tx_abrt(true);
- })
- },
- )
- .await;
+ }
- p.ic_clr_intr().read();
+ if let Some(chunk) = chunks.next() {
+ me.write_to_fifo(chunk);
- ret
+ p.ic_clr_rd_req().read();
+
+ Poll::Pending
+ } else {
+ let stat = p.ic_raw_intr_stat().read();
+
+ if stat.rx_done() && stat.stop_det() {
+ p.ic_clr_rx_done().read();
+ p.ic_clr_stop_det().read();
+ Poll::Ready(Ok(ReadStatus::Done))
+ } else if stat.rd_req() && stat.tx_empty() {
+ Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
+ } else {
+ Poll::Pending
+ }
+ }
+ },
+ |_me| {
+ p.ic_intr_mask().modify(|w| {
+ w.set_m_stop_det(true);
+ w.set_m_rx_done(true);
+ w.set_m_tx_empty(true);
+ w.set_m_tx_abrt(true);
+ })
+ },
+ )
+ .await
}
/// Respond to reads with the fill byte until the controller stops asking
@@ -294,10 +356,6 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
let p = T::regs();
let mut abort_reason = p.ic_tx_abrt_source().read();
- // Mask off fifo flush count
- let tx_flush_cnt = abort_reason.tx_flush_cnt();
- abort_reason.set_tx_flush_cnt(0);
-
// Mask off master_dis
abort_reason.set_abrt_master_dis(false);
@@ -314,8 +372,8 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
AbortReason::NoAcknowledge
} else if abort_reason.arb_lost() {
AbortReason::ArbitrationLoss
- } else if abort_reason.abrt_slvflush_txfifo() {
- AbortReason::TxNotEmpty(tx_flush_cnt)
+ } else if abort_reason.tx_flush_cnt() > 0 {
+ AbortReason::TxNotEmpty(abort_reason.tx_flush_cnt())
} else {
AbortReason::Other(abort_reason.0)
};
diff --git a/examples/rp/src/bin/i2c_slave.rs b/examples/rp/src/bin/i2c_slave.rs
index ac470d2be..9fffb4646 100644
--- a/examples/rp/src/bin/i2c_slave.rs
+++ b/examples/rp/src/bin/i2c_slave.rs
@@ -110,7 +110,7 @@ async fn main(spawner: Spawner) {
let c_sda = p.PIN_1;
let c_scl = p.PIN_0;
let mut config = i2c::Config::default();
- config.frequency = 5_000;
+ config.frequency = 1_000_000;
let controller = i2c::I2c::new_async(p.I2C0, c_sda, c_scl, Irqs, config);
unwrap!(spawner.spawn(controller_task(controller)));
From 396041ad1a954a09bb2cf45ea685ca8a1bbd8623 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 16 Feb 2024 00:04:35 +0100
Subject: [PATCH 216/392] Commented out currently unused constants
---
embassy-stm32/src/rcc/g4.rs | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index edd14ab23..c9ac2bb0b 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -357,13 +357,13 @@ mod max {
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
/// SYSCLK ?-170MHz (RM0440 p282)
- pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
+ //pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
/// PLL Output frequency ?-170MHz (RM0440 p281)
- pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
+ //pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
// Left over from f.rs, remove if not necessary
- pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
- pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
- pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
+ //pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
+ //pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
+ //pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
}
From a75007f5ccff25e5bc3afcc806ceb197f61be0bf Mon Sep 17 00:00:00 2001
From: DafabHoid <github@dafabhoid.de>
Date: Fri, 16 Feb 2024 00:30:24 +0100
Subject: [PATCH 217/392] cyw43: Reuse buf to reduce stack usage
---
cyw43/src/runner.rs | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/cyw43/src/runner.rs b/cyw43/src/runner.rs
index b2a9e3e80..c72cf0def 100644
--- a/cyw43/src/runner.rs
+++ b/cyw43/src/runner.rs
@@ -242,13 +242,12 @@ where
cmd,
iface,
}) => {
- self.send_ioctl(kind, cmd, iface, unsafe { &*iobuf }).await;
+ self.send_ioctl(kind, cmd, iface, unsafe { &*iobuf }, &mut buf).await;
self.check_status(&mut buf).await;
}
Either3::Second(packet) => {
trace!("tx pkt {:02x}", Bytes(&packet[..packet.len().min(48)]));
- let mut buf = [0; 512];
let buf8 = slice8_mut(&mut buf);
// There MUST be 2 bytes of padding between the SDPCM and BDC headers.
@@ -480,9 +479,8 @@ where
self.sdpcm_seq != self.sdpcm_seq_max && self.sdpcm_seq_max.wrapping_sub(self.sdpcm_seq) & 0x80 == 0
}
- async fn send_ioctl(&mut self, kind: IoctlType, cmd: u32, iface: u32, data: &[u8]) {
- let mut buf = [0; 512];
- let buf8 = slice8_mut(&mut buf);
+ async fn send_ioctl(&mut self, kind: IoctlType, cmd: u32, iface: u32, data: &[u8], buf: &mut [u32; 512]) {
+ let buf8 = slice8_mut(buf);
let total_len = SdpcmHeader::SIZE + CdcHeader::SIZE + data.len();
From 72e92647e2634958d2229f35264a3dc696c3d33e Mon Sep 17 00:00:00 2001
From: Adam Snaider <adam.snaider@bluerivertech.com>
Date: Thu, 15 Feb 2024 18:10:20 -0500
Subject: [PATCH 218/392] Add unsafe constructor for AnyPin
---
embassy-rp/src/gpio.rs | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index 93b29bbf9..a121a8036 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -889,6 +889,17 @@ pub struct AnyPin {
pin_bank: u8,
}
+impl AnyPin {
+ /// Unsafely create a new type-erased pin.
+ ///
+ /// # Safety
+ ///
+ /// You must ensure that you’re only using one instance of this type at a time.
+ pub unsafe fn steal(pin_bank: u8) -> Self {
+ Self { pin_bank }
+ }
+}
+
impl_peripheral!(AnyPin);
impl Pin for AnyPin {}
From ae02467434a344abbbb367123044c5e407c80a14 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Fri, 16 Feb 2024 02:07:21 +0100
Subject: [PATCH 219/392] stm32: update metapac.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/build.rs | 76 ++++++++++++------------------------
embassy-stm32/src/rcc/wba.rs | 2 +-
3 files changed, 27 insertions(+), 55 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index c384f14f1..389ed0041 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -68,7 +68,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6097928f720646c73d6483a3245f922bd5faee2f" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -89,7 +89,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-3cc1a1603e61881a6f0a1a47c12c16c57c245ba8", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6097928f720646c73d6483a3245f922bd5faee2f", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 35023bf1f..ee88d4541 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -5,8 +5,7 @@ use std::{env, fs};
use proc_macro2::{Ident, TokenStream};
use quote::{format_ident, quote};
-use stm32_metapac::metadata::ir::{BlockItemInner, Enum, FieldSet};
-use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccRegister, StopMode, METADATA};
+use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccKernelClock, StopMode, METADATA};
fn main() {
let target = env::var("TARGET").unwrap();
@@ -414,38 +413,6 @@ fn main() {
.find(|r| r.kind == "rcc")
.unwrap();
- // ========
- // Generate rcc fieldset and enum maps
- let rcc_enum_map: HashMap<&str, HashMap<&str, &Enum>> = {
- let rcc_blocks = rcc_registers.ir.blocks.iter().find(|b| b.name == "Rcc").unwrap().items;
- let rcc_fieldsets: HashMap<&str, &FieldSet> = rcc_registers.ir.fieldsets.iter().map(|f| (f.name, f)).collect();
- let rcc_enums: HashMap<&str, &Enum> = rcc_registers.ir.enums.iter().map(|e| (e.name, e)).collect();
-
- rcc_blocks
- .iter()
- .filter_map(|b| match &b.inner {
- BlockItemInner::Register(register) => register.fieldset.map(|f| (b.name, f)),
- _ => None,
- })
- .filter_map(|(b, f)| {
- rcc_fieldsets.get(f).map(|f| {
- (
- b,
- f.fields
- .iter()
- .filter_map(|f| {
- let enumm = f.enumm?;
- let enumm = rcc_enums.get(enumm)?;
-
- Some((f.name, *enumm))
- })
- .collect(),
- )
- })
- })
- .collect()
- };
-
// ========
// Generate RccPeripheral impls
@@ -494,8 +461,8 @@ fn main() {
let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
let pname = format_ident!("{}", p.name);
- let en_reg = format_ident!("{}", en.register);
- let set_en_field = format_ident!("set_{}", en.field);
+ let en_reg = format_ident!("{}", en.register.to_ascii_lowercase());
+ let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
let refcount =
force_refcount.contains(ptype) || *rcc_field_count.get(&(en.register, en.field)).unwrap() > 1;
@@ -523,21 +490,25 @@ fn main() {
(TokenStream::new(), TokenStream::new())
};
- let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
- let mux = mux?;
- let fieldset = rcc_enum_map.get(mux.register)?;
- let enumm = fieldset.get(mux.field)?;
+ let clock_frequency = match &rcc.kernel_clock {
+ PeripheralRccKernelClock::Mux(mux) => {
+ let ir = &rcc_registers.ir;
+ let fieldset_name = mux.register.to_ascii_lowercase();
+ let fieldset = ir
+ .fieldsets
+ .iter()
+ .find(|i| i.name.eq_ignore_ascii_case(&fieldset_name))
+ .unwrap();
+ let field_name = mux.field.to_ascii_lowercase();
+ let field = fieldset.fields.iter().find(|i| i.name == field_name).unwrap();
+ let enum_name = field.enumm.unwrap();
+ let enumm = ir.enums.iter().find(|i| i.name == enum_name).unwrap();
- Some((mux, *enumm))
- };
+ let fieldset_name = format_ident!("{}", fieldset_name);
+ let field_name = format_ident!("{}", field_name);
+ let enum_name = format_ident!("{}", enum_name);
- let clock_frequency = match mux_for(rcc.mux.as_ref()) {
- Some((mux, rcc_enumm)) => {
- let fieldset_name = format_ident!("{}", mux.register);
- let field_name = format_ident!("{}", mux.field);
- let enum_name = format_ident!("{}", rcc_enumm.name);
-
- let match_arms: TokenStream = rcc_enumm
+ let match_arms: TokenStream = enumm
.variants
.iter()
.filter(|v| v.name != "DISABLE")
@@ -561,9 +532,10 @@ fn main() {
}
}
}
- None => {
- let clock_name = format_ident!("{}", rcc.clock);
- clock_names.insert(rcc.clock.to_string());
+ PeripheralRccKernelClock::Clock(clock) => {
+ let clock = clock.to_ascii_lowercase();
+ let clock_name = format_ident!("{}", clock);
+ clock_names.insert(clock.to_string());
quote! {
unsafe { crate::rcc::get_freqs().#clock_name.unwrap() }
}
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 47ce4783c..fbf2d1cf9 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -49,7 +49,7 @@ impl Default for Config {
apb2_pre: APBPrescaler::DIV1,
apb7_pre: APBPrescaler::DIV1,
ls: Default::default(),
- adc_clock_source: AdcClockSource::HCLK1,
+ adc_clock_source: AdcClockSource::HCLK4,
voltage_scale: VoltageScale::RANGE2,
}
}
From 169f1ce928177a6ff85ce7e9ff5a995063b6aace Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 19:50:42 -0800
Subject: [PATCH 220/392] I believe that this enables the PLL clock input to
different TIMs for the STM32F3xx Series of chips.
---
embassy-stm32/src/rcc/f013.rs | 241 ++++++++++++++++++++++++++++++++++
1 file changed, 241 insertions(+)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index c2933186c..0d2877755 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -74,6 +74,107 @@ pub enum HrtimClockSource {
PllClk,
}
+#[cfg(all(stm32f3, not(rcc_f37)))]
+#[derive(Clone, Copy, PartialEq, Eq)]
+pub enum TimClockSource {
+ PClk2,
+ PllClk,
+}
+
+#[cfg(all(stm32f3, not(rcc_f37)))]
+#[derive(Clone, Copy)]
+pub struct TimClockSources {
+ pub tim1: TimClockSource,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ ))]
+ pub tim2: TimClockSource,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ ))]
+ pub tim34: TimClockSource,
+ #[cfg(any(
+ all(stm32f303, any(package_B, package_C, package_D, package_E)),
+ stm32f358,
+ ))]
+ pub tim8: TimClockSource,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
+ pub tim15: TimClockSource,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
+ pub tim16: TimClockSource,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
+ pub tim17: TimClockSource,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ ))]
+ pub tim20: TimClockSource
+}
+
+impl Default for TimClockSources {
+ fn default() -> Self {
+ Self {
+ tim1: TimClockSource::PClk2,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ ))]
+ tim2: TimClockSource::PClk2,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ ))]
+ tim34: TimClockSource::PClk2,
+ #[cfg(any(
+ all(stm32f303, any(package_B, package_C, package_D, package_E)),
+ stm32f358,
+ ))]
+ tim8: TimClockSource::PClk2,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
+ tim15: TimClockSource::PClk2,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
+ tim16: TimClockSource::PClk2,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
+ tim17: TimClockSource::PClk2,
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ ))]
+ tim20: TimClockSource::PClk2
+ }
+ }
+}
+
/// Clocks configutation
#[non_exhaustive]
pub struct Config {
@@ -99,6 +200,8 @@ pub struct Config {
pub adc34: AdcClockSource,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
+ #[cfg(not(stm32f37))]
+ pub tim: TimClockSources,
pub ls: super::LsConfig,
}
@@ -129,6 +232,8 @@ impl Default for Config {
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(stm32f334)]
hrtim: HrtimClockSource::BusClk,
+ #[cfg(not(stm32f37))]
+ tim: Default::default()
}
}
}
@@ -364,6 +469,126 @@ pub(crate) unsafe fn init(config: Config) {
}
};
+ #[cfg(all(stm32f3, not(rcc_f37)))]
+ let tim1 = match config.tim.tim1 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim1(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ let tim2 = match config.tim.tim2 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim2(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ let tim34 = match config.tim.tim34 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim34(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+ let tim8 = match config.tim.tim8 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim8(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ let tim15 = match config.tim.tim15 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim15(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ let tim16 = match config.tim.tim16 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim16(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ let tim17 = match config.tim.tim17 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim17(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
+ #[cfg(any(all(stm32f303, any(package_D, package_E))))]
+ let tim20 = match config.tim.tim20 {
+ TimClockSource::PClk2 => None,
+ TimClockSource::PllClk => {
+ use crate::pac::rcc::vals::Timsw;
+
+ let pll = unwrap!(pll);
+ assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+
+ RCC.cfgr3().modify(|w| w.set_tim20(Timsw::PLL1_P));
+
+ Some(pll * 2u32)
+ }
+ };
+
set_clocks!(
hsi: hsi,
hse: hse,
@@ -380,6 +605,22 @@ pub(crate) unsafe fn init(config: Config) {
adc34: Some(adc34),
#[cfg(stm32f334)]
hrtim: hrtim,
+ #[cfg(all(stm32f3, not(rcc_f37)))]
+ tim1: tim1,
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ tim2: tim2,
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ tim34: tim34,
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+ tim8: tim8,
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ tim15: tim15,
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ tim16: tim16,
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ tim17: tim17,
+ #[cfg(any(all(stm32f303, any(package_D, package_E))))]
+ tim20: tim20,
rtc: rtc,
hsi48: hsi48,
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
From 029d6383b56c45167b99ef5c5c862946410d8f52 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 20:02:25 -0800
Subject: [PATCH 221/392] Rust fmt and fix build.
---
embassy-stm32/src/rcc/f013.rs | 97 ++++++++++++++++-------------------
1 file changed, 45 insertions(+), 52 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 0d2877755..766a4a0f5 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,20 +85,11 @@ pub enum TimClockSource {
#[derive(Clone, Copy)]
pub struct TimClockSources {
pub tim1: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- ))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
pub tim2: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- ))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
pub tim34: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_B, package_C, package_D, package_E)),
- stm32f358,
- ))]
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
pub tim8: TimClockSource,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
@@ -121,30 +112,19 @@ pub struct TimClockSources {
all(stm32f302, any(package_6, package_8))
))]
pub tim17: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- ))]
- pub tim20: TimClockSource
+ #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+ pub tim20: TimClockSource,
}
impl Default for TimClockSources {
fn default() -> Self {
Self {
tim1: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- ))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
tim2: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- ))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
tim34: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_B, package_C, package_D, package_E)),
- stm32f358,
- ))]
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
tim8: TimClockSource::PClk2,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
@@ -167,10 +147,8 @@ impl Default for TimClockSources {
all(stm32f302, any(package_6, package_8))
))]
tim17: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- ))]
- tim20: TimClockSource::PClk2
+ #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+ tim20: TimClockSource::PClk2,
}
}
}
@@ -233,7 +211,7 @@ impl Default for Config {
#[cfg(stm32f334)]
hrtim: HrtimClockSource::BusClk,
#[cfg(not(stm32f37))]
- tim: Default::default()
+ tim: Default::default(),
}
}
}
@@ -476,9 +454,9 @@ pub(crate) unsafe fn init(config: Config) {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim1(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim1sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
@@ -491,9 +469,9 @@ pub(crate) unsafe fn init(config: Config) {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim2(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim2sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
@@ -506,9 +484,9 @@ pub(crate) unsafe fn init(config: Config) {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim34(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim34sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
@@ -521,54 +499,69 @@ pub(crate) unsafe fn init(config: Config) {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim8(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim8sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
};
- #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
let tim15 = match config.tim.tim15 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim15(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim15sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
};
- #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
let tim16 = match config.tim.tim16 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim16(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim16sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
};
- #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ stm32f301,
+ stm32f318,
+ all(stm32f302, any(package_6, package_8))
+ ))]
let tim17 = match config.tim.tim17 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim17(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim17sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
@@ -581,9 +574,9 @@ pub(crate) unsafe fn init(config: Config) {
use crate::pac::rcc::vals::Timsw;
let pll = unwrap!(pll);
- assert((pclk2 == pll) || (pclk2 * 2u32 == pll));
+ assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
- RCC.cfgr3().modify(|w| w.set_tim20(Timsw::PLL1_P));
+ RCC.cfgr3().modify(|w| w.set_tim20sw(Timsw::PLL1_P));
Some(pll * 2u32)
}
From f41b0f6ba95d0323f058a1ec2a2dc9b6f3317fee Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Thu, 15 Feb 2024 23:06:57 -0500
Subject: [PATCH 222/392] Remove unused imports
---
embassy-rp/src/i2c_slave.rs | 1 -
1 file changed, 1 deletion(-)
diff --git a/embassy-rp/src/i2c_slave.rs b/embassy-rp/src/i2c_slave.rs
index d3cc20f39..979686627 100644
--- a/embassy-rp/src/i2c_slave.rs
+++ b/embassy-rp/src/i2c_slave.rs
@@ -4,7 +4,6 @@ use core::marker::PhantomData;
use core::task::Poll;
use embassy_hal_internal::into_ref;
-use embassy_time::{block_for, Duration};
use pac::i2c;
use crate::i2c::{
From 4408c169a5c3961f1a5163ce6c09762988c1a471 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 22:53:00 -0800
Subject: [PATCH 223/392] Fix cfg lines
---
embassy-stm32/src/rcc/f013.rs | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 766a4a0f5..b5ec8585e 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -116,6 +116,7 @@ pub struct TimClockSources {
pub tim20: TimClockSource,
}
+#[cfg(all(stm32f3, not(rcc_f37)))]
impl Default for TimClockSources {
fn default() -> Self {
Self {
@@ -178,7 +179,7 @@ pub struct Config {
pub adc34: AdcClockSource,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
- #[cfg(not(stm32f37))]
+ #[cfg(all(stm32f3, not(stm32f37)))]
pub tim: TimClockSources,
pub ls: super::LsConfig,
@@ -210,7 +211,7 @@ impl Default for Config {
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(stm32f334)]
hrtim: HrtimClockSource::BusClk,
- #[cfg(not(stm32f37))]
+ #[cfg(all(stm32f3, not(stm32f37)))]
tim: Default::default(),
}
}
From 56b345c722aa22e778eb8551c4d019441bf5520e Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 23:12:18 -0800
Subject: [PATCH 224/392] Clean up register setting
---
embassy-stm32/src/rcc/f013.rs | 118 +++++++---------------------------
1 file changed, 23 insertions(+), 95 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index b5ec8585e..2352b057d 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -179,7 +179,7 @@ pub struct Config {
pub adc34: AdcClockSource,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
- #[cfg(all(stm32f3, not(stm32f37)))]
+ #[cfg(all(stm32f3, not(rcc_f37)))]
pub tim: TimClockSources,
pub ls: super::LsConfig,
@@ -449,62 +449,34 @@ pub(crate) unsafe fn init(config: Config) {
};
#[cfg(all(stm32f3, not(rcc_f37)))]
- let tim1 = match config.tim.tim1 {
- TimClockSource::PClk2 => None,
+ match config.tim.tim1 {
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim1sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
#[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
- let tim2 = match config.tim.tim2 {
- TimClockSource::PClk2 => None,
+ match config.tim.tim2 {
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim2sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
#[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
- let tim34 = match config.tim.tim34 {
- TimClockSource::PClk2 => None,
+ match config.tim.tim34 {
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim34sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
#[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
- let tim8 = match config.tim.tim8 {
- TimClockSource::PClk2 => None,
+ match config.tim.tim8 {
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim8sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
@@ -514,17 +486,10 @@ pub(crate) unsafe fn init(config: Config) {
stm32f318,
all(stm32f302, any(package_6, package_8))
))]
- let tim15 = match config.tim.tim15 {
+ match config.tim.tim15 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim15sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
@@ -534,17 +499,10 @@ pub(crate) unsafe fn init(config: Config) {
stm32f318,
all(stm32f302, any(package_6, package_8))
))]
- let tim16 = match config.tim.tim16 {
+ match config.tim.tim16 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim16sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
@@ -554,34 +512,20 @@ pub(crate) unsafe fn init(config: Config) {
stm32f318,
all(stm32f302, any(package_6, package_8))
))]
- let tim17 = match config.tim.tim17 {
+ match config.tim.tim17 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim17sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
- };
+ }
#[cfg(any(all(stm32f303, any(package_D, package_E))))]
- let tim20 = match config.tim.tim20 {
+ match config.tim.tim20 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- use crate::pac::rcc::vals::Timsw;
-
- let pll = unwrap!(pll);
- assert!((pclk2 == pll) || (pclk2 * 2u32 == pll));
-
- RCC.cfgr3().modify(|w| w.set_tim20sw(Timsw::PLL1_P));
-
- Some(pll * 2u32)
+ RCC.cfgr3().modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
- };
+ }
set_clocks!(
hsi: hsi,
@@ -599,22 +543,6 @@ pub(crate) unsafe fn init(config: Config) {
adc34: Some(adc34),
#[cfg(stm32f334)]
hrtim: hrtim,
- #[cfg(all(stm32f3, not(rcc_f37)))]
- tim1: tim1,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
- tim2: tim2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
- tim34: tim34,
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
- tim8: tim8,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
- tim15: tim15,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
- tim16: tim16,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), stm32f301, stm32f318, all(stm32f302, any(package_6, package_8))))]
- tim17: tim17,
- #[cfg(any(all(stm32f303, any(package_D, package_E))))]
- tim20: tim20,
rtc: rtc,
hsi48: hsi48,
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
From d28ba1d60689e5a0d5623c5ea4890663d899523a Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 23:16:17 -0800
Subject: [PATCH 225/392] rustfmt
---
embassy-stm32/src/rcc/f013.rs | 35 +++++++++++++++++++++--------------
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 2352b057d..17c734f09 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -204,14 +204,13 @@ impl Default for Config {
// ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
adc_pre: ADCPrescaler::DIV6,
-
#[cfg(all(stm32f3, not(rcc_f37)))]
adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(stm32f334)]
hrtim: HrtimClockSource::BusClk,
- #[cfg(all(stm32f3, not(stm32f37)))]
+ #[cfg(all(stm32f3, not(rcc_f37)))]
tim: Default::default(),
}
}
@@ -450,33 +449,37 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(all(stm32f3, not(rcc_f37)))]
match config.tim.tim1 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
#[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
match config.tim.tim2 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
#[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
match config.tim.tim34 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
#[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
match config.tim.tim8 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
@@ -489,7 +492,8 @@ pub(crate) unsafe fn init(config: Config) {
match config.tim.tim15 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
@@ -502,7 +506,8 @@ pub(crate) unsafe fn init(config: Config) {
match config.tim.tim16 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
};
@@ -515,7 +520,8 @@ pub(crate) unsafe fn init(config: Config) {
match config.tim.tim17 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
}
@@ -523,7 +529,8 @@ pub(crate) unsafe fn init(config: Config) {
match config.tim.tim20 {
TimClockSource::PClk2 => None,
TimClockSource::PllClk => {
- RCC.cfgr3().modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ RCC.cfgr3()
+ .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
}
}
From d7623c79291cfba562f9881e062180d5c92b875e Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Thu, 15 Feb 2024 23:20:35 -0800
Subject: [PATCH 226/392] Remove extraneous , in cfg
---
embassy-stm32/src/rcc/f013.rs | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 17c734f09..4d5116a56 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,11 +85,11 @@ pub enum TimClockSource {
#[derive(Clone, Copy)]
pub struct TimClockSources {
pub tim1: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
pub tim2: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
pub tim34: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
pub tim8: TimClockSource,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
@@ -112,7 +112,7 @@ pub struct TimClockSources {
all(stm32f302, any(package_6, package_8))
))]
pub tim17: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E))))]
pub tim20: TimClockSource,
}
@@ -121,11 +121,11 @@ impl Default for TimClockSources {
fn default() -> Self {
Self {
tim1: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
tim2: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)),))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
tim34: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358,))]
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
tim8: TimClockSource::PClk2,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
@@ -148,7 +148,7 @@ impl Default for TimClockSources {
all(stm32f302, any(package_6, package_8))
))]
tim17: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)),))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E))))]
tim20: TimClockSource::PClk2,
}
}
From bcb0be21c180d4107e636083f5a1543a1f51447b Mon Sep 17 00:00:00 2001
From: Frank Plowman <post@frankplowman.com>
Date: Fri, 16 Feb 2024 17:24:58 +0000
Subject: [PATCH 227/392] embassy-nrf: Fix PDM gain register value derivation
Co-authored-by: Sol Harter <sol@glowinthedark.co.uk>
---
embassy-nrf/src/pdm.rs | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs
index 24fa29a4a..64d414d8f 100644
--- a/embassy-nrf/src/pdm.rs
+++ b/embassy-nrf/src/pdm.rs
@@ -4,6 +4,7 @@
use core::future::poll_fn;
use core::marker::PhantomData;
+use core::mem;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
@@ -145,15 +146,14 @@ impl<'d, T: Instance> Pdm<'d, T> {
}
fn _set_gain(r: &crate::pac::pdm::RegisterBlock, gain_left: I7F1, gain_right: I7F1) {
- let gain_left = gain_left
- .saturating_add(I7F1::from_bits(40))
- .saturating_to_num::<u8>()
- .clamp(0, 0x50);
- let gain_right = gain_right
- .saturating_add(I7F1::from_bits(40))
- .saturating_to_num::<u8>()
- .clamp(0, 0x50);
-
+ let gain_to_bits = |gain: I7F1| -> u8 {
+ let gain = gain.saturating_add(I7F1::from_bits(0x28))
+ .to_bits()
+ .clamp(0, 0x50);
+ unsafe { mem::transmute(gain) }
+ };
+ let gain_left = gain_to_bits(gain_left);
+ let gain_right = gain_to_bits(gain_right);
r.gainl.write(|w| unsafe { w.gainl().bits(gain_left) });
r.gainr.write(|w| unsafe { w.gainr().bits(gain_right) });
}
From 32e4c93954abb3add1c9b2c8fff627c497d47258 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 16 Feb 2024 19:58:19 +0100
Subject: [PATCH 228/392] Removed dangling doc comments
---
embassy-stm32/src/rcc/g4.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index c9ac2bb0b..5ac933af4 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -356,10 +356,10 @@ mod max {
/// External Clock ?-48MHz (RM0440 p280)
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
- /// SYSCLK ?-170MHz (RM0440 p282)
+ // SYSCLK ?-170MHz (RM0440 p282)
//pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
- /// PLL Output frequency ?-170MHz (RM0440 p281)
+ // PLL Output frequency ?-170MHz (RM0440 p281)
//pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
// Left over from f.rs, remove if not necessary
From ae748339999034854a78629c2e2f160d0d8417f9 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 16 Feb 2024 20:32:35 +0100
Subject: [PATCH 229/392] Removed redundant HSI48 configuration
---
embassy-stm32/src/rcc/g4.rs | 32 ++++++++------------------
examples/stm32g4/src/bin/usb_serial.rs | 7 +++---
2 files changed, 14 insertions(+), 25 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 5ac933af4..7ca741fc7 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -3,8 +3,9 @@ use stm32_metapac::rcc::vals::{Adcsel, Sw};
use stm32_metapac::FLASH;
pub use crate::pac::rcc::vals::{
- Adcsel as AdcClockSource, Clk48sel, Fdcansel as FdCanClockSource, Hpre as AHBPrescaler, Pllm as PllPreDiv,
- Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc, Ppre as APBPrescaler, Sw as Sysclk,
+ Adcsel as AdcClockSource, Clk48sel as Clk48Src, Fdcansel as FdCanClockSource, Hpre as AHBPrescaler,
+ Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc, Ppre as APBPrescaler,
+ Sw as Sysclk,
};
use crate::pac::{PWR, RCC};
use crate::time::Hertz;
@@ -53,17 +54,6 @@ pub struct Pll {
pub divr: Option<PllRDiv>,
}
-/// Sets the source for the 48MHz clock to the USB and RNG peripherals.
-pub enum Clock48MhzSrc {
- /// Use the High Speed Internal Oscillator. For USB usage, the CRS must be used to calibrate the
- /// oscillator to comply with the USB specification for oscillator tolerance.
- Hsi48(super::Hsi48Config),
- /// Use the PLLQ output. The PLL must be configured to output a 48MHz clock. For USB usage the
- /// PLL needs to be using the HSE source to comply with the USB specification for oscillator
- /// tolerance.
- PllQ,
-}
-
/// Clocks configutation
#[non_exhaustive]
pub struct Config {
@@ -82,7 +72,7 @@ pub struct Config {
pub low_power_run: bool,
/// Sets the clock source for the 48MHz clock used by the USB and RNG peripherals.
- pub clk48_src: Option<Clock48MhzSrc>,
+ pub clk48_src: Clk48Src,
pub ls: super::LsConfig,
@@ -106,7 +96,7 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
low_power_run: false,
- clk48_src: Some(Clock48MhzSrc::Hsi48(Default::default())),
+ clk48_src: Clk48Src::HSI48,
ls: Default::default(),
adc12_clock_source: Adcsel::DISABLE,
adc345_clock_source: Adcsel::DISABLE,
@@ -283,19 +273,17 @@ pub(crate) unsafe fn init(config: Config) {
};
// Setup the 48 MHz clock if needed
- if let Some(clock_48mhz_src) = config.clk48_src {
- let source = match clock_48mhz_src {
- Clock48MhzSrc::PllQ => {
+ {
+ let source = match config.clk48_src {
+ Clk48Src::PLL1_Q => {
// Make sure the PLLQ is enabled and running at 48Mhz
let pllq_freq = pll_freq.as_ref().and_then(|f| f.pll_q);
assert!(pllq_freq.is_some() && pllq_freq.unwrap().0 == 48_000_000);
crate::pac::rcc::vals::Clk48sel::PLL1_Q
}
- Clock48MhzSrc::Hsi48(config) => {
- super::init_hsi48(config);
- crate::pac::rcc::vals::Clk48sel::HSI48
- }
+ Clk48Src::HSI48 => crate::pac::rcc::vals::Clk48sel::HSI48,
+ _ => unreachable!(),
};
RCC.ccipr().modify(|w| w.set_clk48sel(source));
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index d9207e4cd..353ac1799 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -4,7 +4,7 @@
use defmt::{panic, *};
use embassy_executor::Spawner;
use embassy_stm32::rcc::{
- Clock48MhzSrc, Hse, HseMode, Hsi48Config, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, Pllsrc, Sysclk,
+ Clk48Src, Hse, HseMode, Hsi48Config, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, Pllsrc, Sysclk,
};
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{self, Driver, Instance};
@@ -47,9 +47,10 @@ async fn main(_spawner: Spawner) {
if USE_HSI48 {
// Sets up the Clock Recovery System (CRS) to use the USB SOF to trim the HSI48 oscillator.
- config.rcc.clk48_src = Some(Clock48MhzSrc::Hsi48(Hsi48Config { sync_from_usb: true }));
+ config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true });
+ config.rcc.clk48_src = Clk48Src::HSI48;
} else {
- config.rcc.clk48_src = Some(Clock48MhzSrc::PllQ);
+ config.rcc.clk48_src = Clk48Src::PLL1_Q;
}
let p = embassy_stm32::init(config);
From 25a95503f661f064e57854df8f831ad681868a4c Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 16 Feb 2024 20:41:04 +0100
Subject: [PATCH 230/392] Configured HSI48 if enabled, assert is enabled if
chosen as clk48 source
---
embassy-stm32/src/rcc/g4.rs | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 7ca741fc7..22dfa25c6 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -145,6 +145,11 @@ pub(crate) unsafe fn init(config: Config) {
}
};
+ // Configure HSI48 if required
+ if let Some(hsi48_config) = config.hsi48 {
+ super::init_hsi48(hsi48_config);
+ }
+
let pll_freq = config.pll.map(|pll_config| {
let src_freq = match pll_config.source {
Pllsrc::HSI => unwrap!(hsi),
@@ -272,7 +277,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- // Setup the 48 MHz clock if needed
+ // Configure the 48MHz clock source for USB and RNG peripherals.
{
let source = match config.clk48_src {
Clk48Src::PLL1_Q => {
@@ -282,7 +287,11 @@ pub(crate) unsafe fn init(config: Config) {
crate::pac::rcc::vals::Clk48sel::PLL1_Q
}
- Clk48Src::HSI48 => crate::pac::rcc::vals::Clk48sel::HSI48,
+ Clk48Src::HSI48 => {
+ // Make sure HSI48 is enabled
+ assert!(config.hsi48.is_some());
+ crate::pac::rcc::vals::Clk48sel::HSI48
+ }
_ => unreachable!(),
};
From e465dacf739e499f64b7943f4674edfe060f83b7 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 16 Feb 2024 21:34:12 +0100
Subject: [PATCH 231/392] Added documentation, fixed and refined boost and
flash read latency config
---
embassy-stm32/src/rcc/g4.rs | 69 +++++++++++++++++++++----------------
1 file changed, 39 insertions(+), 30 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 22dfa25c6..e2afd5260 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -13,6 +13,7 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
+/// HSE Mode
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum HseMode {
/// crystal/ceramic oscillator (HSEBYP=0)
@@ -21,6 +22,7 @@ pub enum HseMode {
Bypass,
}
+/// HSE Configuration
#[derive(Clone, Copy, Eq, PartialEq)]
pub struct Hse {
/// HSE frequency.
@@ -57,11 +59,19 @@ pub struct Pll {
/// Clocks configutation
#[non_exhaustive]
pub struct Config {
+ /// HSI Enable
pub hsi: bool,
+
+ /// HSE Configuration
pub hse: Option<Hse>,
+
+ /// System Clock Configuration
pub sys: Sysclk,
+
+ /// HSI48 Configuration
pub hsi48: Option<super::Hsi48Config>,
+ /// PLL Configuration
pub pll: Option<Pll>,
/// Iff PLL is requested as the main clock source in the `mux` field then the PLL configuration
@@ -69,17 +79,26 @@ pub struct Config {
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
+
pub low_power_run: bool,
/// Sets the clock source for the 48MHz clock used by the USB and RNG peripherals.
pub clk48_src: Clk48Src,
+ /// Low-Speed Clock Configuration
pub ls: super::LsConfig,
+ /// Clock Source for ADCs 1 and 2
pub adc12_clock_source: AdcClockSource,
+
+ /// Clock Source for ADCs 3, 4 and 5
pub adc345_clock_source: AdcClockSource,
+
+ /// Clock Source for FDCAN
pub fdcan_clock_source: FdCanClockSource,
+ /// Enable range1 boost mode
+ /// Recommended when the SYSCLK frequency is greater than 150MHz.
pub boost: bool,
}
@@ -217,36 +236,6 @@ pub(crate) unsafe fn init(config: Config) {
assert!(freq <= 170_000_000);
- if config.boost {
- // Enable Core Boost mode ([RM0440] p234)
- PWR.cr5().modify(|w| w.set_r1mode(false));
- if freq <= 36_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS0));
- } else if freq <= 68_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS1));
- } else if freq <= 102_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS2));
- } else if freq <= 136_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS3));
- } else {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS4));
- }
- } else {
- // Enable Core Boost mode ([RM0440] p234)
- PWR.cr5().modify(|w| w.set_r1mode(true));
- if freq <= 30_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS0));
- } else if freq <= 60_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS1));
- } else if freq <= 80_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS2));
- } else if freq <= 120_000_000 {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS3));
- } else {
- FLASH.acr().modify(|w| w.set_latency(Latency::WS4));
- }
- }
-
(Hertz(freq), Sw::PLL1_R)
}
_ => unreachable!(),
@@ -261,6 +250,26 @@ pub(crate) unsafe fn init(config: Config) {
let ahb_freq = sys_clk / config.ahb_pre;
+ // Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
+ PWR.cr5().modify(|w| w.set_r1mode(!config.boost));
+
+ // Configure flash read access latency based on boost mode and frequency (RM0440 p98)
+ FLASH.acr().modify(|w| {
+ w.set_latency(match (config.boost, ahb_freq.0) {
+ (true, ..=34_000_000) => Latency::WS0,
+ (true, ..=68_000_000) => Latency::WS1,
+ (true, ..=102_000_000) => Latency::WS2,
+ (true, ..=136_000_000) => Latency::WS3,
+ (true, _) => Latency::WS4,
+
+ (false, ..=36_000_000) => Latency::WS0,
+ (false, ..=60_000_000) => Latency::WS1,
+ (false, ..=90_000_000) => Latency::WS2,
+ (false, ..=120_000_000) => Latency::WS3,
+ (false, _) => Latency::WS4,
+ })
+ });
+
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
From c5f39d5c89240d17b0d7c8ee48fc48757c163bba Mon Sep 17 00:00:00 2001
From: Frank Plowman <post@frankplowman.com>
Date: Fri, 16 Feb 2024 20:42:14 +0000
Subject: [PATCH 232/392] embassy-nrf: Use fully-qualified
`core::mem::transmute`
---
embassy-nrf/src/pdm.rs | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs
index 64d414d8f..d03315fb6 100644
--- a/embassy-nrf/src/pdm.rs
+++ b/embassy-nrf/src/pdm.rs
@@ -4,7 +4,6 @@
use core::future::poll_fn;
use core::marker::PhantomData;
-use core::mem;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
@@ -150,7 +149,7 @@ impl<'d, T: Instance> Pdm<'d, T> {
let gain = gain.saturating_add(I7F1::from_bits(0x28))
.to_bits()
.clamp(0, 0x50);
- unsafe { mem::transmute(gain) }
+ unsafe { core::mem::transmute(gain) }
};
let gain_left = gain_to_bits(gain_left);
let gain_right = gain_to_bits(gain_right);
From 07987aea4e2706d8a7fa252ba3f6e31d576537ee Mon Sep 17 00:00:00 2001
From: Frank Plowman <post@frankplowman.com>
Date: Fri, 16 Feb 2024 20:45:58 +0000
Subject: [PATCH 233/392] embassy-nrf: Fix various typos and make style more
consistent
---
embassy-nrf/src/pdm.rs | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs
index d03315fb6..dcaeffe0f 100644
--- a/embassy-nrf/src/pdm.rs
+++ b/embassy-nrf/src/pdm.rs
@@ -1,4 +1,4 @@
-//! Pulse Density Modulation (PDM) mirophone driver.
+//! Pulse Density Modulation (PDM) mirophone driver
#![macro_use]
@@ -26,7 +26,7 @@ pub use crate::pac::pdm::pdmclkctrl::FREQ_A as Frequency;
pub use crate::pac::pdm::ratio::RATIO_A as Ratio;
use crate::{interrupt, Peripheral};
-/// Interrupt handler.
+/// Interrupt handler
pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
@@ -56,12 +56,12 @@ pub struct Pdm<'d, T: Instance> {
_peri: PeripheralRef<'d, T>,
}
-/// PDM error.
+/// PDM error
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
pub enum Error {
- /// Buffer is too long.
+ /// Buffer is too long
BufferTooLong,
/// Buffer is empty
BufferZeroLength,
@@ -75,13 +75,13 @@ static DUMMY_BUFFER: [i16; 1] = [0; 1];
/// The state of a continuously running sampler. While it reflects
/// the progress of a sampler, it also signals what should be done
-/// next. For example, if the sampler has stopped then the Pdm implementation
-/// can then tear down its infrastructure.
+/// next. For example, if the sampler has stopped then the PDM implementation
+/// can then tear down its infrastructure
#[derive(PartialEq)]
pub enum SamplerState {
- /// The sampler processed the samples and is ready for more.
+ /// The sampler processed the samples and is ready for more
Sampled,
- /// The sampler is done processing samples.
+ /// The sampler is done processing samples
Stopped,
}
@@ -162,12 +162,12 @@ impl<'d, T: Instance> Pdm<'d, T> {
Self::_set_gain(T::regs(), gain_left, gain_right)
}
- /// Start sampling microphon data into a dummy buffer
- /// Usefull to start the microphon and keep it active between recording samples
+ /// Start sampling microphone data into a dummy buffer.
+ /// Useful to start the microphone and keep it active between recording samples.
pub async fn start(&mut self) {
let r = T::regs();
- // start dummy sampling because microphon needs some setup time
+ // start dummy sampling because microphone needs some setup time
r.sample
.ptr
.write(|w| unsafe { w.sampleptr().bits(DUMMY_BUFFER.as_ptr() as u32) });
@@ -178,14 +178,14 @@ impl<'d, T: Instance> Pdm<'d, T> {
r.tasks_start.write(|w| unsafe { w.bits(1) });
}
- /// Stop sampling microphon data inta a dummy buffer
+ /// Stop sampling microphone data inta a dummy buffer
pub async fn stop(&mut self) {
let r = T::regs();
r.tasks_stop.write(|w| unsafe { w.bits(1) });
r.events_started.reset();
}
- /// Sample data into the given buffer.
+ /// Sample data into the given buffer
pub async fn sample(&mut self, buffer: &mut [i16]) -> Result<(), Error> {
if buffer.len() == 0 {
return Err(Error::BufferZeroLength);
@@ -302,7 +302,7 @@ impl<'d, T: Instance> Pdm<'d, T> {
});
// Don't reorder the start event before the previous writes. Hopefully self
- // wouldn't happen anyway.
+ // wouldn't happen anyway
compiler_fence(Ordering::SeqCst);
r.tasks_start.write(|w| unsafe { w.bits(1) });
@@ -313,11 +313,11 @@ impl<'d, T: Instance> Pdm<'d, T> {
let drop = OnDrop::new(|| {
r.tasks_stop.write(|w| unsafe { w.bits(1) });
- // N.B. It would be better if this were async, but Drop only support sync code.
+ // N.B. It would be better if this were async, but Drop only support sync code
while r.events_stopped.read().bits() != 0 {}
});
- // Wait for events and complete when the sampler indicates it has had enough.
+ // Wait for events and complete when the sampler indicates it has had enough
poll_fn(|cx| {
let r = T::regs();
@@ -330,7 +330,7 @@ impl<'d, T: Instance> Pdm<'d, T> {
r.intenset.write(|w| w.end().set());
if !done {
- // Discard the last buffer after the user requested a stop.
+ // Discard the last buffer after the user requested a stop
if sampler(&bufs[current_buffer]) == SamplerState::Sampled {
let next_buffer = 1 - current_buffer;
current_buffer = next_buffer;
@@ -404,7 +404,7 @@ impl Default for Config {
}
}
-/// PDM operation mode.
+/// PDM operation mode
#[derive(PartialEq)]
pub enum OperationMode {
/// Mono (1 channel)
@@ -475,9 +475,9 @@ pub(crate) mod sealed {
}
}
-/// PDM peripheral instance.
+/// PDM peripheral instance
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
- /// Interrupt for this peripheral.
+ /// Interrupt for this peripheral
type Interrupt: interrupt::typelevel::Interrupt;
}
From 7d111191689460ddfdce08dec7195cb9fa1b598b Mon Sep 17 00:00:00 2001
From: Frank Plowman <post@frankplowman.com>
Date: Fri, 16 Feb 2024 20:47:19 +0000
Subject: [PATCH 234/392] embassy-nrf: Don't break lines; make rustfmt happy
---
embassy-nrf/src/pdm.rs | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs
index dcaeffe0f..6ddc4dc0a 100644
--- a/embassy-nrf/src/pdm.rs
+++ b/embassy-nrf/src/pdm.rs
@@ -146,9 +146,7 @@ impl<'d, T: Instance> Pdm<'d, T> {
fn _set_gain(r: &crate::pac::pdm::RegisterBlock, gain_left: I7F1, gain_right: I7F1) {
let gain_to_bits = |gain: I7F1| -> u8 {
- let gain = gain.saturating_add(I7F1::from_bits(0x28))
- .to_bits()
- .clamp(0, 0x50);
+ let gain = gain.saturating_add(I7F1::from_bits(0x28)).to_bits().clamp(0, 0x50);
unsafe { core::mem::transmute(gain) }
};
let gain_left = gain_to_bits(gain_left);
From a24087c36c60e97f8b0aaefe57111c3a2edd6e8a Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 16 Feb 2024 21:52:58 +0100
Subject: [PATCH 235/392] Configured SYSCLK after boost mode, added comments
---
embassy-stm32/src/rcc/g4.rs | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index e2afd5260..0c1a1e4b1 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -241,16 +241,13 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};
- RCC.cfgr().modify(|w| {
- w.set_sw(sw);
- w.set_hpre(config.ahb_pre);
- w.set_ppre1(config.apb1_pre);
- w.set_ppre2(config.apb2_pre);
- });
-
+ // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let ahb_freq = sys_clk / config.ahb_pre;
// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
+ // TODO: according to RM0440 p235, when switching from range1-normal to range1-boost, it’s necessary to divide
+ // SYSCLK by 2 using the AHB prescaler, set boost and flash read latency, switch system frequency, wait 1us and
+ // reconfigure the AHB prescaler as desired. Unclear whether this is always necessary.
PWR.cr5().modify(|w| w.set_r1mode(!config.boost));
// Configure flash read access latency based on boost mode and frequency (RM0440 p98)
@@ -270,6 +267,14 @@ pub(crate) unsafe fn init(config: Config) {
})
});
+ // Now that boost mode and flash read access latency are configured, set up SYSCLK
+ RCC.cfgr().modify(|w| {
+ w.set_sw(sw);
+ w.set_hpre(config.ahb_pre);
+ w.set_ppre1(config.apb1_pre);
+ w.set_ppre2(config.apb2_pre);
+ });
+
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
From 6d7458dac7e768425342910e04a75c85e667cb82 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Sat, 17 Feb 2024 00:30:16 +0100
Subject: [PATCH 236/392] Refinements
* Implemented boost mode dance (RM0440 p234-245, 6.5.1)
* Enabled boost mode in usb_serial example, tested on hardware
* Removed hard requirement of a valid 48MHz source (HSI48 is checked if
requested, PLL passed through as-is and assumed to be valid)
* Used calc_pclk to calculate APB frequencies
* Refactored 48MHz configuration code to remove unnecessary let and block
* Renamed ahb_freq to hclk for clarity and consistency
---
embassy-stm32/src/rcc/g4.rs | 67 ++++++++++++--------------
examples/stm32g4/src/bin/usb_serial.rs | 1 +
2 files changed, 33 insertions(+), 35 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 0c1a1e4b1..382ffbead 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -242,17 +242,25 @@ pub(crate) unsafe fn init(config: Config) {
};
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
- let ahb_freq = sys_clk / config.ahb_pre;
+ let hclk = sys_clk / config.ahb_pre;
// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
- // TODO: according to RM0440 p235, when switching from range1-normal to range1-boost, it’s necessary to divide
- // SYSCLK by 2 using the AHB prescaler, set boost and flash read latency, switch system frequency, wait 1us and
- // reconfigure the AHB prescaler as desired. Unclear whether this is always necessary.
- PWR.cr5().modify(|w| w.set_r1mode(!config.boost));
+ if config.boost {
+ // RM0440 p235
+ // “The sequence to switch from Range1 normal mode to Range1 boost mode is:
+ // 1. The system clock must be divided by 2 using the AHB prescaler before switching to a higher system frequency.
+ RCC.cfgr().modify(|w| w.set_hpre(AHBPrescaler::DIV2));
+ // 2. Clear the R1MODE bit in the PWR_CR5 register. (enables boost mode)
+ PWR.cr5().modify(|w| w.set_r1mode(false));
+
+ // Below:
+ // 3. Adjust wait states according to new freq target
+ // 4. Configure and switch to new frequency
+ }
// Configure flash read access latency based on boost mode and frequency (RM0440 p98)
FLASH.acr().modify(|w| {
- w.set_latency(match (config.boost, ahb_freq.0) {
+ w.set_latency(match (config.boost, hclk.0) {
(true, ..=34_000_000) => Latency::WS0,
(true, ..=68_000_000) => Latency::WS1,
(true, ..=102_000_000) => Latency::WS2,
@@ -267,6 +275,11 @@ pub(crate) unsafe fn init(config: Config) {
})
});
+ if config.boost {
+ // 5. Wait for at least 1us and then reconfigure the AHB prescaler to get the needed HCLK clock frequency.
+ cortex_m::asm::delay(16);
+ }
+
// Now that boost mode and flash read access latency are configured, set up SYSCLK
RCC.cfgr().modify(|w| {
w.set_sw(sw);
@@ -275,30 +288,16 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre2(config.apb2_pre);
});
- let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
-
- let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
+ let (apb1_freq, apb1_tim_freq) = super::util::calc_pclk(hclk, config.apb1_pre);
+ let (apb2_freq, apb2_tim_freq) = super::util::calc_pclk(hclk, config.apb2_pre);
// Configure the 48MHz clock source for USB and RNG peripherals.
- {
- let source = match config.clk48_src {
+ RCC.ccipr().modify(|w| {
+ w.set_clk48sel(match config.clk48_src {
Clk48Src::PLL1_Q => {
- // Make sure the PLLQ is enabled and running at 48Mhz
- let pllq_freq = pll_freq.as_ref().and_then(|f| f.pll_q);
- assert!(pllq_freq.is_some() && pllq_freq.unwrap().0 == 48_000_000);
-
+ // Not checking that PLL1_Q is 48MHz here so as not to require the user to have a 48MHz clock.
+ // Peripherals which require one (USB, RNG) should check that they‘re driven by a valid 48MHz
+ // clock at init.
crate::pac::rcc::vals::Clk48sel::PLL1_Q
}
Clk48Src::HSI48 => {
@@ -307,10 +306,8 @@ pub(crate) unsafe fn init(config: Config) {
crate::pac::rcc::vals::Clk48sel::HSI48
}
_ => unreachable!(),
- };
-
- RCC.ccipr().modify(|w| w.set_clk48sel(source));
- }
+ })
+ });
RCC.ccipr().modify(|w| w.set_adc12sel(config.adc12_clock_source));
RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
@@ -339,9 +336,9 @@ pub(crate) unsafe fn init(config: Config) {
set_clocks!(
sys: Some(sys_clk),
- hclk1: Some(ahb_freq),
- hclk2: Some(ahb_freq),
- hclk3: Some(ahb_freq),
+ hclk1: Some(hclk),
+ hclk2: Some(hclk),
+ hclk3: Some(hclk),
pclk1: Some(apb1_freq),
pclk1_tim: Some(apb1_tim_freq),
pclk2: Some(apb2_freq),
@@ -355,7 +352,7 @@ pub(crate) unsafe fn init(config: Config) {
);
}
-// TODO: if necessary, make more of these gated behind cfg attrs
+// TODO: if necessary, make more of these, gated behind cfg attrs
mod max {
use core::ops::RangeInclusive;
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index 353ac1799..989fef5b0 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -44,6 +44,7 @@ async fn main(_spawner: Spawner) {
});
config.rcc.sys = Sysclk::PLL1_R;
+ config.rcc.boost = true; // BOOST!
if USE_HSI48 {
// Sets up the Clock Recovery System (CRS) to use the USB SOF to trim the HSI48 oscillator.
From 370db9fb06862695433c9314585a492d8c1684ae Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:39:23 -0800
Subject: [PATCH 237/392] Update f013.rs
Add stm32f398
---
embassy-stm32/src/rcc/f013.rs | 45 +++++++++++++++++++++--------------
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 4d5116a56..3f1b88e5c 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,31 +85,34 @@ pub enum TimClockSource {
#[derive(Clone, Copy)]
pub struct TimClockSources {
pub tim1: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
pub tim2: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
pub tim34: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
pub tim8: TimClockSource,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
pub tim15: TimClockSource,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
pub tim16: TimClockSource,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
pub tim17: TimClockSource,
#[cfg(any(all(stm32f303, any(package_D, package_E))))]
@@ -121,31 +124,34 @@ impl Default for TimClockSources {
fn default() -> Self {
Self {
tim1: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
tim2: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
tim34: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
tim8: TimClockSource::PClk2,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
tim15: TimClockSource::PClk2,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
tim16: TimClockSource::PClk2,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
tim17: TimClockSource::PClk2,
#[cfg(any(all(stm32f303, any(package_D, package_E))))]
@@ -456,7 +462,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
match config.tim.tim2 {
TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
@@ -465,7 +471,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E))))]
+ #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
match config.tim.tim34 {
TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
@@ -474,7 +480,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358))]
+ #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
match config.tim.tim8 {
TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
@@ -487,7 +493,8 @@ pub(crate) unsafe fn init(config: Config) {
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
match config.tim.tim15 {
TimClockSource::PClk2 => None,
@@ -501,7 +508,8 @@ pub(crate) unsafe fn init(config: Config) {
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
match config.tim.tim16 {
TimClockSource::PClk2 => None,
@@ -515,7 +523,8 @@ pub(crate) unsafe fn init(config: Config) {
all(stm32f303, any(package_D, package_E)),
stm32f301,
stm32f318,
- all(stm32f302, any(package_6, package_8))
+ all(stm32f302, any(package_6, package_8)),
+ stm32f398
))]
match config.tim.tim17 {
TimClockSource::PClk2 => None,
From 77739faaeb155478d3d50e7b8a3add79b5e94222 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:42:19 -0800
Subject: [PATCH 238/392] Rustfmt
---
embassy-stm32/src/rcc/f013.rs | 54 +++++++++++++++++++++++++++++------
1 file changed, 45 insertions(+), 9 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 3f1b88e5c..1a0e34614 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -85,11 +85,23 @@ pub enum TimClockSource {
#[derive(Clone, Copy)]
pub struct TimClockSources {
pub tim1: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E))
+ stm32f398
+ ))]
pub tim2: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ stm32f398
+ ))]
pub tim34: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_B, package_C, package_D, package_E)),
+ stm32f358,
+ stm32f398
+ ))]
pub tim8: TimClockSource,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
@@ -124,11 +136,23 @@ impl Default for TimClockSources {
fn default() -> Self {
Self {
tim1: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ stm32f398
+ ))]
tim2: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ stm32f398
+ ))]
tim34: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_B, package_C, package_D, package_E)),
+ stm32f358,
+ stm32f398
+ ))]
tim8: TimClockSource::PClk2,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
@@ -462,7 +486,11 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ stm32f398
+ ))]
match config.tim.tim2 {
TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
@@ -471,7 +499,11 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(any(all(stm32f303, any(package_D, package_E)), all(stm32f302, any(package_D, package_E)), stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_D, package_E)),
+ all(stm32f302, any(package_D, package_E)),
+ stm32f398
+ ))]
match config.tim.tim34 {
TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
@@ -480,7 +512,11 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(any(all(stm32f303, any(package_B, package_C, package_D, package_E)), stm32f358, stm32f398))]
+ #[cfg(any(
+ all(stm32f303, any(package_B, package_C, package_D, package_E)),
+ stm32f358,
+ stm32f398
+ ))]
match config.tim.tim8 {
TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
From 7592e8be6e40dc6be655bcf011f3ce2aee5b9743 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:45:58 -0800
Subject: [PATCH 239/392] Fix build
---
embassy-stm32/src/rcc/f013.rs | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 1a0e34614..8ceae6a8a 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -495,7 +495,7 @@ pub(crate) unsafe fn init(config: Config) {
TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
RCC.cfgr3()
- .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P));
+ .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
}
};
@@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398
))]
match config.tim.tim15 {
- TimClockSource::PClk2 => None,
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398
))]
match config.tim.tim16 {
- TimClockSource::PClk2 => None,
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398
))]
match config.tim.tim17 {
- TimClockSource::PClk2 => None,
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(all(stm32f303, any(package_D, package_E))))]
match config.tim.tim20 {
- TimClockSource::PClk2 => None,
+ TimClockSource::PClk2 => {},
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
From c99c4a01a99d953805f11bf838c9f6c0b5338fae Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 16:47:38 -0800
Subject: [PATCH 240/392] Update f013.rs
---
embassy-stm32/src/rcc/f013.rs | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 8ceae6a8a..02c3425d1 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -87,7 +87,7 @@ pub struct TimClockSources {
pub tim1: TimClockSource,
#[cfg(any(
all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E))
+ all(stm32f302, any(package_D, package_E)),
stm32f398
))]
pub tim2: TimClockSource,
@@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398
))]
match config.tim.tim15 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398
))]
match config.tim.tim16 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398
))]
match config.tim.tim17 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(all(stm32f303, any(package_D, package_E))))]
match config.tim.tim20 {
- TimClockSource::PClk2 => {},
+ TimClockSource::PClk2 => {}
TimClockSource::PllClk => {
RCC.cfgr3()
.modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
From 0e80dc4cd929f201dd35b569aa0aadd891c58682 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 17 Feb 2024 02:36:48 +0100
Subject: [PATCH 241/392] tests/stm32: add stm32f091rc, stm32h503rb.
---
tests/stm32/Cargo.toml | 2 ++
tests/stm32/build.rs | 2 ++
tests/stm32/src/bin/hash.rs | 1 +
tests/stm32/src/common.rs | 58 ++++++++++++++++++++++++++++++++++++-
4 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index d94045737..8554682a4 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -30,6 +30,8 @@ stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"]
stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
+stm32f091rc = ["embassy-stm32/stm32f091rc", "cm0", "not-gpdma", "chrono"]
+stm32h503rb = ["embassy-stm32/stm32h503rb", "rng"]
hash = []
eth = ["embassy-executor/task-arena-size-16384"]
diff --git a/tests/stm32/build.rs b/tests/stm32/build.rs
index f32a7b2f8..bc5589164 100644
--- a/tests/stm32/build.rs
+++ b/tests/stm32/build.rs
@@ -16,6 +16,8 @@ fn main() -> Result<(), Box<dyn Error>> {
feature = "stm32l073rz",
// wrong ram size in stm32-data
feature = "stm32wl55jc",
+ // no VTOR, so interrupts can't work when running from RAM
+ feature = "stm32f091rc",
)) {
println!("cargo:rustc-link-arg-bins=-Tlink.x");
println!("cargo:rerun-if-changed=link.x");
diff --git a/tests/stm32/src/bin/hash.rs b/tests/stm32/src/bin/hash.rs
index d1cfac5ce..8cc5d593f 100644
--- a/tests/stm32/src/bin/hash.rs
+++ b/tests/stm32/src/bin/hash.rs
@@ -24,6 +24,7 @@ bind_interrupts!(struct Irqs {
feature = "stm32wba52cg",
feature = "stm32l552ze",
feature = "stm32h563zi",
+ feature = "stm32h503rb",
feature = "stm32u5a5zj",
feature = "stm32u585ai"
))]
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 182ad6298..50a7f9bae 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -54,6 +54,10 @@ teleprobe_meta::target!(b"nucleo-stm32l496zg");
teleprobe_meta::target!(b"nucleo-stm32wl55jc");
#[cfg(feature = "stm32wba52cg")]
teleprobe_meta::target!(b"nucleo-stm32wba52cg");
+#[cfg(feature = "stm32f091rc")]
+teleprobe_meta::target!(b"nucleo-stm32f091rc");
+#[cfg(feature = "stm32h503rb")]
+teleprobe_meta::target!(b"nucleo-stm32h503rb");
macro_rules! define_peris {
($($name:ident = $peri:ident,)* $(@irq $irq_name:ident = $irq_code:tt,)*) => {
@@ -85,6 +89,12 @@ macro_rules! define_peris {
};
}
+#[cfg(feature = "stm32f091rc")]
+define_peris!(
+ UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
+ SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
+ @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+);
#[cfg(feature = "stm32f103c8")]
define_peris!(
UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
@@ -157,6 +167,12 @@ define_peris!(
SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
);
+#[cfg(feature = "stm32h503rb")]
+define_peris!(
+ UART = USART1, UART_TX = PB14, UART_RX = PB15, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
+ SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
+ @irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
+);
#[cfg(feature = "stm32c031c6")]
define_peris!(
UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
@@ -247,6 +263,22 @@ pub fn config() -> Config {
config.rcc = embassy_stm32::rcc::WPAN_DEFAULT;
}
+ #[cfg(feature = "stm32f091rc")]
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(8_000_000),
+ mode: HseMode::Bypass,
+ });
+ config.rcc.pll = Some(Pll {
+ src: PllSource::HSE,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL6,
+ });
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV1;
+ }
#[cfg(feature = "stm32f103c8")]
{
use embassy_stm32::rcc::*;
@@ -264,7 +296,6 @@ pub fn config() -> Config {
config.rcc.apb1_pre = APBPrescaler::DIV2;
config.rcc.apb2_pre = APBPrescaler::DIV1;
}
-
#[cfg(feature = "stm32f207zg")]
{
use embassy_stm32::rcc::*;
@@ -400,6 +431,31 @@ pub fn config() -> Config {
config.rcc.voltage_scale = VoltageScale::Scale0;
}
+ #[cfg(feature = "stm32h503rb")]
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hsi = None;
+ config.rcc.hsi48 = Some(Default::default()); // needed for RNG
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(24_000_000),
+ mode: HseMode::Oscillator,
+ });
+ config.rcc.pll1 = Some(Pll {
+ source: PllSource::HSE,
+ prediv: PllPreDiv::DIV6,
+ mul: PllMul::MUL125,
+ divp: Some(PllDiv::DIV2),
+ divq: Some(PllDiv::DIV2),
+ divr: None,
+ });
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV1;
+ config.rcc.apb2_pre = APBPrescaler::DIV1;
+ config.rcc.apb3_pre = APBPrescaler::DIV1;
+ config.rcc.sys = Sysclk::PLL1_P;
+ config.rcc.voltage_scale = VoltageScale::Scale0;
+ }
+
#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
{
use embassy_stm32::rcc::*;
From cb7863aea548b8cda65ca3eb14e543c226dbedb8 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 17 Feb 2024 03:37:51 +0100
Subject: [PATCH 242/392] tests/stm32: actually add stm32f091rc, stm32h503rb.
---
ci.sh | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ci.sh b/ci.sh
index 7ecca92af..ef706bdc5 100755
--- a/ci.sh
+++ b/ci.sh
@@ -230,6 +230,8 @@ cargo batch \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f303ze --out-dir out/tests/stm32f303ze \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l496zg --out-dir out/tests/stm32l496zg \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wl55jc --out-dir out/tests/stm32wl55jc \
+ --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f091rc --out-dir out/tests/stm32f091rc \
+ --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h503rb --out-dir out/tests/stm32h503rb \
--- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
--- build --release --manifest-path tests/nrf52840/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \
--- build --release --manifest-path tests/nrf51422/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/nrf51-dk \
From f9aea0fb54cf2f74dc4cd5ce205c7f1bfaf5dc39 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 17 Feb 2024 03:37:51 +0100
Subject: [PATCH 243/392] tests/rp: reenable i2c test.
---
ci.sh | 3 ---
1 file changed, 3 deletions(-)
diff --git a/ci.sh b/ci.sh
index ef706bdc5..b2170a225 100755
--- a/ci.sh
+++ b/ci.sh
@@ -239,9 +239,6 @@ cargo batch \
$BUILD_EXTRA
-# failed, a wire must've come loose, will check asap.
-rm out/tests/rpi-pico/i2c
-
rm out/tests/stm32wb55rg/wpan_mac
rm out/tests/stm32wb55rg/wpan_ble
From e99ef496116b4cdfa0dd0706ac1bfc600f45c97b Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Fri, 16 Feb 2024 19:56:07 -0800
Subject: [PATCH 244/392] Move to auto-generated based system.
---
embassy-stm32/build.rs | 69 ++++++++
embassy-stm32/src/rcc/f013.rs | 221 +-------------------------
examples/stm32f3/src/bin/usart_dma.rs | 4 +-
3 files changed, 78 insertions(+), 216 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index ee88d4541..f45a571f2 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -430,6 +430,8 @@ fn main() {
let mut clock_names = BTreeSet::new();
+ let mut rcc_cfgr_regs = BTreeMap::new();
+
for p in METADATA.peripherals {
if !singletons.contains(&p.name.to_string()) {
continue;
@@ -508,6 +510,16 @@ fn main() {
let field_name = format_ident!("{}", field_name);
let enum_name = format_ident!("{}", enum_name);
+ if !rcc_cfgr_regs.contains_key(mux.register) {
+ rcc_cfgr_regs.insert(mux.register, Vec::new());
+ }
+
+ rcc_cfgr_regs.get_mut(mux.register).unwrap().push((
+ fieldset_name.clone(),
+ field_name.clone(),
+ enum_name.clone(),
+ ));
+
let match_arms: TokenStream = enumm
.variants
.iter()
@@ -590,6 +602,63 @@ fn main() {
}
}
+ for (rcc_cfgr_reg, fields) in rcc_cfgr_regs {
+ println!("cargo:rustc-cfg={}", rcc_cfgr_reg.to_ascii_lowercase());
+
+ let struct_fields: Vec<_> = fields
+ .iter()
+ .map(|(_fieldset, fieldname, enum_name)| {
+ quote! {
+ pub #fieldname: Option<crate::pac::rcc::vals::#enum_name>
+ }
+ })
+ .collect();
+
+ let field_names: Vec<_> = fields
+ .iter()
+ .map(|(_fieldset, fieldname, _enum_name)| fieldname)
+ .collect();
+
+ let inits: Vec<_> = fields
+ .iter()
+ .map(|(fieldset, fieldname, _enum_name)| {
+ let setter = format_ident!("set_{}", fieldname);
+ quote! {
+ match self.#fieldname {
+ None => {}
+ Some(val) => {
+ crate::pac::RCC.#fieldset()
+ .modify(|w| w.#setter(val));
+ }
+ };
+ }
+ })
+ .collect();
+
+ let cfgr_reg = format_ident!("{}", rcc_cfgr_reg);
+
+ g.extend(quote! {
+ #[derive(Clone, Copy)]
+ pub struct #cfgr_reg {
+ #( #struct_fields, )*
+ }
+
+ impl Default for #cfgr_reg {
+ fn default() -> Self {
+ Self {
+ #( #field_names: None, )*
+ }
+ }
+ }
+
+ impl #cfgr_reg {
+ pub fn init(self) {
+ #( #inits )*
+ }
+ }
+ });
+ }
+
// Generate RCC
clock_names.insert("sys".to_string());
clock_names.insert("rtc".to_string());
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 02c3425d1..a61aae0e8 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -74,116 +74,6 @@ pub enum HrtimClockSource {
PllClk,
}
-#[cfg(all(stm32f3, not(rcc_f37)))]
-#[derive(Clone, Copy, PartialEq, Eq)]
-pub enum TimClockSource {
- PClk2,
- PllClk,
-}
-
-#[cfg(all(stm32f3, not(rcc_f37)))]
-#[derive(Clone, Copy)]
-pub struct TimClockSources {
- pub tim1: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- stm32f398
- ))]
- pub tim2: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- stm32f398
- ))]
- pub tim34: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_B, package_C, package_D, package_E)),
- stm32f358,
- stm32f398
- ))]
- pub tim8: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- pub tim15: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- pub tim16: TimClockSource,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- pub tim17: TimClockSource,
- #[cfg(any(all(stm32f303, any(package_D, package_E))))]
- pub tim20: TimClockSource,
-}
-
-#[cfg(all(stm32f3, not(rcc_f37)))]
-impl Default for TimClockSources {
- fn default() -> Self {
- Self {
- tim1: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- stm32f398
- ))]
- tim2: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- stm32f398
- ))]
- tim34: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_B, package_C, package_D, package_E)),
- stm32f358,
- stm32f398
- ))]
- tim8: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- tim15: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- tim16: TimClockSource::PClk2,
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- tim17: TimClockSource::PClk2,
- #[cfg(any(all(stm32f303, any(package_D, package_E))))]
- tim20: TimClockSource::PClk2,
- }
- }
-}
-
/// Clocks configutation
#[non_exhaustive]
pub struct Config {
@@ -209,8 +99,8 @@ pub struct Config {
pub adc34: AdcClockSource,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
- #[cfg(all(stm32f3, not(rcc_f37)))]
- pub tim: TimClockSources,
+ #[cfg(cfgr3)]
+ pub cfgr3: crate::_generated::CFGR3,
pub ls: super::LsConfig,
}
@@ -240,8 +130,8 @@ impl Default for Config {
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(stm32f334)]
hrtim: HrtimClockSource::BusClk,
- #[cfg(all(stm32f3, not(rcc_f37)))]
- tim: Default::default(),
+ #[cfg(cfgr3)]
+ cfgr3: Default::default(),
}
}
}
@@ -477,107 +367,8 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(all(stm32f3, not(rcc_f37)))]
- match config.tim.tim1 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim1sw(crate::pac::rcc::vals::Timsw::PLL1_P));
- }
- };
-
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- stm32f398
- ))]
- match config.tim.tim2 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
- }
- };
-
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- all(stm32f302, any(package_D, package_E)),
- stm32f398
- ))]
- match config.tim.tim34 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim34sw(crate::pac::rcc::vals::Timsw::PLL1_P));
- }
- };
-
- #[cfg(any(
- all(stm32f303, any(package_B, package_C, package_D, package_E)),
- stm32f358,
- stm32f398
- ))]
- match config.tim.tim8 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim8sw(crate::pac::rcc::vals::Timsw::PLL1_P));
- }
- };
-
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- match config.tim.tim15 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
- }
- };
-
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- match config.tim.tim16 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
- }
- };
-
- #[cfg(any(
- all(stm32f303, any(package_D, package_E)),
- stm32f301,
- stm32f318,
- all(stm32f302, any(package_6, package_8)),
- stm32f398
- ))]
- match config.tim.tim17 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
- }
- }
-
- #[cfg(any(all(stm32f303, any(package_D, package_E))))]
- match config.tim.tim20 {
- TimClockSource::PClk2 => {}
- TimClockSource::PllClk => {
- RCC.cfgr3()
- .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));
- }
- }
+ #[cfg(cfgr3)]
+ config.cfgr3.init();
set_clocks!(
hsi: hsi,
diff --git a/examples/stm32f3/src/bin/usart_dma.rs b/examples/stm32f3/src/bin/usart_dma.rs
index 5234e53b9..7dc905adc 100644
--- a/examples/stm32f3/src/bin/usart_dma.rs
+++ b/examples/stm32f3/src/bin/usart_dma.rs
@@ -17,7 +17,9 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
- let p = embassy_stm32::init(Default::default());
+ let mut init_config = embassy_stm32::Config::default();
+ init_config.rcc.cfgr3.usart1sw = Some(embassy_stm32::pac::rcc::vals::Usart1sw::HSI);
+ let p = embassy_stm32::init(init_config);
info!("Hello World!");
let config = Config::default();
From 0097cbcfe3311ca89f52284a4a1187e19666a330 Mon Sep 17 00:00:00 2001
From: Mick Chanthaseth <mchant@users.noreply.github.com>
Date: Fri, 16 Feb 2024 22:22:13 -0800
Subject: [PATCH 245/392] Update imports in usb_hid_mouse.rs
---
examples/rp/src/bin/usb_hid_mouse.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/rp/src/bin/usb_hid_mouse.rs b/examples/rp/src/bin/usb_hid_mouse.rs
index ec125a47e..a812b22c3 100644
--- a/examples/rp/src/bin/usb_hid_mouse.rs
+++ b/examples/rp/src/bin/usb_hid_mouse.rs
@@ -15,7 +15,7 @@ use embassy_rp::usb::{Driver, InterruptHandler};
use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
use embassy_usb::control::OutResponse;
use embassy_usb::{Builder, Config, Handler};
-use rand::{Rng, RngCore};
+use rand::Rng;
use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
use {defmt_rtt as _, panic_probe as _};
From 70b3c4374d57ab638e0cb76013b725e1ea229546 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 3 Feb 2024 09:44:00 +1000
Subject: [PATCH 246/392] Port FDCAN HAL to use PAC directly instead of fdcan
crate.
- Provide separate FDCAN capable and Classic CAN API's
- Don't use fdcan crate dep anymore
- Provide embedded-can traits.
---
embassy-stm32/Cargo.toml | 901 +++++++++---------
embassy-stm32/src/can/enums.rs | 17 +
embassy-stm32/src/can/fd/config.rs | 438 +++++++++
embassy-stm32/src/can/fd/filter.rs | 379 ++++++++
.../src/can/fd/message_ram/common.rs | 134 +++
embassy-stm32/src/can/fd/message_ram/enums.rs | 233 +++++
.../src/can/fd/message_ram/extended_filter.rs | 136 +++
.../src/can/fd/message_ram/generic.rs | 168 ++++
embassy-stm32/src/can/fd/message_ram/mod.rs | 170 ++++
.../src/can/fd/message_ram/rxfifo_element.rs | 122 +++
.../src/can/fd/message_ram/standard_filter.rs | 136 +++
.../can/fd/message_ram/txbuffer_element.rs | 433 +++++++++
.../src/can/fd/message_ram/txevent_element.rs | 138 +++
embassy-stm32/src/can/fd/mod.rs | 6 +
embassy-stm32/src/can/fd/peripheral.rs | 776 +++++++++++++++
embassy-stm32/src/can/fdcan.rs | 633 ++++++------
embassy-stm32/src/can/frame.rs | 370 +++++++
examples/stm32g4/Cargo.toml | 1 +
examples/stm32g4/src/bin/can.rs | 96 +-
examples/stm32h5/src/bin/can.rs | 89 +-
examples/stm32h7/src/bin/can.rs | 89 +-
tests/stm32/Cargo.toml | 1 +
tests/stm32/src/bin/fdcan.rs | 109 +--
23 files changed, 4659 insertions(+), 916 deletions(-)
create mode 100644 embassy-stm32/src/can/fd/config.rs
create mode 100644 embassy-stm32/src/can/fd/filter.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/common.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/enums.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/extended_filter.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/generic.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/mod.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/rxfifo_element.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/standard_filter.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
create mode 100644 embassy-stm32/src/can/fd/message_ram/txevent_element.rs
create mode 100644 embassy-stm32/src/can/fd/mod.rs
create mode 100644 embassy-stm32/src/can/fd/peripheral.rs
create mode 100644 embassy-stm32/src/can/frame.rs
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 389ed0041..d585d2cd6 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -55,10 +55,12 @@ embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["un
embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
embedded-hal-async = { version = "1.0" }
embedded-hal-nb = { version = "1.0" }
+embedded-can = "0.4"
embedded-storage = "0.3.1"
embedded-storage-async = { version = "0.4.1" }
+
defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
cortex-m-rt = ">=0.6.15,<0.8"
@@ -80,7 +82,10 @@ chrono = { version = "^0.4", default-features = false, optional = true}
bit_field = "0.10.2"
document-features = "0.2.7"
-fdcan = { version = "0.2.0", optional = true }
+static_assertions = { version = "1.1" }
+volatile-register = { version = "0.2.1" }
+
+
[dev-dependencies]
critical-section = { version = "1.1", features = ["std"] }
@@ -695,373 +700,373 @@ stm32f779ai = [ "stm32-metapac/stm32f779ai" ]
stm32f779bi = [ "stm32-metapac/stm32f779bi" ]
stm32f779ii = [ "stm32-metapac/stm32f779ii" ]
stm32f779ni = [ "stm32-metapac/stm32f779ni" ]
-stm32g030c6 = [ "stm32-metapac/stm32g030c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g030c8 = [ "stm32-metapac/stm32g030c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g030f6 = [ "stm32-metapac/stm32g030f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g030j6 = [ "stm32-metapac/stm32g030j6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g030k6 = [ "stm32-metapac/stm32g030k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g030k8 = [ "stm32-metapac/stm32g030k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031c4 = [ "stm32-metapac/stm32g031c4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031c6 = [ "stm32-metapac/stm32g031c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031c8 = [ "stm32-metapac/stm32g031c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031f4 = [ "stm32-metapac/stm32g031f4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031f6 = [ "stm32-metapac/stm32g031f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031f8 = [ "stm32-metapac/stm32g031f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031g4 = [ "stm32-metapac/stm32g031g4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031g6 = [ "stm32-metapac/stm32g031g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031g8 = [ "stm32-metapac/stm32g031g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031j4 = [ "stm32-metapac/stm32g031j4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031j6 = [ "stm32-metapac/stm32g031j6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031k4 = [ "stm32-metapac/stm32g031k4", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031k6 = [ "stm32-metapac/stm32g031k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031k8 = [ "stm32-metapac/stm32g031k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g031y8 = [ "stm32-metapac/stm32g031y8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041c6 = [ "stm32-metapac/stm32g041c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041c8 = [ "stm32-metapac/stm32g041c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041f6 = [ "stm32-metapac/stm32g041f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041f8 = [ "stm32-metapac/stm32g041f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041g6 = [ "stm32-metapac/stm32g041g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041g8 = [ "stm32-metapac/stm32g041g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041j6 = [ "stm32-metapac/stm32g041j6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041k6 = [ "stm32-metapac/stm32g041k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041k8 = [ "stm32-metapac/stm32g041k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g041y8 = [ "stm32-metapac/stm32g041y8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g050c6 = [ "stm32-metapac/stm32g050c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g050c8 = [ "stm32-metapac/stm32g050c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g050f6 = [ "stm32-metapac/stm32g050f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g050k6 = [ "stm32-metapac/stm32g050k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g050k8 = [ "stm32-metapac/stm32g050k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051c6 = [ "stm32-metapac/stm32g051c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051c8 = [ "stm32-metapac/stm32g051c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051f6 = [ "stm32-metapac/stm32g051f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051f8 = [ "stm32-metapac/stm32g051f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051g6 = [ "stm32-metapac/stm32g051g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051g8 = [ "stm32-metapac/stm32g051g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051k6 = [ "stm32-metapac/stm32g051k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g051k8 = [ "stm32-metapac/stm32g051k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061c6 = [ "stm32-metapac/stm32g061c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061c8 = [ "stm32-metapac/stm32g061c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061f6 = [ "stm32-metapac/stm32g061f6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061f8 = [ "stm32-metapac/stm32g061f8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061g6 = [ "stm32-metapac/stm32g061g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061g8 = [ "stm32-metapac/stm32g061g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061k6 = [ "stm32-metapac/stm32g061k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g061k8 = [ "stm32-metapac/stm32g061k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g070cb = [ "stm32-metapac/stm32g070cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g070kb = [ "stm32-metapac/stm32g070kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g070rb = [ "stm32-metapac/stm32g070rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071c6 = [ "stm32-metapac/stm32g071c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071c8 = [ "stm32-metapac/stm32g071c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071cb = [ "stm32-metapac/stm32g071cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071eb = [ "stm32-metapac/stm32g071eb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071g6 = [ "stm32-metapac/stm32g071g6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071g8 = [ "stm32-metapac/stm32g071g8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071gb = [ "stm32-metapac/stm32g071gb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071k6 = [ "stm32-metapac/stm32g071k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071k8 = [ "stm32-metapac/stm32g071k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071kb = [ "stm32-metapac/stm32g071kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071r6 = [ "stm32-metapac/stm32g071r6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071r8 = [ "stm32-metapac/stm32g071r8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g071rb = [ "stm32-metapac/stm32g071rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g081cb = [ "stm32-metapac/stm32g081cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g081eb = [ "stm32-metapac/stm32g081eb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g081gb = [ "stm32-metapac/stm32g081gb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g081kb = [ "stm32-metapac/stm32g081kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g081rb = [ "stm32-metapac/stm32g081rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b0ce = [ "stm32-metapac/stm32g0b0ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b0ke = [ "stm32-metapac/stm32g0b0ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b0re = [ "stm32-metapac/stm32g0b0re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b0ve = [ "stm32-metapac/stm32g0b0ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1cb = [ "stm32-metapac/stm32g0b1cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1cc = [ "stm32-metapac/stm32g0b1cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1ce = [ "stm32-metapac/stm32g0b1ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1kb = [ "stm32-metapac/stm32g0b1kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1kc = [ "stm32-metapac/stm32g0b1kc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1ke = [ "stm32-metapac/stm32g0b1ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1mb = [ "stm32-metapac/stm32g0b1mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1mc = [ "stm32-metapac/stm32g0b1mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1me = [ "stm32-metapac/stm32g0b1me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1ne = [ "stm32-metapac/stm32g0b1ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1rb = [ "stm32-metapac/stm32g0b1rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1rc = [ "stm32-metapac/stm32g0b1rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1re = [ "stm32-metapac/stm32g0b1re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1vb = [ "stm32-metapac/stm32g0b1vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1vc = [ "stm32-metapac/stm32g0b1vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0b1ve = [ "stm32-metapac/stm32g0b1ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1cc = [ "stm32-metapac/stm32g0c1cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1ce = [ "stm32-metapac/stm32g0c1ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1kc = [ "stm32-metapac/stm32g0c1kc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1ke = [ "stm32-metapac/stm32g0c1ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1mc = [ "stm32-metapac/stm32g0c1mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1me = [ "stm32-metapac/stm32g0c1me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1ne = [ "stm32-metapac/stm32g0c1ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1rc = [ "stm32-metapac/stm32g0c1rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1re = [ "stm32-metapac/stm32g0c1re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1vc = [ "stm32-metapac/stm32g0c1vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g0c1ve = [ "stm32-metapac/stm32g0c1ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431c6 = [ "stm32-metapac/stm32g431c6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431c8 = [ "stm32-metapac/stm32g431c8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431cb = [ "stm32-metapac/stm32g431cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431k6 = [ "stm32-metapac/stm32g431k6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431k8 = [ "stm32-metapac/stm32g431k8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431kb = [ "stm32-metapac/stm32g431kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431m6 = [ "stm32-metapac/stm32g431m6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431m8 = [ "stm32-metapac/stm32g431m8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431mb = [ "stm32-metapac/stm32g431mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431r6 = [ "stm32-metapac/stm32g431r6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431r8 = [ "stm32-metapac/stm32g431r8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431rb = [ "stm32-metapac/stm32g431rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431v6 = [ "stm32-metapac/stm32g431v6", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431v8 = [ "stm32-metapac/stm32g431v8", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g431vb = [ "stm32-metapac/stm32g431vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g441cb = [ "stm32-metapac/stm32g441cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g441kb = [ "stm32-metapac/stm32g441kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g441mb = [ "stm32-metapac/stm32g441mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g441rb = [ "stm32-metapac/stm32g441rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g441vb = [ "stm32-metapac/stm32g441vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471cc = [ "stm32-metapac/stm32g471cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471ce = [ "stm32-metapac/stm32g471ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471mc = [ "stm32-metapac/stm32g471mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471me = [ "stm32-metapac/stm32g471me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471qc = [ "stm32-metapac/stm32g471qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471qe = [ "stm32-metapac/stm32g471qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471rc = [ "stm32-metapac/stm32g471rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471re = [ "stm32-metapac/stm32g471re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471vc = [ "stm32-metapac/stm32g471vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g471ve = [ "stm32-metapac/stm32g471ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473cb = [ "stm32-metapac/stm32g473cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473cc = [ "stm32-metapac/stm32g473cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473ce = [ "stm32-metapac/stm32g473ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473mb = [ "stm32-metapac/stm32g473mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473mc = [ "stm32-metapac/stm32g473mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473me = [ "stm32-metapac/stm32g473me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473pb = [ "stm32-metapac/stm32g473pb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473pc = [ "stm32-metapac/stm32g473pc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473pe = [ "stm32-metapac/stm32g473pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473qb = [ "stm32-metapac/stm32g473qb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473qc = [ "stm32-metapac/stm32g473qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473qe = [ "stm32-metapac/stm32g473qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473rb = [ "stm32-metapac/stm32g473rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473rc = [ "stm32-metapac/stm32g473rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473re = [ "stm32-metapac/stm32g473re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473vb = [ "stm32-metapac/stm32g473vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473vc = [ "stm32-metapac/stm32g473vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g473ve = [ "stm32-metapac/stm32g473ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474cb = [ "stm32-metapac/stm32g474cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474cc = [ "stm32-metapac/stm32g474cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474ce = [ "stm32-metapac/stm32g474ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474mb = [ "stm32-metapac/stm32g474mb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474mc = [ "stm32-metapac/stm32g474mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474me = [ "stm32-metapac/stm32g474me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474pb = [ "stm32-metapac/stm32g474pb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474pc = [ "stm32-metapac/stm32g474pc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474pe = [ "stm32-metapac/stm32g474pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474qb = [ "stm32-metapac/stm32g474qb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474qc = [ "stm32-metapac/stm32g474qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474qe = [ "stm32-metapac/stm32g474qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474rb = [ "stm32-metapac/stm32g474rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474rc = [ "stm32-metapac/stm32g474rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474re = [ "stm32-metapac/stm32g474re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474vb = [ "stm32-metapac/stm32g474vb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474vc = [ "stm32-metapac/stm32g474vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g474ve = [ "stm32-metapac/stm32g474ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g483ce = [ "stm32-metapac/stm32g483ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g483me = [ "stm32-metapac/stm32g483me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g483pe = [ "stm32-metapac/stm32g483pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g483qe = [ "stm32-metapac/stm32g483qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g483re = [ "stm32-metapac/stm32g483re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g483ve = [ "stm32-metapac/stm32g483ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g484ce = [ "stm32-metapac/stm32g484ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g484me = [ "stm32-metapac/stm32g484me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g484pe = [ "stm32-metapac/stm32g484pe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g484qe = [ "stm32-metapac/stm32g484qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g484re = [ "stm32-metapac/stm32g484re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g484ve = [ "stm32-metapac/stm32g484ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491cc = [ "stm32-metapac/stm32g491cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491ce = [ "stm32-metapac/stm32g491ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491kc = [ "stm32-metapac/stm32g491kc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491ke = [ "stm32-metapac/stm32g491ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491mc = [ "stm32-metapac/stm32g491mc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491me = [ "stm32-metapac/stm32g491me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491rc = [ "stm32-metapac/stm32g491rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491re = [ "stm32-metapac/stm32g491re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491vc = [ "stm32-metapac/stm32g491vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g491ve = [ "stm32-metapac/stm32g491ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g4a1ce = [ "stm32-metapac/stm32g4a1ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g4a1ke = [ "stm32-metapac/stm32g4a1ke", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g4a1me = [ "stm32-metapac/stm32g4a1me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g4a1re = [ "stm32-metapac/stm32g4a1re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32g4a1ve = [ "stm32-metapac/stm32g4a1ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h503cb = [ "stm32-metapac/stm32h503cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h503eb = [ "stm32-metapac/stm32h503eb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h503kb = [ "stm32-metapac/stm32h503kb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h503rb = [ "stm32-metapac/stm32h503rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562ag = [ "stm32-metapac/stm32h562ag", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562ai = [ "stm32-metapac/stm32h562ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562ig = [ "stm32-metapac/stm32h562ig", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562ii = [ "stm32-metapac/stm32h562ii", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562rg = [ "stm32-metapac/stm32h562rg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562ri = [ "stm32-metapac/stm32h562ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562vg = [ "stm32-metapac/stm32h562vg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562vi = [ "stm32-metapac/stm32h562vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562zg = [ "stm32-metapac/stm32h562zg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h562zi = [ "stm32-metapac/stm32h562zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563ag = [ "stm32-metapac/stm32h563ag", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563ai = [ "stm32-metapac/stm32h563ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563ig = [ "stm32-metapac/stm32h563ig", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563ii = [ "stm32-metapac/stm32h563ii", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563mi = [ "stm32-metapac/stm32h563mi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563rg = [ "stm32-metapac/stm32h563rg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563ri = [ "stm32-metapac/stm32h563ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563vg = [ "stm32-metapac/stm32h563vg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563vi = [ "stm32-metapac/stm32h563vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563zg = [ "stm32-metapac/stm32h563zg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h563zi = [ "stm32-metapac/stm32h563zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h573ai = [ "stm32-metapac/stm32h573ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h573ii = [ "stm32-metapac/stm32h573ii", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h573mi = [ "stm32-metapac/stm32h573mi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h573ri = [ "stm32-metapac/stm32h573ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h573vi = [ "stm32-metapac/stm32h573vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h573zi = [ "stm32-metapac/stm32h573zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32h723ve = [ "stm32-metapac/stm32h723ve", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h723vg = [ "stm32-metapac/stm32h723vg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h723ze = [ "stm32-metapac/stm32h723ze", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h723zg = [ "stm32-metapac/stm32h723zg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725ae = [ "stm32-metapac/stm32h725ae", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725ag = [ "stm32-metapac/stm32h725ag", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725ie = [ "stm32-metapac/stm32h725ie", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725ig = [ "stm32-metapac/stm32h725ig", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725re = [ "stm32-metapac/stm32h725re", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725rg = [ "stm32-metapac/stm32h725rg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725ve = [ "stm32-metapac/stm32h725ve", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725vg = [ "stm32-metapac/stm32h725vg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725ze = [ "stm32-metapac/stm32h725ze", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h725zg = [ "stm32-metapac/stm32h725zg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h730ab = [ "stm32-metapac/stm32h730ab", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h730ib = [ "stm32-metapac/stm32h730ib", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h730vb = [ "stm32-metapac/stm32h730vb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h730zb = [ "stm32-metapac/stm32h730zb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h733vg = [ "stm32-metapac/stm32h733vg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h733zg = [ "stm32-metapac/stm32h733zg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h735ag = [ "stm32-metapac/stm32h735ag", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h735ig = [ "stm32-metapac/stm32h735ig", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h735rg = [ "stm32-metapac/stm32h735rg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h735vg = [ "stm32-metapac/stm32h735vg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h735zg = [ "stm32-metapac/stm32h735zg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742ag = [ "stm32-metapac/stm32h742ag", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742ai = [ "stm32-metapac/stm32h742ai", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742bg = [ "stm32-metapac/stm32h742bg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742bi = [ "stm32-metapac/stm32h742bi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742ig = [ "stm32-metapac/stm32h742ig", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742ii = [ "stm32-metapac/stm32h742ii", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742vg = [ "stm32-metapac/stm32h742vg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742vi = [ "stm32-metapac/stm32h742vi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742xg = [ "stm32-metapac/stm32h742xg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742xi = [ "stm32-metapac/stm32h742xi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742zg = [ "stm32-metapac/stm32h742zg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h742zi = [ "stm32-metapac/stm32h742zi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743ag = [ "stm32-metapac/stm32h743ag", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743ai = [ "stm32-metapac/stm32h743ai", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743bg = [ "stm32-metapac/stm32h743bg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743bi = [ "stm32-metapac/stm32h743bi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743ig = [ "stm32-metapac/stm32h743ig", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743ii = [ "stm32-metapac/stm32h743ii", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743vg = [ "stm32-metapac/stm32h743vg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743vi = [ "stm32-metapac/stm32h743vi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743xg = [ "stm32-metapac/stm32h743xg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743xi = [ "stm32-metapac/stm32h743xi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743zg = [ "stm32-metapac/stm32h743zg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h743zi = [ "stm32-metapac/stm32h743zi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h750ib = [ "stm32-metapac/stm32h750ib", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h750vb = [ "stm32-metapac/stm32h750vb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h750xb = [ "stm32-metapac/stm32h750xb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h750zb = [ "stm32-metapac/stm32h750zb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h753ai = [ "stm32-metapac/stm32h753ai", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h753bi = [ "stm32-metapac/stm32h753bi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h753ii = [ "stm32-metapac/stm32h753ii", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h753vi = [ "stm32-metapac/stm32h753vi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h753xi = [ "stm32-metapac/stm32h753xi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h753zi = [ "stm32-metapac/stm32h753zi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3ii = [ "stm32-metapac/stm32h7a3ii", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3lg = [ "stm32-metapac/stm32h7a3lg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3li = [ "stm32-metapac/stm32h7a3li", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3ng = [ "stm32-metapac/stm32h7a3ng", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3ni = [ "stm32-metapac/stm32h7a3ni", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3qi = [ "stm32-metapac/stm32h7a3qi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3rg = [ "stm32-metapac/stm32h7a3rg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3ri = [ "stm32-metapac/stm32h7a3ri", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3vg = [ "stm32-metapac/stm32h7a3vg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3vi = [ "stm32-metapac/stm32h7a3vi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3zg = [ "stm32-metapac/stm32h7a3zg", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7a3zi = [ "stm32-metapac/stm32h7a3zi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b0ab = [ "stm32-metapac/stm32h7b0ab", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b0ib = [ "stm32-metapac/stm32h7b0ib", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b0rb = [ "stm32-metapac/stm32h7b0rb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b0vb = [ "stm32-metapac/stm32h7b0vb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b0zb = [ "stm32-metapac/stm32h7b0zb", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3ai = [ "stm32-metapac/stm32h7b3ai", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3ii = [ "stm32-metapac/stm32h7b3ii", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3li = [ "stm32-metapac/stm32h7b3li", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3ni = [ "stm32-metapac/stm32h7b3ni", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3qi = [ "stm32-metapac/stm32h7b3qi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3ri = [ "stm32-metapac/stm32h7b3ri", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3vi = [ "stm32-metapac/stm32h7b3vi", "dep:fdcan", "fdcan/fdcan_h7" ]
-stm32h7b3zi = [ "stm32-metapac/stm32h7b3zi", "dep:fdcan", "fdcan/fdcan_h7" ]
+stm32g030c6 = [ "stm32-metapac/stm32g030c6" ]
+stm32g030c8 = [ "stm32-metapac/stm32g030c8" ]
+stm32g030f6 = [ "stm32-metapac/stm32g030f6" ]
+stm32g030j6 = [ "stm32-metapac/stm32g030j6" ]
+stm32g030k6 = [ "stm32-metapac/stm32g030k6" ]
+stm32g030k8 = [ "stm32-metapac/stm32g030k8" ]
+stm32g031c4 = [ "stm32-metapac/stm32g031c4" ]
+stm32g031c6 = [ "stm32-metapac/stm32g031c6" ]
+stm32g031c8 = [ "stm32-metapac/stm32g031c8" ]
+stm32g031f4 = [ "stm32-metapac/stm32g031f4" ]
+stm32g031f6 = [ "stm32-metapac/stm32g031f6" ]
+stm32g031f8 = [ "stm32-metapac/stm32g031f8" ]
+stm32g031g4 = [ "stm32-metapac/stm32g031g4" ]
+stm32g031g6 = [ "stm32-metapac/stm32g031g6" ]
+stm32g031g8 = [ "stm32-metapac/stm32g031g8" ]
+stm32g031j4 = [ "stm32-metapac/stm32g031j4" ]
+stm32g031j6 = [ "stm32-metapac/stm32g031j6" ]
+stm32g031k4 = [ "stm32-metapac/stm32g031k4" ]
+stm32g031k6 = [ "stm32-metapac/stm32g031k6" ]
+stm32g031k8 = [ "stm32-metapac/stm32g031k8" ]
+stm32g031y8 = [ "stm32-metapac/stm32g031y8" ]
+stm32g041c6 = [ "stm32-metapac/stm32g041c6" ]
+stm32g041c8 = [ "stm32-metapac/stm32g041c8" ]
+stm32g041f6 = [ "stm32-metapac/stm32g041f6" ]
+stm32g041f8 = [ "stm32-metapac/stm32g041f8" ]
+stm32g041g6 = [ "stm32-metapac/stm32g041g6" ]
+stm32g041g8 = [ "stm32-metapac/stm32g041g8" ]
+stm32g041j6 = [ "stm32-metapac/stm32g041j6" ]
+stm32g041k6 = [ "stm32-metapac/stm32g041k6" ]
+stm32g041k8 = [ "stm32-metapac/stm32g041k8" ]
+stm32g041y8 = [ "stm32-metapac/stm32g041y8" ]
+stm32g050c6 = [ "stm32-metapac/stm32g050c6" ]
+stm32g050c8 = [ "stm32-metapac/stm32g050c8" ]
+stm32g050f6 = [ "stm32-metapac/stm32g050f6" ]
+stm32g050k6 = [ "stm32-metapac/stm32g050k6" ]
+stm32g050k8 = [ "stm32-metapac/stm32g050k8" ]
+stm32g051c6 = [ "stm32-metapac/stm32g051c6" ]
+stm32g051c8 = [ "stm32-metapac/stm32g051c8" ]
+stm32g051f6 = [ "stm32-metapac/stm32g051f6" ]
+stm32g051f8 = [ "stm32-metapac/stm32g051f8" ]
+stm32g051g6 = [ "stm32-metapac/stm32g051g6" ]
+stm32g051g8 = [ "stm32-metapac/stm32g051g8" ]
+stm32g051k6 = [ "stm32-metapac/stm32g051k6" ]
+stm32g051k8 = [ "stm32-metapac/stm32g051k8" ]
+stm32g061c6 = [ "stm32-metapac/stm32g061c6" ]
+stm32g061c8 = [ "stm32-metapac/stm32g061c8" ]
+stm32g061f6 = [ "stm32-metapac/stm32g061f6" ]
+stm32g061f8 = [ "stm32-metapac/stm32g061f8" ]
+stm32g061g6 = [ "stm32-metapac/stm32g061g6" ]
+stm32g061g8 = [ "stm32-metapac/stm32g061g8" ]
+stm32g061k6 = [ "stm32-metapac/stm32g061k6" ]
+stm32g061k8 = [ "stm32-metapac/stm32g061k8" ]
+stm32g070cb = [ "stm32-metapac/stm32g070cb" ]
+stm32g070kb = [ "stm32-metapac/stm32g070kb" ]
+stm32g070rb = [ "stm32-metapac/stm32g070rb" ]
+stm32g071c6 = [ "stm32-metapac/stm32g071c6" ]
+stm32g071c8 = [ "stm32-metapac/stm32g071c8" ]
+stm32g071cb = [ "stm32-metapac/stm32g071cb" ]
+stm32g071eb = [ "stm32-metapac/stm32g071eb" ]
+stm32g071g6 = [ "stm32-metapac/stm32g071g6" ]
+stm32g071g8 = [ "stm32-metapac/stm32g071g8" ]
+stm32g071gb = [ "stm32-metapac/stm32g071gb" ]
+stm32g071k6 = [ "stm32-metapac/stm32g071k6" ]
+stm32g071k8 = [ "stm32-metapac/stm32g071k8" ]
+stm32g071kb = [ "stm32-metapac/stm32g071kb" ]
+stm32g071r6 = [ "stm32-metapac/stm32g071r6" ]
+stm32g071r8 = [ "stm32-metapac/stm32g071r8" ]
+stm32g071rb = [ "stm32-metapac/stm32g071rb" ]
+stm32g081cb = [ "stm32-metapac/stm32g081cb" ]
+stm32g081eb = [ "stm32-metapac/stm32g081eb" ]
+stm32g081gb = [ "stm32-metapac/stm32g081gb" ]
+stm32g081kb = [ "stm32-metapac/stm32g081kb" ]
+stm32g081rb = [ "stm32-metapac/stm32g081rb" ]
+stm32g0b0ce = [ "stm32-metapac/stm32g0b0ce" ]
+stm32g0b0ke = [ "stm32-metapac/stm32g0b0ke" ]
+stm32g0b0re = [ "stm32-metapac/stm32g0b0re" ]
+stm32g0b0ve = [ "stm32-metapac/stm32g0b0ve" ]
+stm32g0b1cb = [ "stm32-metapac/stm32g0b1cb" ]
+stm32g0b1cc = [ "stm32-metapac/stm32g0b1cc" ]
+stm32g0b1ce = [ "stm32-metapac/stm32g0b1ce" ]
+stm32g0b1kb = [ "stm32-metapac/stm32g0b1kb" ]
+stm32g0b1kc = [ "stm32-metapac/stm32g0b1kc" ]
+stm32g0b1ke = [ "stm32-metapac/stm32g0b1ke" ]
+stm32g0b1mb = [ "stm32-metapac/stm32g0b1mb" ]
+stm32g0b1mc = [ "stm32-metapac/stm32g0b1mc" ]
+stm32g0b1me = [ "stm32-metapac/stm32g0b1me" ]
+stm32g0b1ne = [ "stm32-metapac/stm32g0b1ne" ]
+stm32g0b1rb = [ "stm32-metapac/stm32g0b1rb" ]
+stm32g0b1rc = [ "stm32-metapac/stm32g0b1rc" ]
+stm32g0b1re = [ "stm32-metapac/stm32g0b1re" ]
+stm32g0b1vb = [ "stm32-metapac/stm32g0b1vb" ]
+stm32g0b1vc = [ "stm32-metapac/stm32g0b1vc" ]
+stm32g0b1ve = [ "stm32-metapac/stm32g0b1ve" ]
+stm32g0c1cc = [ "stm32-metapac/stm32g0c1cc" ]
+stm32g0c1ce = [ "stm32-metapac/stm32g0c1ce" ]
+stm32g0c1kc = [ "stm32-metapac/stm32g0c1kc" ]
+stm32g0c1ke = [ "stm32-metapac/stm32g0c1ke" ]
+stm32g0c1mc = [ "stm32-metapac/stm32g0c1mc" ]
+stm32g0c1me = [ "stm32-metapac/stm32g0c1me" ]
+stm32g0c1ne = [ "stm32-metapac/stm32g0c1ne" ]
+stm32g0c1rc = [ "stm32-metapac/stm32g0c1rc" ]
+stm32g0c1re = [ "stm32-metapac/stm32g0c1re" ]
+stm32g0c1vc = [ "stm32-metapac/stm32g0c1vc" ]
+stm32g0c1ve = [ "stm32-metapac/stm32g0c1ve" ]
+stm32g431c6 = [ "stm32-metapac/stm32g431c6" ]
+stm32g431c8 = [ "stm32-metapac/stm32g431c8" ]
+stm32g431cb = [ "stm32-metapac/stm32g431cb" ]
+stm32g431k6 = [ "stm32-metapac/stm32g431k6" ]
+stm32g431k8 = [ "stm32-metapac/stm32g431k8" ]
+stm32g431kb = [ "stm32-metapac/stm32g431kb" ]
+stm32g431m6 = [ "stm32-metapac/stm32g431m6" ]
+stm32g431m8 = [ "stm32-metapac/stm32g431m8" ]
+stm32g431mb = [ "stm32-metapac/stm32g431mb" ]
+stm32g431r6 = [ "stm32-metapac/stm32g431r6" ]
+stm32g431r8 = [ "stm32-metapac/stm32g431r8" ]
+stm32g431rb = [ "stm32-metapac/stm32g431rb" ]
+stm32g431v6 = [ "stm32-metapac/stm32g431v6" ]
+stm32g431v8 = [ "stm32-metapac/stm32g431v8" ]
+stm32g431vb = [ "stm32-metapac/stm32g431vb" ]
+stm32g441cb = [ "stm32-metapac/stm32g441cb" ]
+stm32g441kb = [ "stm32-metapac/stm32g441kb" ]
+stm32g441mb = [ "stm32-metapac/stm32g441mb" ]
+stm32g441rb = [ "stm32-metapac/stm32g441rb" ]
+stm32g441vb = [ "stm32-metapac/stm32g441vb" ]
+stm32g471cc = [ "stm32-metapac/stm32g471cc" ]
+stm32g471ce = [ "stm32-metapac/stm32g471ce" ]
+stm32g471mc = [ "stm32-metapac/stm32g471mc" ]
+stm32g471me = [ "stm32-metapac/stm32g471me" ]
+stm32g471qc = [ "stm32-metapac/stm32g471qc" ]
+stm32g471qe = [ "stm32-metapac/stm32g471qe" ]
+stm32g471rc = [ "stm32-metapac/stm32g471rc" ]
+stm32g471re = [ "stm32-metapac/stm32g471re" ]
+stm32g471vc = [ "stm32-metapac/stm32g471vc" ]
+stm32g471ve = [ "stm32-metapac/stm32g471ve" ]
+stm32g473cb = [ "stm32-metapac/stm32g473cb" ]
+stm32g473cc = [ "stm32-metapac/stm32g473cc" ]
+stm32g473ce = [ "stm32-metapac/stm32g473ce" ]
+stm32g473mb = [ "stm32-metapac/stm32g473mb" ]
+stm32g473mc = [ "stm32-metapac/stm32g473mc" ]
+stm32g473me = [ "stm32-metapac/stm32g473me" ]
+stm32g473pb = [ "stm32-metapac/stm32g473pb" ]
+stm32g473pc = [ "stm32-metapac/stm32g473pc" ]
+stm32g473pe = [ "stm32-metapac/stm32g473pe" ]
+stm32g473qb = [ "stm32-metapac/stm32g473qb" ]
+stm32g473qc = [ "stm32-metapac/stm32g473qc" ]
+stm32g473qe = [ "stm32-metapac/stm32g473qe" ]
+stm32g473rb = [ "stm32-metapac/stm32g473rb" ]
+stm32g473rc = [ "stm32-metapac/stm32g473rc" ]
+stm32g473re = [ "stm32-metapac/stm32g473re" ]
+stm32g473vb = [ "stm32-metapac/stm32g473vb" ]
+stm32g473vc = [ "stm32-metapac/stm32g473vc" ]
+stm32g473ve = [ "stm32-metapac/stm32g473ve" ]
+stm32g474cb = [ "stm32-metapac/stm32g474cb" ]
+stm32g474cc = [ "stm32-metapac/stm32g474cc" ]
+stm32g474ce = [ "stm32-metapac/stm32g474ce" ]
+stm32g474mb = [ "stm32-metapac/stm32g474mb" ]
+stm32g474mc = [ "stm32-metapac/stm32g474mc" ]
+stm32g474me = [ "stm32-metapac/stm32g474me" ]
+stm32g474pb = [ "stm32-metapac/stm32g474pb" ]
+stm32g474pc = [ "stm32-metapac/stm32g474pc" ]
+stm32g474pe = [ "stm32-metapac/stm32g474pe" ]
+stm32g474qb = [ "stm32-metapac/stm32g474qb" ]
+stm32g474qc = [ "stm32-metapac/stm32g474qc" ]
+stm32g474qe = [ "stm32-metapac/stm32g474qe" ]
+stm32g474rb = [ "stm32-metapac/stm32g474rb" ]
+stm32g474rc = [ "stm32-metapac/stm32g474rc" ]
+stm32g474re = [ "stm32-metapac/stm32g474re" ]
+stm32g474vb = [ "stm32-metapac/stm32g474vb" ]
+stm32g474vc = [ "stm32-metapac/stm32g474vc" ]
+stm32g474ve = [ "stm32-metapac/stm32g474ve" ]
+stm32g483ce = [ "stm32-metapac/stm32g483ce" ]
+stm32g483me = [ "stm32-metapac/stm32g483me" ]
+stm32g483pe = [ "stm32-metapac/stm32g483pe" ]
+stm32g483qe = [ "stm32-metapac/stm32g483qe" ]
+stm32g483re = [ "stm32-metapac/stm32g483re" ]
+stm32g483ve = [ "stm32-metapac/stm32g483ve" ]
+stm32g484ce = [ "stm32-metapac/stm32g484ce" ]
+stm32g484me = [ "stm32-metapac/stm32g484me" ]
+stm32g484pe = [ "stm32-metapac/stm32g484pe" ]
+stm32g484qe = [ "stm32-metapac/stm32g484qe" ]
+stm32g484re = [ "stm32-metapac/stm32g484re" ]
+stm32g484ve = [ "stm32-metapac/stm32g484ve" ]
+stm32g491cc = [ "stm32-metapac/stm32g491cc" ]
+stm32g491ce = [ "stm32-metapac/stm32g491ce" ]
+stm32g491kc = [ "stm32-metapac/stm32g491kc" ]
+stm32g491ke = [ "stm32-metapac/stm32g491ke" ]
+stm32g491mc = [ "stm32-metapac/stm32g491mc" ]
+stm32g491me = [ "stm32-metapac/stm32g491me" ]
+stm32g491rc = [ "stm32-metapac/stm32g491rc" ]
+stm32g491re = [ "stm32-metapac/stm32g491re" ]
+stm32g491vc = [ "stm32-metapac/stm32g491vc" ]
+stm32g491ve = [ "stm32-metapac/stm32g491ve" ]
+stm32g4a1ce = [ "stm32-metapac/stm32g4a1ce" ]
+stm32g4a1ke = [ "stm32-metapac/stm32g4a1ke" ]
+stm32g4a1me = [ "stm32-metapac/stm32g4a1me" ]
+stm32g4a1re = [ "stm32-metapac/stm32g4a1re" ]
+stm32g4a1ve = [ "stm32-metapac/stm32g4a1ve" ]
+stm32h503cb = [ "stm32-metapac/stm32h503cb" ]
+stm32h503eb = [ "stm32-metapac/stm32h503eb" ]
+stm32h503kb = [ "stm32-metapac/stm32h503kb" ]
+stm32h503rb = [ "stm32-metapac/stm32h503rb" ]
+stm32h562ag = [ "stm32-metapac/stm32h562ag" ]
+stm32h562ai = [ "stm32-metapac/stm32h562ai" ]
+stm32h562ig = [ "stm32-metapac/stm32h562ig" ]
+stm32h562ii = [ "stm32-metapac/stm32h562ii" ]
+stm32h562rg = [ "stm32-metapac/stm32h562rg" ]
+stm32h562ri = [ "stm32-metapac/stm32h562ri" ]
+stm32h562vg = [ "stm32-metapac/stm32h562vg" ]
+stm32h562vi = [ "stm32-metapac/stm32h562vi" ]
+stm32h562zg = [ "stm32-metapac/stm32h562zg" ]
+stm32h562zi = [ "stm32-metapac/stm32h562zi" ]
+stm32h563ag = [ "stm32-metapac/stm32h563ag" ]
+stm32h563ai = [ "stm32-metapac/stm32h563ai" ]
+stm32h563ig = [ "stm32-metapac/stm32h563ig" ]
+stm32h563ii = [ "stm32-metapac/stm32h563ii" ]
+stm32h563mi = [ "stm32-metapac/stm32h563mi" ]
+stm32h563rg = [ "stm32-metapac/stm32h563rg" ]
+stm32h563ri = [ "stm32-metapac/stm32h563ri" ]
+stm32h563vg = [ "stm32-metapac/stm32h563vg" ]
+stm32h563vi = [ "stm32-metapac/stm32h563vi" ]
+stm32h563zg = [ "stm32-metapac/stm32h563zg" ]
+stm32h563zi = [ "stm32-metapac/stm32h563zi" ]
+stm32h573ai = [ "stm32-metapac/stm32h573ai" ]
+stm32h573ii = [ "stm32-metapac/stm32h573ii" ]
+stm32h573mi = [ "stm32-metapac/stm32h573mi" ]
+stm32h573ri = [ "stm32-metapac/stm32h573ri" ]
+stm32h573vi = [ "stm32-metapac/stm32h573vi" ]
+stm32h573zi = [ "stm32-metapac/stm32h573zi" ]
+stm32h723ve = [ "stm32-metapac/stm32h723ve" ]
+stm32h723vg = [ "stm32-metapac/stm32h723vg" ]
+stm32h723ze = [ "stm32-metapac/stm32h723ze" ]
+stm32h723zg = [ "stm32-metapac/stm32h723zg" ]
+stm32h725ae = [ "stm32-metapac/stm32h725ae" ]
+stm32h725ag = [ "stm32-metapac/stm32h725ag" ]
+stm32h725ie = [ "stm32-metapac/stm32h725ie" ]
+stm32h725ig = [ "stm32-metapac/stm32h725ig" ]
+stm32h725re = [ "stm32-metapac/stm32h725re" ]
+stm32h725rg = [ "stm32-metapac/stm32h725rg" ]
+stm32h725ve = [ "stm32-metapac/stm32h725ve" ]
+stm32h725vg = [ "stm32-metapac/stm32h725vg" ]
+stm32h725ze = [ "stm32-metapac/stm32h725ze" ]
+stm32h725zg = [ "stm32-metapac/stm32h725zg" ]
+stm32h730ab = [ "stm32-metapac/stm32h730ab" ]
+stm32h730ib = [ "stm32-metapac/stm32h730ib" ]
+stm32h730vb = [ "stm32-metapac/stm32h730vb" ]
+stm32h730zb = [ "stm32-metapac/stm32h730zb" ]
+stm32h733vg = [ "stm32-metapac/stm32h733vg" ]
+stm32h733zg = [ "stm32-metapac/stm32h733zg" ]
+stm32h735ag = [ "stm32-metapac/stm32h735ag" ]
+stm32h735ig = [ "stm32-metapac/stm32h735ig" ]
+stm32h735rg = [ "stm32-metapac/stm32h735rg" ]
+stm32h735vg = [ "stm32-metapac/stm32h735vg" ]
+stm32h735zg = [ "stm32-metapac/stm32h735zg" ]
+stm32h742ag = [ "stm32-metapac/stm32h742ag" ]
+stm32h742ai = [ "stm32-metapac/stm32h742ai" ]
+stm32h742bg = [ "stm32-metapac/stm32h742bg" ]
+stm32h742bi = [ "stm32-metapac/stm32h742bi" ]
+stm32h742ig = [ "stm32-metapac/stm32h742ig" ]
+stm32h742ii = [ "stm32-metapac/stm32h742ii" ]
+stm32h742vg = [ "stm32-metapac/stm32h742vg" ]
+stm32h742vi = [ "stm32-metapac/stm32h742vi" ]
+stm32h742xg = [ "stm32-metapac/stm32h742xg" ]
+stm32h742xi = [ "stm32-metapac/stm32h742xi" ]
+stm32h742zg = [ "stm32-metapac/stm32h742zg" ]
+stm32h742zi = [ "stm32-metapac/stm32h742zi" ]
+stm32h743ag = [ "stm32-metapac/stm32h743ag" ]
+stm32h743ai = [ "stm32-metapac/stm32h743ai" ]
+stm32h743bg = [ "stm32-metapac/stm32h743bg" ]
+stm32h743bi = [ "stm32-metapac/stm32h743bi" ]
+stm32h743ig = [ "stm32-metapac/stm32h743ig" ]
+stm32h743ii = [ "stm32-metapac/stm32h743ii" ]
+stm32h743vg = [ "stm32-metapac/stm32h743vg" ]
+stm32h743vi = [ "stm32-metapac/stm32h743vi" ]
+stm32h743xg = [ "stm32-metapac/stm32h743xg" ]
+stm32h743xi = [ "stm32-metapac/stm32h743xi" ]
+stm32h743zg = [ "stm32-metapac/stm32h743zg" ]
+stm32h743zi = [ "stm32-metapac/stm32h743zi" ]
+stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7" ]
+stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4" ]
+stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7" ]
+stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4" ]
+stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7" ]
+stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4" ]
+stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7" ]
+stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4" ]
+stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7" ]
+stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4" ]
+stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7" ]
+stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4" ]
+stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7" ]
+stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4" ]
+stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7" ]
+stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4" ]
+stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7" ]
+stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4" ]
+stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7" ]
+stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4" ]
+stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7" ]
+stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4" ]
+stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7" ]
+stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4" ]
+stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7" ]
+stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4" ]
+stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7" ]
+stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4" ]
+stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7" ]
+stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4" ]
+stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7" ]
+stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4" ]
+stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7" ]
+stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4" ]
+stm32h750ib = [ "stm32-metapac/stm32h750ib" ]
+stm32h750vb = [ "stm32-metapac/stm32h750vb" ]
+stm32h750xb = [ "stm32-metapac/stm32h750xb" ]
+stm32h750zb = [ "stm32-metapac/stm32h750zb" ]
+stm32h753ai = [ "stm32-metapac/stm32h753ai" ]
+stm32h753bi = [ "stm32-metapac/stm32h753bi" ]
+stm32h753ii = [ "stm32-metapac/stm32h753ii" ]
+stm32h753vi = [ "stm32-metapac/stm32h753vi" ]
+stm32h753xi = [ "stm32-metapac/stm32h753xi" ]
+stm32h753zi = [ "stm32-metapac/stm32h753zi" ]
+stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7" ]
+stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4" ]
+stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7" ]
+stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4" ]
+stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7" ]
+stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4" ]
+stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7" ]
+stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4" ]
+stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7" ]
+stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4" ]
+stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7" ]
+stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4" ]
+stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7" ]
+stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4" ]
+stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7" ]
+stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4" ]
+stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7" ]
+stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4" ]
+stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag" ]
+stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai" ]
+stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig" ]
+stm32h7a3ii = [ "stm32-metapac/stm32h7a3ii" ]
+stm32h7a3lg = [ "stm32-metapac/stm32h7a3lg" ]
+stm32h7a3li = [ "stm32-metapac/stm32h7a3li" ]
+stm32h7a3ng = [ "stm32-metapac/stm32h7a3ng" ]
+stm32h7a3ni = [ "stm32-metapac/stm32h7a3ni" ]
+stm32h7a3qi = [ "stm32-metapac/stm32h7a3qi" ]
+stm32h7a3rg = [ "stm32-metapac/stm32h7a3rg" ]
+stm32h7a3ri = [ "stm32-metapac/stm32h7a3ri" ]
+stm32h7a3vg = [ "stm32-metapac/stm32h7a3vg" ]
+stm32h7a3vi = [ "stm32-metapac/stm32h7a3vi" ]
+stm32h7a3zg = [ "stm32-metapac/stm32h7a3zg" ]
+stm32h7a3zi = [ "stm32-metapac/stm32h7a3zi" ]
+stm32h7b0ab = [ "stm32-metapac/stm32h7b0ab" ]
+stm32h7b0ib = [ "stm32-metapac/stm32h7b0ib" ]
+stm32h7b0rb = [ "stm32-metapac/stm32h7b0rb" ]
+stm32h7b0vb = [ "stm32-metapac/stm32h7b0vb" ]
+stm32h7b0zb = [ "stm32-metapac/stm32h7b0zb" ]
+stm32h7b3ai = [ "stm32-metapac/stm32h7b3ai" ]
+stm32h7b3ii = [ "stm32-metapac/stm32h7b3ii" ]
+stm32h7b3li = [ "stm32-metapac/stm32h7b3li" ]
+stm32h7b3ni = [ "stm32-metapac/stm32h7b3ni" ]
+stm32h7b3qi = [ "stm32-metapac/stm32h7b3qi" ]
+stm32h7b3ri = [ "stm32-metapac/stm32h7b3ri" ]
+stm32h7b3vi = [ "stm32-metapac/stm32h7b3vi" ]
+stm32h7b3zi = [ "stm32-metapac/stm32h7b3zi" ]
stm32l010c6 = [ "stm32-metapac/stm32l010c6" ]
stm32l010f4 = [ "stm32-metapac/stm32l010f4" ]
stm32l010k4 = [ "stm32-metapac/stm32l010k4" ]
@@ -1388,86 +1393,86 @@ stm32l4s7zi = [ "stm32-metapac/stm32l4s7zi" ]
stm32l4s9ai = [ "stm32-metapac/stm32l4s9ai" ]
stm32l4s9vi = [ "stm32-metapac/stm32l4s9vi" ]
stm32l4s9zi = [ "stm32-metapac/stm32l4s9zi" ]
-stm32l552cc = [ "stm32-metapac/stm32l552cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552ce = [ "stm32-metapac/stm32l552ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552me = [ "stm32-metapac/stm32l552me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552qc = [ "stm32-metapac/stm32l552qc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552qe = [ "stm32-metapac/stm32l552qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552rc = [ "stm32-metapac/stm32l552rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552re = [ "stm32-metapac/stm32l552re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552vc = [ "stm32-metapac/stm32l552vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552ve = [ "stm32-metapac/stm32l552ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552zc = [ "stm32-metapac/stm32l552zc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l552ze = [ "stm32-metapac/stm32l552ze", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l562ce = [ "stm32-metapac/stm32l562ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l562me = [ "stm32-metapac/stm32l562me", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l562qe = [ "stm32-metapac/stm32l562qe", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l562re = [ "stm32-metapac/stm32l562re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l562ve = [ "stm32-metapac/stm32l562ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32l562ze = [ "stm32-metapac/stm32l562ze", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535cb = [ "stm32-metapac/stm32u535cb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535cc = [ "stm32-metapac/stm32u535cc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535ce = [ "stm32-metapac/stm32u535ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535je = [ "stm32-metapac/stm32u535je", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535nc = [ "stm32-metapac/stm32u535nc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535ne = [ "stm32-metapac/stm32u535ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535rb = [ "stm32-metapac/stm32u535rb", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535rc = [ "stm32-metapac/stm32u535rc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535re = [ "stm32-metapac/stm32u535re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535vc = [ "stm32-metapac/stm32u535vc", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u535ve = [ "stm32-metapac/stm32u535ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u545ce = [ "stm32-metapac/stm32u545ce", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u545je = [ "stm32-metapac/stm32u545je", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u545ne = [ "stm32-metapac/stm32u545ne", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u545re = [ "stm32-metapac/stm32u545re", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u545ve = [ "stm32-metapac/stm32u545ve", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575ag = [ "stm32-metapac/stm32u575ag", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575ai = [ "stm32-metapac/stm32u575ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575cg = [ "stm32-metapac/stm32u575cg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575ci = [ "stm32-metapac/stm32u575ci", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575og = [ "stm32-metapac/stm32u575og", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575oi = [ "stm32-metapac/stm32u575oi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575qg = [ "stm32-metapac/stm32u575qg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575qi = [ "stm32-metapac/stm32u575qi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575rg = [ "stm32-metapac/stm32u575rg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575ri = [ "stm32-metapac/stm32u575ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575vg = [ "stm32-metapac/stm32u575vg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575vi = [ "stm32-metapac/stm32u575vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575zg = [ "stm32-metapac/stm32u575zg", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u575zi = [ "stm32-metapac/stm32u575zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u585ai = [ "stm32-metapac/stm32u585ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u585ci = [ "stm32-metapac/stm32u585ci", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u585oi = [ "stm32-metapac/stm32u585oi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u585qi = [ "stm32-metapac/stm32u585qi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u585ri = [ "stm32-metapac/stm32u585ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u585vi = [ "stm32-metapac/stm32u585vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u585zi = [ "stm32-metapac/stm32u585zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595ai = [ "stm32-metapac/stm32u595ai", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595aj = [ "stm32-metapac/stm32u595aj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595qi = [ "stm32-metapac/stm32u595qi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595qj = [ "stm32-metapac/stm32u595qj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595ri = [ "stm32-metapac/stm32u595ri", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595rj = [ "stm32-metapac/stm32u595rj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595vi = [ "stm32-metapac/stm32u595vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595vj = [ "stm32-metapac/stm32u595vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595zi = [ "stm32-metapac/stm32u595zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u595zj = [ "stm32-metapac/stm32u595zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u599bj = [ "stm32-metapac/stm32u599bj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u599ni = [ "stm32-metapac/stm32u599ni", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u599nj = [ "stm32-metapac/stm32u599nj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u599vi = [ "stm32-metapac/stm32u599vi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u599vj = [ "stm32-metapac/stm32u599vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u599zi = [ "stm32-metapac/stm32u599zi", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u599zj = [ "stm32-metapac/stm32u599zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a5aj = [ "stm32-metapac/stm32u5a5aj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a5qj = [ "stm32-metapac/stm32u5a5qj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a5rj = [ "stm32-metapac/stm32u5a5rj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a5vj = [ "stm32-metapac/stm32u5a5vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a5zj = [ "stm32-metapac/stm32u5a5zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a9bj = [ "stm32-metapac/stm32u5a9bj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a9nj = [ "stm32-metapac/stm32u5a9nj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a9vj = [ "stm32-metapac/stm32u5a9vj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
-stm32u5a9zj = [ "stm32-metapac/stm32u5a9zj", "dep:fdcan", "fdcan/fdcan_g0_g4_l5" ]
+stm32l552cc = [ "stm32-metapac/stm32l552cc" ]
+stm32l552ce = [ "stm32-metapac/stm32l552ce" ]
+stm32l552me = [ "stm32-metapac/stm32l552me" ]
+stm32l552qc = [ "stm32-metapac/stm32l552qc" ]
+stm32l552qe = [ "stm32-metapac/stm32l552qe" ]
+stm32l552rc = [ "stm32-metapac/stm32l552rc" ]
+stm32l552re = [ "stm32-metapac/stm32l552re" ]
+stm32l552vc = [ "stm32-metapac/stm32l552vc" ]
+stm32l552ve = [ "stm32-metapac/stm32l552ve" ]
+stm32l552zc = [ "stm32-metapac/stm32l552zc" ]
+stm32l552ze = [ "stm32-metapac/stm32l552ze" ]
+stm32l562ce = [ "stm32-metapac/stm32l562ce" ]
+stm32l562me = [ "stm32-metapac/stm32l562me" ]
+stm32l562qe = [ "stm32-metapac/stm32l562qe" ]
+stm32l562re = [ "stm32-metapac/stm32l562re" ]
+stm32l562ve = [ "stm32-metapac/stm32l562ve" ]
+stm32l562ze = [ "stm32-metapac/stm32l562ze" ]
+stm32u535cb = [ "stm32-metapac/stm32u535cb" ]
+stm32u535cc = [ "stm32-metapac/stm32u535cc" ]
+stm32u535ce = [ "stm32-metapac/stm32u535ce" ]
+stm32u535je = [ "stm32-metapac/stm32u535je" ]
+stm32u535nc = [ "stm32-metapac/stm32u535nc" ]
+stm32u535ne = [ "stm32-metapac/stm32u535ne" ]
+stm32u535rb = [ "stm32-metapac/stm32u535rb" ]
+stm32u535rc = [ "stm32-metapac/stm32u535rc" ]
+stm32u535re = [ "stm32-metapac/stm32u535re" ]
+stm32u535vc = [ "stm32-metapac/stm32u535vc" ]
+stm32u535ve = [ "stm32-metapac/stm32u535ve" ]
+stm32u545ce = [ "stm32-metapac/stm32u545ce" ]
+stm32u545je = [ "stm32-metapac/stm32u545je" ]
+stm32u545ne = [ "stm32-metapac/stm32u545ne" ]
+stm32u545re = [ "stm32-metapac/stm32u545re" ]
+stm32u545ve = [ "stm32-metapac/stm32u545ve" ]
+stm32u575ag = [ "stm32-metapac/stm32u575ag" ]
+stm32u575ai = [ "stm32-metapac/stm32u575ai" ]
+stm32u575cg = [ "stm32-metapac/stm32u575cg" ]
+stm32u575ci = [ "stm32-metapac/stm32u575ci" ]
+stm32u575og = [ "stm32-metapac/stm32u575og" ]
+stm32u575oi = [ "stm32-metapac/stm32u575oi" ]
+stm32u575qg = [ "stm32-metapac/stm32u575qg" ]
+stm32u575qi = [ "stm32-metapac/stm32u575qi" ]
+stm32u575rg = [ "stm32-metapac/stm32u575rg" ]
+stm32u575ri = [ "stm32-metapac/stm32u575ri" ]
+stm32u575vg = [ "stm32-metapac/stm32u575vg" ]
+stm32u575vi = [ "stm32-metapac/stm32u575vi" ]
+stm32u575zg = [ "stm32-metapac/stm32u575zg" ]
+stm32u575zi = [ "stm32-metapac/stm32u575zi" ]
+stm32u585ai = [ "stm32-metapac/stm32u585ai" ]
+stm32u585ci = [ "stm32-metapac/stm32u585ci" ]
+stm32u585oi = [ "stm32-metapac/stm32u585oi" ]
+stm32u585qi = [ "stm32-metapac/stm32u585qi" ]
+stm32u585ri = [ "stm32-metapac/stm32u585ri" ]
+stm32u585vi = [ "stm32-metapac/stm32u585vi" ]
+stm32u585zi = [ "stm32-metapac/stm32u585zi" ]
+stm32u595ai = [ "stm32-metapac/stm32u595ai" ]
+stm32u595aj = [ "stm32-metapac/stm32u595aj" ]
+stm32u595qi = [ "stm32-metapac/stm32u595qi" ]
+stm32u595qj = [ "stm32-metapac/stm32u595qj" ]
+stm32u595ri = [ "stm32-metapac/stm32u595ri" ]
+stm32u595rj = [ "stm32-metapac/stm32u595rj" ]
+stm32u595vi = [ "stm32-metapac/stm32u595vi" ]
+stm32u595vj = [ "stm32-metapac/stm32u595vj" ]
+stm32u595zi = [ "stm32-metapac/stm32u595zi" ]
+stm32u595zj = [ "stm32-metapac/stm32u595zj" ]
+stm32u599bj = [ "stm32-metapac/stm32u599bj" ]
+stm32u599ni = [ "stm32-metapac/stm32u599ni" ]
+stm32u599nj = [ "stm32-metapac/stm32u599nj" ]
+stm32u599vi = [ "stm32-metapac/stm32u599vi" ]
+stm32u599vj = [ "stm32-metapac/stm32u599vj" ]
+stm32u599zi = [ "stm32-metapac/stm32u599zi" ]
+stm32u599zj = [ "stm32-metapac/stm32u599zj" ]
+stm32u5a5aj = [ "stm32-metapac/stm32u5a5aj" ]
+stm32u5a5qj = [ "stm32-metapac/stm32u5a5qj" ]
+stm32u5a5rj = [ "stm32-metapac/stm32u5a5rj" ]
+stm32u5a5vj = [ "stm32-metapac/stm32u5a5vj" ]
+stm32u5a5zj = [ "stm32-metapac/stm32u5a5zj" ]
+stm32u5a9bj = [ "stm32-metapac/stm32u5a9bj" ]
+stm32u5a9nj = [ "stm32-metapac/stm32u5a9nj" ]
+stm32u5a9vj = [ "stm32-metapac/stm32u5a9vj" ]
+stm32u5a9zj = [ "stm32-metapac/stm32u5a9zj" ]
stm32wb10cc = [ "stm32-metapac/stm32wb10cc" ]
stm32wb15cc = [ "stm32-metapac/stm32wb15cc" ]
stm32wb30ce = [ "stm32-metapac/stm32wb30ce" ]
diff --git a/embassy-stm32/src/can/enums.rs b/embassy-stm32/src/can/enums.rs
index 36139a45c..135010011 100644
--- a/embassy-stm32/src/can/enums.rs
+++ b/embassy-stm32/src/can/enums.rs
@@ -1,4 +1,5 @@
//! Enums shared between CAN controller types.
+use core::convert::TryFrom;
/// Bus error
#[derive(Debug)]
@@ -28,3 +29,19 @@ pub enum BusError {
/// At least one of error counter has reached the Error_Warning limit of 96.
BusWarning,
}
+impl TryFrom<u8> for BusError {
+ type Error = ();
+ fn try_from(value: u8) -> Result<Self, Self::Error> {
+ match value {
+ //0b000 => None,
+ 0b001 => Ok(Self::Stuff),
+ 0b010 => Ok(Self::Form),
+ 0b011 => Ok(Self::Acknowledge),
+ 0b100 => Ok(Self::BitRecessive),
+ 0b101 => Ok(Self::BitDominant),
+ 0b110 => Ok(Self::Crc),
+ //0b111 => Ok(Self::NoError),
+ _ => Err(()),
+ }
+ }
+}
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
new file mode 100644
index 000000000..38b409121
--- /dev/null
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -0,0 +1,438 @@
+//! Configuration for FDCAN Module
+//! Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+use core::num::{NonZeroU16, NonZeroU8};
+
+/// Configures the bit timings.
+///
+/// You can use <http://www.bittiming.can-wiki.info/> to calculate the `btr` parameter. Enter
+/// parameters as follows:
+///
+/// - *Clock Rate*: The input clock speed to the CAN peripheral (*not* the CPU clock speed).
+/// This is the clock rate of the peripheral bus the CAN peripheral is attached to (eg. APB1).
+/// - *Sample Point*: Should normally be left at the default value of 87.5%.
+/// - *SJW*: Should normally be left at the default value of 1.
+///
+/// Then copy the `CAN_BUS_TIME` register value from the table and pass it as the `btr`
+/// parameter to this method.
+#[derive(Clone, Copy, Debug)]
+pub struct NominalBitTiming {
+ /// Value by which the oscillator frequency is divided for generating the bit time quanta. The bit
+ /// time is built up from a multiple of this quanta. Valid values are 1 to 512.
+ pub prescaler: NonZeroU16,
+ /// Valid values are 1 to 128.
+ pub seg1: NonZeroU8,
+ /// Valid values are 1 to 255.
+ pub seg2: NonZeroU8,
+ /// Valid values are 1 to 128.
+ pub sync_jump_width: NonZeroU8,
+}
+impl NominalBitTiming {
+ #[inline]
+ pub(crate) fn nbrp(&self) -> u16 {
+ u16::from(self.prescaler) & 0x1FF
+ }
+ #[inline]
+ pub(crate) fn ntseg1(&self) -> u8 {
+ u8::from(self.seg1)
+ }
+ #[inline]
+ pub(crate) fn ntseg2(&self) -> u8 {
+ u8::from(self.seg2) & 0x7F
+ }
+ #[inline]
+ pub(crate) fn nsjw(&self) -> u8 {
+ u8::from(self.sync_jump_width) & 0x7F
+ }
+}
+
+impl Default for NominalBitTiming {
+ #[inline]
+ fn default() -> Self {
+ // Kernel Clock 8MHz, Bit rate: 500kbit/s. Corresponds to a NBTP
+ // register value of 0x0600_0A03
+ Self {
+ prescaler: NonZeroU16::new(1).unwrap(),
+ seg1: NonZeroU8::new(11).unwrap(),
+ seg2: NonZeroU8::new(4).unwrap(),
+ sync_jump_width: NonZeroU8::new(4).unwrap(),
+ }
+ }
+}
+
+/// Configures the data bit timings for the FdCan Variable Bitrates.
+/// This is not used when frame_transmit is set to anything other than AllowFdCanAndBRS.
+#[derive(Clone, Copy, Debug)]
+pub struct DataBitTiming {
+ /// Tranceiver Delay Compensation
+ pub transceiver_delay_compensation: bool,
+ /// The value by which the oscillator frequency is divided to generate the bit time quanta. The bit
+ /// time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 1
+ /// to 31.
+ pub prescaler: NonZeroU16,
+ /// Valid values are 1 to 31.
+ pub seg1: NonZeroU8,
+ /// Valid values are 1 to 15.
+ pub seg2: NonZeroU8,
+ /// Must always be smaller than DTSEG2, valid values are 1 to 15.
+ pub sync_jump_width: NonZeroU8,
+}
+impl DataBitTiming {
+ // #[inline]
+ // fn tdc(&self) -> u8 {
+ // let tsd = self.transceiver_delay_compensation as u8;
+ // //TODO: stm32g4 does not export the TDC field
+ // todo!()
+ // }
+ #[inline]
+ pub(crate) fn dbrp(&self) -> u8 {
+ (u16::from(self.prescaler) & 0x001F) as u8
+ }
+ #[inline]
+ pub(crate) fn dtseg1(&self) -> u8 {
+ u8::from(self.seg1) & 0x1F
+ }
+ #[inline]
+ pub(crate) fn dtseg2(&self) -> u8 {
+ u8::from(self.seg2) & 0x0F
+ }
+ #[inline]
+ pub(crate) fn dsjw(&self) -> u8 {
+ u8::from(self.sync_jump_width) & 0x0F
+ }
+}
+
+impl Default for DataBitTiming {
+ #[inline]
+ fn default() -> Self {
+ // Kernel Clock 8MHz, Bit rate: 500kbit/s. Corresponds to a DBTP
+ // register value of 0x0000_0A33
+ Self {
+ transceiver_delay_compensation: false,
+ prescaler: NonZeroU16::new(1).unwrap(),
+ seg1: NonZeroU8::new(11).unwrap(),
+ seg2: NonZeroU8::new(4).unwrap(),
+ sync_jump_width: NonZeroU8::new(4).unwrap(),
+ }
+ }
+}
+
+/// Configures which modes to use
+/// Individual headers can contain a desire to be send via FdCan
+/// or use Bit rate switching. But if this general setting does not allow
+/// that, only classic CAN is used instead.
+#[derive(Clone, Copy, Debug)]
+pub enum FrameTransmissionConfig {
+ /// Only allow Classic CAN message Frames
+ ClassicCanOnly,
+ /// Allow (non-brs) FdCAN Message Frames
+ AllowFdCan,
+ /// Allow FdCAN Message Frames and allow Bit Rate Switching
+ AllowFdCanAndBRS,
+}
+
+///
+#[derive(Clone, Copy, Debug)]
+pub enum ClockDivider {
+ /// Divide by 1
+ _1 = 0b0000,
+ /// Divide by 2
+ _2 = 0b0001,
+ /// Divide by 4
+ _4 = 0b0010,
+ /// Divide by 6
+ _6 = 0b0011,
+ /// Divide by 8
+ _8 = 0b0100,
+ /// Divide by 10
+ _10 = 0b0101,
+ /// Divide by 12
+ _12 = 0b0110,
+ /// Divide by 14
+ _14 = 0b0111,
+ /// Divide by 16
+ _16 = 0b1000,
+ /// Divide by 18
+ _18 = 0b1001,
+ /// Divide by 20
+ _20 = 0b1010,
+ /// Divide by 22
+ _22 = 0b1011,
+ /// Divide by 24
+ _24 = 0b1100,
+ /// Divide by 26
+ _26 = 0b1101,
+ /// Divide by 28
+ _28 = 0b1110,
+ /// Divide by 30
+ _30 = 0b1111,
+}
+
+/// Prescaler of the Timestamp counter
+#[derive(Clone, Copy, Debug)]
+pub enum TimestampPrescaler {
+ /// 1
+ _1 = 1,
+ /// 2
+ _2 = 2,
+ /// 3
+ _3 = 3,
+ /// 4
+ _4 = 4,
+ /// 5
+ _5 = 5,
+ /// 6
+ _6 = 6,
+ /// 7
+ _7 = 7,
+ /// 8
+ _8 = 8,
+ /// 9
+ _9 = 9,
+ /// 10
+ _10 = 10,
+ /// 11
+ _11 = 11,
+ /// 12
+ _12 = 12,
+ /// 13
+ _13 = 13,
+ /// 14
+ _14 = 14,
+ /// 15
+ _15 = 15,
+ /// 16
+ _16 = 16,
+}
+
+/// Selects the source of the Timestamp counter
+#[derive(Clone, Copy, Debug)]
+pub enum TimestampSource {
+ /// The Timestamp counter is disabled
+ None,
+ /// Using the FdCan input clock as the Timstamp counter's source,
+ /// and using a specific prescaler
+ Prescaler(TimestampPrescaler),
+ /// Using TIM3 as a source
+ FromTIM3,
+}
+
+/// How to handle frames in the global filter
+#[derive(Clone, Copy, Debug)]
+pub enum NonMatchingFilter {
+ /// Frames will go to Fifo0 when they do no match any specific filter
+ IntoRxFifo0 = 0b00,
+ /// Frames will go to Fifo1 when they do no match any specific filter
+ IntoRxFifo1 = 0b01,
+ /// Frames will be rejected when they do not match any specific filter
+ Reject = 0b11,
+}
+
+/// How to handle frames which do not match a specific filter
+#[derive(Clone, Copy, Debug)]
+pub struct GlobalFilter {
+ /// How to handle non-matching standard frames
+ pub handle_standard_frames: NonMatchingFilter,
+
+ /// How to handle non-matching extended frames
+ pub handle_extended_frames: NonMatchingFilter,
+
+ /// How to handle remote standard frames
+ pub reject_remote_standard_frames: bool,
+
+ /// How to handle remote extended frames
+ pub reject_remote_extended_frames: bool,
+}
+impl GlobalFilter {
+ /// Reject all non-matching and remote frames
+ pub const fn reject_all() -> Self {
+ Self {
+ handle_standard_frames: NonMatchingFilter::Reject,
+ handle_extended_frames: NonMatchingFilter::Reject,
+ reject_remote_standard_frames: true,
+ reject_remote_extended_frames: true,
+ }
+ }
+
+ /// How to handle non-matching standard frames
+ pub const fn set_handle_standard_frames(mut self, filter: NonMatchingFilter) -> Self {
+ self.handle_standard_frames = filter;
+ self
+ }
+ /// How to handle non-matching exteded frames
+ pub const fn set_handle_extended_frames(mut self, filter: NonMatchingFilter) -> Self {
+ self.handle_extended_frames = filter;
+ self
+ }
+ /// How to handle remote standard frames
+ pub const fn set_reject_remote_standard_frames(mut self, filter: bool) -> Self {
+ self.reject_remote_standard_frames = filter;
+ self
+ }
+ /// How to handle remote extended frames
+ pub const fn set_reject_remote_extended_frames(mut self, filter: bool) -> Self {
+ self.reject_remote_extended_frames = filter;
+ self
+ }
+}
+impl Default for GlobalFilter {
+ #[inline]
+ fn default() -> Self {
+ Self {
+ handle_standard_frames: NonMatchingFilter::IntoRxFifo0,
+ handle_extended_frames: NonMatchingFilter::IntoRxFifo0,
+ reject_remote_standard_frames: false,
+ reject_remote_extended_frames: false,
+ }
+ }
+}
+
+/// FdCan Config Struct
+#[derive(Clone, Copy, Debug)]
+pub struct FdCanConfig {
+ /// Nominal Bit Timings
+ pub nbtr: NominalBitTiming,
+ /// (Variable) Data Bit Timings
+ pub dbtr: DataBitTiming,
+ /// Enables or disables automatic retransmission of messages
+ ///
+ /// If this is enabled, the CAN peripheral will automatically try to retransmit each frame
+ /// util it can be sent. Otherwise, it will try only once to send each frame.
+ ///
+ /// Automatic retransmission is enabled by default.
+ pub automatic_retransmit: bool,
+ /// Enabled or disables the pausing between transmissions
+ ///
+ /// This feature looses up burst transmissions coming from a single node and it protects against
+ /// "babbling idiot" scenarios where the application program erroneously requests too many
+ /// transmissions.
+ pub transmit_pause: bool,
+ /// Enabled or disables the pausing between transmissions
+ ///
+ /// This feature looses up burst transmissions coming from a single node and it protects against
+ /// "babbling idiot" scenarios where the application program erroneously requests too many
+ /// transmissions.
+ pub frame_transmit: FrameTransmissionConfig,
+ /// Non Isoe Mode
+ /// If this is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN
+ /// FD Specification V1.0.
+ pub non_iso_mode: bool,
+ /// Edge Filtering: Two consecutive dominant tq required to detect an edge for hard synchronization
+ pub edge_filtering: bool,
+ /// Enables protocol exception handling
+ pub protocol_exception_handling: bool,
+ /// Sets the general clock divider for this FdCAN instance
+ pub clock_divider: ClockDivider,
+ /// Sets the timestamp source
+ pub timestamp_source: TimestampSource,
+ /// Configures the Global Filter
+ pub global_filter: GlobalFilter,
+}
+
+impl FdCanConfig {
+ /// Configures the bit timings.
+ #[inline]
+ pub const fn set_nominal_bit_timing(mut self, btr: NominalBitTiming) -> Self {
+ self.nbtr = btr;
+ self
+ }
+
+ /// Configures the bit timings.
+ #[inline]
+ pub const fn set_data_bit_timing(mut self, btr: DataBitTiming) -> Self {
+ self.dbtr = btr;
+ self
+ }
+
+ /// Enables or disables automatic retransmission of messages
+ ///
+ /// If this is enabled, the CAN peripheral will automatically try to retransmit each frame
+ /// util it can be sent. Otherwise, it will try only once to send each frame.
+ ///
+ /// Automatic retransmission is enabled by default.
+ #[inline]
+ pub const fn set_automatic_retransmit(mut self, enabled: bool) -> Self {
+ self.automatic_retransmit = enabled;
+ self
+ }
+
+ /// Enabled or disables the pausing between transmissions
+ ///
+ /// This feature looses up burst transmissions coming from a single node and it protects against
+ /// "babbling idiot" scenarios where the application program erroneously requests too many
+ /// transmissions.
+ #[inline]
+ pub const fn set_transmit_pause(mut self, enabled: bool) -> Self {
+ self.transmit_pause = enabled;
+ self
+ }
+
+ /// If this is set, the FDCAN uses the CAN FD frame format as specified by the Bosch CAN
+ /// FD Specification V1.0.
+ #[inline]
+ pub const fn set_non_iso_mode(mut self, enabled: bool) -> Self {
+ self.non_iso_mode = enabled;
+ self
+ }
+
+ /// Two consecutive dominant tq required to detect an edge for hard synchronization
+ #[inline]
+ pub const fn set_edge_filtering(mut self, enabled: bool) -> Self {
+ self.edge_filtering = enabled;
+ self
+ }
+
+ /// Sets the allowed transmission types for messages.
+ #[inline]
+ pub const fn set_frame_transmit(mut self, fts: FrameTransmissionConfig) -> Self {
+ self.frame_transmit = fts;
+ self
+ }
+
+ /// Enables protocol exception handling
+ #[inline]
+ pub const fn set_protocol_exception_handling(mut self, peh: bool) -> Self {
+ self.protocol_exception_handling = peh;
+ self
+ }
+
+ /// Sets the general clock divider for this FdCAN instance
+ #[inline]
+ pub const fn set_clock_divider(mut self, div: ClockDivider) -> Self {
+ self.clock_divider = div;
+ self
+ }
+
+ /// Sets the timestamp source
+ #[inline]
+ pub const fn set_timestamp_source(mut self, tss: TimestampSource) -> Self {
+ self.timestamp_source = tss;
+ self
+ }
+
+ /// Sets the global filter settings
+ #[inline]
+ pub const fn set_global_filter(mut self, filter: GlobalFilter) -> Self {
+ self.global_filter = filter;
+ self
+ }
+}
+
+impl Default for FdCanConfig {
+ #[inline]
+ fn default() -> Self {
+ Self {
+ nbtr: NominalBitTiming::default(),
+ dbtr: DataBitTiming::default(),
+ automatic_retransmit: true,
+ transmit_pause: false,
+ frame_transmit: FrameTransmissionConfig::ClassicCanOnly,
+ non_iso_mode: false,
+ edge_filtering: false,
+ protocol_exception_handling: true,
+ clock_divider: ClockDivider::_1,
+ timestamp_source: TimestampSource::None,
+ global_filter: GlobalFilter::default(),
+ }
+ }
+}
diff --git a/embassy-stm32/src/can/fd/filter.rs b/embassy-stm32/src/can/fd/filter.rs
new file mode 100644
index 000000000..3e2129e6e
--- /dev/null
+++ b/embassy-stm32/src/can/fd/filter.rs
@@ -0,0 +1,379 @@
+//! Definition of Filter structs for FDCAN Module
+//! Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+use embedded_can::{ExtendedId, StandardId};
+
+use crate::can::fd::message_ram;
+pub use crate::can::fd::message_ram::{EXTENDED_FILTER_MAX, STANDARD_FILTER_MAX};
+
+/// A Standard Filter
+pub type StandardFilter = Filter<StandardId, u16>;
+/// An Extended Filter
+pub type ExtendedFilter = Filter<ExtendedId, u32>;
+
+impl Default for StandardFilter {
+ fn default() -> Self {
+ StandardFilter::disable()
+ }
+}
+impl Default for ExtendedFilter {
+ fn default() -> Self {
+ ExtendedFilter::disable()
+ }
+}
+
+impl StandardFilter {
+ /// Accept all messages in FIFO 0
+ pub fn accept_all_into_fifo0() -> StandardFilter {
+ StandardFilter {
+ filter: FilterType::BitMask { filter: 0x0, mask: 0x0 },
+ action: Action::StoreInFifo0,
+ }
+ }
+
+ /// Accept all messages in FIFO 1
+ pub fn accept_all_into_fifo1() -> StandardFilter {
+ StandardFilter {
+ filter: FilterType::BitMask { filter: 0x0, mask: 0x0 },
+ action: Action::StoreInFifo1,
+ }
+ }
+
+ /// Reject all messages
+ pub fn reject_all() -> StandardFilter {
+ StandardFilter {
+ filter: FilterType::BitMask { filter: 0x0, mask: 0x0 },
+ action: Action::Reject,
+ }
+ }
+
+ /// Disable the filter
+ pub fn disable() -> StandardFilter {
+ StandardFilter {
+ filter: FilterType::Disabled,
+ action: Action::Disable,
+ }
+ }
+}
+
+impl ExtendedFilter {
+ /// Accept all messages in FIFO 0
+ pub fn accept_all_into_fifo0() -> ExtendedFilter {
+ ExtendedFilter {
+ filter: FilterType::BitMask { filter: 0x0, mask: 0x0 },
+ action: Action::StoreInFifo0,
+ }
+ }
+
+ /// Accept all messages in FIFO 1
+ pub fn accept_all_into_fifo1() -> ExtendedFilter {
+ ExtendedFilter {
+ filter: FilterType::BitMask { filter: 0x0, mask: 0x0 },
+ action: Action::StoreInFifo1,
+ }
+ }
+
+ /// Reject all messages
+ pub fn reject_all() -> ExtendedFilter {
+ ExtendedFilter {
+ filter: FilterType::BitMask { filter: 0x0, mask: 0x0 },
+ action: Action::Reject,
+ }
+ }
+
+ /// Disable the filter
+ pub fn disable() -> ExtendedFilter {
+ ExtendedFilter {
+ filter: FilterType::Disabled,
+ action: Action::Disable,
+ }
+ }
+}
+
+/// Filter Type
+#[derive(Clone, Copy, Debug)]
+pub enum FilterType<ID, UNIT>
+where
+ ID: Copy + Clone + core::fmt::Debug,
+ UNIT: Copy + Clone + core::fmt::Debug,
+{
+ /// Match with a range between two messages
+ Range {
+ /// First Id of the range
+ from: ID,
+ /// Last Id of the range
+ to: ID,
+ },
+ /// Match with a bitmask
+ BitMask {
+ /// Filter of the bitmask
+ filter: UNIT,
+ /// Mask of the bitmask
+ mask: UNIT,
+ },
+ /// Match with a single ID
+ DedicatedSingle(ID),
+ /// Match with one of two ID's
+ DedicatedDual(ID, ID),
+ /// Filter is disabled
+ Disabled,
+}
+impl<ID, UNIT> From<FilterType<ID, UNIT>> for message_ram::enums::FilterType
+where
+ ID: Copy + Clone + core::fmt::Debug,
+ UNIT: Copy + Clone + core::fmt::Debug,
+{
+ fn from(f: FilterType<ID, UNIT>) -> Self {
+ match f {
+ FilterType::Range { to: _, from: _ } => Self::RangeFilter,
+ FilterType::BitMask { filter: _, mask: _ } => Self::ClassicFilter,
+ FilterType::DedicatedSingle(_) => Self::DualIdFilter,
+ FilterType::DedicatedDual(_, _) => Self::DualIdFilter,
+ FilterType::Disabled => Self::FilterDisabled,
+ }
+ }
+}
+
+/// Filter Action
+#[derive(Clone, Copy, Debug)]
+pub enum Action {
+ /// No Action
+ Disable = 0b000,
+ /// Store an matching message in FIFO 0
+ StoreInFifo0 = 0b001,
+ /// Store an matching message in FIFO 1
+ StoreInFifo1 = 0b010,
+ /// Reject an matching message
+ Reject = 0b011,
+ /// Flag a matching message (But not store?!?)
+ FlagHighPrio = 0b100,
+ /// Flag a matching message as a High Priority message and store it in FIFO 0
+ FlagHighPrioAndStoreInFifo0 = 0b101,
+ /// Flag a matching message as a High Priority message and store it in FIFO 1
+ FlagHighPrioAndStoreInFifo1 = 0b110,
+}
+impl From<Action> for message_ram::enums::FilterElementConfig {
+ fn from(a: Action) -> Self {
+ match a {
+ Action::Disable => Self::DisableFilterElement,
+ Action::StoreInFifo0 => Self::StoreInFifo0,
+ Action::StoreInFifo1 => Self::StoreInFifo1,
+ Action::Reject => Self::Reject,
+ Action::FlagHighPrio => Self::SetPriority,
+ Action::FlagHighPrioAndStoreInFifo0 => Self::SetPriorityAndStoreInFifo0,
+ Action::FlagHighPrioAndStoreInFifo1 => Self::SetPriorityAndStoreInFifo1,
+ }
+ }
+}
+
+/// Filter
+#[derive(Clone, Copy, Debug)]
+pub struct Filter<ID, UNIT>
+where
+ ID: Copy + Clone + core::fmt::Debug,
+ UNIT: Copy + Clone + core::fmt::Debug,
+{
+ /// How to match an incoming message
+ pub filter: FilterType<ID, UNIT>,
+ /// What to do with a matching message
+ pub action: Action,
+}
+
+/// Standard Filter Slot
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub enum StandardFilterSlot {
+ /// 0
+ _0 = 0,
+ /// 1
+ _1 = 1,
+ /// 2
+ _2 = 2,
+ /// 3
+ _3 = 3,
+ /// 4
+ _4 = 4,
+ /// 5
+ _5 = 5,
+ /// 6
+ _6 = 6,
+ /// 7
+ _7 = 7,
+ /// 8
+ _8 = 8,
+ /// 9
+ _9 = 9,
+ /// 10
+ _10 = 10,
+ /// 11
+ _11 = 11,
+ /// 12
+ _12 = 12,
+ /// 13
+ _13 = 13,
+ /// 14
+ _14 = 14,
+ /// 15
+ _15 = 15,
+ /// 16
+ _16 = 16,
+ /// 17
+ _17 = 17,
+ /// 18
+ _18 = 18,
+ /// 19
+ _19 = 19,
+ /// 20
+ _20 = 20,
+ /// 21
+ _21 = 21,
+ /// 22
+ _22 = 22,
+ /// 23
+ _23 = 23,
+ /// 24
+ _24 = 24,
+ /// 25
+ _25 = 25,
+ /// 26
+ _26 = 26,
+ /// 27
+ _27 = 27,
+}
+impl From<u8> for StandardFilterSlot {
+ fn from(u: u8) -> Self {
+ match u {
+ 0 => StandardFilterSlot::_0,
+ 1 => StandardFilterSlot::_1,
+ 2 => StandardFilterSlot::_2,
+ 3 => StandardFilterSlot::_3,
+ 4 => StandardFilterSlot::_4,
+ 5 => StandardFilterSlot::_5,
+ 6 => StandardFilterSlot::_6,
+ 7 => StandardFilterSlot::_7,
+ 8 => StandardFilterSlot::_8,
+ 9 => StandardFilterSlot::_9,
+ 10 => StandardFilterSlot::_10,
+ 11 => StandardFilterSlot::_11,
+ 12 => StandardFilterSlot::_12,
+ 13 => StandardFilterSlot::_13,
+ 14 => StandardFilterSlot::_14,
+ 15 => StandardFilterSlot::_15,
+ 16 => StandardFilterSlot::_16,
+ 17 => StandardFilterSlot::_17,
+ 18 => StandardFilterSlot::_18,
+ 19 => StandardFilterSlot::_19,
+ 20 => StandardFilterSlot::_20,
+ 21 => StandardFilterSlot::_21,
+ 22 => StandardFilterSlot::_22,
+ 23 => StandardFilterSlot::_23,
+ 24 => StandardFilterSlot::_24,
+ 25 => StandardFilterSlot::_25,
+ 26 => StandardFilterSlot::_26,
+ 27 => StandardFilterSlot::_27,
+ _ => panic!("Standard Filter Slot Too High!"),
+ }
+ }
+}
+
+/// Extended Filter Slot
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub enum ExtendedFilterSlot {
+ /// 0
+ _0 = 0,
+ /// 1
+ _1 = 1,
+ /// 2
+ _2 = 2,
+ /// 3
+ _3 = 3,
+ /// 4
+ _4 = 4,
+ /// 5
+ _5 = 5,
+ /// 6
+ _6 = 6,
+ /// 7
+ _7 = 7,
+}
+impl From<u8> for ExtendedFilterSlot {
+ fn from(u: u8) -> Self {
+ match u {
+ 0 => ExtendedFilterSlot::_0,
+ 1 => ExtendedFilterSlot::_1,
+ 2 => ExtendedFilterSlot::_2,
+ 3 => ExtendedFilterSlot::_3,
+ 4 => ExtendedFilterSlot::_4,
+ 5 => ExtendedFilterSlot::_5,
+ 6 => ExtendedFilterSlot::_6,
+ 7 => ExtendedFilterSlot::_7,
+ _ => panic!("Extended Filter Slot Too High!"), // Should be unreachable
+ }
+ }
+}
+
+/// Enum over both Standard and Extended Filter ID's
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+pub enum FilterId {
+ /// Standard Filter Slots
+ Standard(StandardFilterSlot),
+ /// Extended Filter Slots
+ Extended(ExtendedFilterSlot),
+}
+
+pub(crate) trait ActivateFilter<ID, UNIT>
+where
+ ID: Copy + Clone + core::fmt::Debug,
+ UNIT: Copy + Clone + core::fmt::Debug,
+{
+ fn activate(&mut self, f: Filter<ID, UNIT>);
+ // fn read(&self) -> Filter<ID, UNIT>;
+}
+
+impl ActivateFilter<StandardId, u16> for message_ram::StandardFilter {
+ fn activate(&mut self, f: Filter<StandardId, u16>) {
+ let sft = f.filter.into();
+
+ let (sfid1, sfid2) = match f.filter {
+ FilterType::Range { to, from } => (to.as_raw(), from.as_raw()),
+ FilterType::DedicatedSingle(id) => (id.as_raw(), id.as_raw()),
+ FilterType::DedicatedDual(id1, id2) => (id1.as_raw(), id2.as_raw()),
+ FilterType::BitMask { filter, mask } => (filter, mask),
+ FilterType::Disabled => (0x0, 0x0),
+ };
+ let sfec = f.action.into();
+ self.write(|w| {
+ unsafe { w.sfid1().bits(sfid1).sfid2().bits(sfid2) }
+ .sft()
+ .set_filter_type(sft)
+ .sfec()
+ .set_filter_element_config(sfec)
+ });
+ }
+ // fn read(&self) -> Filter<StandardId, u16> {
+ // todo!()
+ // }
+}
+impl ActivateFilter<ExtendedId, u32> for message_ram::ExtendedFilter {
+ fn activate(&mut self, f: Filter<ExtendedId, u32>) {
+ let eft = f.filter.into();
+
+ let (efid1, efid2) = match f.filter {
+ FilterType::Range { to, from } => (to.as_raw(), from.as_raw()),
+ FilterType::DedicatedSingle(id) => (id.as_raw(), id.as_raw()),
+ FilterType::DedicatedDual(id1, id2) => (id1.as_raw(), id2.as_raw()),
+ FilterType::BitMask { filter, mask } => (filter, mask),
+ FilterType::Disabled => (0x0, 0x0),
+ };
+ let efec = f.action.into();
+ self.write(|w| {
+ unsafe { w.efid1().bits(efid1).efid2().bits(efid2) }
+ .eft()
+ .set_filter_type(eft)
+ .efec()
+ .set_filter_element_config(efec)
+ });
+ }
+ // fn read(&self) -> Filter<ExtendedId, u32> {
+ // todo!()
+ // }
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/common.rs b/embassy-stm32/src/can/fd/message_ram/common.rs
new file mode 100644
index 000000000..a67d68fa0
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/common.rs
@@ -0,0 +1,134 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![allow(unused)]
+
+use super::enums::{
+ BitRateSwitching, ErrorStateIndicator, FilterElementConfig, FilterType, FrameFormat, IdType,
+ RemoteTransmissionRequest,
+};
+use super::generic;
+
+#[doc = "Reader of field `ID`"]
+pub type ID_R = generic::R<u32, u32>;
+
+#[doc = "Reader of field `RTR`"]
+pub type RTR_R = generic::R<bool, RemoteTransmissionRequest>;
+impl RTR_R {
+ pub fn rtr(&self) -> RemoteTransmissionRequest {
+ match self.bits {
+ false => RemoteTransmissionRequest::TransmitDataFrame,
+ true => RemoteTransmissionRequest::TransmitRemoteFrame,
+ }
+ }
+ pub fn is_transmit_remote_frame(&self) -> bool {
+ *self == RemoteTransmissionRequest::TransmitRemoteFrame
+ }
+ pub fn is_transmit_data_frame(&self) -> bool {
+ *self == RemoteTransmissionRequest::TransmitDataFrame
+ }
+}
+
+#[doc = "Reader of field `XTD`"]
+pub type XTD_R = generic::R<bool, IdType>;
+impl XTD_R {
+ pub fn id_type(&self) -> IdType {
+ match self.bits() {
+ false => IdType::StandardId,
+ true => IdType::ExtendedId,
+ }
+ }
+ pub fn is_standard_id(&self) -> bool {
+ *self == IdType::StandardId
+ }
+ pub fn is_exteded_id(&self) -> bool {
+ *self == IdType::ExtendedId
+ }
+}
+
+#[doc = "Reader of field `ESI`"]
+pub type ESI_R = generic::R<bool, ErrorStateIndicator>;
+impl ESI_R {
+ pub fn error_state(&self) -> ErrorStateIndicator {
+ match self.bits() {
+ false => ErrorStateIndicator::ErrorActive,
+ true => ErrorStateIndicator::ErrorPassive,
+ }
+ }
+ pub fn is_error_active(&self) -> bool {
+ *self == ErrorStateIndicator::ErrorActive
+ }
+ pub fn is_error_passive(&self) -> bool {
+ *self == ErrorStateIndicator::ErrorPassive
+ }
+}
+
+#[doc = "Reader of field `DLC`"]
+pub type DLC_R = generic::R<u8, u8>;
+
+#[doc = "Reader of field `BRS`"]
+pub type BRS_R = generic::R<bool, BitRateSwitching>;
+impl BRS_R {
+ pub fn bit_rate_switching(&self) -> BitRateSwitching {
+ match self.bits() {
+ true => BitRateSwitching::WithBRS,
+ false => BitRateSwitching::WithoutBRS,
+ }
+ }
+ pub fn is_with_brs(&self) -> bool {
+ *self == BitRateSwitching::WithBRS
+ }
+ pub fn is_without_brs(&self) -> bool {
+ *self == BitRateSwitching::WithoutBRS
+ }
+}
+
+#[doc = "Reader of field `FDF`"]
+pub type FDF_R = generic::R<bool, FrameFormat>;
+impl FDF_R {
+ pub fn frame_format(&self) -> FrameFormat {
+ match self.bits() {
+ false => FrameFormat::Standard,
+ true => FrameFormat::Fdcan,
+ }
+ }
+ pub fn is_standard_format(&self) -> bool {
+ *self == FrameFormat::Standard
+ }
+ pub fn is_fdcan_format(&self) -> bool {
+ *self == FrameFormat::Fdcan
+ }
+}
+
+#[doc = "Reader of field `(X|S)FT`"]
+pub type ESFT_R = generic::R<u8, FilterType>;
+impl ESFT_R {
+ #[doc = r"Gets the Filtertype"]
+ #[inline(always)]
+ pub fn to_filter_type(&self) -> FilterType {
+ match self.bits() {
+ 0b00 => FilterType::RangeFilter,
+ 0b01 => FilterType::DualIdFilter,
+ 0b10 => FilterType::ClassicFilter,
+ 0b11 => FilterType::FilterDisabled,
+ _ => unreachable!(),
+ }
+ }
+}
+
+#[doc = "Reader of field `(E|S)FEC`"]
+pub type ESFEC_R = generic::R<u8, FilterElementConfig>;
+impl ESFEC_R {
+ pub fn to_filter_element_config(&self) -> FilterElementConfig {
+ match self.bits() {
+ 0b000 => FilterElementConfig::DisableFilterElement,
+ 0b001 => FilterElementConfig::StoreInFifo0,
+ 0b010 => FilterElementConfig::StoreInFifo1,
+ 0b011 => FilterElementConfig::Reject,
+ 0b100 => FilterElementConfig::SetPriority,
+ 0b101 => FilterElementConfig::SetPriorityAndStoreInFifo0,
+ 0b110 => FilterElementConfig::SetPriorityAndStoreInFifo1,
+ _ => unimplemented!(),
+ }
+ }
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/enums.rs b/embassy-stm32/src/can/fd/message_ram/enums.rs
new file mode 100644
index 000000000..78285bf81
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/enums.rs
@@ -0,0 +1,233 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+/// Datalength is the message length generalised over
+/// the Standard (Classic) and FDCAN message types
+
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DataLength {
+ Standard(u8),
+ Fdcan(u8),
+}
+impl DataLength {
+ /// Creates a DataLength type
+ ///
+ /// Uses the byte length and Type of frame as input
+ pub fn new(len: u8, ff: FrameFormat) -> DataLength {
+ match ff {
+ FrameFormat::Standard => match len {
+ 0..=8 => DataLength::Standard(len),
+ _ => panic!("DataLength > 8"),
+ },
+ FrameFormat::Fdcan => match len {
+ 0..=64 => DataLength::Fdcan(len),
+ _ => panic!("DataLength > 64"),
+ },
+ }
+ }
+ /// Specialised function to create standard frames
+ pub fn new_standard(len: u8) -> DataLength {
+ Self::new(len, FrameFormat::Standard)
+ }
+ /// Specialised function to create FDCAN frames
+ pub fn new_fdcan(len: u8) -> DataLength {
+ Self::new(len, FrameFormat::Fdcan)
+ }
+
+ /// returns the length in bytes
+ pub fn len(&self) -> u8 {
+ match self {
+ DataLength::Standard(l) | DataLength::Fdcan(l) => *l,
+ }
+ }
+
+ pub(crate) fn dlc(&self) -> u8 {
+ match self {
+ DataLength::Standard(l) => *l,
+ // See RM0433 Rev 7 Table 475. DLC coding
+ DataLength::Fdcan(l) => match l {
+ 0..=8 => *l,
+ 9..=12 => 9,
+ 13..=16 => 10,
+ 17..=20 => 11,
+ 21..=24 => 12,
+ 25..=32 => 13,
+ 33..=48 => 14,
+ 49..=64 => 15,
+ _ => panic!("DataLength > 64"),
+ },
+ }
+ }
+}
+impl From<DataLength> for FrameFormat {
+ fn from(dl: DataLength) -> FrameFormat {
+ match dl {
+ DataLength::Standard(_) => FrameFormat::Standard,
+ DataLength::Fdcan(_) => FrameFormat::Fdcan,
+ }
+ }
+}
+
+/// Wheter or not to generate an Tx Event
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum Event {
+ /// Do not generate an Tx Event
+ NoEvent,
+ /// Generate an Tx Event with a specified ID
+ Event(u8),
+}
+
+impl From<Event> for EventControl {
+ fn from(e: Event) -> Self {
+ match e {
+ Event::NoEvent => EventControl::DoNotStore,
+ Event::Event(_) => EventControl::Store,
+ }
+ }
+}
+
+impl From<Option<u8>> for Event {
+ fn from(mm: Option<u8>) -> Self {
+ match mm {
+ None => Event::NoEvent,
+ Some(mm) => Event::Event(mm),
+ }
+ }
+}
+
+impl From<Event> for Option<u8> {
+ fn from(e: Event) -> Option<u8> {
+ match e {
+ Event::NoEvent => None,
+ Event::Event(mm) => Some(mm),
+ }
+ }
+}
+
+/// TODO
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ErrorStateIndicator {
+ /// TODO
+ ErrorActive = 0,
+ /// TODO
+ ErrorPassive = 1,
+}
+impl From<ErrorStateIndicator> for bool {
+ #[inline(always)]
+ fn from(e: ErrorStateIndicator) -> Self {
+ e as u8 != 0
+ }
+}
+
+/// Type of frame, standard (classic) or FdCAN
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FrameFormat {
+ Standard = 0,
+ Fdcan = 1,
+}
+impl From<FrameFormat> for bool {
+ #[inline(always)]
+ fn from(e: FrameFormat) -> Self {
+ e as u8 != 0
+ }
+}
+
+/// Type of Id, Standard or Extended
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IdType {
+ /// Standard ID
+ StandardId = 0,
+ /// Extended ID
+ ExtendedId = 1,
+}
+impl From<IdType> for bool {
+ #[inline(always)]
+ fn from(e: IdType) -> Self {
+ e as u8 != 0
+ }
+}
+
+/// Whether the frame contains data or requests data
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RemoteTransmissionRequest {
+ /// Frame contains data
+ TransmitDataFrame = 0,
+ /// frame does not contain data
+ TransmitRemoteFrame = 1,
+}
+impl From<RemoteTransmissionRequest> for bool {
+ #[inline(always)]
+ fn from(e: RemoteTransmissionRequest) -> Self {
+ e as u8 != 0
+ }
+}
+
+/// Whether BitRateSwitching should be or was enabled
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BitRateSwitching {
+ /// disable bit rate switching
+ WithoutBRS = 0,
+ /// enable bit rate switching
+ WithBRS = 1,
+}
+impl From<BitRateSwitching> for bool {
+ #[inline(always)]
+ fn from(e: BitRateSwitching) -> Self {
+ e as u8 != 0
+ }
+}
+
+/// Whether to store transmit Events
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EventControl {
+ /// do not store an tx event
+ DoNotStore,
+ /// store transmit events
+ Store,
+}
+impl From<EventControl> for bool {
+ #[inline(always)]
+ fn from(e: EventControl) -> Self {
+ e as u8 != 0
+ }
+}
+
+/// If an received message matched any filters
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FilterFrameMatch {
+ /// This did match filter <id>
+ DidMatch(u8),
+ /// This received frame did not match any specific filters
+ DidNotMatch,
+}
+
+/// Type of filter to be used
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FilterType {
+ /// Filter uses the range between two id's
+ RangeFilter = 0b00,
+ /// The filter matches on two specific id's (or one ID checked twice)
+ DualIdFilter = 0b01,
+ /// Filter is using a bitmask
+ ClassicFilter = 0b10,
+ /// Filter is disabled
+ FilterDisabled = 0b11,
+}
+
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FilterElementConfig {
+ /// Filter is disabled
+ DisableFilterElement = 0b000,
+ /// Store a matching message in FIFO 0
+ StoreInFifo0 = 0b001,
+ /// Store a matching message in FIFO 1
+ StoreInFifo1 = 0b010,
+ /// Reject a matching message
+ Reject = 0b011,
+ /// Flag that a priority message has been received, *But do note store!*??
+ SetPriority = 0b100,
+ /// Flag and store message in FIFO 0
+ SetPriorityAndStoreInFifo0 = 0b101,
+ /// Flag and store message in FIFO 1
+ SetPriorityAndStoreInFifo1 = 0b110,
+ //_Unused = 0b111,
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/extended_filter.rs b/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
new file mode 100644
index 000000000..453e9056e
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/extended_filter.rs
@@ -0,0 +1,136 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![allow(unused)]
+
+use super::common::{ESFEC_R, ESFT_R};
+use super::enums::{FilterElementConfig, FilterType};
+use super::generic;
+
+#[doc = "Reader of register ExtendedFilter"]
+pub(crate) type R = generic::R<super::ExtendedFilterType, super::ExtendedFilter>;
+#[doc = "Writer for register ExtendedFilter"]
+pub(crate) type W = generic::W<super::ExtendedFilterType, super::ExtendedFilter>;
+#[doc = "Register ExtendedFilter `reset()`'s"]
+impl generic::ResetValue for super::ExtendedFilter {
+ type Type = super::ExtendedFilterType;
+ #[inline(always)]
+ fn reset_value() -> Self::Type {
+ // Sets filter element to Disabled
+ [0x0, 0x0]
+ }
+}
+
+#[doc = "Reader of field `EFID2`"]
+pub(crate) type EFID2_R = generic::R<u32, u32>;
+#[doc = "Write proxy for field `EFID2`"]
+pub(crate) struct EFID2_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EFID2_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u32) -> &'a mut W {
+ self.w.bits[1] = (self.w.bits[1] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF);
+ self.w
+ }
+}
+
+#[doc = "Reader of field `EFID1`"]
+pub(crate) type EFID1_R = generic::R<u32, u32>;
+#[doc = "Write proxy for field `EFID1`"]
+pub(crate) struct EFID1_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EFID1_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u32) -> &'a mut W {
+ self.w.bits[0] = (self.w.bits[0] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `EFEC`"]
+pub(crate) struct EFEC_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EFEC_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits[0] = (self.w.bits[0] & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
+ self.w
+ }
+ #[doc = r"Sets the field according to FilterElementConfig"]
+ #[inline(always)]
+ pub fn set_filter_element_config(self, fec: FilterElementConfig) -> &'a mut W {
+ //SAFETY: FilterElementConfig only be valid options
+ unsafe { self.bits(fec as u8) }
+ }
+}
+
+#[doc = "Write proxy for field `EFT`"]
+pub(crate) struct EFT_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EFT_W<'a> {
+ #[doc = r"Sets the field according the FilterType"]
+ #[inline(always)]
+ pub fn set_filter_type(self, filter: FilterType) -> &'a mut W {
+ //SAFETY: FilterType only be valid options
+ unsafe { self.bits(filter as u8) }
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits[1] = (self.w.bits[1] & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
+ self.w
+ }
+}
+
+impl R {
+ #[doc = "Byte 0 - Bits 0:28 - EFID1"]
+ #[inline(always)]
+ pub fn sfid1(&self) -> EFID1_R {
+ EFID1_R::new(((self.bits[0]) & 0x1FFFFFFF) as u32)
+ }
+ #[doc = "Byte 0 - Bits 29:31 - EFEC"]
+ #[inline(always)]
+ pub fn efec(&self) -> ESFEC_R {
+ ESFEC_R::new(((self.bits[0] >> 29) & 0x07) as u8)
+ }
+ #[doc = "Byte 1 - Bits 0:28 - EFID2"]
+ #[inline(always)]
+ pub fn sfid2(&self) -> EFID2_R {
+ EFID2_R::new(((self.bits[1]) & 0x1FFFFFFF) as u32)
+ }
+ #[doc = "Byte 1 - Bits 30:31 - EFT"]
+ #[inline(always)]
+ pub fn eft(&self) -> ESFT_R {
+ ESFT_R::new(((self.bits[1] >> 30) & 0x03) as u8)
+ }
+}
+impl W {
+ #[doc = "Byte 0 - Bits 0:28 - EFID1"]
+ #[inline(always)]
+ pub fn efid1(&mut self) -> EFID1_W {
+ EFID1_W { w: self }
+ }
+ #[doc = "Byte 0 - Bits 29:31 - EFEC"]
+ #[inline(always)]
+ pub fn efec(&mut self) -> EFEC_W {
+ EFEC_W { w: self }
+ }
+ #[doc = "Byte 1 - Bits 0:28 - EFID2"]
+ #[inline(always)]
+ pub fn efid2(&mut self) -> EFID2_W {
+ EFID2_W { w: self }
+ }
+ #[doc = "Byte 1 - Bits 30:31 - EFT"]
+ #[inline(always)]
+ pub fn eft(&mut self) -> EFT_W {
+ EFT_W { w: self }
+ }
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/generic.rs b/embassy-stm32/src/can/fd/message_ram/generic.rs
new file mode 100644
index 000000000..1a5e121b4
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/generic.rs
@@ -0,0 +1,168 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+use core::marker;
+
+///This trait shows that register has `read` method
+///
+///Registers marked with `Writable` can be also `modify`'ed
+pub trait Readable {}
+
+///This trait shows that register has `write`, `write_with_zero` and `reset` method
+///
+///Registers marked with `Readable` can be also `modify`'ed
+pub trait Writable {}
+
+///Reset value of the register
+///
+///This value is initial value for `write` method.
+///It can be also directly writed to register by `reset` method.
+pub trait ResetValue {
+ ///Register size
+ type Type;
+ ///Reset value of the register
+ fn reset_value() -> Self::Type;
+}
+
+///This structure provides volatile access to register
+pub struct Reg<U, REG> {
+ register: vcell::VolatileCell<U>,
+ _marker: marker::PhantomData<REG>,
+}
+
+unsafe impl<U: Send, REG> Send for Reg<U, REG> {}
+
+impl<U, REG> Reg<U, REG>
+where
+ Self: Readable,
+ U: Copy,
+{
+ ///Reads the contents of `Readable` register
+ ///
+ ///You can read the contents of a register in such way:
+ ///```ignore
+ ///let bits = periph.reg.read().bits();
+ ///```
+ ///or get the content of a particular field of a register.
+ ///```ignore
+ ///let reader = periph.reg.read();
+ ///let bits = reader.field1().bits();
+ ///let flag = reader.field2().bit_is_set();
+ ///```
+ #[inline(always)]
+ pub fn read(&self) -> R<U, Self> {
+ R {
+ bits: self.register.get(),
+ _reg: marker::PhantomData,
+ }
+ }
+}
+
+impl<U, REG> Reg<U, REG>
+where
+ Self: ResetValue<Type = U> + Writable,
+ U: Copy,
+{
+ ///Writes the reset value to `Writable` register
+ ///
+ ///Resets the register to its initial state
+ #[inline(always)]
+ pub fn reset(&self) {
+ self.register.set(Self::reset_value())
+ }
+}
+
+impl<U, REG> Reg<U, REG>
+where
+ Self: ResetValue<Type = U> + Writable,
+ U: Copy,
+{
+ ///Writes bits to `Writable` register
+ ///
+ ///You can write raw bits into a register:
+ ///```ignore
+ ///periph.reg.write(|w| unsafe { w.bits(rawbits) });
+ ///```
+ ///or write only the fields you need:
+ ///```ignore
+ ///periph.reg.write(|w| w
+ /// .field1().bits(newfield1bits)
+ /// .field2().set_bit()
+ /// .field3().variant(VARIANT)
+ ///);
+ ///```
+ ///Other fields will have reset value.
+ #[inline(always)]
+ pub fn write<F>(&self, f: F)
+ where
+ F: FnOnce(&mut W<U, Self>) -> &mut W<U, Self>,
+ {
+ self.register.set(
+ f(&mut W {
+ bits: Self::reset_value(),
+ _reg: marker::PhantomData,
+ })
+ .bits,
+ );
+ }
+}
+
+///Register/field reader
+///
+///Result of the [`read`](Reg::read) method of a register.
+///Also it can be used in the [`modify`](Reg::read) method
+pub struct R<U, T> {
+ pub(crate) bits: U,
+ _reg: marker::PhantomData<T>,
+}
+
+impl<U, T> R<U, T>
+where
+ U: Copy,
+{
+ ///Create new instance of reader
+ #[inline(always)]
+ pub(crate) fn new(bits: U) -> Self {
+ Self {
+ bits,
+ _reg: marker::PhantomData,
+ }
+ }
+ ///Read raw bits from register/field
+ #[inline(always)]
+ pub fn bits(&self) -> U {
+ self.bits
+ }
+}
+
+impl<U, T, FI> PartialEq<FI> for R<U, T>
+where
+ U: PartialEq,
+ FI: Copy + Into<U>,
+{
+ #[inline(always)]
+ fn eq(&self, other: &FI) -> bool {
+ self.bits.eq(&(*other).into())
+ }
+}
+
+impl<FI> R<bool, FI> {
+ ///Value of the field as raw bits
+ #[inline(always)]
+ pub fn bit(&self) -> bool {
+ self.bits
+ }
+ ///Returns `true` if the bit is clear (0)
+ #[inline(always)]
+ pub fn bit_is_clear(&self) -> bool {
+ !self.bit()
+ }
+}
+
+///Register writer
+///
+///Used as an argument to the closures in the [`write`](Reg::write) and [`modify`](Reg::modify) methods of the register
+pub struct W<U, REG> {
+ ///Writable bits
+ pub(crate) bits: U,
+ _reg: marker::PhantomData<REG>,
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/mod.rs b/embassy-stm32/src/can/fd/message_ram/mod.rs
new file mode 100644
index 000000000..830edf3bb
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/mod.rs
@@ -0,0 +1,170 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+use volatile_register::RW;
+
+pub(crate) mod common;
+pub(crate) mod enums;
+pub(crate) mod generic;
+
+/// Number of Receive Fifos configured by this module
+pub const RX_FIFOS_MAX: u8 = 2;
+/// Number of Receive Messages per RxFifo configured by this module
+pub const RX_FIFO_MAX: u8 = 3;
+/// Number of Transmit Messages configured by this module
+pub const TX_FIFO_MAX: u8 = 3;
+/// Number of Transmit Events configured by this module
+pub const TX_EVENT_MAX: u8 = 3;
+/// Number of Standard Filters configured by this module
+pub const STANDARD_FILTER_MAX: u8 = 28;
+/// Number of Extended Filters configured by this module
+pub const EXTENDED_FILTER_MAX: u8 = 8;
+
+/// MessageRam Overlay
+#[repr(C)]
+pub struct RegisterBlock {
+ pub(crate) filters: Filters,
+ pub(crate) receive: [Receive; RX_FIFOS_MAX as usize],
+ pub(crate) transmit: Transmit,
+}
+impl RegisterBlock {
+ pub fn reset(&mut self) {
+ self.filters.reset();
+ self.receive[0].reset();
+ self.receive[1].reset();
+ self.transmit.reset();
+ }
+}
+
+#[repr(C)]
+pub(crate) struct Filters {
+ pub(crate) flssa: [StandardFilter; STANDARD_FILTER_MAX as usize],
+ pub(crate) flesa: [ExtendedFilter; EXTENDED_FILTER_MAX as usize],
+}
+impl Filters {
+ pub fn reset(&mut self) {
+ for sf in &mut self.flssa {
+ sf.reset();
+ }
+ for ef in &mut self.flesa {
+ ef.reset();
+ }
+ }
+}
+
+#[repr(C)]
+pub(crate) struct Receive {
+ pub(crate) fxsa: [RxFifoElement; RX_FIFO_MAX as usize],
+}
+impl Receive {
+ pub fn reset(&mut self) {
+ for fe in &mut self.fxsa {
+ fe.reset();
+ }
+ }
+}
+
+#[repr(C)]
+pub(crate) struct Transmit {
+ pub(crate) efsa: [TxEventElement; TX_EVENT_MAX as usize],
+ pub(crate) tbsa: [TxBufferElement; TX_FIFO_MAX as usize],
+}
+impl Transmit {
+ pub fn reset(&mut self) {
+ for ee in &mut self.efsa {
+ ee.reset();
+ }
+ for be in &mut self.tbsa {
+ be.reset();
+ }
+ }
+}
+
+pub(crate) mod standard_filter;
+pub(crate) type StandardFilterType = u32;
+pub(crate) type StandardFilter = generic::Reg<StandardFilterType, _StandardFilter>;
+pub(crate) struct _StandardFilter;
+impl generic::Readable for StandardFilter {}
+impl generic::Writable for StandardFilter {}
+
+pub(crate) mod extended_filter;
+pub(crate) type ExtendedFilterType = [u32; 2];
+pub(crate) type ExtendedFilter = generic::Reg<ExtendedFilterType, _ExtendedFilter>;
+pub(crate) struct _ExtendedFilter;
+impl generic::Readable for ExtendedFilter {}
+impl generic::Writable for ExtendedFilter {}
+
+pub(crate) mod txevent_element;
+pub(crate) type TxEventElementType = [u32; 2];
+pub(crate) type TxEventElement = generic::Reg<TxEventElementType, _TxEventElement>;
+pub(crate) struct _TxEventElement;
+impl generic::Readable for TxEventElement {}
+impl generic::Writable for TxEventElement {}
+
+pub(crate) mod rxfifo_element;
+#[repr(C)]
+pub(crate) struct RxFifoElement {
+ pub(crate) header: RxFifoElementHeader,
+ pub(crate) data: [RW<u32>; 16],
+}
+impl RxFifoElement {
+ pub(crate) fn reset(&mut self) {
+ self.header.reset();
+ for byte in self.data.iter_mut() {
+ unsafe { byte.write(0) };
+ }
+ }
+}
+pub(crate) type RxFifoElementHeaderType = [u32; 2];
+pub(crate) type RxFifoElementHeader = generic::Reg<RxFifoElementHeaderType, _RxFifoElement>;
+pub(crate) struct _RxFifoElement;
+impl generic::Readable for RxFifoElementHeader {}
+impl generic::Writable for RxFifoElementHeader {}
+
+pub(crate) mod txbuffer_element;
+#[repr(C)]
+pub(crate) struct TxBufferElement {
+ pub(crate) header: TxBufferElementHeader,
+ pub(crate) data: [RW<u32>; 16],
+}
+impl TxBufferElement {
+ pub(crate) fn reset(&mut self) {
+ self.header.reset();
+ for byte in self.data.iter_mut() {
+ unsafe { byte.write(0) };
+ }
+ }
+}
+pub(crate) type TxBufferElementHeader = generic::Reg<TxBufferElementHeaderType, _TxBufferElement>;
+pub(crate) type TxBufferElementHeaderType = [u32; 2];
+pub(crate) struct _TxBufferElement;
+impl generic::Readable for TxBufferElementHeader {}
+impl generic::Writable for TxBufferElementHeader {}
+
+/// FdCan Message RAM instance.
+///
+/// # Safety
+///
+/// It is only safe to implement this trait, when:
+///
+/// * The implementing type has ownership of the Message RAM, preventing any
+/// other accesses to the register block.
+/// * `MSG_RAM` is a pointer to the Message RAM block and can be safely accessed
+/// for as long as ownership or a borrow of the implementing type is present.
+pub unsafe trait Instance {
+ const MSG_RAM: *mut RegisterBlock;
+ fn msg_ram(&self) -> &RegisterBlock {
+ unsafe { &*Self::MSG_RAM }
+ }
+ fn msg_ram_mut(&mut self) -> &mut RegisterBlock {
+ unsafe { &mut *Self::MSG_RAM }
+ }
+}
+
+// Ensure the RegisterBlock is the same size as on pg 1957 of RM0440.
+static_assertions::assert_eq_size!(Filters, [u32; 28 + 16]);
+static_assertions::assert_eq_size!(Receive, [u32; 54]);
+static_assertions::assert_eq_size!(Transmit, [u32; 6 + 54]);
+static_assertions::assert_eq_size!(
+ RegisterBlock,
+ [u32; 28 /*Standard Filters*/ +16 /*Extended Filters*/ +54 /*RxFifo0*/ +54 /*RxFifo1*/ +6 /*TxEvent*/ +54 /*TxFifo */]
+);
diff --git a/embassy-stm32/src/can/fd/message_ram/rxfifo_element.rs b/embassy-stm32/src/can/fd/message_ram/rxfifo_element.rs
new file mode 100644
index 000000000..48fc3a091
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/rxfifo_element.rs
@@ -0,0 +1,122 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![allow(unused)]
+
+use super::common::{BRS_R, DLC_R, ESI_R, FDF_R, ID_R, RTR_R, XTD_R};
+use super::enums::{DataLength, FilterFrameMatch, FrameFormat};
+use super::generic;
+
+#[doc = "Reader of register RxFifoElement"]
+pub(crate) type R = generic::R<super::RxFifoElementHeaderType, super::RxFifoElementHeader>;
+// #[doc = "Writer for register ExtendedFilter"]
+// pub(crate) type W = generic::W<super::RxFifoElementHeaderType, super::RxFifoElementHeader>;
+#[doc = "Register ExtendedFilter `reset()`'s"]
+impl generic::ResetValue for super::RxFifoElementHeader {
+ type Type = super::RxFifoElementHeaderType;
+ #[inline(always)]
+ fn reset_value() -> Self::Type {
+ [0x0, 0x0]
+ }
+}
+
+#[doc = "Reader of field `RXTS`"]
+pub(crate) type RXTS_R = generic::R<u16, u16>;
+
+#[doc = "Reader of field `FIDX`"]
+pub(crate) type FIDX_R = generic::R<u8, u8>;
+
+pub(crate) struct _ANMF;
+#[doc = "Reader of field `ANMF`"]
+pub(crate) type ANMF_R = generic::R<bool, _ANMF>;
+impl ANMF_R {
+ pub fn is_matching_frame(&self) -> bool {
+ self.bit_is_clear()
+ }
+}
+
+impl R {
+ #[doc = "Byte 0 - Bits 0:28 - ID"]
+ #[inline(always)]
+ pub fn id(&self) -> ID_R {
+ ID_R::new(((self.bits[0]) & 0x1FFFFFFF) as u32)
+ }
+ #[doc = "Byte 0 - Bit 29 - RTR"]
+ #[inline(always)]
+ pub fn rtr(&self) -> RTR_R {
+ RTR_R::new(((self.bits[0] >> 29) & 0x01) != 0)
+ }
+ #[doc = "Byte 0 - Bit 30 - XTD"]
+ #[inline(always)]
+ pub fn xtd(&self) -> XTD_R {
+ XTD_R::new(((self.bits[0] >> 30) & 0x01) != 0)
+ }
+ #[doc = "Byte 0 - Bit 30 - ESI"]
+ #[inline(always)]
+ pub fn esi(&self) -> ESI_R {
+ ESI_R::new(((self.bits[0] >> 31) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 0:15 - RXTS"]
+ #[inline(always)]
+ pub fn txts(&self) -> RXTS_R {
+ RXTS_R::new(((self.bits[1]) & 0xFFFF) as u16)
+ }
+ #[doc = "Byte 1 - Bits 16:19 - DLC"]
+ #[inline(always)]
+ pub fn dlc(&self) -> DLC_R {
+ DLC_R::new(((self.bits[1] >> 16) & 0x0F) as u8)
+ }
+ #[doc = "Byte 1 - Bits 20 - BRS"]
+ #[inline(always)]
+ pub fn brs(&self) -> BRS_R {
+ BRS_R::new(((self.bits[1] >> 20) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 20 - FDF"]
+ #[inline(always)]
+ pub fn fdf(&self) -> FDF_R {
+ FDF_R::new(((self.bits[1] >> 21) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 24:30 - FIDX"]
+ #[inline(always)]
+ pub fn fidx(&self) -> FIDX_R {
+ FIDX_R::new(((self.bits[1] >> 24) & 0xFF) as u8)
+ }
+ #[doc = "Byte 1 - Bits 31 - ANMF"]
+ #[inline(always)]
+ pub fn anmf(&self) -> ANMF_R {
+ ANMF_R::new(((self.bits[1] >> 31) & 0x01) != 0)
+ }
+ pub fn to_data_length(&self) -> DataLength {
+ let dlc = self.dlc().bits();
+ let ff = self.fdf().frame_format();
+ let len = if ff == FrameFormat::Fdcan {
+ // See RM0433 Rev 7 Table 475. DLC coding
+ match dlc {
+ 0..=8 => dlc,
+ 9 => 12,
+ 10 => 16,
+ 11 => 20,
+ 12 => 24,
+ 13 => 32,
+ 14 => 48,
+ 15 => 64,
+ _ => panic!("DLC > 15"),
+ }
+ } else {
+ match dlc {
+ 0..=8 => dlc,
+ 9..=15 => 8,
+ _ => panic!("DLC > 15"),
+ }
+ };
+ DataLength::new(len, ff)
+ }
+ pub fn to_filter_match(&self) -> FilterFrameMatch {
+ if self.anmf().is_matching_frame() {
+ FilterFrameMatch::DidMatch(self.fidx().bits())
+ } else {
+ FilterFrameMatch::DidNotMatch
+ }
+ }
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/standard_filter.rs b/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
new file mode 100644
index 000000000..3a3bbcf12
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/standard_filter.rs
@@ -0,0 +1,136 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![allow(unused)]
+
+use super::common::{ESFEC_R, ESFT_R};
+use super::enums::{FilterElementConfig, FilterType};
+use super::generic;
+
+#[doc = "Reader of register StandardFilter"]
+pub(crate) type R = generic::R<super::StandardFilterType, super::StandardFilter>;
+#[doc = "Writer for register StandardFilter"]
+pub(crate) type W = generic::W<super::StandardFilterType, super::StandardFilter>;
+#[doc = "Register StandardFilter `reset()`'s with value 0xC0000"]
+impl generic::ResetValue for super::StandardFilter {
+ type Type = super::StandardFilterType;
+ #[inline(always)]
+ fn reset_value() -> Self::Type {
+ // Sets filter element to Disabled
+ 0xC000
+ }
+}
+
+#[doc = "Reader of field `SFID2`"]
+pub(crate) type SFID2_R = generic::R<u16, u16>;
+#[doc = "Write proxy for field `SFID2`"]
+pub(crate) struct SFID2_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> SFID2_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u16) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x07ff)) | ((value as u32) & 0x07ff);
+ self.w
+ }
+}
+
+#[doc = "Reader of field `SFID1`"]
+pub(crate) type SFID1_R = generic::R<u16, u16>;
+#[doc = "Write proxy for field `SFID1`"]
+pub(crate) struct SFID1_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> SFID1_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u16) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x07ff << 16)) | (((value as u32) & 0x07ff) << 16);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `SFEC`"]
+pub(crate) struct SFEC_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> SFEC_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x07 << 27)) | (((value as u32) & 0x07) << 27);
+ self.w
+ }
+ #[doc = r"Sets the field according to FilterElementConfig"]
+ #[inline(always)]
+ pub fn set_filter_element_config(self, fec: FilterElementConfig) -> &'a mut W {
+ //SAFETY: FilterElementConfig only be valid options
+ unsafe { self.bits(fec as u8) }
+ }
+}
+
+#[doc = "Write proxy for field `SFT`"]
+pub(crate) struct SFT_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> SFT_W<'a> {
+ #[doc = r"Sets the field according the FilterType"]
+ #[inline(always)]
+ pub fn set_filter_type(self, filter: FilterType) -> &'a mut W {
+ //SAFETY: FilterType only be valid options
+ unsafe { self.bits(filter as u8) }
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
+ self.w
+ }
+}
+
+impl R {
+ #[doc = "Bits 0:10 - SFID2"]
+ #[inline(always)]
+ pub fn sfid2(&self) -> SFID2_R {
+ SFID2_R::new((self.bits & 0x07ff) as u16)
+ }
+ #[doc = "Bits 16:26 - SFID1"]
+ #[inline(always)]
+ pub fn sfid1(&self) -> SFID1_R {
+ SFID1_R::new(((self.bits >> 16) & 0x07ff) as u16)
+ }
+ #[doc = "Bits 27:29 - SFEC"]
+ #[inline(always)]
+ pub fn sfec(&self) -> ESFEC_R {
+ ESFEC_R::new(((self.bits >> 27) & 0x07) as u8)
+ }
+ #[doc = "Bits 30:31 - SFT"]
+ #[inline(always)]
+ pub fn sft(&self) -> ESFT_R {
+ ESFT_R::new(((self.bits >> 30) & 0x03) as u8)
+ }
+}
+impl W {
+ #[doc = "Bits 0:10 - SFID2"]
+ #[inline(always)]
+ pub fn sfid2(&mut self) -> SFID2_W {
+ SFID2_W { w: self }
+ }
+ #[doc = "Bits 16:26 - SFID1"]
+ #[inline(always)]
+ pub fn sfid1(&mut self) -> SFID1_W {
+ SFID1_W { w: self }
+ }
+ #[doc = "Bits 27:29 - SFEC"]
+ #[inline(always)]
+ pub fn sfec(&mut self) -> SFEC_W {
+ SFEC_W { w: self }
+ }
+ #[doc = "Bits 30:31 - SFT"]
+ #[inline(always)]
+ pub fn sft(&mut self) -> SFT_W {
+ SFT_W { w: self }
+ }
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs b/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
new file mode 100644
index 000000000..455406a1c
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/txbuffer_element.rs
@@ -0,0 +1,433 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![allow(unused)]
+
+use super::common::{BRS_R, DLC_R, ESI_R, FDF_R, ID_R, RTR_R, XTD_R};
+use super::enums::{
+ BitRateSwitching, DataLength, ErrorStateIndicator, Event, EventControl, FrameFormat, IdType,
+ RemoteTransmissionRequest,
+};
+use super::generic;
+
+#[doc = "Reader of register TxBufferElement"]
+pub(crate) type R = generic::R<super::TxBufferElementHeaderType, super::TxBufferElementHeader>;
+#[doc = "Writer for register TxBufferElement"]
+pub(crate) type W = generic::W<super::TxBufferElementHeaderType, super::TxBufferElementHeader>;
+impl generic::ResetValue for super::TxBufferElementHeader {
+ type Type = super::TxBufferElementHeaderType;
+
+ #[allow(dead_code)]
+ #[inline(always)]
+ fn reset_value() -> Self::Type {
+ [0; 2]
+ }
+}
+
+#[doc = "Write proxy for field `ESI`"]
+pub(crate) struct ESI_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> ESI_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_error_indicator(self, esi: ErrorStateIndicator) -> &'a mut W {
+ self.bit(esi as u8 != 0)
+ }
+
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits[0] = (self.w.bits[0] & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `XTD`"]
+pub(crate) struct XTD_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> XTD_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_id_type(self, idt: IdType) -> &'a mut W {
+ self.bit(idt as u8 != 0)
+ }
+
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits[0] = (self.w.bits[0] & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `RTR`"]
+pub(crate) struct RTR_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> RTR_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_rtr(self, rtr: RemoteTransmissionRequest) -> &'a mut W {
+ self.bit(rtr as u8 != 0)
+ }
+
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits[0] = (self.w.bits[0] & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `ID`"]
+pub(crate) struct ID_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> ID_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub unsafe fn bits(self, value: u32) -> &'a mut W {
+ self.w.bits[0] = (self.w.bits[0] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `DLC`"]
+pub(crate) struct DLC_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> DLC_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits[1] = (self.w.bits[1] & !(0x0F << 16)) | (((value as u32) & 0x0F) << 16);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `BRS`"]
+pub(crate) struct BRS_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> BRS_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_brs(self, brs: BitRateSwitching) -> &'a mut W {
+ self.bit(brs as u8 != 0)
+ }
+
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits[1] = (self.w.bits[1] & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
+ self.w
+ }
+}
+
+#[doc = "Write proxy for field `FDF`"]
+pub(crate) struct FDF_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> FDF_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_format(self, fdf: FrameFormat) -> &'a mut W {
+ self.bit(fdf as u8 != 0)
+ }
+
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits[1] = (self.w.bits[1] & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
+ self.w
+ }
+}
+
+#[doc = "Reader of field `EFC`"]
+pub(crate) type EFC_R = generic::R<bool, EventControl>;
+impl EFC_R {
+ pub fn to_event_control(&self) -> EventControl {
+ match self.bit() {
+ false => EventControl::DoNotStore,
+ true => EventControl::Store,
+ }
+ }
+}
+#[doc = "Write proxy for field `EFC`"]
+pub(crate) struct EFC_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> EFC_W<'a> {
+ #[doc = r"Writes `variant` to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_event_control(self, efc: EventControl) -> &'a mut W {
+ self.bit(match efc {
+ EventControl::DoNotStore => false,
+ EventControl::Store => true,
+ })
+ }
+
+ #[doc = r"Sets the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn set_bit(self) -> &'a mut W {
+ self.bit(true)
+ }
+ #[doc = r"Clears the field bit"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn clear_bit(self) -> &'a mut W {
+ self.bit(false)
+ }
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ #[allow(dead_code)]
+ pub fn bit(self, value: bool) -> &'a mut W {
+ self.w.bits[1] = (self.w.bits[1] & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
+ self.w
+ }
+}
+
+struct Marker(u8);
+impl From<Event> for Marker {
+ fn from(e: Event) -> Marker {
+ match e {
+ Event::NoEvent => Marker(0),
+ Event::Event(mm) => Marker(mm),
+ }
+ }
+}
+
+#[doc = "Reader of field `MM`"]
+pub(crate) type MM_R = generic::R<u8, u8>;
+#[doc = "Write proxy for field `MM`"]
+pub(crate) struct MM_W<'a> {
+ w: &'a mut W,
+}
+impl<'a> MM_W<'a> {
+ #[doc = r"Writes raw bits to the field"]
+ #[inline(always)]
+ pub unsafe fn bits(self, value: u8) -> &'a mut W {
+ self.w.bits[1] = (self.w.bits[1] & !(0x7F << 24)) | (((value as u32) & 0x7F) << 24);
+ self.w
+ }
+
+ fn set_message_marker(self, mm: Marker) -> &'a mut W {
+ unsafe { self.bits(mm.0) }
+ }
+}
+
+impl R {
+ #[doc = "Byte 0 - Bits 0:28 - ID"]
+ #[inline(always)]
+ pub fn id(&self) -> ID_R {
+ ID_R::new(((self.bits[0]) & 0x1FFFFFFF) as u32)
+ }
+ #[doc = "Byte 0 - Bit 29 - RTR"]
+ #[inline(always)]
+ pub fn rtr(&self) -> RTR_R {
+ RTR_R::new(((self.bits[0] >> 29) & 0x01) != 0)
+ }
+ #[doc = "Byte 0 - Bit 30 - XTD"]
+ #[inline(always)]
+ pub fn xtd(&self) -> XTD_R {
+ XTD_R::new(((self.bits[0] >> 30) & 0x01) != 0)
+ }
+ #[doc = "Byte 0 - Bit 30 - ESI"]
+ #[inline(always)]
+ pub fn esi(&self) -> ESI_R {
+ ESI_R::new(((self.bits[0] >> 31) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 16:19 - DLC"]
+ #[inline(always)]
+ pub fn dlc(&self) -> DLC_R {
+ DLC_R::new(((self.bits[1] >> 16) & 0x0F) as u8)
+ }
+ #[doc = "Byte 1 - Bits 20 - BRS"]
+ #[inline(always)]
+ pub fn brs(&self) -> BRS_R {
+ BRS_R::new(((self.bits[1] >> 20) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 20 - FDF"]
+ #[inline(always)]
+ pub fn fdf(&self) -> FDF_R {
+ FDF_R::new(((self.bits[1] >> 21) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 23 - EFC"]
+ #[inline(always)]
+ pub fn efc(&self) -> EFC_R {
+ EFC_R::new(((self.bits[1] >> 23) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 24:31 - MM"]
+ #[inline(always)]
+ pub fn mm(&self) -> MM_R {
+ MM_R::new(((self.bits[1] >> 24) & 0xFF) as u8)
+ }
+ pub fn to_data_length(&self) -> DataLength {
+ let dlc = self.dlc().bits();
+ let ff = self.fdf().frame_format();
+ let len = if ff == FrameFormat::Fdcan {
+ // See RM0433 Rev 7 Table 475. DLC coding
+ match dlc {
+ 0..=8 => dlc,
+ 9 => 12,
+ 10 => 16,
+ 11 => 20,
+ 12 => 24,
+ 13 => 32,
+ 14 => 48,
+ 15 => 64,
+ _ => panic!("DLC > 15"),
+ }
+ } else {
+ match dlc {
+ 0..=8 => dlc,
+ 9..=15 => 8,
+ _ => panic!("DLC > 15"),
+ }
+ };
+ DataLength::new(len, ff)
+ }
+ pub fn to_event(&self) -> Event {
+ let mm = self.mm().bits();
+ let efc = self.efc().to_event_control();
+ match efc {
+ EventControl::DoNotStore => Event::NoEvent,
+ EventControl::Store => Event::Event(mm),
+ }
+ }
+}
+impl W {
+ #[doc = "Byte 0 - Bits 0:28 - ID"]
+ #[inline(always)]
+ pub fn id(&mut self) -> ID_W {
+ ID_W { w: self }
+ }
+ #[doc = "Byte 0 - Bit 29 - RTR"]
+ #[inline(always)]
+ pub fn rtr(&mut self) -> RTR_W {
+ RTR_W { w: self }
+ }
+ #[doc = "Byte 0 - Bit 30 - XTD"]
+ #[inline(always)]
+ pub fn xtd(&mut self) -> XTD_W {
+ XTD_W { w: self }
+ }
+ #[doc = "Byte 0 - Bit 31 - ESI"]
+ #[inline(always)]
+ pub fn esi(&mut self) -> ESI_W {
+ ESI_W { w: self }
+ }
+ #[doc = "Byte 1 - Bit 16:19 - DLC"]
+ #[inline(always)]
+ pub fn dlc(&mut self) -> DLC_W {
+ DLC_W { w: self }
+ }
+ #[doc = "Byte 1 - Bit 20 - BRS"]
+ #[inline(always)]
+ pub fn brs(&mut self) -> BRS_W {
+ BRS_W { w: self }
+ }
+ #[doc = "Byte 1 - Bit 21 - FDF"]
+ #[inline(always)]
+ pub fn fdf(&mut self) -> FDF_W {
+ FDF_W { w: self }
+ }
+ #[doc = "Byte 1 - Bit 23 - EFC"]
+ #[inline(always)]
+ pub fn efc(&mut self) -> EFC_W {
+ EFC_W { w: self }
+ }
+ #[doc = "Byte 1 - Bit 24:31 - MM"]
+ #[inline(always)]
+ pub fn mm(&mut self) -> MM_W {
+ MM_W { w: self }
+ }
+ #[doc = "Convenience function for setting the data length and frame format"]
+ #[inline(always)]
+ pub fn set_len(&mut self, dl: impl Into<DataLength>) -> &mut Self {
+ let dl: DataLength = dl.into();
+ self.fdf().set_format(dl.into());
+ unsafe { self.dlc().bits(dl.dlc()) }
+ }
+ pub fn set_event(&mut self, event: Event) -> &mut Self {
+ self.mm().set_message_marker(event.into());
+ self.efc().set_event_control(event.into())
+ }
+}
diff --git a/embassy-stm32/src/can/fd/message_ram/txevent_element.rs b/embassy-stm32/src/can/fd/message_ram/txevent_element.rs
new file mode 100644
index 000000000..817a4449f
--- /dev/null
+++ b/embassy-stm32/src/can/fd/message_ram/txevent_element.rs
@@ -0,0 +1,138 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+#![allow(non_camel_case_types)]
+#![allow(non_snake_case)]
+#![allow(unused)]
+
+use super::common::{BRS_R, DLC_R, ESI_R, RTR_R, XTD_R};
+use super::generic;
+
+#[doc = "Reader of register TxEventElement"]
+pub(crate) type R = generic::R<super::TxEventElementType, super::TxEventElement>;
+// #[doc = "Writer for register TxEventElement"]
+// pub(crate) type W = generic::W<super::TxEventElementType, super::TxEventElement>;
+#[doc = "Register TxEventElement `reset()`'s"]
+impl generic::ResetValue for super::TxEventElement {
+ type Type = super::TxEventElementType;
+ #[inline(always)]
+ fn reset_value() -> Self::Type {
+ [0, 0]
+ }
+}
+
+#[doc = "Reader of field `ID`"]
+pub(crate) type ID_R = generic::R<u32, u32>;
+
+#[doc = "Reader of field `TXTS`"]
+pub(crate) type TXTS_R = generic::R<u16, u16>;
+
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub(crate) enum DataLengthFormat {
+ StandardLength = 0,
+ FDCANLength = 1,
+}
+impl From<DataLengthFormat> for bool {
+ #[inline(always)]
+ fn from(dlf: DataLengthFormat) -> Self {
+ dlf as u8 != 0
+ }
+}
+
+#[doc = "Reader of field `EDL`"]
+pub(crate) type EDL_R = generic::R<bool, DataLengthFormat>;
+impl EDL_R {
+ pub fn data_length_format(&self) -> DataLengthFormat {
+ match self.bits() {
+ false => DataLengthFormat::StandardLength,
+ true => DataLengthFormat::FDCANLength,
+ }
+ }
+ pub fn is_standard_length(&self) -> bool {
+ *self == DataLengthFormat::StandardLength
+ }
+ pub fn is_fdcan_length(&self) -> bool {
+ *self == DataLengthFormat::FDCANLength
+ }
+}
+
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub(crate) enum EventType {
+ //_Reserved = 0b00,
+ TxEvent = 0b01,
+ TxDespiteAbort = 0b10,
+ //_Reserved = 0b10,
+}
+
+#[doc = "Reader of field `EFC`"]
+pub(crate) type EFC_R = generic::R<u8, EventType>;
+impl EFC_R {
+ pub fn event_type(&self) -> EventType {
+ match self.bits() {
+ 0b01 => EventType::TxEvent,
+ 0b10 => EventType::TxDespiteAbort,
+ _ => unimplemented!(),
+ }
+ }
+ pub fn is_tx_event(&self) -> bool {
+ self.event_type() == EventType::TxEvent
+ }
+ pub fn is_despite_abort(&self) -> bool {
+ self.event_type() == EventType::TxDespiteAbort
+ }
+}
+
+#[doc = "Reader of field `MM`"]
+pub(crate) type MM_R = generic::R<u8, u8>;
+
+impl R {
+ #[doc = "Byte 0 - Bits 0:28 - ID"]
+ #[inline(always)]
+ pub fn id(&self) -> ID_R {
+ ID_R::new(((self.bits[0]) & 0x1FFFFFFF) as u32)
+ }
+ #[doc = "Byte 0 - Bit 29 - RTR"]
+ #[inline(always)]
+ pub fn rtr(&self) -> RTR_R {
+ RTR_R::new(((self.bits[0] >> 29) & 0x01) != 0)
+ }
+ #[doc = "Byte 0 - Bit 30 - XTD"]
+ #[inline(always)]
+ pub fn xtd(&self) -> XTD_R {
+ XTD_R::new(((self.bits[0] >> 30) & 0x01) != 0)
+ }
+ #[doc = "Byte 0 - Bit 30 - ESI"]
+ #[inline(always)]
+ pub fn esi(&self) -> ESI_R {
+ ESI_R::new(((self.bits[0] >> 31) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 0:15 - TXTS"]
+ #[inline(always)]
+ pub fn txts(&self) -> TXTS_R {
+ TXTS_R::new(((self.bits[1]) & 0xFFFF) as u16)
+ }
+ #[doc = "Byte 1 - Bits 16:19 - DLC"]
+ #[inline(always)]
+ pub fn dlc(&self) -> DLC_R {
+ DLC_R::new(((self.bits[1] >> 16) & 0x0F) as u8)
+ }
+ #[doc = "Byte 1 - Bits 20 - BRS"]
+ #[inline(always)]
+ pub fn brs(&self) -> BRS_R {
+ BRS_R::new(((self.bits[1] >> 20) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 21 - EDL"]
+ #[inline(always)]
+ pub fn edl(&self) -> EDL_R {
+ EDL_R::new(((self.bits[1] >> 21) & 0x01) != 0)
+ }
+ #[doc = "Byte 1 - Bits 22:23 - EFC"]
+ #[inline(always)]
+ pub fn efc(&self) -> EFC_R {
+ EFC_R::new(((self.bits[1] >> 22) & 0x03) as u8)
+ }
+ #[doc = "Byte 1 - Bits 24:31 - MM"]
+ #[inline(always)]
+ pub fn mm(&self) -> MM_R {
+ MM_R::new(((self.bits[1] >> 24) & 0xFF) as u8)
+ }
+}
diff --git a/embassy-stm32/src/can/fd/mod.rs b/embassy-stm32/src/can/fd/mod.rs
new file mode 100644
index 000000000..0008fd3a8
--- /dev/null
+++ b/embassy-stm32/src/can/fd/mod.rs
@@ -0,0 +1,6 @@
+//! Module containing that which is speciffic to fdcan hardware variant
+
+pub mod config;
+pub mod filter;
+pub(crate) mod message_ram;
+pub(crate) mod peripheral;
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
new file mode 100644
index 000000000..6f390abb4
--- /dev/null
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -0,0 +1,776 @@
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
+
+use core::convert::Infallible;
+use core::slice;
+
+use crate::can::fd::config::*;
+use crate::can::fd::message_ram::enums::*;
+use crate::can::fd::message_ram::{RegisterBlock, RxFifoElement, TxBufferElement};
+use crate::can::frame::*;
+
+/// Loopback Mode
+#[derive(Clone, Copy, Debug)]
+enum LoopbackMode {
+ None,
+ Internal,
+ External,
+}
+
+pub struct Registers {
+ pub regs: &'static crate::pac::can::Fdcan,
+ pub msgram: &'static crate::pac::fdcanram::Fdcanram,
+}
+
+impl Registers {
+ fn tx_buffer_element(&self, bufidx: usize) -> &mut TxBufferElement {
+ &mut self.msg_ram_mut().transmit.tbsa[bufidx]
+ }
+ pub fn msg_ram_mut(&self) -> &mut RegisterBlock {
+ let ptr = self.msgram.as_ptr() as *mut RegisterBlock;
+ unsafe { &mut (*ptr) }
+ }
+
+ fn rx_fifo_element(&self, fifonr: usize, bufnum: usize) -> &mut RxFifoElement {
+ &mut self.msg_ram_mut().receive[fifonr].fxsa[bufnum]
+ }
+
+ pub fn read_classic(&self, fifonr: usize) -> Option<(ClassicFrame, u16)> {
+ // Fill level - do we have a msg?
+ if self.regs.rxfs(fifonr).read().ffl() < 1 {
+ return None;
+ }
+
+ let read_idx = self.regs.rxfs(fifonr).read().fgi();
+ let mailbox = self.rx_fifo_element(fifonr, read_idx as usize);
+
+ let mut buffer: [u8; 8] = [0; 8];
+ let maybe_header = extract_frame(mailbox, &mut buffer);
+
+ // Clear FIFO, reduces count and increments read buf
+ self.regs.rxfa(fifonr).modify(|w| w.set_fai(read_idx));
+
+ match maybe_header {
+ Some((header, ts)) => {
+ let data = ClassicData::new(&buffer[0..header.len() as usize]);
+ Some((ClassicFrame::new(header, data.unwrap()), ts))
+ }
+ None => None,
+ }
+ }
+
+ pub fn read_fd(&self, fifonr: usize) -> Option<(FdFrame, u16)> {
+ // Fill level - do we have a msg?
+ if self.regs.rxfs(fifonr).read().ffl() < 1 {
+ return None;
+ }
+
+ let read_idx = self.regs.rxfs(fifonr).read().fgi();
+ let mailbox = self.rx_fifo_element(fifonr, read_idx as usize);
+
+ let mut buffer: [u8; 64] = [0; 64];
+ let maybe_header = extract_frame(mailbox, &mut buffer);
+
+ // Clear FIFO, reduces count and increments read buf
+ self.regs.rxfa(fifonr).modify(|w| w.set_fai(read_idx));
+
+ match maybe_header {
+ Some((header, ts)) => {
+ let data = FdData::new(&buffer[0..header.len() as usize]);
+ Some((FdFrame::new(header, data.unwrap()), ts))
+ }
+ None => None,
+ }
+ }
+
+ pub fn put_tx_frame(&self, bufidx: usize, header: &Header, buffer: &[u8]) {
+ // Fill level - do we have a msg?
+ //if self.regs.rxfs(fifonr).read().ffl() < 1 { return None; }
+
+ //let read_idx = self.regs.rxfs(fifonr).read().fgi();
+
+ let mailbox = self.tx_buffer_element(bufidx);
+
+ mailbox.reset();
+ put_tx_header(mailbox, header);
+ put_tx_data(mailbox, &buffer[..header.len() as usize]);
+
+ // Set <idx as Mailbox> as ready to transmit
+ self.regs.txbar().modify(|w| w.set_ar(bufidx, true));
+ }
+
+ /// Returns if the tx queue is able to accept new messages without having to cancel an existing one
+ #[inline]
+ pub fn tx_queue_is_full(&self) -> bool {
+ self.regs.txfqs().read().tfqf()
+ }
+
+ #[inline]
+ pub fn has_pending_frame(&self, idx: usize) -> bool {
+ self.regs.txbrp().read().trp(idx)
+ }
+
+ /// Returns `Ok` when the mailbox is free or if it contains pending frame with a
+ /// lower priority (higher ID) than the identifier `id`.
+ #[inline]
+ pub fn is_available(&self, bufidx: usize, id: &embedded_can::Id) -> bool {
+ if self.has_pending_frame(bufidx) {
+ let mailbox = self.tx_buffer_element(bufidx);
+
+ let header_reg = mailbox.header.read();
+ let old_id = make_id(header_reg.id().bits(), header_reg.xtd().bits());
+
+ *id > old_id
+ } else {
+ true
+ }
+ }
+
+ /// Attempts to abort the sending of a frame that is pending in a mailbox.
+ ///
+ /// If there is no frame in the provided mailbox, or its transmission succeeds before it can be
+ /// aborted, this function has no effect and returns `false`.
+ ///
+ /// If there is a frame in the provided mailbox, and it is canceled successfully, this function
+ /// returns `true`.
+ #[inline]
+ pub fn abort(&self, bufidx: usize) -> bool {
+ let can = self.regs;
+
+ // Check if there is a request pending to abort
+ if self.has_pending_frame(bufidx) {
+ // Abort Request
+ can.txbcr().write(|w| w.set_cr(bufidx, true));
+
+ // Wait for the abort request to be finished.
+ loop {
+ if can.txbcf().read().cf(bufidx) {
+ // Return false when a transmission has occured
+ break can.txbto().read().to(bufidx) == false;
+ }
+ }
+ } else {
+ false
+ }
+ }
+
+ #[inline]
+ //fn abort_pending_mailbox<PTX, R>(&mut self, idx: Mailbox, pending: PTX) -> Option<R>
+ pub fn abort_pending_mailbox(&self, bufidx: usize) -> Option<ClassicFrame>
+//where
+ // PTX: FnOnce(Mailbox, TxFrameHeader, &[u32]) -> R,
+ {
+ if self.abort(bufidx) {
+ let mailbox = self.tx_buffer_element(bufidx);
+
+ let header_reg = mailbox.header.read();
+ let id = make_id(header_reg.id().bits(), header_reg.xtd().bits());
+
+ let len = match header_reg.to_data_length() {
+ DataLength::Fdcan(len) => len,
+ DataLength::Standard(len) => len,
+ };
+ if len as usize > ClassicFrame::MAX_DATA_LEN {
+ return None;
+ }
+
+ //let tx_ram = self.tx_msg_ram();
+ let mut data = [0u8; 64];
+ data_from_tx_buffer(&mut data, mailbox, len as usize);
+
+ let cd = ClassicData::new(&data).unwrap();
+ Some(ClassicFrame::new(Header::new(id, len, header_reg.rtr().bit()), cd))
+ } else {
+ // Abort request failed because the frame was already sent (or being sent) on
+ // the bus. All mailboxes are now free. This can happen for small prescaler
+ // values (e.g. 1MBit/s bit timing with a source clock of 8MHz) or when an ISR
+ // has preempted the execution.
+ None
+ }
+ }
+
+ #[inline]
+ //fn abort_pending_mailbox<PTX, R>(&mut self, idx: Mailbox, pending: PTX) -> Option<R>
+ pub fn abort_pending_fd_mailbox(&self, bufidx: usize) -> Option<FdFrame>
+//where
+ // PTX: FnOnce(Mailbox, TxFrameHeader, &[u32]) -> R,
+ {
+ if self.abort(bufidx) {
+ let mailbox = self.tx_buffer_element(bufidx);
+
+ let header_reg = mailbox.header.read();
+ let id = make_id(header_reg.id().bits(), header_reg.xtd().bits());
+
+ let len = match header_reg.to_data_length() {
+ DataLength::Fdcan(len) => len,
+ DataLength::Standard(len) => len,
+ };
+ if len as usize > FdFrame::MAX_DATA_LEN {
+ return None;
+ }
+
+ //let tx_ram = self.tx_msg_ram();
+ let mut data = [0u8; 64];
+ data_from_tx_buffer(&mut data, mailbox, len as usize);
+
+ let cd = FdData::new(&data).unwrap();
+
+ let header = if header_reg.fdf().frame_format() == FrameFormat::Fdcan {
+ Header::new_fd(id, len, header_reg.rtr().bit(), header_reg.brs().bit())
+ } else {
+ Header::new(id, len, header_reg.rtr().bit())
+ };
+
+ Some(FdFrame::new(header, cd))
+ } else {
+ // Abort request failed because the frame was already sent (or being sent) on
+ // the bus. All mailboxes are now free. This can happen for small prescaler
+ // values (e.g. 1MBit/s bit timing with a source clock of 8MHz) or when an ISR
+ // has preempted the execution.
+ None
+ }
+ }
+
+ /// As Transmit, but if there is a pending frame, `pending` will be called so that the frame can
+ /// be preserved.
+ //pub fn transmit_preserve<PTX, P>(
+ pub fn write_classic(&self, frame: &ClassicFrame) -> nb::Result<Option<ClassicFrame>, Infallible> {
+ let queue_is_full = self.tx_queue_is_full();
+
+ let id = frame.header().id();
+
+ // If the queue is full,
+ // Discard the first slot with a lower priority message
+ let (idx, pending_frame) = if queue_is_full {
+ if self.is_available(0, id) {
+ (0, self.abort_pending_mailbox(0))
+ } else if self.is_available(1, id) {
+ (1, self.abort_pending_mailbox(1))
+ } else if self.is_available(2, id) {
+ (2, self.abort_pending_mailbox(2))
+ } else {
+ // For now we bail when there is no lower priority slot available
+ // Can this lead to priority inversion?
+ return Err(nb::Error::WouldBlock);
+ }
+ } else {
+ // Read the Write Pointer
+ let idx = self.regs.txfqs().read().tfqpi();
+
+ (idx, None)
+ };
+
+ self.put_tx_frame(idx as usize, frame.header(), frame.data());
+
+ Ok(pending_frame)
+ }
+
+ /// As Transmit, but if there is a pending frame, `pending` will be called so that the frame can
+ /// be preserved.
+ //pub fn transmit_preserve<PTX, P>(
+ pub fn write_fd(&self, frame: &FdFrame) -> nb::Result<Option<FdFrame>, Infallible> {
+ let queue_is_full = self.tx_queue_is_full();
+
+ let id = frame.header().id();
+
+ // If the queue is full,
+ // Discard the first slot with a lower priority message
+ let (idx, pending_frame) = if queue_is_full {
+ if self.is_available(0, id) {
+ (0, self.abort_pending_fd_mailbox(0))
+ } else if self.is_available(1, id) {
+ (1, self.abort_pending_fd_mailbox(1))
+ } else if self.is_available(2, id) {
+ (2, self.abort_pending_fd_mailbox(2))
+ } else {
+ // For now we bail when there is no lower priority slot available
+ // Can this lead to priority inversion?
+ return Err(nb::Error::WouldBlock);
+ }
+ } else {
+ // Read the Write Pointer
+ let idx = self.regs.txfqs().read().tfqpi();
+
+ (idx, None)
+ };
+
+ self.put_tx_frame(idx as usize, frame.header(), frame.data());
+
+ Ok(pending_frame)
+ }
+
+ #[inline]
+ fn reset_msg_ram(&mut self) {
+ self.msg_ram_mut().reset();
+ }
+
+ #[inline]
+ fn enter_init_mode(&mut self) {
+ self.regs.cccr().modify(|w| w.set_init(true));
+ while false == self.regs.cccr().read().init() {}
+ self.regs.cccr().modify(|w| w.set_cce(true));
+ }
+
+ /// Enables or disables loopback mode: Internally connects the TX and RX
+ /// signals together.
+ #[inline]
+ fn set_loopback_mode(&mut self, mode: LoopbackMode) {
+ let (test, mon, lbck) = match mode {
+ LoopbackMode::None => (false, false, false),
+ LoopbackMode::Internal => (true, true, true),
+ LoopbackMode::External => (true, false, true),
+ };
+
+ self.set_test_mode(test);
+ self.set_bus_monitoring_mode(mon);
+
+ self.regs.test().modify(|w| w.set_lbck(lbck));
+ }
+
+ /// Enables or disables silent mode: Disconnects the TX signal from the pin.
+ #[inline]
+ fn set_bus_monitoring_mode(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_mon(enabled));
+ }
+
+ #[inline]
+ fn set_restricted_operations(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_asm(enabled));
+ }
+
+ #[inline]
+ fn set_normal_operations(&mut self, _enabled: bool) {
+ self.set_loopback_mode(LoopbackMode::None);
+ }
+
+ #[inline]
+ fn set_test_mode(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_test(enabled));
+ }
+
+ #[inline]
+ fn set_power_down_mode(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_csr(enabled));
+ while self.regs.cccr().read().csa() != enabled {}
+ }
+
+ /// Moves out of PoweredDownMode and into ConfigMode
+ #[inline]
+ pub fn into_config_mode(mut self, _config: FdCanConfig) {
+ self.set_power_down_mode(false);
+ self.enter_init_mode();
+
+ self.reset_msg_ram();
+
+ // check the FDCAN core matches our expections
+ assert!(
+ self.regs.crel().read().rel() == 3,
+ "Expected FDCAN core major release 3"
+ );
+ assert!(
+ self.regs.endn().read().etv() == 0x87654321_u32,
+ "Error reading endianness test value from FDCAN core"
+ );
+
+ // Framework specific settings are set here
+
+ // set TxBuffer to Queue Mode
+ self.regs.txbc().write(|w| w.set_tfqm(true));
+
+ // set standard filters list size to 28
+ // set extended filters list size to 8
+ // REQUIRED: we use the memory map as if these settings are set
+ // instead of re-calculating them.
+ #[cfg(not(stm32h7))]
+ {
+ self.regs.rxgfc().modify(|w| {
+ w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX);
+ w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX);
+ });
+ }
+ #[cfg(stm32h7)]
+ {
+ self.regs
+ .sidfc()
+ .modify(|w| w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX));
+ self.regs
+ .xidfc()
+ .modify(|w| w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX));
+ }
+
+ /*
+ for fid in 0..crate::can::message_ram::STANDARD_FILTER_MAX {
+ self.set_standard_filter((fid as u8).into(), StandardFilter::disable());
+ }
+ for fid in 0..Ecrate::can::message_ram::XTENDED_FILTER_MAX {
+ self.set_extended_filter(fid.into(), ExtendedFilter::disable());
+ }
+ */
+ }
+
+ /// Disables the CAN interface and returns back the raw peripheral it was created from.
+ #[inline]
+ pub fn free(mut self) {
+ //self.disable_interrupts(Interrupts::all());
+
+ //TODO check this!
+ self.enter_init_mode();
+ self.set_power_down_mode(true);
+ //self.control.instance
+ }
+
+ /// Applies the settings of a new FdCanConfig See [`FdCanConfig`]
+ #[inline]
+ pub fn apply_config(&mut self, config: FdCanConfig) {
+ self.set_data_bit_timing(config.dbtr);
+ self.set_nominal_bit_timing(config.nbtr);
+ self.set_automatic_retransmit(config.automatic_retransmit);
+ self.set_transmit_pause(config.transmit_pause);
+ self.set_frame_transmit(config.frame_transmit);
+ //self.set_interrupt_line_config(config.interrupt_line_config);
+ self.set_non_iso_mode(config.non_iso_mode);
+ self.set_edge_filtering(config.edge_filtering);
+ self.set_protocol_exception_handling(config.protocol_exception_handling);
+ self.set_global_filter(config.global_filter);
+ }
+
+ #[inline]
+ fn leave_init_mode(&mut self, config: FdCanConfig) {
+ self.apply_config(config);
+
+ self.regs.cccr().modify(|w| w.set_cce(false));
+ self.regs.cccr().modify(|w| w.set_init(false));
+ while self.regs.cccr().read().init() == true {}
+ }
+
+ /// Moves out of ConfigMode and into InternalLoopbackMode
+ #[inline]
+ pub fn into_internal_loopback(mut self, config: FdCanConfig) {
+ self.set_loopback_mode(LoopbackMode::Internal);
+ self.leave_init_mode(config);
+ }
+
+ /// Moves out of ConfigMode and into ExternalLoopbackMode
+ #[inline]
+ pub fn into_external_loopback(mut self, config: FdCanConfig) {
+ self.set_loopback_mode(LoopbackMode::External);
+ self.leave_init_mode(config);
+ }
+
+ /// Moves out of ConfigMode and into RestrictedOperationMode
+ #[inline]
+ pub fn into_restricted(mut self, config: FdCanConfig) {
+ self.set_restricted_operations(true);
+ self.leave_init_mode(config);
+ }
+
+ /// Moves out of ConfigMode and into NormalOperationMode
+ #[inline]
+ pub fn into_normal(mut self, config: FdCanConfig) {
+ self.set_normal_operations(true);
+ self.leave_init_mode(config);
+ }
+
+ /// Moves out of ConfigMode and into BusMonitoringMode
+ #[inline]
+ pub fn into_bus_monitoring(mut self, config: FdCanConfig) {
+ self.set_bus_monitoring_mode(true);
+ self.leave_init_mode(config);
+ }
+
+ /// Moves out of ConfigMode and into Testmode
+ #[inline]
+ pub fn into_test_mode(mut self, config: FdCanConfig) {
+ self.set_test_mode(true);
+ self.leave_init_mode(config);
+ }
+
+ /// Moves out of ConfigMode and into PoweredDownmode
+ #[inline]
+ pub fn into_powered_down(mut self, config: FdCanConfig) {
+ self.set_power_down_mode(true);
+ self.leave_init_mode(config);
+ }
+
+ /// Configures the bit timings.
+ ///
+ /// You can use <http://www.bittiming.can-wiki.info/> to calculate the `btr` parameter. Enter
+ /// parameters as follows:
+ ///
+ /// - *Clock Rate*: The input clock speed to the CAN peripheral (*not* the CPU clock speed).
+ /// This is the clock rate of the peripheral bus the CAN peripheral is attached to (eg. APB1).
+ /// - *Sample Point*: Should normally be left at the default value of 87.5%.
+ /// - *SJW*: Should normally be left at the default value of 1.
+ ///
+ /// Then copy the `CAN_BUS_TIME` register value from the table and pass it as the `btr`
+ /// parameter to this method.
+ #[inline]
+ pub fn set_nominal_bit_timing(&mut self, btr: NominalBitTiming) {
+ //self.control.config.nbtr = btr;
+
+ self.regs.nbtp().write(|w| {
+ w.set_nbrp(btr.nbrp() - 1);
+ w.set_ntseg1(btr.ntseg1() - 1);
+ w.set_ntseg2(btr.ntseg2() - 1);
+ w.set_nsjw(btr.nsjw() - 1);
+ });
+ }
+
+ /// Configures the data bit timings for the FdCan Variable Bitrates.
+ /// This is not used when frame_transmit is set to anything other than AllowFdCanAndBRS.
+ #[inline]
+ pub fn set_data_bit_timing(&mut self, btr: DataBitTiming) {
+ //self.control.config.dbtr = btr;
+
+ self.regs.dbtp().write(|w| {
+ w.set_dbrp(btr.dbrp() - 1);
+ w.set_dtseg1(btr.dtseg1() - 1);
+ w.set_dtseg2(btr.dtseg2() - 1);
+ w.set_dsjw(btr.dsjw() - 1);
+ });
+ }
+
+ /// Enables or disables automatic retransmission of messages
+ ///
+ /// If this is enabled, the CAN peripheral will automatically try to retransmit each frame
+ /// util it can be sent. Otherwise, it will try only once to send each frame.
+ ///
+ /// Automatic retransmission is enabled by default.
+ #[inline]
+ pub fn set_automatic_retransmit(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_dar(!enabled));
+ //self.control.config.automatic_retransmit = enabled;
+ }
+
+ /// Configures the transmit pause feature. See
+ /// [`FdCanConfig::set_transmit_pause`]
+ #[inline]
+ pub fn set_transmit_pause(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_txp(!enabled));
+ //self.control.config.transmit_pause = enabled;
+ }
+
+ /// Configures non-iso mode. See [`FdCanConfig::set_non_iso_mode`]
+ #[inline]
+ pub fn set_non_iso_mode(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_niso(enabled));
+ //self.control.config.non_iso_mode = enabled;
+ }
+
+ /// Configures edge filtering. See [`FdCanConfig::set_edge_filtering`]
+ #[inline]
+ pub fn set_edge_filtering(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_efbi(enabled));
+ //self.control.config.edge_filtering = enabled;
+ }
+
+ /// Configures frame transmission mode. See
+ /// [`FdCanConfig::set_frame_transmit`]
+ #[inline]
+ pub fn set_frame_transmit(&mut self, fts: FrameTransmissionConfig) {
+ let (fdoe, brse) = match fts {
+ FrameTransmissionConfig::ClassicCanOnly => (false, false),
+ FrameTransmissionConfig::AllowFdCan => (true, false),
+ FrameTransmissionConfig::AllowFdCanAndBRS => (true, true),
+ };
+
+ self.regs.cccr().modify(|w| {
+ w.set_fdoe(fdoe);
+ #[cfg(stm32h7)]
+ w.set_bse(brse);
+ #[cfg(not(stm32h7))]
+ w.set_brse(brse);
+ });
+
+ //self.control.config.frame_transmit = fts;
+ }
+
+ /// Sets the protocol exception handling on/off
+ #[inline]
+ pub fn set_protocol_exception_handling(&mut self, enabled: bool) {
+ self.regs.cccr().modify(|w| w.set_pxhd(!enabled));
+
+ //self.control.config.protocol_exception_handling = enabled;
+ }
+
+ /// Configures and resets the timestamp counter
+ #[inline]
+ pub fn set_timestamp_counter_source(&mut self, select: TimestampSource) {
+ #[cfg(stm32h7)]
+ let (tcp, tss) = match select {
+ TimestampSource::None => (0, 0),
+ TimestampSource::Prescaler(p) => (p as u8, 1),
+ TimestampSource::FromTIM3 => (0, 2),
+ };
+
+ #[cfg(not(stm32h7))]
+ let (tcp, tss) = match select {
+ TimestampSource::None => (0, stm32_metapac::can::vals::Tss::ZERO),
+ TimestampSource::Prescaler(p) => (p as u8, stm32_metapac::can::vals::Tss::INCREMENT),
+ TimestampSource::FromTIM3 => (0, stm32_metapac::can::vals::Tss::EXTERNAL),
+ };
+
+ self.regs.tscc().write(|w| {
+ w.set_tcp(tcp);
+ w.set_tss(tss);
+ });
+
+ //self.control.config.timestamp_source = select;
+ }
+
+ #[cfg(not(stm32h7))]
+ /// Configures the global filter settings
+ #[inline]
+ pub fn set_global_filter(&mut self, filter: GlobalFilter) {
+ let anfs = match filter.handle_standard_frames {
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo0 => stm32_metapac::can::vals::Anfs::ACCEPT_FIFO_0,
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo1 => stm32_metapac::can::vals::Anfs::ACCEPT_FIFO_1,
+ crate::can::fd::config::NonMatchingFilter::Reject => stm32_metapac::can::vals::Anfs::REJECT,
+ };
+ let anfe = match filter.handle_extended_frames {
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo0 => stm32_metapac::can::vals::Anfe::ACCEPT_FIFO_0,
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo1 => stm32_metapac::can::vals::Anfe::ACCEPT_FIFO_1,
+ crate::can::fd::config::NonMatchingFilter::Reject => stm32_metapac::can::vals::Anfe::REJECT,
+ };
+
+ self.regs.rxgfc().modify(|w| {
+ w.set_anfs(anfs);
+ w.set_anfe(anfe);
+ w.set_rrfs(filter.reject_remote_standard_frames);
+ w.set_rrfe(filter.reject_remote_extended_frames);
+ });
+ }
+
+ #[cfg(stm32h7)]
+ /// Configures the global filter settings
+ #[inline]
+ pub fn set_global_filter(&mut self, filter: GlobalFilter) {
+ let anfs = match filter.handle_standard_frames {
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo0 => 0,
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo1 => 1,
+ crate::can::fd::config::NonMatchingFilter::Reject => 2,
+ };
+
+ let anfe = match filter.handle_extended_frames {
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo0 => 0,
+ crate::can::fd::config::NonMatchingFilter::IntoRxFifo1 => 1,
+ crate::can::fd::config::NonMatchingFilter::Reject => 2,
+ };
+
+ self.regs.gfc().modify(|w| {
+ w.set_anfs(anfs);
+ w.set_anfe(anfe);
+ w.set_rrfs(filter.reject_remote_standard_frames);
+ w.set_rrfe(filter.reject_remote_extended_frames);
+ });
+ }
+}
+
+fn make_id(id: u32, extended: bool) -> embedded_can::Id {
+ if extended {
+ embedded_can::Id::from(unsafe { embedded_can::ExtendedId::new_unchecked(id & 0x1FFFFFFF) })
+ } else {
+ embedded_can::Id::from(unsafe { embedded_can::StandardId::new_unchecked((id & 0x000007FF) as u16) })
+ }
+}
+
+fn put_tx_header(mailbox: &mut TxBufferElement, header: &Header) {
+ let (id, id_type) = match header.id() {
+ embedded_can::Id::Standard(id) => (id.as_raw() as u32, IdType::StandardId),
+ embedded_can::Id::Extended(id) => (id.as_raw() as u32, IdType::ExtendedId),
+ };
+
+ // Use FDCAN only for DLC > 8. FDCAN users can revise this if required.
+ let frame_format = if header.len() > 8 || header.fdcan() {
+ FrameFormat::Fdcan
+ } else {
+ FrameFormat::Standard
+ };
+ let brs = header.len() > 8 || header.bit_rate_switching();
+
+ mailbox.header.write(|w| {
+ unsafe { w.id().bits(id) }
+ .rtr()
+ .bit(header.len() == 0 && header.rtr())
+ .xtd()
+ .set_id_type(id_type)
+ .set_len(DataLength::new(header.len(), frame_format))
+ .set_event(Event::NoEvent)
+ .fdf()
+ .set_format(frame_format)
+ .brs()
+ .bit(brs)
+ //esi.set_error_indicator(//TODO//)
+ });
+}
+
+fn put_tx_data(mailbox: &mut TxBufferElement, buffer: &[u8]) {
+ let mut lbuffer = [0_u32; 16];
+ let len = buffer.len();
+ let data = unsafe { slice::from_raw_parts_mut(lbuffer.as_mut_ptr() as *mut u8, len) };
+ data[..len].copy_from_slice(&buffer[..len]);
+ let data_len = ((len) + 3) / 4;
+ for (register, byte) in mailbox.data.iter_mut().zip(lbuffer[..data_len].iter()) {
+ unsafe { register.write(*byte) };
+ }
+}
+
+fn data_from_fifo(buffer: &mut [u8], mailbox: &RxFifoElement, len: usize) {
+ for (i, register) in mailbox.data.iter().enumerate() {
+ let register_value = register.read();
+ let register_bytes = unsafe { slice::from_raw_parts(®ister_value as *const u32 as *const u8, 4) };
+ let num_bytes = (len) - i * 4;
+ if num_bytes <= 4 {
+ buffer[i * 4..i * 4 + num_bytes].copy_from_slice(®ister_bytes[..num_bytes]);
+ break;
+ }
+ buffer[i * 4..(i + 1) * 4].copy_from_slice(register_bytes);
+ }
+}
+
+fn data_from_tx_buffer(buffer: &mut [u8], mailbox: &TxBufferElement, len: usize) {
+ for (i, register) in mailbox.data.iter().enumerate() {
+ let register_value = register.read();
+ let register_bytes = unsafe { slice::from_raw_parts(®ister_value as *const u32 as *const u8, 4) };
+ let num_bytes = (len) - i * 4;
+ if num_bytes <= 4 {
+ buffer[i * 4..i * 4 + num_bytes].copy_from_slice(®ister_bytes[..num_bytes]);
+ break;
+ }
+ buffer[i * 4..(i + 1) * 4].copy_from_slice(register_bytes);
+ }
+}
+
+impl From<&RxFifoElement> for ClassicFrame {
+ fn from(mailbox: &RxFifoElement) -> Self {
+ let header_reg = mailbox.header.read();
+
+ let id = make_id(header_reg.id().bits(), header_reg.xtd().bits());
+ let dlc = header_reg.to_data_length().len();
+ let len = dlc as usize;
+
+ let mut buffer: [u8; 64] = [0; 64];
+ data_from_fifo(&mut buffer, mailbox, len);
+ let data = ClassicData::new(&buffer[0..len]);
+ let header = Header::new(id, dlc, header_reg.rtr().bits());
+ ClassicFrame::new(header, data.unwrap())
+ }
+}
+
+fn extract_frame(mailbox: &RxFifoElement, buffer: &mut [u8]) -> Option<(Header, u16)> {
+ let header_reg = mailbox.header.read();
+
+ let id = make_id(header_reg.id().bits(), header_reg.xtd().bits());
+ let dlc = header_reg.to_data_length().len();
+ let len = dlc as usize;
+ let timestamp = header_reg.txts().bits;
+ if len > buffer.len() {
+ return None;
+ }
+ data_from_fifo(buffer, mailbox, len);
+ let header = if header_reg.fdf().bits {
+ Header::new_fd(id, dlc, header_reg.rtr().bits(), header_reg.brs().bits())
+ } else {
+ Header::new(id, dlc, header_reg.rtr().bits())
+ };
+ Some((header, timestamp))
+}
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index faf4af73f..b94e42707 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -1,16 +1,15 @@
+#[allow(unused_variables)]
use core::future::poll_fn;
use core::marker::PhantomData;
-use core::ops::{Deref, DerefMut};
use core::task::Poll;
+pub mod fd;
use cfg_if::cfg_if;
use embassy_hal_internal::{into_ref, PeripheralRef};
-pub use fdcan::frame::{FrameFormat, RxFrameInfo, TxFrameHeader};
-pub use fdcan::id::{ExtendedId, Id, StandardId};
-use fdcan::message_ram::RegisterBlock;
-use fdcan::{self, LastErrorCode};
-pub use fdcan::{config, filter};
+use fd::config::*;
+use fd::filter::*;
+use crate::can::fd::peripheral::Registers;
use crate::gpio::sealed::AFType;
use crate::interrupt::typelevel::Interrupt;
use crate::rcc::RccPeripheral;
@@ -20,127 +19,14 @@ pub mod enums;
use enums::*;
pub mod util;
-/// CAN Frame returned by read
-pub struct RxFrame {
- /// CAN Header info: frame ID, data length and other meta
- pub header: RxFrameInfo,
- /// CAN(0-8 bytes) or FDCAN(0-64 bytes) Frame data
- pub data: Data,
- /// Reception time.
- #[cfg(feature = "time")]
- pub timestamp: embassy_time::Instant,
-}
+pub mod frame;
+use frame::*;
-/// CAN frame used for write
-pub struct TxFrame {
- /// CAN Header info: frame ID, data length and other meta
- pub header: TxFrameHeader,
- /// CAN(0-8 bytes) or FDCAN(0-64 bytes) Frame data
- pub data: Data,
-}
+#[cfg(feature = "time")]
+type Timestamp = embassy_time::Instant;
-impl TxFrame {
- /// Create new TX frame from header and data
- pub fn new(header: TxFrameHeader, data: &[u8]) -> Option<Self> {
- if data.len() < header.len as usize {
- return None;
- }
-
- let Some(data) = Data::new(data) else { return None };
-
- Some(TxFrame { header, data })
- }
-
- fn from_preserved(header: TxFrameHeader, data32: &[u32]) -> Option<Self> {
- let mut data = [0u8; 64];
-
- for i in 0..data32.len() {
- data[4 * i..][..4].copy_from_slice(&data32[i].to_le_bytes());
- }
-
- let Some(data) = Data::new(&data) else { return None };
-
- Some(TxFrame { header, data })
- }
-
- /// Access frame data. Slice length will match header.
- pub fn data(&self) -> &[u8] {
- &self.data.bytes[..(self.header.len as usize)]
- }
-}
-
-impl RxFrame {
- pub(crate) fn new(
- header: RxFrameInfo,
- data: &[u8],
- #[cfg(feature = "time")] timestamp: embassy_time::Instant,
- ) -> Self {
- let data = Data::new(&data).unwrap_or_else(|| Data::empty());
-
- RxFrame {
- header,
- data,
- #[cfg(feature = "time")]
- timestamp,
- }
- }
-
- /// Access frame data. Slice length will match header.
- pub fn data(&self) -> &[u8] {
- &self.data.bytes[..(self.header.len as usize)]
- }
-}
-
-/// Payload of a (FD)CAN data frame.
-///
-/// Contains 0 to 64 Bytes of data.
-#[derive(Debug, Copy, Clone)]
-pub struct Data {
- pub(crate) bytes: [u8; 64],
-}
-
-impl Data {
- /// Creates a data payload from a raw byte slice.
- ///
- /// Returns `None` if `data` is more than 64 bytes (which is the maximum) or
- /// cannot be represented with an FDCAN DLC.
- pub fn new(data: &[u8]) -> Option<Self> {
- if !Data::is_valid_len(data.len()) {
- return None;
- }
-
- let mut bytes = [0; 64];
- bytes[..data.len()].copy_from_slice(data);
-
- Some(Self { bytes })
- }
-
- /// Raw read access to data.
- pub fn raw(&self) -> &[u8] {
- &self.bytes
- }
-
- /// Checks if the length can be encoded in FDCAN DLC field.
- pub const fn is_valid_len(len: usize) -> bool {
- match len {
- 0..=8 => true,
- 12 => true,
- 16 => true,
- 20 => true,
- 24 => true,
- 32 => true,
- 48 => true,
- 64 => true,
- _ => false,
- }
- }
-
- /// Creates an empty data payload containing 0 bytes.
- #[inline]
- pub const fn empty() -> Self {
- Self { bytes: [0; 64] }
- }
-}
+#[cfg(not(feature = "time"))]
+type Timestamp = u16;
/// Interrupt handler channel 0.
pub struct IT0InterruptHandler<T: Instance> {
@@ -172,7 +58,9 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
}
if ir.rfn(0) {
- regs.ir().write(|w| w.set_rfn(0, true));
+ let fifonr = 0 as usize;
+ regs.ir().write(|w| w.set_rfn(fifonr, true));
+
T::state().rx_waker.wake();
}
@@ -192,44 +80,82 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT1Interrupt> for IT1Interrup
unsafe fn on_interrupt() {}
}
-impl BusError {
- fn try_from(lec: LastErrorCode) -> Option<BusError> {
- match lec {
- LastErrorCode::AckError => Some(BusError::Acknowledge),
- // `0` data bit encodes a dominant state. `1` data bit is recessive.
- // Bit0Error: During transmit, the node wanted to send a 0 but monitored a 1
- LastErrorCode::Bit0Error => Some(BusError::BitRecessive),
- LastErrorCode::Bit1Error => Some(BusError::BitDominant),
- LastErrorCode::CRCError => Some(BusError::Crc),
- LastErrorCode::FormError => Some(BusError::Form),
- LastErrorCode::StuffError => Some(BusError::Stuff),
- _ => None,
- }
- }
-}
+/// Allows for Transmit Operations
+pub trait Transmit {}
+/// Allows for Receive Operations
+pub trait Receive {}
+
+/// Allows for the FdCan Instance to be released or to enter ConfigMode
+pub struct PoweredDownMode;
+/// Allows for the configuration for the Instance
+pub struct ConfigMode;
+/// This mode can be used for a “Hot Selftest”, meaning the FDCAN can be tested without
+/// affecting a running CAN system connected to the FDCAN_TX and FDCAN_RX pins. In this
+/// mode, FDCAN_RX pin is disconnected from the FDCAN and FDCAN_TX pin is held
+/// recessive.
+pub struct InternalLoopbackMode;
+impl Transmit for InternalLoopbackMode {}
+impl Receive for InternalLoopbackMode {}
+/// This mode is provided for hardware self-test. To be independent from external stimulation,
+/// the FDCAN ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a
+/// data / remote frame) in Loop Back mode. In this mode the FDCAN performs an internal
+/// feedback from its transmit output to its receive input. The actual value of the FDCAN_RX
+/// input pin is disregarded by the FDCAN. The transmitted messages can be monitored at the
+/// FDCAN_TX transmit pin.
+pub struct ExternalLoopbackMode;
+impl Transmit for ExternalLoopbackMode {}
+impl Receive for ExternalLoopbackMode {}
+/// The normal use of the FdCan instance after configurations
+pub struct NormalOperationMode;
+impl Transmit for NormalOperationMode {}
+impl Receive for NormalOperationMode {}
+/// In Restricted operation mode the node is able to receive data and remote frames and to give
+/// acknowledge to valid frames, but it does not send data frames, remote frames, active error
+/// frames, or overload frames. In case of an error condition or overload condition, it does not
+/// send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize
+/// itself to the CAN communication. The error counters for transmit and receive are frozen while
+/// error logging (can_errors) is active. TODO: automatically enter in this mode?
+pub struct RestrictedOperationMode;
+impl Receive for RestrictedOperationMode {}
+/// In Bus monitoring mode (for more details refer to ISO11898-1, 10.12 Bus monitoring),
+/// the FDCAN is able to receive valid data frames and valid remote frames, but cannot start a
+/// transmission. In this mode, it sends only recessive bits on the CAN bus. If the FDCAN is
+/// required to send a dominant bit (ACK bit, overload flag, active error flag), the bit is
+/// rerouted internally so that the FDCAN can monitor it, even if the CAN bus remains in recessive
+/// state. In Bus monitoring mode the TXBRP register is held in reset state. The Bus monitoring
+/// mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
+/// of dominant bits.
+pub struct BusMonitoringMode;
+impl Receive for BusMonitoringMode {}
+/// Test mode must be used for production tests or self test only. The software control for
+/// FDCAN_TX pin interferes with all CAN protocol functions. It is not recommended to use test
+/// modes for application.
+pub struct TestMode;
/// Operating modes trait
pub trait FdcanOperatingMode {}
-impl FdcanOperatingMode for fdcan::PoweredDownMode {}
-impl FdcanOperatingMode for fdcan::ConfigMode {}
-impl FdcanOperatingMode for fdcan::InternalLoopbackMode {}
-impl FdcanOperatingMode for fdcan::ExternalLoopbackMode {}
-impl FdcanOperatingMode for fdcan::NormalOperationMode {}
-impl FdcanOperatingMode for fdcan::RestrictedOperationMode {}
-impl FdcanOperatingMode for fdcan::BusMonitoringMode {}
-impl FdcanOperatingMode for fdcan::TestMode {}
+impl FdcanOperatingMode for PoweredDownMode {}
+impl FdcanOperatingMode for ConfigMode {}
+impl FdcanOperatingMode for InternalLoopbackMode {}
+impl FdcanOperatingMode for ExternalLoopbackMode {}
+impl FdcanOperatingMode for NormalOperationMode {}
+impl FdcanOperatingMode for RestrictedOperationMode {}
+impl FdcanOperatingMode for BusMonitoringMode {}
+impl FdcanOperatingMode for TestMode {}
/// FDCAN Instance
pub struct Fdcan<'d, T: Instance, M: FdcanOperatingMode> {
+ config: crate::can::fd::config::FdCanConfig,
/// Reference to internals.
- pub can: fdcan::FdCan<FdcanInstance<'d, T>, M>,
+ instance: FdcanInstance<'d, T>,
+ _mode: PhantomData<M>,
ns_per_timer_tick: u64, // For FDCAN internal timer
}
-fn calc_ns_per_timer_tick<T: Instance>(mode: config::FrameTransmissionConfig) -> u64 {
+fn calc_ns_per_timer_tick<T: Instance>(mode: crate::can::fd::config::FrameTransmissionConfig) -> u64 {
match mode {
// Use timestamp from Rx FIFO to adjust timestamp reported to user
- config::FrameTransmissionConfig::ClassicCanOnly => {
+ crate::can::fd::config::FrameTransmissionConfig::ClassicCanOnly => {
let freq = T::frequency();
let prescale: u64 =
({ T::regs().nbtp().read().nbrp() } + 1) as u64 * ({ T::regs().tscc().read().tcp() } + 1) as u64;
@@ -242,17 +168,22 @@ fn calc_ns_per_timer_tick<T: Instance>(mode: config::FrameTransmissionConfig) ->
}
#[cfg(feature = "time")]
-fn calc_timestamp<T: Instance>(ns_per_timer_tick: u64, ts_val: u16) -> embassy_time::Instant {
+fn calc_timestamp<T: Instance>(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
let now_embassy = embassy_time::Instant::now();
if ns_per_timer_tick == 0 {
return now_embassy;
}
- let now_can = { T::regs().tscv().read().tsc() };
- let delta = now_can.overflowing_sub(ts_val).0 as u64;
+ let cantime = { T::regs().tscv().read().tsc() };
+ let delta = cantime.overflowing_sub(ts_val).0 as u64;
let ns = ns_per_timer_tick * delta as u64;
now_embassy - embassy_time::Duration::from_nanos(ns)
}
+#[cfg(not(feature = "time"))]
+fn calc_timestamp<T: Instance>(_ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
+ ts_val
+}
+
fn curr_error<T: Instance>() -> Option<BusError> {
let err = { T::regs().psr().read() };
if err.bo() {
@@ -269,14 +200,14 @@ fn curr_error<T: Instance>() -> Option<BusError> {
let lec = err.lec().to_bits();
}
}
- if let Ok(err) = LastErrorCode::try_from(lec) {
- return BusError::try_from(err);
+ if let Ok(err) = BusError::try_from(lec) {
+ return Some(err);
}
}
None
}
-impl<'d, T: Instance> Fdcan<'d, T, fdcan::ConfigMode> {
+impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
/// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
/// You must call [Fdcan::enable_non_blocking] to use the peripheral.
pub fn new(
@@ -286,7 +217,7 @@ impl<'d, T: Instance> Fdcan<'d, T, fdcan::ConfigMode> {
_irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
+ interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
+ 'd,
- ) -> Fdcan<'d, T, fdcan::ConfigMode> {
+ ) -> Fdcan<'d, T, ConfigMode> {
into_ref!(peri, rx, tx);
rx.set_as_af(rx.af_num(), AFType::Input);
@@ -294,11 +225,12 @@ impl<'d, T: Instance> Fdcan<'d, T, fdcan::ConfigMode> {
T::enable_and_reset();
+ let mut config = crate::can::fd::config::FdCanConfig::default();
+ T::registers().into_config_mode(config);
+
rx.set_as_af(rx.af_num(), AFType::Input);
tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
- let mut can = fdcan::FdCan::new(FdcanInstance(peri)).into_config_mode();
-
T::configure_msg_ram();
unsafe {
// Enable timestamping
@@ -308,6 +240,7 @@ impl<'d, T: Instance> Fdcan<'d, T, fdcan::ConfigMode> {
.write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
#[cfg(stm32h7)]
T::regs().tscc().write(|w| w.set_tss(0x01));
+ config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
T::IT0Interrupt::unpend(); // Not unsafe
T::IT0Interrupt::enable();
@@ -320,38 +253,104 @@ impl<'d, T: Instance> Fdcan<'d, T, fdcan::ConfigMode> {
T::regs().txbtie().write(|w| w.0 = 0xffff_ffff);
}
- can.enable_interrupt(fdcan::interrupt::Interrupt::RxFifo0NewMsg);
- can.enable_interrupt(fdcan::interrupt::Interrupt::RxFifo1NewMsg);
- can.enable_interrupt(fdcan::interrupt::Interrupt::TxComplete);
- can.enable_interrupt_line(fdcan::interrupt::InterruptLine::_0, true);
- can.enable_interrupt_line(fdcan::interrupt::InterruptLine::_1, true);
+ T::regs().ie().modify(|w| {
+ w.set_rfne(0, true); // Rx Fifo 0 New Msg
+ w.set_rfne(1, true); // Rx Fifo 1 New Msg
+ w.set_tce(true); // Tx Complete
+ });
+ T::regs().ile().modify(|w| {
+ w.set_eint0(true); // Interrupt Line 0
+ w.set_eint1(true); // Interrupt Line 1
+ });
- let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(can.get_config().frame_transmit);
- Self { can, ns_per_timer_tick }
+ let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(config.frame_transmit);
+ Self {
+ config,
+ instance: FdcanInstance(peri),
+ _mode: PhantomData::<ConfigMode>,
+ ns_per_timer_tick,
+ }
+ }
+
+ /// Get configuration
+ pub fn config(&self) -> crate::can::fd::config::FdCanConfig {
+ return self.config;
+ }
+
+ /// Set configuration
+ pub fn set_config(&mut self, config: crate::can::fd::config::FdCanConfig) {
+ self.config = config;
}
/// Configures the bit timings calculated from supplied bitrate.
pub fn set_bitrate(&mut self, bitrate: u32) {
let bit_timing = util::calc_can_timings(T::frequency(), bitrate).unwrap();
- self.can.set_nominal_bit_timing(config::NominalBitTiming {
+
+ let nbtr = crate::can::fd::config::NominalBitTiming {
sync_jump_width: bit_timing.sync_jump_width,
prescaler: bit_timing.prescaler,
seg1: bit_timing.seg1,
seg2: bit_timing.seg2,
- });
+ };
+ self.config = self.config.set_nominal_bit_timing(nbtr);
+ }
+
+ /// Configures the bit timings for VBR data calculated from supplied bitrate.
+ pub fn set_fd_data_bitrate(&mut self, bitrate: u32, transceiver_delay_compensation: bool) {
+ let bit_timing = util::calc_can_timings(T::frequency(), bitrate).unwrap();
+ // Note, used existing calcluation for normal(non-VBR) bitrate, appears to work for 250k/1M
+ let nbtr = crate::can::fd::config::DataBitTiming {
+ transceiver_delay_compensation,
+ sync_jump_width: bit_timing.sync_jump_width,
+ prescaler: bit_timing.prescaler,
+ seg1: bit_timing.seg1,
+ seg2: bit_timing.seg2,
+ };
+ self.config.frame_transmit = FrameTransmissionConfig::AllowFdCanAndBRS;
+ self.config = self.config.set_data_bit_timing(nbtr);
+ }
+
+ /// Set an Standard Address CAN filter into slot 'id'
+ #[inline]
+ pub fn set_standard_filter(&mut self, slot: StandardFilterSlot, filter: StandardFilter) {
+ T::registers().msg_ram_mut().filters.flssa[slot as usize].activate(filter);
+ }
+
+ /// Set an array of Standard Address CAN filters and overwrite the current set
+ pub fn set_standard_filters(&mut self, filters: &[StandardFilter; STANDARD_FILTER_MAX as usize]) {
+ for (i, f) in filters.iter().enumerate() {
+ T::registers().msg_ram_mut().filters.flssa[i].activate(*f);
+ }
+ }
+
+ /// Set an Extended Address CAN filter into slot 'id'
+ #[inline]
+ pub fn set_extended_filter(&mut self, slot: ExtendedFilterSlot, filter: ExtendedFilter) {
+ T::registers().msg_ram_mut().filters.flesa[slot as usize].activate(filter);
+ }
+
+ /// Set an array of Extended Address CAN filters and overwrite the current set
+ pub fn set_extended_filters(&mut self, filters: &[ExtendedFilter; EXTENDED_FILTER_MAX as usize]) {
+ for (i, f) in filters.iter().enumerate() {
+ T::registers().msg_ram_mut().filters.flesa[i].activate(*f);
+ }
}
}
macro_rules! impl_transition {
($from_mode:ident, $to_mode:ident, $name:ident, $func: ident) => {
- impl<'d, T: Instance> Fdcan<'d, T, fdcan::$from_mode> {
+ impl<'d, T: Instance> Fdcan<'d, T, $from_mode> {
/// Transition from $from_mode:ident mode to $to_mode:ident mode
- pub fn $name(self) -> Fdcan<'d, T, fdcan::$to_mode> {
- let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(self.can.get_config().frame_transmit);
- Fdcan {
- can: self.can.$func(),
+ pub fn $name(self) -> Fdcan<'d, T, $to_mode> {
+ let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(self.config.frame_transmit);
+ T::registers().$func(self.config);
+ let ret = Fdcan {
+ config: self.config,
+ instance: self.instance,
+ _mode: PhantomData::<$to_mode>,
ns_per_timer_tick,
- }
+ };
+ ret
}
}
};
@@ -376,38 +375,16 @@ impl_transition!(
impl<'d, T: Instance, M: FdcanOperatingMode> Fdcan<'d, T, M>
where
- M: fdcan::Transmit,
- M: fdcan::Receive,
+ M: Transmit,
+ M: Receive,
{
- /// Queues the message to be sent but exerts backpressure. If a lower-priority
- /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
- /// can be replaced, this call asynchronously waits for a frame to be successfully
- /// transmitted, then tries again.
- pub async fn write(&mut self, frame: &TxFrame) -> Option<TxFrame> {
- poll_fn(|cx| {
- T::state().tx_waker.register(cx.waker());
- if let Ok(dropped) = self
- .can
- .transmit_preserve(frame.header, &frame.data.bytes, &mut |_, hdr, data32| {
- TxFrame::from_preserved(hdr, data32)
- })
- {
- return Poll::Ready(dropped.flatten());
- }
-
- // Couldn't replace any lower priority frames. Need to wait for some mailboxes
- // to clear.
- Poll::Pending
- })
- .await
- }
-
/// Flush one of the TX mailboxes.
- pub async fn flush(&self, mb: fdcan::Mailbox) {
+ pub async fn flush(&self, idx: usize) {
poll_fn(|cx| {
T::state().tx_waker.register(cx.waker());
-
- let idx: u8 = mb.into();
+ if idx > 3 {
+ panic!("Bad mailbox");
+ }
let idx = 1 << idx;
if !T::regs().txbrp().read().trp(idx) {
return Poll::Ready(());
@@ -418,37 +395,77 @@ where
.await;
}
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write(&mut self, frame: &ClassicFrame) -> Option<ClassicFrame> {
+ poll_fn(|cx| {
+ T::state().tx_waker.register(cx.waker());
+
+ if let Ok(dropped) = T::registers().write_classic(frame) {
+ return Poll::Ready(dropped);
+ }
+
+ // Couldn't replace any lower priority frames. Need to wait for some mailboxes
+ // to clear.
+ Poll::Pending
+ })
+ .await
+ }
+
/// Returns the next received message frame
- pub async fn read(&mut self) -> Result<RxFrame, BusError> {
+ pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
poll_fn(|cx| {
T::state().err_waker.register(cx.waker());
T::state().rx_waker.register(cx.waker());
- let mut buffer: [u8; 64] = [0; 64];
- if let Ok(rx) = self.can.receive0(&mut buffer) {
- // rx: fdcan::ReceiveOverrun<RxFrameInfo>
- // TODO: report overrun?
- // for now we just drop it
+ if let Some((msg, ts)) = T::registers().read_classic(0) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some((msg, ts)) = T::registers().read_classic(1) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some(err) = curr_error::<T>() {
+ // TODO: this is probably wrong
+ return Poll::Ready(Err(err));
+ }
+ Poll::Pending
+ })
+ .await
+ }
- let frame: RxFrame = RxFrame::new(
- rx.unwrap(),
- &buffer,
- #[cfg(feature = "time")]
- calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
- );
- return Poll::Ready(Ok(frame));
- } else if let Ok(rx) = self.can.receive1(&mut buffer) {
- // rx: fdcan::ReceiveOverrun<RxFrameInfo>
- // TODO: report overrun?
- // for now we just drop it
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
+ poll_fn(|cx| {
+ T::state().tx_waker.register(cx.waker());
- let frame: RxFrame = RxFrame::new(
- rx.unwrap(),
- &buffer,
- #[cfg(feature = "time")]
- calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
- );
- return Poll::Ready(Ok(frame));
+ if let Ok(dropped) = T::registers().write_fd(frame) {
+ return Poll::Ready(dropped);
+ }
+
+ // Couldn't replace any lower priority frames. Need to wait for some mailboxes
+ // to clear.
+ Poll::Pending
+ })
+ .await
+ }
+
+ /// Returns the next received message frame
+ pub async fn read_fd(&mut self) -> Result<(FdFrame, Timestamp), BusError> {
+ poll_fn(|cx| {
+ T::state().err_waker.register(cx.waker());
+ T::state().rx_waker.register(cx.waker());
+
+ if let Some((msg, ts)) = T::registers().read_fd(0) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some((msg, ts)) = T::registers().read_fd(1) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
} else if let Some(err) = curr_error::<T>() {
// TODO: this is probably wrong
return Poll::Ready(Err(err));
@@ -459,40 +476,67 @@ where
}
/// Split instance into separate Tx(write) and Rx(read) portions
- pub fn split<'c>(&'c mut self) -> (FdcanTx<'c, 'd, T, M>, FdcanRx<'c, 'd, T, M>) {
- let (mut _control, tx, rx0, rx1) = self.can.split_by_ref();
+ pub fn split(self) -> (FdcanTx<'d, T, M>, FdcanRx<'d, T, M>) {
(
- FdcanTx { _control, tx },
+ FdcanTx {
+ _instance: self.instance,
+ _mode: self._mode,
+ },
FdcanRx {
- rx0,
- rx1,
+ _instance1: PhantomData::<T>,
+ _instance2: T::regs(),
+ _mode: self._mode,
ns_per_timer_tick: self.ns_per_timer_tick,
},
)
}
}
-/// FDCAN Tx only Instance
-pub struct FdcanTx<'c, 'd, T: Instance, M: fdcan::Transmit> {
- _control: &'c mut fdcan::FdCanControl<FdcanInstance<'d, T>, M>,
- tx: &'c mut fdcan::Tx<FdcanInstance<'d, T>, M>,
+/// FDCAN Rx only Instance
+#[allow(dead_code)]
+pub struct FdcanRx<'d, T: Instance, M: Receive> {
+ _instance1: PhantomData<T>,
+ _instance2: &'d crate::pac::can::Fdcan,
+ _mode: PhantomData<M>,
+ ns_per_timer_tick: u64, // For FDCAN internal timer
}
-impl<'c, 'd, T: Instance, M: fdcan::Transmit> FdcanTx<'c, 'd, T, M> {
+/// FDCAN Tx only Instance
+pub struct FdcanTx<'d, T: Instance, M: Transmit> {
+ _instance: FdcanInstance<'d, T>, //(PeripheralRef<'a, T>);
+ _mode: PhantomData<M>,
+}
+
+impl<'c, 'd, T: Instance, M: Transmit> FdcanTx<'d, T, M> {
/// Queues the message to be sent but exerts backpressure. If a lower-priority
/// frame is dropped from the mailbox, it is returned. If no lower-priority frames
/// can be replaced, this call asynchronously waits for a frame to be successfully
/// transmitted, then tries again.
- pub async fn write(&mut self, frame: &TxFrame) -> Option<TxFrame> {
+ pub async fn write(&mut self, frame: &ClassicFrame) -> Option<ClassicFrame> {
poll_fn(|cx| {
T::state().tx_waker.register(cx.waker());
- if let Ok(dropped) = self
- .tx
- .transmit_preserve(frame.header, &frame.data.bytes, &mut |_, hdr, data32| {
- TxFrame::from_preserved(hdr, data32)
- })
- {
- return Poll::Ready(dropped.flatten());
+
+ if let Ok(dropped) = T::registers().write_classic(frame) {
+ return Poll::Ready(dropped);
+ }
+
+ // Couldn't replace any lower priority frames. Need to wait for some mailboxes
+ // to clear.
+ Poll::Pending
+ })
+ .await
+ }
+
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
+ poll_fn(|cx| {
+ T::state().tx_waker.register(cx.waker());
+
+ if let Ok(dropped) = T::registers().write_fd(frame) {
+ return Poll::Ready(dropped);
}
// Couldn't replace any lower priority frames. Need to wait for some mailboxes
@@ -503,65 +547,47 @@ impl<'c, 'd, T: Instance, M: fdcan::Transmit> FdcanTx<'c, 'd, T, M> {
}
}
-/// FDCAN Rx only Instance
-#[allow(dead_code)]
-pub struct FdcanRx<'c, 'd, T: Instance, M: fdcan::Receive> {
- rx0: &'c mut fdcan::Rx<FdcanInstance<'d, T>, M, fdcan::Fifo0>,
- rx1: &'c mut fdcan::Rx<FdcanInstance<'d, T>, M, fdcan::Fifo1>,
- ns_per_timer_tick: u64, // For FDCAN internal timer
-}
-
-impl<'c, 'd, T: Instance, M: fdcan::Receive> FdcanRx<'c, 'd, T, M> {
+impl<'c, 'd, T: Instance, M: Receive> FdcanRx<'d, T, M> {
/// Returns the next received message frame
- pub async fn read(&mut self) -> Result<RxFrame, BusError> {
+ pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
poll_fn(|cx| {
T::state().err_waker.register(cx.waker());
T::state().rx_waker.register(cx.waker());
- let mut buffer: [u8; 64] = [0; 64];
- if let Ok(rx) = self.rx0.receive(&mut buffer) {
- // rx: fdcan::ReceiveOverrun<RxFrameInfo>
- // TODO: report overrun?
- // for now we just drop it
- let frame: RxFrame = RxFrame::new(
- rx.unwrap(),
- &buffer,
- #[cfg(feature = "time")]
- calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
- );
- return Poll::Ready(Ok(frame));
- } else if let Ok(rx) = self.rx1.receive(&mut buffer) {
- // rx: fdcan::ReceiveOverrun<RxFrameInfo>
- // TODO: report overrun?
- // for now we just drop it
- let frame: RxFrame = RxFrame::new(
- rx.unwrap(),
- &buffer,
- #[cfg(feature = "time")]
- calc_timestamp::<T>(self.ns_per_timer_tick, rx.unwrap().time_stamp),
- );
- return Poll::Ready(Ok(frame));
+ if let Some((msg, ts)) = T::registers().read_classic(0) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some((msg, ts)) = T::registers().read_classic(1) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
} else if let Some(err) = curr_error::<T>() {
// TODO: this is probably wrong
return Poll::Ready(Err(err));
}
-
Poll::Pending
})
.await
}
-}
-impl<'d, T: Instance, M: FdcanOperatingMode> Deref for Fdcan<'d, T, M> {
- type Target = fdcan::FdCan<FdcanInstance<'d, T>, M>;
- fn deref(&self) -> &Self::Target {
- &self.can
- }
-}
+ /// Returns the next received message frame
+ pub async fn read_fd(&mut self) -> Result<(FdFrame, Timestamp), BusError> {
+ poll_fn(|cx| {
+ T::state().err_waker.register(cx.waker());
+ T::state().rx_waker.register(cx.waker());
-impl<'d, T: Instance, M: FdcanOperatingMode> DerefMut for Fdcan<'d, T, M> {
- fn deref_mut(&mut self) -> &mut Self::Target {
- &mut self.can
+ if let Some((msg, ts)) = T::registers().read_fd(0) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some((msg, ts)) = T::registers().read_fd(1) {
+ let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some(err) = curr_error::<T>() {
+ // TODO: this is probably wrong
+ return Poll::Ready(Err(err));
+ }
+ Poll::Pending
+ })
+ .await
}
}
@@ -585,11 +611,11 @@ pub(crate) mod sealed {
}
pub trait Instance {
- const REGISTERS: *mut fdcan::RegisterBlock;
- const MSG_RAM: *mut fdcan::message_ram::RegisterBlock;
const MSG_RAM_OFFSET: usize;
fn regs() -> &'static crate::pac::can::Fdcan;
+ fn registers() -> crate::can::fd::peripheral::Registers;
+ fn ram() -> &'static crate::pac::fdcanram::Fdcanram;
fn state() -> &'static State;
#[cfg(not(stm32h7))]
@@ -599,7 +625,8 @@ pub(crate) mod sealed {
fn configure_msg_ram() {
let r = Self::regs();
- use fdcan::message_ram::*;
+ use crate::can::fd::message_ram::*;
+ //use fdcan::message_ram::*;
let mut offset_words = Self::MSG_RAM_OFFSET as u16;
// 11-bit filter
@@ -677,28 +704,20 @@ pub trait Instance: sealed::Instance + RccPeripheral + InterruptableInstance + '
/// Fdcan Instance struct
pub struct FdcanInstance<'a, T>(PeripheralRef<'a, T>);
-unsafe impl<'d, T: Instance> fdcan::message_ram::Instance for FdcanInstance<'d, T> {
- const MSG_RAM: *mut RegisterBlock = T::MSG_RAM;
-}
-
-unsafe impl<'d, T: Instance> fdcan::Instance for FdcanInstance<'d, T>
-where
- FdcanInstance<'d, T>: fdcan::message_ram::Instance,
-{
- const REGISTERS: *mut fdcan::RegisterBlock = T::REGISTERS;
-}
-
macro_rules! impl_fdcan {
($inst:ident, $msg_ram_inst:ident, $msg_ram_offset:literal) => {
impl sealed::Instance for peripherals::$inst {
- const REGISTERS: *mut fdcan::RegisterBlock = crate::pac::$inst.as_ptr() as *mut _;
- const MSG_RAM: *mut fdcan::message_ram::RegisterBlock = crate::pac::$msg_ram_inst.as_ptr() as *mut _;
const MSG_RAM_OFFSET: usize = $msg_ram_offset;
fn regs() -> &'static crate::pac::can::Fdcan {
&crate::pac::$inst
}
-
+ fn registers() -> Registers {
+ Registers{regs: &crate::pac::$inst, msgram: &crate::pac::$msg_ram_inst}
+ }
+ fn ram() -> &'static crate::pac::fdcanram::Fdcanram {
+ &crate::pac::$msg_ram_inst
+ }
fn state() -> &'static sealed::State {
static STATE: sealed::State = sealed::State::new();
&STATE
diff --git a/embassy-stm32/src/can/frame.rs b/embassy-stm32/src/can/frame.rs
new file mode 100644
index 000000000..725a9b1ab
--- /dev/null
+++ b/embassy-stm32/src/can/frame.rs
@@ -0,0 +1,370 @@
+//! Definition for CAN Frames
+use bit_field::BitField;
+
+/// CAN Header, without meta data
+#[derive(Debug, Copy, Clone)]
+pub struct Header {
+ id: embedded_can::Id,
+ len: u8,
+ flags: u8,
+}
+
+impl Header {
+ const FLAG_RTR: usize = 0; // Remote
+ const FLAG_FDCAN: usize = 1; // FDCan vs Classic CAN
+ const FLAG_BRS: usize = 2; // Bit-rate switching, ignored for Classic CAN
+
+ /// Create new CAN Header
+ pub fn new(id: embedded_can::Id, len: u8, rtr: bool) -> Header {
+ let mut flags = 0u8;
+ flags.set_bit(Self::FLAG_RTR, rtr);
+ Header { id, len, flags }
+ }
+
+ /// Create new CAN FD Header
+ pub fn new_fd(id: embedded_can::Id, len: u8, rtr: bool, brs: bool) -> Header {
+ let mut flags = 0u8;
+ flags.set_bit(Self::FLAG_RTR, rtr);
+ flags.set_bit(Self::FLAG_FDCAN, true);
+ flags.set_bit(Self::FLAG_BRS, brs);
+ Header { id, len, flags }
+ }
+
+ /// Return ID
+ pub fn id(&self) -> &embedded_can::Id {
+ &self.id
+ }
+
+ /// Return length as u8
+ pub fn len(&self) -> u8 {
+ self.len
+ }
+
+ /// Is remote frame
+ pub fn rtr(&self) -> bool {
+ self.flags.get_bit(Self::FLAG_RTR)
+ }
+
+ /// Request/is FDCAN frame
+ pub fn fdcan(&self) -> bool {
+ self.flags.get_bit(Self::FLAG_FDCAN)
+ }
+
+ /// Request/is Flexible Data Rate
+ pub fn bit_rate_switching(&self) -> bool {
+ self.flags.get_bit(Self::FLAG_BRS)
+ }
+}
+
+/// Payload of a classic CAN data frame.
+///
+/// Contains 0 to 8 Bytes of data.
+#[derive(Debug, Copy, Clone)]
+pub struct ClassicData {
+ pub(crate) bytes: [u8; 8],
+}
+
+impl ClassicData {
+ /// Creates a data payload from a raw byte slice.
+ ///
+ /// Returns `None` if `data` is more than 64 bytes (which is the maximum) or
+ /// cannot be represented with an FDCAN DLC.
+ pub fn new(data: &[u8]) -> Option<Self> {
+ if !FdData::is_valid_len(data.len()) {
+ return None;
+ }
+
+ let mut bytes = [0; 8];
+ bytes[..data.len()].copy_from_slice(data);
+
+ Some(Self { bytes })
+ }
+
+ /// Raw read access to data.
+ pub fn raw(&self) -> &[u8] {
+ &self.bytes
+ }
+
+ /// Checks if the length can be encoded in FDCAN DLC field.
+ pub const fn is_valid_len(len: usize) -> bool {
+ match len {
+ 0..=8 => true,
+ _ => false,
+ }
+ }
+
+ /// Creates an empty data payload containing 0 bytes.
+ #[inline]
+ pub const fn empty() -> Self {
+ Self { bytes: [0; 8] }
+ }
+}
+
+/// Frame with up to 8 bytes of data payload as per Classic CAN
+#[derive(Debug, Copy, Clone)]
+pub struct ClassicFrame {
+ can_header: Header,
+ data: ClassicData,
+}
+
+impl ClassicFrame {
+ pub(crate) const MAX_DATA_LEN: usize = 8;
+
+ /// Create a new CAN classic Frame
+ pub fn new(can_header: Header, data: ClassicData) -> ClassicFrame {
+ ClassicFrame { can_header, data }
+ }
+
+ /// Create new extended frame
+ pub fn new_extended(raw_id: u32, raw_data: &[u8]) -> Option<Self> {
+ if let Some(id) = embedded_can::ExtendedId::new(raw_id) {
+ match ClassicData::new(raw_data) {
+ Some(data) => Some(ClassicFrame::new(
+ Header::new(id.into(), raw_data.len() as u8, false),
+ data,
+ )),
+ None => None,
+ }
+ } else {
+ None
+ }
+ }
+
+ /// Create new standard frame
+ pub fn new_standard(raw_id: u16, raw_data: &[u8]) -> Option<Self> {
+ if let Some(id) = embedded_can::StandardId::new(raw_id) {
+ match ClassicData::new(raw_data) {
+ Some(data) => Some(ClassicFrame::new(
+ Header::new(id.into(), raw_data.len() as u8, false),
+ data,
+ )),
+ None => None,
+ }
+ } else {
+ None
+ }
+ }
+
+ /// Create new remote frame
+ pub fn new_remote(id: impl Into<embedded_can::Id>, len: usize) -> Option<Self> {
+ if len <= 8usize {
+ Some(ClassicFrame::new(
+ Header::new(id.into(), len as u8, true),
+ ClassicData::empty(),
+ ))
+ } else {
+ None
+ }
+ }
+
+ /// Get reference to data
+ pub fn header(&self) -> &Header {
+ &self.can_header
+ }
+
+ /// Return ID
+ pub fn id(&self) -> &embedded_can::Id {
+ &self.can_header.id
+ }
+
+ /// Get reference to data
+ pub fn data(&self) -> &[u8] {
+ &self.data.raw()
+ }
+}
+
+impl embedded_can::Frame for ClassicFrame {
+ fn new(id: impl Into<embedded_can::Id>, raw_data: &[u8]) -> Option<Self> {
+ match ClassicData::new(raw_data) {
+ Some(data) => Some(ClassicFrame::new(
+ Header::new(id.into(), raw_data.len() as u8, false),
+ data,
+ )),
+ None => None,
+ }
+ }
+ fn new_remote(id: impl Into<embedded_can::Id>, len: usize) -> Option<Self> {
+ if len <= 8 {
+ Some(ClassicFrame::new(
+ Header::new(id.into(), len as u8, true),
+ ClassicData::empty(),
+ ))
+ } else {
+ None
+ }
+ }
+ fn is_extended(&self) -> bool {
+ match self.can_header.id {
+ embedded_can::Id::Extended(_) => true,
+ embedded_can::Id::Standard(_) => true,
+ }
+ }
+ fn is_remote_frame(&self) -> bool {
+ self.can_header.rtr()
+ }
+ fn id(&self) -> embedded_can::Id {
+ self.can_header.id
+ }
+ fn dlc(&self) -> usize {
+ self.can_header.len as usize
+ }
+ fn data(&self) -> &[u8] {
+ &self.data.raw()
+ }
+}
+
+/// Payload of a (FD)CAN data frame.
+///
+/// Contains 0 to 64 Bytes of data.
+#[derive(Debug, Copy, Clone)]
+pub struct FdData {
+ pub(crate) bytes: [u8; 64],
+}
+
+impl FdData {
+ /// Creates a data payload from a raw byte slice.
+ ///
+ /// Returns `None` if `data` is more than 64 bytes (which is the maximum) or
+ /// cannot be represented with an FDCAN DLC.
+ pub fn new(data: &[u8]) -> Option<Self> {
+ if !FdData::is_valid_len(data.len()) {
+ return None;
+ }
+
+ let mut bytes = [0; 64];
+ bytes[..data.len()].copy_from_slice(data);
+
+ Some(Self { bytes })
+ }
+
+ /// Raw read access to data.
+ pub fn raw(&self) -> &[u8] {
+ &self.bytes
+ }
+
+ /// Checks if the length can be encoded in FDCAN DLC field.
+ pub const fn is_valid_len(len: usize) -> bool {
+ match len {
+ 0..=8 => true,
+ 12 => true,
+ 16 => true,
+ 20 => true,
+ 24 => true,
+ 32 => true,
+ 48 => true,
+ 64 => true,
+ _ => false,
+ }
+ }
+
+ /// Creates an empty data payload containing 0 bytes.
+ #[inline]
+ pub const fn empty() -> Self {
+ Self { bytes: [0; 64] }
+ }
+}
+
+/// Frame with up to 8 bytes of data payload as per Fd CAN
+#[derive(Debug, Copy, Clone)]
+pub struct FdFrame {
+ can_header: Header,
+ data: FdData,
+}
+
+impl FdFrame {
+ pub(crate) const MAX_DATA_LEN: usize = 64;
+
+ /// Create a new CAN classic Frame
+ pub fn new(can_header: Header, data: FdData) -> FdFrame {
+ FdFrame { can_header, data }
+ }
+
+ /// Create new extended frame
+ pub fn new_extended(raw_id: u32, raw_data: &[u8]) -> Option<Self> {
+ if let Some(id) = embedded_can::ExtendedId::new(raw_id) {
+ match FdData::new(raw_data) {
+ Some(data) => Some(FdFrame::new(Header::new(id.into(), raw_data.len() as u8, false), data)),
+ None => None,
+ }
+ } else {
+ None
+ }
+ }
+
+ /// Create new standard frame
+ pub fn new_standard(raw_id: u16, raw_data: &[u8]) -> Option<Self> {
+ if let Some(id) = embedded_can::StandardId::new(raw_id) {
+ match FdData::new(raw_data) {
+ Some(data) => Some(FdFrame::new(Header::new(id.into(), raw_data.len() as u8, false), data)),
+ None => None,
+ }
+ } else {
+ None
+ }
+ }
+
+ /// Create new remote frame
+ pub fn new_remote(id: impl Into<embedded_can::Id>, len: usize) -> Option<Self> {
+ if len <= 8 {
+ Some(FdFrame::new(Header::new(id.into(), len as u8, true), FdData::empty()))
+ } else {
+ None
+ }
+ }
+
+ /// Get reference to data
+ pub fn header(&self) -> &Header {
+ &self.can_header
+ }
+
+ /// Return ID
+ pub fn id(&self) -> &embedded_can::Id {
+ &self.can_header.id
+ }
+
+ /// Get reference to data
+ pub fn data(&self) -> &[u8] {
+ &self.data.raw()
+ }
+}
+
+impl embedded_can::Frame for FdFrame {
+ fn new(id: impl Into<embedded_can::Id>, raw_data: &[u8]) -> Option<Self> {
+ match FdData::new(raw_data) {
+ Some(data) => Some(FdFrame::new(
+ Header::new_fd(id.into(), raw_data.len() as u8, false, true),
+ data,
+ )),
+ None => None,
+ }
+ }
+ fn new_remote(id: impl Into<embedded_can::Id>, len: usize) -> Option<Self> {
+ if len <= 8 {
+ Some(FdFrame::new(
+ Header::new_fd(id.into(), len as u8, true, true),
+ FdData::empty(),
+ ))
+ } else {
+ None
+ }
+ }
+ fn is_extended(&self) -> bool {
+ match self.can_header.id {
+ embedded_can::Id::Extended(_) => true,
+ embedded_can::Id::Standard(_) => true,
+ }
+ }
+ fn is_remote_frame(&self) -> bool {
+ self.can_header.rtr()
+ }
+ fn id(&self) -> embedded_can::Id {
+ self.can_header.id
+ }
+ // Returns length in bytes even for CANFD packets which embedded-can does not really mention.
+ fn dlc(&self) -> usize {
+ self.can_header.len as usize
+ }
+ fn data(&self) -> &[u8] {
+ &self.data.raw()
+ }
+}
diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index 895ad3e7c..fdb325f06 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -20,6 +20,7 @@ defmt-rtt = "0.4"
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7.0"
embedded-hal = "0.2.6"
+embedded-can = { version = "0.4" }
panic-probe = { version = "0.3", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
heapless = { version = "0.8", default-features = false }
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
index 727921fba..5ff4f0ef0 100644
--- a/examples/stm32g4/src/bin/can.rs
+++ b/examples/stm32g4/src/bin/can.rs
@@ -20,32 +20,100 @@ async fn main(_spawner: Spawner) {
let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
+ can.set_extended_filter(
+ can::fd::filter::ExtendedFilterSlot::_0,
+ can::fd::filter::ExtendedFilter::accept_all_into_fifo1(),
+ );
+
// 250k bps
can.set_bitrate(250_000);
+ // 1M bps
+ can.set_fd_data_bitrate(1_000_000, false);
+
info!("Configured");
- //let mut can = can.into_external_loopback_mode();
- let mut can = can.into_normal_mode();
+ //let mut can = can.into_normal_mode();
+ let mut can = can.into_internal_loopback_mode();
let mut i = 0;
+ let mut last_read_ts = embassy_time::Instant::now();
+
loop {
- let frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::StandardId::new(0x123).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
+ let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
info!("Writing frame");
+
_ = can.write(&frame).await;
match can.read().await {
- Ok(rx_frame) => info!("Rx: {}", rx_frame.data()[0]),
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {} {:02x} --- {}ms",
+ rx_frame.header().len(),
+ rx_frame.data()[0..rx_frame.header().len() as usize],
+ delta,
+ )
+ }
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ if i > 2 {
+ break;
+ }
+ }
+
+ // Use the FD API's even if we don't get FD packets.
+ loop {
+ let frame = can::frame::FdFrame::new_extended(0x123456F, &[i; 16]).unwrap();
+ info!("Writing frame using FD API");
+
+ _ = can.write_fd(&frame).await;
+
+ match can.read_fd().await {
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {} {:02x} --- using FD API {}ms",
+ rx_frame.header().len(),
+ rx_frame.data()[0..rx_frame.header().len() as usize],
+ delta,
+ )
+ }
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ if i > 4 {
+ break;
+ }
+ }
+
+ let (mut tx, mut rx) = can.split();
+ // With split
+ loop {
+ let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
+ info!("Writing frame");
+ _ = tx.write(&frame).await;
+
+ match rx.read().await {
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {} {:02x} --- {}ms",
+ rx_frame.header().len(),
+ rx_frame.data()[0..rx_frame.header().len() as usize],
+ delta,
+ )
+ }
Err(_err) => error!("Error in frame"),
}
diff --git a/examples/stm32h5/src/bin/can.rs b/examples/stm32h5/src/bin/can.rs
index 2906d1576..4b29a0d21 100644
--- a/examples/stm32h5/src/bin/can.rs
+++ b/examples/stm32h5/src/bin/can.rs
@@ -16,54 +16,77 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
-
- // configure FDCAN to use PLL1_Q at 64 MHz
- config.rcc.pll1 = Some(rcc::Pll {
- source: rcc::PllSource::HSI,
- prediv: rcc::PllPreDiv::DIV4,
- mul: rcc::PllMul::MUL8,
- divp: None,
- divq: Some(rcc::PllDiv::DIV2),
- divr: None,
+ config.rcc.hse = Some(rcc::Hse {
+ freq: embassy_stm32::time::Hertz(25_000_000),
+ mode: rcc::HseMode::Oscillator,
});
- config.rcc.fdcan_clock_source = rcc::FdCanClockSource::PLL1_Q;
+ config.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
let peripherals = embassy_stm32::init(config);
+ //let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
- can.can.apply_config(
- can::config::FdCanConfig::default().set_nominal_bit_timing(can::config::NominalBitTiming {
- sync_jump_width: 1.try_into().unwrap(),
- prescaler: 8.try_into().unwrap(),
- seg1: 13.try_into().unwrap(),
- seg2: 2.try_into().unwrap(),
- }),
- );
+ // 250k bps
+ can.set_bitrate(250_000);
- info!("Configured");
+ //let mut can = can.into_internal_loopback_mode();
+ let mut can = can.into_normal_mode();
- let mut can = can.into_external_loopback_mode();
- //let mut can = can.into_normal_mode();
+ info!("CAN Configured");
let mut i = 0;
+ let mut last_read_ts = embassy_time::Instant::now();
+
loop {
- let frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::StandardId::new(0x123).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
+ let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
info!("Writing frame");
_ = can.write(&frame).await;
match can.read().await {
- Ok(rx_frame) => info!("Rx: {}", rx_frame.data()[0]),
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {:x} {:x} {:x} {:x} --- NEW {}",
+ rx_frame.data()[0],
+ rx_frame.data()[1],
+ rx_frame.data()[2],
+ rx_frame.data()[3],
+ delta,
+ )
+ }
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ if i > 3 {
+ break;
+ }
+ }
+
+ let (mut tx, mut rx) = can.split();
+ // With split
+ loop {
+ let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
+ info!("Writing frame");
+ _ = tx.write(&frame).await;
+
+ match rx.read().await {
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {:x} {:x} {:x} {:x} --- NEW {}",
+ rx_frame.data()[0],
+ rx_frame.data()[1],
+ rx_frame.data()[2],
+ rx_frame.data()[3],
+ delta,
+ )
+ }
Err(_err) => error!("Error in frame"),
}
diff --git a/examples/stm32h7/src/bin/can.rs b/examples/stm32h7/src/bin/can.rs
index 2906d1576..4b29a0d21 100644
--- a/examples/stm32h7/src/bin/can.rs
+++ b/examples/stm32h7/src/bin/can.rs
@@ -16,54 +16,77 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
-
- // configure FDCAN to use PLL1_Q at 64 MHz
- config.rcc.pll1 = Some(rcc::Pll {
- source: rcc::PllSource::HSI,
- prediv: rcc::PllPreDiv::DIV4,
- mul: rcc::PllMul::MUL8,
- divp: None,
- divq: Some(rcc::PllDiv::DIV2),
- divr: None,
+ config.rcc.hse = Some(rcc::Hse {
+ freq: embassy_stm32::time::Hertz(25_000_000),
+ mode: rcc::HseMode::Oscillator,
});
- config.rcc.fdcan_clock_source = rcc::FdCanClockSource::PLL1_Q;
+ config.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
let peripherals = embassy_stm32::init(config);
+ //let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
- can.can.apply_config(
- can::config::FdCanConfig::default().set_nominal_bit_timing(can::config::NominalBitTiming {
- sync_jump_width: 1.try_into().unwrap(),
- prescaler: 8.try_into().unwrap(),
- seg1: 13.try_into().unwrap(),
- seg2: 2.try_into().unwrap(),
- }),
- );
+ // 250k bps
+ can.set_bitrate(250_000);
- info!("Configured");
+ //let mut can = can.into_internal_loopback_mode();
+ let mut can = can.into_normal_mode();
- let mut can = can.into_external_loopback_mode();
- //let mut can = can.into_normal_mode();
+ info!("CAN Configured");
let mut i = 0;
+ let mut last_read_ts = embassy_time::Instant::now();
+
loop {
- let frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::StandardId::new(0x123).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
+ let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
info!("Writing frame");
_ = can.write(&frame).await;
match can.read().await {
- Ok(rx_frame) => info!("Rx: {}", rx_frame.data()[0]),
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {:x} {:x} {:x} {:x} --- NEW {}",
+ rx_frame.data()[0],
+ rx_frame.data()[1],
+ rx_frame.data()[2],
+ rx_frame.data()[3],
+ delta,
+ )
+ }
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ if i > 3 {
+ break;
+ }
+ }
+
+ let (mut tx, mut rx) = can.split();
+ // With split
+ loop {
+ let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
+ info!("Writing frame");
+ _ = tx.write(&frame).await;
+
+ match rx.read().await {
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {:x} {:x} {:x} {:x} --- NEW {}",
+ rx_frame.data()[0],
+ rx_frame.data()[1],
+ rx_frame.data()[2],
+ rx_frame.data()[3],
+ delta,
+ )
+ }
Err(_err) => error!("Error in frame"),
}
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 8554682a4..5b28b5849 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -69,6 +69,7 @@ cortex-m-rt = "0.7.0"
embedded-hal = "0.2.6"
embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
embedded-hal-async = { version = "1.0" }
+embedded-can = { version = "0.4" }
micromath = "2.0.0"
panic-probe = { version = "0.3.0", features = ["print-defmt"] }
rand_core = { version = "0.6", default-features = false }
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
index 7363eaa16..76c27d091 100644
--- a/tests/stm32/src/bin/fdcan.rs
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -36,7 +36,7 @@ fn options() -> TestOptions {
c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
TestOptions {
config: c,
- max_latency: Duration::from_micros(3800),
+ max_latency: Duration::from_micros(1200),
second_fifo_working: false,
}
}
@@ -53,12 +53,12 @@ fn options() -> TestOptions {
c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
TestOptions {
config: c,
- max_latency: Duration::from_micros(5500),
+ max_latency: Duration::from_micros(1200),
second_fifo_working: false,
}
}
-#[cfg(any(feature = "stm32g491re"))]
+#[cfg(any(feature = "stm32g491re", feature = "stm32g431cb"))]
fn options() -> TestOptions {
info!("G4 config");
TestOptions {
@@ -80,9 +80,9 @@ async fn main(_spawner: Spawner) {
// 250k bps
can.set_bitrate(250_000);
- can.can.set_extended_filter(
- can::filter::ExtendedFilterSlot::_0,
- can::filter::ExtendedFilter::accept_all_into_fifo1(),
+ can.set_extended_filter(
+ can::fd::filter::ExtendedFilterSlot::_0,
+ can::fd::filter::ExtendedFilter::accept_all_into_fifo1(),
);
let mut can = can.into_internal_loopback_mode();
@@ -91,31 +91,21 @@ async fn main(_spawner: Spawner) {
let mut i: u8 = 0;
loop {
- let tx_frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::StandardId::new(0x123).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
+ let tx_frame = can::frame::ClassicFrame::new_standard(0x123, &[i; 1]).unwrap();
info!("Transmitting frame...");
let tx_ts = Instant::now();
can.write(&tx_frame).await;
- let envelope = can.read().await.unwrap();
+ let (frame, timestamp) = can.read().await.unwrap();
info!("Frame received!");
// Check data.
- assert!(i == envelope.data()[0], "{} == {}", i, envelope.data()[0]);
+ assert!(i == frame.data()[0], "{} == {}", i, frame.data()[0]);
- info!("loopback time {}", envelope.header.time_stamp);
- info!("loopback frame {=u8}", envelope.data()[0]);
- let latency = envelope.timestamp.saturating_duration_since(tx_ts);
+ info!("loopback time {}", timestamp);
+ info!("loopback frame {=u8}", frame.data()[0]);
+ let latency = timestamp.saturating_duration_since(tx_ts);
info!("loopback latency {} us", latency.as_micros());
// Theoretical minimum latency is 55us, actual is usually ~80us
@@ -143,47 +133,26 @@ async fn main(_spawner: Spawner) {
// in each FIFO so make sure we write enough to fill them both up before reading.
for i in 0..3 {
// Try filling up the RX FIFO0 buffers with standard packets
- let tx_frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::StandardId::new(0x123).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
+ let tx_frame = can::frame::ClassicFrame::new_standard(0x123, &[i; 1]).unwrap();
info!("Transmitting frame {}", i);
can.write(&tx_frame).await;
}
for i in 3..max_buffered {
// Try filling up the RX FIFO0 buffers with extended packets
- let tx_frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::ExtendedId::new(0x1232344).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
-
+ let tx_frame = can::frame::ClassicFrame::new_extended(0x1232344, &[i; 1]).unwrap();
info!("Transmitting frame {}", i);
can.write(&tx_frame).await;
}
// Try and receive all 6 packets
for i in 0..max_buffered {
- let envelope = can.read().await.unwrap();
- match envelope.header.id {
- can::Id::Extended(id) => {
- info!("Extended received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ let (frame, _ts) = can.read().await.unwrap();
+ match frame.id() {
+ embedded_can::Id::Extended(id) => {
+ info!("Extended received! {:x} {} {}", id.as_raw(), frame.data()[0], i);
}
- can::Id::Standard(id) => {
- info!("Standard received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ embedded_can::Id::Standard(id) => {
+ info!("Standard received! {:x} {} {}", id.as_raw(), frame.data()[0], i);
}
}
}
@@ -192,48 +161,26 @@ async fn main(_spawner: Spawner) {
let (mut tx, mut rx) = can.split();
for i in 0..3 {
// Try filling up the RX FIFO0 buffers with standard packets
- let tx_frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::StandardId::new(0x123).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
-
+ let tx_frame = can::frame::ClassicFrame::new_standard(0x123, &[i; 1]).unwrap();
info!("Transmitting frame {}", i);
tx.write(&tx_frame).await;
}
for i in 3..max_buffered {
// Try filling up the RX FIFO0 buffers with extended packets
- let tx_frame = can::TxFrame::new(
- can::TxFrameHeader {
- len: 1,
- frame_format: can::FrameFormat::Standard,
- id: can::ExtendedId::new(0x1232344).unwrap().into(),
- bit_rate_switching: false,
- marker: None,
- },
- &[i],
- )
- .unwrap();
-
+ let tx_frame = can::frame::ClassicFrame::new_extended(0x1232344, &[i; 1]).unwrap();
info!("Transmitting frame {}", i);
tx.write(&tx_frame).await;
}
// Try and receive all 6 packets
for i in 0..max_buffered {
- let envelope = rx.read().await.unwrap();
- match envelope.header.id {
- can::Id::Extended(id) => {
- info!("Extended received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ let (frame, _ts) = rx.read().await.unwrap();
+ match frame.id() {
+ embedded_can::Id::Extended(id) => {
+ info!("Extended received! {:x} {} {}", id.as_raw(), frame.data()[0], i);
}
- can::Id::Standard(id) => {
- info!("Standard received! {:x} {} {}", id.as_raw(), envelope.data()[0], i);
+ embedded_can::Id::Standard(id) => {
+ info!("Standard received! {:x} {} {}", id.as_raw(), frame.data()[0], i);
}
}
}
From 200ace566f3da7db6f4119d6bd3b709a69293297 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 17 Feb 2024 10:51:31 +1000
Subject: [PATCH 247/392] Don't use word Standard for frame format because it
can be confused with ID format. Use Classic instead to mean CAN 2.0B frames.
---
.../src/can/fd/message_ram/common.rs | 6 +++---
embassy-stm32/src/can/fd/message_ram/enums.rs | 20 +++++++++----------
embassy-stm32/src/can/fd/mod.rs | 2 +-
embassy-stm32/src/can/fd/peripheral.rs | 6 +++---
4 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/embassy-stm32/src/can/fd/message_ram/common.rs b/embassy-stm32/src/can/fd/message_ram/common.rs
index a67d68fa0..108c1a428 100644
--- a/embassy-stm32/src/can/fd/message_ram/common.rs
+++ b/embassy-stm32/src/can/fd/message_ram/common.rs
@@ -88,12 +88,12 @@ pub type FDF_R = generic::R<bool, FrameFormat>;
impl FDF_R {
pub fn frame_format(&self) -> FrameFormat {
match self.bits() {
- false => FrameFormat::Standard,
+ false => FrameFormat::Classic,
true => FrameFormat::Fdcan,
}
}
- pub fn is_standard_format(&self) -> bool {
- *self == FrameFormat::Standard
+ pub fn is_classic_format(&self) -> bool {
+ *self == FrameFormat::Classic
}
pub fn is_fdcan_format(&self) -> bool {
*self == FrameFormat::Fdcan
diff --git a/embassy-stm32/src/can/fd/message_ram/enums.rs b/embassy-stm32/src/can/fd/message_ram/enums.rs
index 78285bf81..0ec5e0f34 100644
--- a/embassy-stm32/src/can/fd/message_ram/enums.rs
+++ b/embassy-stm32/src/can/fd/message_ram/enums.rs
@@ -5,7 +5,7 @@
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DataLength {
- Standard(u8),
+ Classic(u8),
Fdcan(u8),
}
impl DataLength {
@@ -14,8 +14,8 @@ impl DataLength {
/// Uses the byte length and Type of frame as input
pub fn new(len: u8, ff: FrameFormat) -> DataLength {
match ff {
- FrameFormat::Standard => match len {
- 0..=8 => DataLength::Standard(len),
+ FrameFormat::Classic => match len {
+ 0..=8 => DataLength::Classic(len),
_ => panic!("DataLength > 8"),
},
FrameFormat::Fdcan => match len {
@@ -24,9 +24,9 @@ impl DataLength {
},
}
}
- /// Specialised function to create standard frames
- pub fn new_standard(len: u8) -> DataLength {
- Self::new(len, FrameFormat::Standard)
+ /// Specialised function to create classic frames
+ pub fn new_classic(len: u8) -> DataLength {
+ Self::new(len, FrameFormat::Classic)
}
/// Specialised function to create FDCAN frames
pub fn new_fdcan(len: u8) -> DataLength {
@@ -36,13 +36,13 @@ impl DataLength {
/// returns the length in bytes
pub fn len(&self) -> u8 {
match self {
- DataLength::Standard(l) | DataLength::Fdcan(l) => *l,
+ DataLength::Classic(l) | DataLength::Fdcan(l) => *l,
}
}
pub(crate) fn dlc(&self) -> u8 {
match self {
- DataLength::Standard(l) => *l,
+ DataLength::Classic(l) => *l,
// See RM0433 Rev 7 Table 475. DLC coding
DataLength::Fdcan(l) => match l {
0..=8 => *l,
@@ -61,7 +61,7 @@ impl DataLength {
impl From<DataLength> for FrameFormat {
fn from(dl: DataLength) -> FrameFormat {
match dl {
- DataLength::Standard(_) => FrameFormat::Standard,
+ DataLength::Classic(_) => FrameFormat::Classic,
DataLength::Fdcan(_) => FrameFormat::Fdcan,
}
}
@@ -121,7 +121,7 @@ impl From<ErrorStateIndicator> for bool {
/// Type of frame, standard (classic) or FdCAN
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FrameFormat {
- Standard = 0,
+ Classic = 0,
Fdcan = 1,
}
impl From<FrameFormat> for bool {
diff --git a/embassy-stm32/src/can/fd/mod.rs b/embassy-stm32/src/can/fd/mod.rs
index 0008fd3a8..271ca0b3c 100644
--- a/embassy-stm32/src/can/fd/mod.rs
+++ b/embassy-stm32/src/can/fd/mod.rs
@@ -1,4 +1,4 @@
-//! Module containing that which is speciffic to fdcan hardware variant
+//! Module containing that which is specific to fdcan hardware variant
pub mod config;
pub mod filter;
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 6f390abb4..3422d7148 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -167,7 +167,7 @@ impl Registers {
let len = match header_reg.to_data_length() {
DataLength::Fdcan(len) => len,
- DataLength::Standard(len) => len,
+ DataLength::Classic(len) => len,
};
if len as usize > ClassicFrame::MAX_DATA_LEN {
return None;
@@ -202,7 +202,7 @@ impl Registers {
let len = match header_reg.to_data_length() {
DataLength::Fdcan(len) => len,
- DataLength::Standard(len) => len,
+ DataLength::Classic(len) => len,
};
if len as usize > FdFrame::MAX_DATA_LEN {
return None;
@@ -683,7 +683,7 @@ fn put_tx_header(mailbox: &mut TxBufferElement, header: &Header) {
let frame_format = if header.len() > 8 || header.fdcan() {
FrameFormat::Fdcan
} else {
- FrameFormat::Standard
+ FrameFormat::Classic
};
let brs = header.len() > 8 || header.bit_rate_switching();
From 5d8c54fdea752d4a52b33a7f776b436f5934409c Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 17 Feb 2024 11:19:05 +1000
Subject: [PATCH 248/392] Move error conversion to peripheral.rs
---
embassy-stm32/src/can/enums.rs | 17 -----------
embassy-stm32/src/can/fd/peripheral.rs | 39 ++++++++++++++++++++++++++
embassy-stm32/src/can/fdcan.rs | 32 +++------------------
3 files changed, 43 insertions(+), 45 deletions(-)
diff --git a/embassy-stm32/src/can/enums.rs b/embassy-stm32/src/can/enums.rs
index 135010011..36139a45c 100644
--- a/embassy-stm32/src/can/enums.rs
+++ b/embassy-stm32/src/can/enums.rs
@@ -1,5 +1,4 @@
//! Enums shared between CAN controller types.
-use core::convert::TryFrom;
/// Bus error
#[derive(Debug)]
@@ -29,19 +28,3 @@ pub enum BusError {
/// At least one of error counter has reached the Error_Warning limit of 96.
BusWarning,
}
-impl TryFrom<u8> for BusError {
- type Error = ();
- fn try_from(value: u8) -> Result<Self, Self::Error> {
- match value {
- //0b000 => None,
- 0b001 => Ok(Self::Stuff),
- 0b010 => Ok(Self::Form),
- 0b011 => Ok(Self::Acknowledge),
- 0b100 => Ok(Self::BitRecessive),
- 0b101 => Ok(Self::BitDominant),
- 0b110 => Ok(Self::Crc),
- //0b111 => Ok(Self::NoError),
- _ => Err(()),
- }
- }
-}
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 3422d7148..487b8f413 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -3,6 +3,9 @@
use core::convert::Infallible;
use core::slice;
+use cfg_if::cfg_if;
+
+use crate::can::enums::*;
use crate::can::fd::config::*;
use crate::can::fd::message_ram::enums::*;
use crate::can::fd::message_ram::{RegisterBlock, RxFifoElement, TxBufferElement};
@@ -98,6 +101,42 @@ impl Registers {
self.regs.txbar().modify(|w| w.set_ar(bufidx, true));
}
+ fn reg_to_error(value: u8) -> Option<BusError> {
+ match value {
+ //0b000 => None,
+ 0b001 => Some(BusError::Stuff),
+ 0b010 => Some(BusError::Form),
+ 0b011 => Some(BusError::Acknowledge),
+ 0b100 => Some(BusError::BitRecessive),
+ 0b101 => Some(BusError::BitDominant),
+ 0b110 => Some(BusError::Crc),
+ //0b111 => Some(BusError::NoError),
+ _ => None,
+ }
+ }
+
+ pub fn curr_error(&self) -> Option<BusError> {
+ let err = { self.regs.psr().read() };
+ if err.bo() {
+ return Some(BusError::BusOff);
+ } else if err.ep() {
+ return Some(BusError::BusPassive);
+ } else if err.ew() {
+ return Some(BusError::BusWarning);
+ } else {
+ cfg_if! {
+ if #[cfg(stm32h7)] {
+ let lec = err.lec();
+ } else {
+ let lec = err.lec().to_bits();
+ }
+ }
+ if let Some(err) = Self::reg_to_error(lec) {
+ return Some(err);
+ }
+ }
+ None
+ }
/// Returns if the tx queue is able to accept new messages without having to cancel an existing one
#[inline]
pub fn tx_queue_is_full(&self) -> bool {
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index b94e42707..987748e06 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -4,7 +4,6 @@ use core::marker::PhantomData;
use core::task::Poll;
pub mod fd;
-use cfg_if::cfg_if;
use embassy_hal_internal::{into_ref, PeripheralRef};
use fd::config::*;
use fd::filter::*;
@@ -184,29 +183,6 @@ fn calc_timestamp<T: Instance>(_ns_per_timer_tick: u64, ts_val: u16) -> Timestam
ts_val
}
-fn curr_error<T: Instance>() -> Option<BusError> {
- let err = { T::regs().psr().read() };
- if err.bo() {
- return Some(BusError::BusOff);
- } else if err.ep() {
- return Some(BusError::BusPassive);
- } else if err.ew() {
- return Some(BusError::BusWarning);
- } else {
- cfg_if! {
- if #[cfg(stm32h7)] {
- let lec = err.lec();
- } else {
- let lec = err.lec().to_bits();
- }
- }
- if let Ok(err) = BusError::try_from(lec) {
- return Some(err);
- }
- }
- None
-}
-
impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
/// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
/// You must call [Fdcan::enable_non_blocking] to use the peripheral.
@@ -426,7 +402,7 @@ where
} else if let Some((msg, ts)) = T::registers().read_classic(1) {
let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = curr_error::<T>() {
+ } else if let Some(err) = T::registers().curr_error() {
// TODO: this is probably wrong
return Poll::Ready(Err(err));
}
@@ -466,7 +442,7 @@ where
} else if let Some((msg, ts)) = T::registers().read_fd(1) {
let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = curr_error::<T>() {
+ } else if let Some(err) = T::registers().curr_error() {
// TODO: this is probably wrong
return Poll::Ready(Err(err));
}
@@ -560,7 +536,7 @@ impl<'c, 'd, T: Instance, M: Receive> FdcanRx<'d, T, M> {
} else if let Some((msg, ts)) = T::registers().read_classic(1) {
let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = curr_error::<T>() {
+ } else if let Some(err) = T::registers().curr_error() {
// TODO: this is probably wrong
return Poll::Ready(Err(err));
}
@@ -581,7 +557,7 @@ impl<'c, 'd, T: Instance, M: Receive> FdcanRx<'d, T, M> {
} else if let Some((msg, ts)) = T::registers().read_fd(1) {
let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = curr_error::<T>() {
+ } else if let Some(err) = T::registers().curr_error() {
// TODO: this is probably wrong
return Poll::Ready(Err(err));
}
From 91c75c92a0e67c93550a163ae62b22a652bf2012 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 17 Feb 2024 18:10:45 +1000
Subject: [PATCH 249/392] Clean up and prep for buffered IRQ mode.
- Reduce code duplicaiton in read/write methods
- General clean-up
- Prepare for buffered mode
---
embassy-stm32/src/can/fdcan.rs | 347 ++++++++++++++++++---------------
1 file changed, 188 insertions(+), 159 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 987748e06..42ce73ded 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -39,14 +39,17 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
let ir = regs.ir().read();
- if ir.tc() {
- regs.ir().write(|w| w.set_tc(true));
- T::state().tx_waker.wake();
- }
+ {
+ if ir.tc() {
+ regs.ir().write(|w| w.set_tc(true));
+ }
+ if ir.tefn() {
+ regs.ir().write(|w| w.set_tefn(true));
+ }
- if ir.tefn() {
- regs.ir().write(|w| w.set_tefn(true));
- T::state().tx_waker.wake();
+ match &T::state().tx_mode {
+ sealed::TxMode::NonBuffered(waker) => waker.wake(),
+ }
}
if ir.ped() || ir.pea() {
@@ -57,15 +60,11 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
}
if ir.rfn(0) {
- let fifonr = 0 as usize;
- regs.ir().write(|w| w.set_rfn(fifonr, true));
-
- T::state().rx_waker.wake();
+ T::state().rx_mode.on_interrupt::<T>(0);
}
if ir.rfn(1) {
- regs.ir().write(|w| w.set_rfn(1, true));
- T::state().rx_waker.wake();
+ T::state().rx_mode.on_interrupt::<T>(1);
}
}
}
@@ -148,7 +147,6 @@ pub struct Fdcan<'d, T: Instance, M: FdcanOperatingMode> {
/// Reference to internals.
instance: FdcanInstance<'d, T>,
_mode: PhantomData<M>,
- ns_per_timer_tick: u64, // For FDCAN internal timer
}
fn calc_ns_per_timer_tick<T: Instance>(mode: crate::can::fd::config::FrameTransmissionConfig) -> u64 {
@@ -166,23 +164,6 @@ fn calc_ns_per_timer_tick<T: Instance>(mode: crate::can::fd::config::FrameTransm
}
}
-#[cfg(feature = "time")]
-fn calc_timestamp<T: Instance>(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
- let now_embassy = embassy_time::Instant::now();
- if ns_per_timer_tick == 0 {
- return now_embassy;
- }
- let cantime = { T::regs().tscv().read().tsc() };
- let delta = cantime.overflowing_sub(ts_val).0 as u64;
- let ns = ns_per_timer_tick * delta as u64;
- now_embassy - embassy_time::Duration::from_nanos(ns)
-}
-
-#[cfg(not(feature = "time"))]
-fn calc_timestamp<T: Instance>(_ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
- ts_val
-}
-
impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
/// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
/// You must call [Fdcan::enable_non_blocking] to use the peripheral.
@@ -239,12 +220,10 @@ impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
w.set_eint1(true); // Interrupt Line 1
});
- let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(config.frame_transmit);
Self {
config,
instance: FdcanInstance(peri),
_mode: PhantomData::<ConfigMode>,
- ns_per_timer_tick,
}
}
@@ -319,12 +298,14 @@ macro_rules! impl_transition {
/// Transition from $from_mode:ident mode to $to_mode:ident mode
pub fn $name(self) -> Fdcan<'d, T, $to_mode> {
let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(self.config.frame_transmit);
+ critical_section::with(|_| unsafe {
+ T::mut_state().ns_per_timer_tick = ns_per_timer_tick;
+ });
T::registers().$func(self.config);
let ret = Fdcan {
config: self.config,
instance: self.instance,
_mode: PhantomData::<$to_mode>,
- ns_per_timer_tick,
};
ret
}
@@ -357,7 +338,8 @@ where
/// Flush one of the TX mailboxes.
pub async fn flush(&self, idx: usize) {
poll_fn(|cx| {
- T::state().tx_waker.register(cx.waker());
+ T::state().tx_mode.register(cx.waker());
+
if idx > 3 {
panic!("Bad mailbox");
}
@@ -376,39 +358,12 @@ where
/// can be replaced, this call asynchronously waits for a frame to be successfully
/// transmitted, then tries again.
pub async fn write(&mut self, frame: &ClassicFrame) -> Option<ClassicFrame> {
- poll_fn(|cx| {
- T::state().tx_waker.register(cx.waker());
-
- if let Ok(dropped) = T::registers().write_classic(frame) {
- return Poll::Ready(dropped);
- }
-
- // Couldn't replace any lower priority frames. Need to wait for some mailboxes
- // to clear.
- Poll::Pending
- })
- .await
+ T::state().tx_mode.write::<T>(frame).await
}
/// Returns the next received message frame
pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
- poll_fn(|cx| {
- T::state().err_waker.register(cx.waker());
- T::state().rx_waker.register(cx.waker());
-
- if let Some((msg, ts)) = T::registers().read_classic(0) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some((msg, ts)) = T::registers().read_classic(1) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = T::registers().curr_error() {
- // TODO: this is probably wrong
- return Poll::Ready(Err(err));
- }
- Poll::Pending
- })
- .await
+ T::state().rx_mode.read::<T>().await
}
/// Queues the message to be sent but exerts backpressure. If a lower-priority
@@ -416,45 +371,29 @@ where
/// can be replaced, this call asynchronously waits for a frame to be successfully
/// transmitted, then tries again.
pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
- poll_fn(|cx| {
- T::state().tx_waker.register(cx.waker());
-
- if let Ok(dropped) = T::registers().write_fd(frame) {
- return Poll::Ready(dropped);
- }
-
- // Couldn't replace any lower priority frames. Need to wait for some mailboxes
- // to clear.
- Poll::Pending
- })
- .await
+ T::state().tx_mode.write_fd::<T>(frame).await
}
/// Returns the next received message frame
pub async fn read_fd(&mut self) -> Result<(FdFrame, Timestamp), BusError> {
- poll_fn(|cx| {
- T::state().err_waker.register(cx.waker());
- T::state().rx_waker.register(cx.waker());
+ T::state().rx_mode.read_fd::<T>().await
+ }
- if let Some((msg, ts)) = T::registers().read_fd(0) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some((msg, ts)) = T::registers().read_fd(1) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = T::registers().curr_error() {
- // TODO: this is probably wrong
- return Poll::Ready(Err(err));
- }
- Poll::Pending
- })
- .await
+ /// Join split rx and tx portions back together
+ pub fn join(tx: FdcanTx<'d, T, M>, rx: FdcanRx<'d, T, M>) -> Self {
+ Fdcan {
+ config: tx.config,
+ //_instance2: T::regs(),
+ instance: tx._instance,
+ _mode: rx._mode,
+ }
}
/// Split instance into separate Tx(write) and Rx(read) portions
pub fn split(self) -> (FdcanTx<'d, T, M>, FdcanRx<'d, T, M>) {
(
FdcanTx {
+ config: self.config,
_instance: self.instance,
_mode: self._mode,
},
@@ -462,10 +401,10 @@ where
_instance1: PhantomData::<T>,
_instance2: T::regs(),
_mode: self._mode,
- ns_per_timer_tick: self.ns_per_timer_tick,
},
)
}
+
}
/// FDCAN Rx only Instance
@@ -474,11 +413,11 @@ pub struct FdcanRx<'d, T: Instance, M: Receive> {
_instance1: PhantomData<T>,
_instance2: &'d crate::pac::can::Fdcan,
_mode: PhantomData<M>,
- ns_per_timer_tick: u64, // For FDCAN internal timer
}
/// FDCAN Tx only Instance
pub struct FdcanTx<'d, T: Instance, M: Transmit> {
+ config: crate::can::fd::config::FdCanConfig,
_instance: FdcanInstance<'d, T>, //(PeripheralRef<'a, T>);
_mode: PhantomData<M>,
}
@@ -489,18 +428,7 @@ impl<'c, 'd, T: Instance, M: Transmit> FdcanTx<'d, T, M> {
/// can be replaced, this call asynchronously waits for a frame to be successfully
/// transmitted, then tries again.
pub async fn write(&mut self, frame: &ClassicFrame) -> Option<ClassicFrame> {
- poll_fn(|cx| {
- T::state().tx_waker.register(cx.waker());
-
- if let Ok(dropped) = T::registers().write_classic(frame) {
- return Poll::Ready(dropped);
- }
-
- // Couldn't replace any lower priority frames. Need to wait for some mailboxes
- // to clear.
- Poll::Pending
- })
- .await
+ T::state().tx_mode.write::<T>(frame).await
}
/// Queues the message to be sent but exerts backpressure. If a lower-priority
@@ -508,80 +436,158 @@ impl<'c, 'd, T: Instance, M: Transmit> FdcanTx<'d, T, M> {
/// can be replaced, this call asynchronously waits for a frame to be successfully
/// transmitted, then tries again.
pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
- poll_fn(|cx| {
- T::state().tx_waker.register(cx.waker());
-
- if let Ok(dropped) = T::registers().write_fd(frame) {
- return Poll::Ready(dropped);
- }
-
- // Couldn't replace any lower priority frames. Need to wait for some mailboxes
- // to clear.
- Poll::Pending
- })
- .await
+ T::state().tx_mode.write_fd::<T>(frame).await
}
}
impl<'c, 'd, T: Instance, M: Receive> FdcanRx<'d, T, M> {
/// Returns the next received message frame
pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
- poll_fn(|cx| {
- T::state().err_waker.register(cx.waker());
- T::state().rx_waker.register(cx.waker());
-
- if let Some((msg, ts)) = T::registers().read_classic(0) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some((msg, ts)) = T::registers().read_classic(1) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = T::registers().curr_error() {
- // TODO: this is probably wrong
- return Poll::Ready(Err(err));
- }
- Poll::Pending
- })
- .await
+ T::state().rx_mode.read::<T>().await
}
/// Returns the next received message frame
pub async fn read_fd(&mut self) -> Result<(FdFrame, Timestamp), BusError> {
- poll_fn(|cx| {
- T::state().err_waker.register(cx.waker());
- T::state().rx_waker.register(cx.waker());
-
- if let Some((msg, ts)) = T::registers().read_fd(0) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some((msg, ts)) = T::registers().read_fd(1) {
- let ts = calc_timestamp::<T>(self.ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = T::registers().curr_error() {
- // TODO: this is probably wrong
- return Poll::Ready(Err(err));
- }
- Poll::Pending
- })
- .await
+ T::state().rx_mode.read_fd::<T>().await
}
}
pub(crate) mod sealed {
+ use core::future::poll_fn;
+ use core::task::Poll;
+
use embassy_sync::waitqueue::AtomicWaker;
+ use crate::can::_version::{BusError, Timestamp};
+ use crate::can::frame::{ClassicFrame, FdFrame};
+ pub enum RxMode {
+ NonBuffered(AtomicWaker),
+ }
+
+ impl RxMode {
+ pub fn register(&self, arg: &core::task::Waker) {
+ match self {
+ RxMode::NonBuffered(waker) => waker.register(arg),
+ }
+ }
+
+ pub fn on_interrupt<T: Instance>(&self, fifonr: usize) {
+ T::regs().ir().write(|w| w.set_rfn(fifonr, true));
+ match self {
+ RxMode::NonBuffered(waker) => {
+ waker.wake();
+ }
+ }
+ }
+
+ pub async fn read<T: Instance>(&self) -> Result<(ClassicFrame, Timestamp), BusError> {
+ poll_fn(|cx| {
+ T::state().err_waker.register(cx.waker());
+ self.register(cx.waker());
+
+ if let Some((msg, ts)) = T::registers().read_classic(0) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some((msg, ts)) = T::registers().read_classic(1) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some(err) = T::registers().curr_error() {
+ // TODO: this is probably wrong
+ return Poll::Ready(Err(err));
+ }
+ Poll::Pending
+ })
+ .await
+ }
+
+ pub async fn read_fd<T: Instance>(&self) -> Result<(FdFrame, Timestamp), BusError> {
+ poll_fn(|cx| {
+ T::state().err_waker.register(cx.waker());
+ self.register(cx.waker());
+
+ if let Some((msg, ts)) = T::registers().read_fd(0) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some((msg, ts)) = T::registers().read_fd(1) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+ return Poll::Ready(Ok((msg, ts)));
+ } else if let Some(err) = T::registers().curr_error() {
+ // TODO: this is probably wrong
+ return Poll::Ready(Err(err));
+ }
+ Poll::Pending
+ })
+ .await
+ }
+ }
+
+ pub enum TxMode {
+ NonBuffered(AtomicWaker),
+ }
+
+ impl TxMode {
+ pub fn register(&self, arg: &core::task::Waker) {
+ match self {
+ TxMode::NonBuffered(waker) => {
+ waker.register(arg);
+ }
+ }
+ }
+
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write<T: Instance>(&self, frame: &ClassicFrame) -> Option<ClassicFrame> {
+ poll_fn(|cx| {
+ self.register(cx.waker());
+
+ if let Ok(dropped) = T::registers().write_classic(frame) {
+ return Poll::Ready(dropped);
+ }
+
+ // Couldn't replace any lower priority frames. Need to wait for some mailboxes
+ // to clear.
+ Poll::Pending
+ })
+ .await
+ }
+
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write_fd<T: Instance>(&self, frame: &FdFrame) -> Option<FdFrame> {
+ poll_fn(|cx| {
+ self.register(cx.waker());
+
+ if let Ok(dropped) = T::registers().write_fd(frame) {
+ return Poll::Ready(dropped);
+ }
+
+ // Couldn't replace any lower priority frames. Need to wait for some mailboxes
+ // to clear.
+ Poll::Pending
+ })
+ .await
+ }
+ }
+
pub struct State {
- pub tx_waker: AtomicWaker,
+ pub rx_mode: RxMode,
+ pub tx_mode: TxMode,
+ pub ns_per_timer_tick: u64,
+
pub err_waker: AtomicWaker,
- pub rx_waker: AtomicWaker,
}
impl State {
pub const fn new() -> Self {
Self {
- tx_waker: AtomicWaker::new(),
+ rx_mode: RxMode::NonBuffered(AtomicWaker::new()),
+ tx_mode: TxMode::NonBuffered(AtomicWaker::new()),
+ ns_per_timer_tick: 0,
err_waker: AtomicWaker::new(),
- rx_waker: AtomicWaker::new(),
}
}
}
@@ -593,6 +599,8 @@ pub(crate) mod sealed {
fn registers() -> crate::can::fd::peripheral::Registers;
fn ram() -> &'static crate::pac::fdcanram::Fdcanram;
fn state() -> &'static State;
+ unsafe fn mut_state() -> &'static mut State;
+ fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp;
#[cfg(not(stm32h7))]
fn configure_msg_ram() {}
@@ -694,10 +702,31 @@ macro_rules! impl_fdcan {
fn ram() -> &'static crate::pac::fdcanram::Fdcanram {
&crate::pac::$msg_ram_inst
}
- fn state() -> &'static sealed::State {
- static STATE: sealed::State = sealed::State::new();
- &STATE
+ unsafe fn mut_state() -> & 'static mut sealed::State {
+ static mut STATE: sealed::State = sealed::State::new();
+ & mut STATE
}
+ fn state() -> &'static sealed::State {
+ unsafe { peripherals::$inst::mut_state() }
+ }
+
+#[cfg(feature = "time")]
+fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
+ let now_embassy = embassy_time::Instant::now();
+ if ns_per_timer_tick == 0 {
+ return now_embassy;
+ }
+ let cantime = { Self::regs().tscv().read().tsc() };
+ let delta = cantime.overflowing_sub(ts_val).0 as u64;
+ let ns = ns_per_timer_tick * delta as u64;
+ now_embassy - embassy_time::Duration::from_nanos(ns)
+}
+
+#[cfg(not(feature = "time"))]
+fn calc_timestamp(_ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
+ ts_val
+}
+
}
impl Instance for peripherals::$inst {}
From 5ad291b708528b5772d6ebcc9309fbd3f8a002c8 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 17 Feb 2024 18:12:47 +1000
Subject: [PATCH 250/392] Add a buffered mode.
---
embassy-stm32/src/can/fdcan.rs | 233 ++++++++++++++++++++++++++++++++
examples/stm32g4/src/bin/can.rs | 97 ++++++++++++-
2 files changed, 323 insertions(+), 7 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 42ce73ded..3ae330e14 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -5,6 +5,8 @@ use core::task::Poll;
pub mod fd;
use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use embassy_sync::channel::Channel;
use fd::config::*;
use fd::filter::*;
@@ -49,6 +51,26 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
match &T::state().tx_mode {
sealed::TxMode::NonBuffered(waker) => waker.wake(),
+ sealed::TxMode::ClassicBuffered(buf) => {
+ if !T::registers().tx_queue_is_full() {
+ match buf.tx_receiver.try_receive() {
+ Ok(frame) => {
+ _ = T::registers().write_classic(&frame);
+ }
+ Err(_) => {}
+ }
+ }
+ }
+ sealed::TxMode::FdBuffered(buf) => {
+ if !T::registers().tx_queue_is_full() {
+ match buf.tx_receiver.try_receive() {
+ Ok(frame) => {
+ _ = T::registers().write_fd(&frame);
+ }
+ Err(_) => {}
+ }
+ }
+ }
}
}
@@ -405,6 +427,179 @@ where
)
}
+ /// Return a buffered instance of driver without CAN FD support. User must supply Buffers
+ pub fn buffered<const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>(
+ &self,
+ tx_buf: &'static mut TxBuf<TX_BUF_SIZE>,
+ rxb: &'static mut RxBuf<RX_BUF_SIZE>,
+ ) -> BufferedCan<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE> {
+ BufferedCan::new(PhantomData::<T>, T::regs(), self._mode, tx_buf, rxb)
+ }
+
+ /// Return a buffered instance of driver with CAN FD support. User must supply Buffers
+ pub fn buffered_fd<const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>(
+ &self,
+ tx_buf: &'static mut TxFdBuf<TX_BUF_SIZE>,
+ rxb: &'static mut RxFdBuf<RX_BUF_SIZE>,
+ ) -> BufferedCanFd<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE> {
+ BufferedCanFd::new(PhantomData::<T>, T::regs(), self._mode, tx_buf, rxb)
+ }
+}
+
+/// User supplied buffer for RX Buffering
+pub type RxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, (ClassicFrame, Timestamp), BUF_SIZE>;
+
+/// User supplied buffer for TX buffering
+pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, ClassicFrame, BUF_SIZE>;
+
+/// Buffered FDCAN Instance
+#[allow(dead_code)]
+pub struct BufferedCan<'d, T: Instance, M: FdcanOperatingMode, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
+ _instance1: PhantomData<T>,
+ _instance2: &'d crate::pac::can::Fdcan,
+ _mode: PhantomData<M>,
+ tx_buf: &'static TxBuf<TX_BUF_SIZE>,
+ rx_buf: &'static RxBuf<RX_BUF_SIZE>,
+}
+
+impl<'c, 'd, T: Instance, M: Transmit, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
+ BufferedCan<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
+where
+ M: FdcanOperatingMode,
+{
+ fn new(
+ _instance1: PhantomData<T>,
+ _instance2: &'d crate::pac::can::Fdcan,
+ _mode: PhantomData<M>,
+ tx_buf: &'static TxBuf<TX_BUF_SIZE>,
+ rx_buf: &'static RxBuf<RX_BUF_SIZE>,
+ ) -> Self {
+ BufferedCan {
+ _instance1,
+ _instance2,
+ _mode,
+ tx_buf,
+ rx_buf,
+ }
+ .setup()
+ }
+
+ fn setup(self) -> Self {
+ // We don't want interrupts being processed while we change modes.
+ critical_section::with(|_| unsafe {
+ let rx_inner = sealed::ClassicBufferedRxInner {
+ rx_sender: self.rx_buf.sender().into(),
+ };
+ let tx_inner = sealed::ClassicBufferedTxInner {
+ tx_receiver: self.tx_buf.receiver().into(),
+ };
+ T::mut_state().rx_mode = sealed::RxMode::ClassicBuffered(rx_inner);
+ T::mut_state().tx_mode = sealed::TxMode::ClassicBuffered(tx_inner);
+ });
+ self
+ }
+
+ /// Async write frame to TX buffer.
+ pub async fn write(&mut self, frame: ClassicFrame) {
+ self.tx_buf.send(frame).await;
+ T::IT0Interrupt::pend(); // Wake for Tx
+ }
+
+ /// Async read frame from RX buffer.
+ pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
+ Ok(self.rx_buf.receive().await)
+ }
+}
+
+impl<'c, 'd, T: Instance, M, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
+ for BufferedCan<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
+where
+ M: FdcanOperatingMode,
+{
+ fn drop(&mut self) {
+ critical_section::with(|_| unsafe {
+ T::mut_state().rx_mode = sealed::RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+ T::mut_state().tx_mode = sealed::TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+ });
+ }
+}
+
+/// User supplied buffer for RX Buffering
+pub type RxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, (FdFrame, Timestamp), BUF_SIZE>;
+
+/// User supplied buffer for TX buffering
+pub type TxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, FdFrame, BUF_SIZE>;
+
+/// Buffered FDCAN Instance
+#[allow(dead_code)]
+pub struct BufferedCanFd<'d, T: Instance, M: FdcanOperatingMode, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
+ _instance1: PhantomData<T>,
+ _instance2: &'d crate::pac::can::Fdcan,
+ _mode: PhantomData<M>,
+ tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
+ rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
+}
+
+impl<'c, 'd, T: Instance, M: Transmit, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
+ BufferedCanFd<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
+where
+ M: FdcanOperatingMode,
+{
+ fn new(
+ _instance1: PhantomData<T>,
+ _instance2: &'d crate::pac::can::Fdcan,
+ _mode: PhantomData<M>,
+ tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
+ rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
+ ) -> Self {
+ BufferedCanFd {
+ _instance1,
+ _instance2,
+ _mode,
+ tx_buf,
+ rx_buf,
+ }
+ .setup()
+ }
+
+ fn setup(self) -> Self {
+ // We don't want interrupts being processed while we change modes.
+ critical_section::with(|_| unsafe {
+ let rx_inner = sealed::FdBufferedRxInner {
+ rx_sender: self.rx_buf.sender().into(),
+ };
+ let tx_inner = sealed::FdBufferedTxInner {
+ tx_receiver: self.tx_buf.receiver().into(),
+ };
+ T::mut_state().rx_mode = sealed::RxMode::FdBuffered(rx_inner);
+ T::mut_state().tx_mode = sealed::TxMode::FdBuffered(tx_inner);
+ });
+ self
+ }
+
+ /// Async write frame to TX buffer.
+ pub async fn write(&mut self, frame: FdFrame) {
+ self.tx_buf.send(frame).await;
+ T::IT0Interrupt::pend(); // Wake for Tx
+ }
+
+ /// Async read frame from RX buffer.
+ pub async fn read(&mut self) -> Result<(FdFrame, Timestamp), BusError> {
+ Ok(self.rx_buf.receive().await)
+ }
+}
+
+impl<'c, 'd, T: Instance, M, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
+ for BufferedCanFd<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
+where
+ M: FdcanOperatingMode,
+{
+ fn drop(&mut self) {
+ critical_section::with(|_| unsafe {
+ T::mut_state().rx_mode = sealed::RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+ T::mut_state().tx_mode = sealed::TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+ });
+ }
}
/// FDCAN Rx only Instance
@@ -456,18 +651,39 @@ pub(crate) mod sealed {
use core::future::poll_fn;
use core::task::Poll;
+ use embassy_sync::channel::{DynamicReceiver, DynamicSender};
use embassy_sync::waitqueue::AtomicWaker;
use crate::can::_version::{BusError, Timestamp};
use crate::can::frame::{ClassicFrame, FdFrame};
+
+ pub struct ClassicBufferedRxInner {
+ pub rx_sender: DynamicSender<'static, (ClassicFrame, Timestamp)>,
+ }
+ pub struct ClassicBufferedTxInner {
+ pub tx_receiver: DynamicReceiver<'static, ClassicFrame>,
+ }
+
+ pub struct FdBufferedRxInner {
+ pub rx_sender: DynamicSender<'static, (FdFrame, Timestamp)>,
+ }
+ pub struct FdBufferedTxInner {
+ pub tx_receiver: DynamicReceiver<'static, FdFrame>,
+ }
+
pub enum RxMode {
NonBuffered(AtomicWaker),
+ ClassicBuffered(ClassicBufferedRxInner),
+ FdBuffered(FdBufferedRxInner),
}
impl RxMode {
pub fn register(&self, arg: &core::task::Waker) {
match self {
RxMode::NonBuffered(waker) => waker.register(arg),
+ _ => {
+ panic!("Bad Mode")
+ }
}
}
@@ -477,6 +693,18 @@ pub(crate) mod sealed {
RxMode::NonBuffered(waker) => {
waker.wake();
}
+ RxMode::ClassicBuffered(buf) => {
+ if let Some(r) = T::registers().read_classic(fifonr) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, r.1);
+ let _ = buf.rx_sender.try_send((r.0, ts));
+ }
+ }
+ RxMode::FdBuffered(buf) => {
+ if let Some(r) = T::registers().read_fd(fifonr) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, r.1);
+ let _ = buf.rx_sender.try_send((r.0, ts));
+ }
+ }
}
}
@@ -523,6 +751,8 @@ pub(crate) mod sealed {
pub enum TxMode {
NonBuffered(AtomicWaker),
+ ClassicBuffered(ClassicBufferedTxInner),
+ FdBuffered(FdBufferedTxInner),
}
impl TxMode {
@@ -531,6 +761,9 @@ pub(crate) mod sealed {
TxMode::NonBuffered(waker) => {
waker.register(arg);
}
+ _ => {
+ panic!("Bad mode");
+ }
}
}
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
index 5ff4f0ef0..043ca7144 100644
--- a/examples/stm32g4/src/bin/can.rs
+++ b/examples/stm32g4/src/bin/can.rs
@@ -5,6 +5,7 @@ use embassy_executor::Spawner;
use embassy_stm32::peripherals::*;
use embassy_stm32::{bind_interrupts, can, Config};
use embassy_time::Timer;
+use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
@@ -28,13 +29,17 @@ async fn main(_spawner: Spawner) {
// 250k bps
can.set_bitrate(250_000);
+ let use_fd = false;
+
// 1M bps
- can.set_fd_data_bitrate(1_000_000, false);
+ if use_fd {
+ can.set_fd_data_bitrate(1_000_000, false);
+ }
info!("Configured");
- //let mut can = can.into_normal_mode();
- let mut can = can.into_internal_loopback_mode();
+ let mut can = can.into_normal_mode();
+ //let mut can = can.into_internal_loopback_mode();
let mut i = 0;
let mut last_read_ts = embassy_time::Instant::now();
@@ -68,11 +73,17 @@ async fn main(_spawner: Spawner) {
}
// Use the FD API's even if we don't get FD packets.
- loop {
- let frame = can::frame::FdFrame::new_extended(0x123456F, &[i; 16]).unwrap();
- info!("Writing frame using FD API");
- _ = can.write_fd(&frame).await;
+ loop {
+ if use_fd {
+ let frame = can::frame::FdFrame::new_extended(0x123456F, &[i; 16]).unwrap();
+ info!("Writing frame using FD API");
+ _ = can.write_fd(&frame).await;
+ } else {
+ let frame = can::frame::FdFrame::new_extended(0x123456F, &[i; 8]).unwrap();
+ info!("Writing frame using FD API");
+ _ = can.write_fd(&frame).await;
+ }
match can.read_fd().await {
Ok((rx_frame, ts)) => {
@@ -96,6 +107,7 @@ async fn main(_spawner: Spawner) {
}
}
+ i = 0;
let (mut tx, mut rx) = can.split();
// With split
loop {
@@ -120,5 +132,76 @@ async fn main(_spawner: Spawner) {
Timer::after_millis(250).await;
i += 1;
+
+ if i > 2 {
+ break;
+ }
+ }
+
+ let can = can::Fdcan::join(tx, rx);
+
+ info!("\n\n\nBuffered\n");
+ if use_fd {
+ static TX_BUF: StaticCell<can::TxFdBuf<8>> = StaticCell::new();
+ static RX_BUF: StaticCell<can::RxFdBuf<10>> = StaticCell::new();
+ let mut can = can.buffered_fd(
+ TX_BUF.init(can::TxFdBuf::<8>::new()),
+ RX_BUF.init(can::RxFdBuf::<10>::new()),
+ );
+ loop {
+ let frame = can::frame::FdFrame::new_extended(0x123456F, &[i; 16]).unwrap();
+ info!("Writing frame");
+
+ _ = can.write(frame).await;
+
+ match can.read().await {
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {} {:02x} --- {}ms",
+ rx_frame.header().len(),
+ rx_frame.data()[0..rx_frame.header().len() as usize],
+ delta,
+ )
+ }
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ }
+ } else {
+ static TX_BUF: StaticCell<can::TxBuf<8>> = StaticCell::new();
+ static RX_BUF: StaticCell<can::RxBuf<10>> = StaticCell::new();
+ let mut can = can.buffered(
+ TX_BUF.init(can::TxBuf::<8>::new()),
+ RX_BUF.init(can::RxBuf::<10>::new()),
+ );
+ loop {
+ let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
+ info!("Writing frame");
+
+ _ = can.write(frame).await;
+
+ match can.read().await {
+ Ok((rx_frame, ts)) => {
+ let delta = (ts - last_read_ts).as_millis();
+ last_read_ts = ts;
+ info!(
+ "Rx: {} {:02x} --- {}ms",
+ rx_frame.header().len(),
+ rx_frame.data()[0..rx_frame.header().len() as usize],
+ delta,
+ )
+ }
+ Err(_err) => error!("Error in frame"),
+ }
+
+ Timer::after_millis(250).await;
+
+ i += 1;
+ }
}
}
From 1aa999c2a825bdaf6fa4c980f47428d9b1d9263f Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Sat, 17 Feb 2024 12:52:20 +0200
Subject: [PATCH 251/392] nrf: Use .is_empty() instead of .len() == 0
---
embassy-nrf/src/pdm.rs | 2 +-
embassy-nrf/src/qspi.rs | 8 ++++----
embassy-nrf/src/rng.rs | 2 +-
embassy-nrf/src/twim.rs | 6 +++---
embassy-nrf/src/uarte.rs | 10 +++++-----
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/embassy-nrf/src/pdm.rs b/embassy-nrf/src/pdm.rs
index 6ddc4dc0a..754d38310 100644
--- a/embassy-nrf/src/pdm.rs
+++ b/embassy-nrf/src/pdm.rs
@@ -185,7 +185,7 @@ impl<'d, T: Instance> Pdm<'d, T> {
/// Sample data into the given buffer
pub async fn sample(&mut self, buffer: &mut [i16]) -> Result<(), Error> {
- if buffer.len() == 0 {
+ if buffer.is_empty() {
return Err(Error::BufferZeroLength);
}
if buffer.len() > EASY_DMA_SIZE {
diff --git a/embassy-nrf/src/qspi.rs b/embassy-nrf/src/qspi.rs
index 8eec09c96..4134a4c87 100755
--- a/embassy-nrf/src/qspi.rs
+++ b/embassy-nrf/src/qspi.rs
@@ -402,7 +402,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
/// a raw bus, not with flash memory.
pub async fn read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> {
// Avoid blocking_wait_ready() blocking forever on zero-length buffers.
- if data.len() == 0 {
+ if data.is_empty() {
return Ok(());
}
@@ -423,7 +423,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
/// a raw bus, not with flash memory.
pub async fn write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> {
// Avoid blocking_wait_ready() blocking forever on zero-length buffers.
- if data.len() == 0 {
+ if data.is_empty() {
return Ok(());
}
@@ -444,7 +444,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
/// a raw bus, not with flash memory.
pub fn blocking_read_raw(&mut self, address: u32, data: &mut [u8]) -> Result<(), Error> {
// Avoid blocking_wait_ready() blocking forever on zero-length buffers.
- if data.len() == 0 {
+ if data.is_empty() {
return Ok(());
}
@@ -460,7 +460,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
/// a raw bus, not with flash memory.
pub fn blocking_write_raw(&mut self, address: u32, data: &[u8]) -> Result<(), Error> {
// Avoid blocking_wait_ready() blocking forever on zero-length buffers.
- if data.len() == 0 {
+ if data.is_empty() {
return Ok(());
}
diff --git a/embassy-nrf/src/rng.rs b/embassy-nrf/src/rng.rs
index 40b73231b..1c463fb7c 100644
--- a/embassy-nrf/src/rng.rs
+++ b/embassy-nrf/src/rng.rs
@@ -108,7 +108,7 @@ impl<'d, T: Instance> Rng<'d, T> {
/// Fill the buffer with random bytes.
pub async fn fill_bytes(&mut self, dest: &mut [u8]) {
- if dest.len() == 0 {
+ if dest.is_empty() {
return; // Nothing to fill
}
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index da8e15d02..83971463f 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -372,7 +372,7 @@ impl<'d, T: Instance> Twim<'d, T> {
// Start write operation.
r.shorts.write(|w| w.lasttx_stop().enabled());
r.tasks_starttx.write(|w| unsafe { w.bits(1) });
- if buffer.len() == 0 {
+ if buffer.is_empty() {
// With a zero-length buffer, LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves.
r.tasks_stop.write(|w| unsafe { w.bits(1) });
}
@@ -403,7 +403,7 @@ impl<'d, T: Instance> Twim<'d, T> {
// Start read operation.
r.shorts.write(|w| w.lastrx_stop().enabled());
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
- if buffer.len() == 0 {
+ if buffer.is_empty() {
// With a zero-length buffer, LASTRX doesn't fire (because there's no last byte!), so do the STOP ourselves.
r.tasks_stop.write(|w| unsafe { w.bits(1) });
}
@@ -447,7 +447,7 @@ impl<'d, T: Instance> Twim<'d, T> {
w
});
r.tasks_starttx.write(|w| unsafe { w.bits(1) });
- if wr_buffer.len() == 0 && rd_buffer.len() == 0 {
+ if wr_buffer.is_empty() && rd_buffer.is_empty() {
// With a zero-length buffer, LASTRX/LASTTX doesn't fire (because there's no last byte!), so do the STOP ourselves.
// TODO handle when only one of the buffers is zero length
r.tasks_stop.write(|w| unsafe { w.bits(1) });
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index de2966ba5..3d486452f 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -386,7 +386,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
/// Same as [`write`](Self::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
pub async fn write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> {
- if buffer.len() == 0 {
+ if buffer.is_empty() {
return Ok(());
}
@@ -456,7 +456,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
/// Same as [`write_from_ram`](Self::write_from_ram) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
pub fn blocking_write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> {
- if buffer.len() == 0 {
+ if buffer.is_empty() {
return Ok(());
}
@@ -694,7 +694,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
/// Read bytes until the buffer is filled.
pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
- if buffer.len() == 0 {
+ if buffer.is_empty() {
return Ok(());
}
if buffer.len() > EASY_DMA_SIZE {
@@ -775,7 +775,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
///
/// Returns the amount of bytes read.
pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
- if buffer.len() == 0 {
+ if buffer.is_empty() {
return Ok(0);
}
if buffer.len() > EASY_DMA_SIZE {
@@ -848,7 +848,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
///
/// Returns the amount of bytes read.
pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
- if buffer.len() == 0 {
+ if buffer.is_empty() {
return Ok(0);
}
if buffer.len() > EASY_DMA_SIZE {
From bb2fb59a87d3aa1322cb13280287851d3ec39f59 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Sat, 17 Feb 2024 13:02:56 +0200
Subject: [PATCH 252/392] nrf: Remove useless borrows
---
embassy-nrf/src/buffered_uarte.rs | 2 +-
embassy-nrf/src/pwm.rs | 4 ++--
embassy-nrf/src/twim.rs | 4 ++--
embassy-nrf/src/twis.rs | 2 +-
embassy-nrf/src/uarte.rs | 10 +++++-----
5 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 2c620798d..fb72422bd 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -377,7 +377,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
});
// Enable UARTE instance
- apply_workaround_for_enable_anomaly(&r);
+ apply_workaround_for_enable_anomaly(r);
r.enable.write(|w| w.enable().enabled());
// Configure byte counter.
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index e0583b770..bfcff60a1 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -697,7 +697,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
// Enable
r.enable.write(|w| w.enable().enabled());
- r.seq0.ptr.write(|w| unsafe { w.bits((&pwm.duty).as_ptr() as u32) });
+ r.seq0.ptr.write(|w| unsafe { w.bits((pwm.duty).as_ptr() as u32) });
r.seq0.cnt.write(|w| unsafe { w.bits(4) });
r.seq0.refresh.write(|w| unsafe { w.bits(0) });
@@ -748,7 +748,7 @@ impl<'d, T: Instance> SimplePwm<'d, T> {
self.duty[channel] = duty & 0x7FFF;
// reload ptr in case self was moved
- r.seq0.ptr.write(|w| unsafe { w.bits((&self.duty).as_ptr() as u32) });
+ r.seq0.ptr.write(|w| unsafe { w.bits((self.duty).as_ptr() as u32) });
// defensive before seqstart
compiler_fence(Ordering::SeqCst);
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index 83971463f..30699283f 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -469,7 +469,7 @@ impl<'d, T: Instance> Twim<'d, T> {
trace!("Copying TWIM tx buffer into RAM for DMA");
let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
tx_ram_buf.copy_from_slice(wr_buffer);
- self.setup_write_read_from_ram(address, &tx_ram_buf, rd_buffer, inten)
+ self.setup_write_read_from_ram(address, tx_ram_buf, rd_buffer, inten)
}
Err(error) => Err(error),
}
@@ -482,7 +482,7 @@ impl<'d, T: Instance> Twim<'d, T> {
trace!("Copying TWIM tx buffer into RAM for DMA");
let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
tx_ram_buf.copy_from_slice(wr_buffer);
- self.setup_write_from_ram(address, &tx_ram_buf, inten)
+ self.setup_write_from_ram(address, tx_ram_buf, inten)
}
Err(error) => Err(error),
}
diff --git a/embassy-nrf/src/twis.rs b/embassy-nrf/src/twis.rs
index c6c020557..415150447 100644
--- a/embassy-nrf/src/twis.rs
+++ b/embassy-nrf/src/twis.rs
@@ -577,7 +577,7 @@ impl<'d, T: Instance> Twis<'d, T> {
trace!("Copying TWIS tx buffer into RAM for DMA");
let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
tx_ram_buf.copy_from_slice(wr_buffer);
- self.setup_respond_from_ram(&tx_ram_buf, inten)
+ self.setup_respond_from_ram(tx_ram_buf, inten)
}
Err(error) => Err(error),
}
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 3d486452f..67b3feae7 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -308,7 +308,7 @@ fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
r.events_txstarted.reset();
// Enable
- apply_workaround_for_enable_anomaly(&r);
+ apply_workaround_for_enable_anomaly(r);
r.enable.write(|w| w.enable().enabled());
}
@@ -378,7 +378,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
trace!("Copying UARTE tx buffer into RAM for DMA");
let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
ram_buf.copy_from_slice(buffer);
- self.write_from_ram(&ram_buf).await
+ self.write_from_ram(ram_buf).await
}
Err(error) => Err(error),
}
@@ -448,7 +448,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
trace!("Copying UARTE tx buffer into RAM for DMA");
let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
ram_buf.copy_from_slice(buffer);
- self.blocking_write_from_ram(&ram_buf)
+ self.blocking_write_from_ram(ram_buf)
}
Err(error) => Err(error),
}
@@ -504,7 +504,7 @@ impl<'a, T: Instance> Drop for UarteTx<'a, T> {
let s = T::state();
- drop_tx_rx(&r, &s);
+ drop_tx_rx(r, s);
}
}
@@ -744,7 +744,7 @@ impl<'a, T: Instance> Drop for UarteRx<'a, T> {
let s = T::state();
- drop_tx_rx(&r, &s);
+ drop_tx_rx(r, s);
}
}
From a8710e943d620f3da878821ec74d44bfae0f9fb2 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Sat, 17 Feb 2024 13:08:53 +0200
Subject: [PATCH 253/392] nrf: Drop needless let
---
embassy-nrf/src/pwm.rs | 4 ++--
embassy-nrf/src/qdec.rs | 5 ++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/embassy-nrf/src/pwm.rs b/embassy-nrf/src/pwm.rs
index bfcff60a1..833370d4b 100644
--- a/embassy-nrf/src/pwm.rs
+++ b/embassy-nrf/src/pwm.rs
@@ -444,7 +444,7 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
return Err(Error::SequenceTimesAtLeastOne);
}
- let _ = self.stop();
+ self.stop();
let r = T::regs();
@@ -507,7 +507,7 @@ impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
impl<'d, 's, T: Instance> Drop for Sequencer<'d, 's, T> {
fn drop(&mut self) {
- let _ = self.stop();
+ self.stop();
}
}
diff --git a/embassy-nrf/src/qdec.rs b/embassy-nrf/src/qdec.rs
index 2aa50a2ba..932790d4f 100644
--- a/embassy-nrf/src/qdec.rs
+++ b/embassy-nrf/src/qdec.rs
@@ -172,7 +172,7 @@ impl<'d, T: Instance> Qdec<'d, T> {
t.intenset.write(|w| w.reportrdy().set());
unsafe { t.tasks_readclracc.write(|w| w.bits(1)) };
- let value = poll_fn(|cx| {
+ poll_fn(|cx| {
T::state().waker.register(cx.waker());
if t.events_reportrdy.read().bits() == 0 {
return Poll::Pending;
@@ -182,8 +182,7 @@ impl<'d, T: Instance> Qdec<'d, T> {
Poll::Ready(acc as i16)
}
})
- .await;
- value
+ .await
}
}
From 580ab484515d8a75f514bd34a5041090ffd9248c Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Sat, 17 Feb 2024 13:18:36 +0200
Subject: [PATCH 254/392] nrf: More nits cleaned up - useless cast and struct
item
---
embassy-nrf/src/nvmc.rs | 2 +-
embassy-nrf/src/uarte.rs | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-nrf/src/nvmc.rs b/embassy-nrf/src/nvmc.rs
index de840b886..4f9eda167 100644
--- a/embassy-nrf/src/nvmc.rs
+++ b/embassy-nrf/src/nvmc.rs
@@ -160,7 +160,7 @@ impl<'d> NorFlash for Nvmc<'d> {
if offset as usize + bytes.len() > FLASH_SIZE {
return Err(Error::OutOfBounds);
}
- if offset as usize % 4 != 0 || bytes.len() as usize % 4 != 0 {
+ if offset as usize % 4 != 0 || bytes.len() % 4 != 0 {
return Err(Error::Unaligned);
}
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 67b3feae7..9e5b85dea 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -619,7 +619,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
UarteRxWithIdle {
rx: self,
timer,
- ppi_ch1: ppi_ch1,
+ ppi_ch1,
_ppi_ch2: ppi_ch2,
}
}
From 7f2f701c87fbbced32c5586bc7b9a3b61ad25c8d Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Sat, 17 Feb 2024 13:20:25 +0200
Subject: [PATCH 255/392] nrf: Remove useless returns
---
embassy-nrf/src/qdec.rs | 2 +-
embassy-nrf/src/temp.rs | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-nrf/src/qdec.rs b/embassy-nrf/src/qdec.rs
index 932790d4f..9455ec925 100644
--- a/embassy-nrf/src/qdec.rs
+++ b/embassy-nrf/src/qdec.rs
@@ -175,7 +175,7 @@ impl<'d, T: Instance> Qdec<'d, T> {
poll_fn(|cx| {
T::state().waker.register(cx.waker());
if t.events_reportrdy.read().bits() == 0 {
- return Poll::Pending;
+ Poll::Pending
} else {
t.events_reportrdy.reset();
let acc = t.accread.read().bits();
diff --git a/embassy-nrf/src/temp.rs b/embassy-nrf/src/temp.rs
index 5e2998b10..ed4a47713 100644
--- a/embassy-nrf/src/temp.rs
+++ b/embassy-nrf/src/temp.rs
@@ -83,7 +83,7 @@ impl<'d> Temp<'d> {
let value = poll_fn(|cx| {
WAKER.register(cx.waker());
if t.events_datardy.read().bits() == 0 {
- return Poll::Pending;
+ Poll::Pending
} else {
t.events_datardy.reset();
let raw = t.temp.read().bits();
From 8507b0ad30d8b801545046e8789aea4f68ec3f22 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Sat, 17 Feb 2024 13:24:10 +0200
Subject: [PATCH 256/392] nrf: Remove useless lifetimes
---
embassy-nrf/src/twim.rs | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/embassy-nrf/src/twim.rs b/embassy-nrf/src/twim.rs
index 30699283f..24810a08c 100644
--- a/embassy-nrf/src/twim.rs
+++ b/embassy-nrf/src/twim.rs
@@ -779,7 +779,7 @@ mod eh02 {
impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Write for Twim<'a, T> {
type Error = Error;
- fn write<'w>(&mut self, addr: u8, bytes: &'w [u8]) -> Result<(), Error> {
+ fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
if slice_in_ram(bytes) {
self.blocking_write(addr, bytes)
} else {
@@ -796,7 +796,7 @@ mod eh02 {
impl<'a, T: Instance> embedded_hal_02::blocking::i2c::Read for Twim<'a, T> {
type Error = Error;
- fn read<'w>(&mut self, addr: u8, bytes: &'w mut [u8]) -> Result<(), Error> {
+ fn read(&mut self, addr: u8, bytes: &mut [u8]) -> Result<(), Error> {
self.blocking_read(addr, bytes)
}
}
@@ -847,10 +847,10 @@ impl<'d, T: Instance> embedded_hal_1::i2c::I2c for Twim<'d, T> {
self.blocking_write_read(address, wr_buffer, rd_buffer)
}
- fn transaction<'a>(
+ fn transaction(
&mut self,
_address: u8,
- _operations: &mut [embedded_hal_1::i2c::Operation<'a>],
+ _operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
todo!();
}
From 6734f52676a9669586492f6c203c10f354f6cf04 Mon Sep 17 00:00:00 2001
From: Andelf <andelf@gmail.com>
Date: Sat, 17 Feb 2024 20:44:59 +0800
Subject: [PATCH 257/392] rp/gpio: fix wrong io _bank calc
---
embassy-rp/src/gpio.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-rp/src/gpio.rs b/embassy-rp/src/gpio.rs
index a121a8036..62eeb4cf6 100644
--- a/embassy-rp/src/gpio.rs
+++ b/embassy-rp/src/gpio.rs
@@ -815,7 +815,7 @@ pub(crate) mod sealed {
#[inline]
fn _bank(&self) -> Bank {
- match self.pin_bank() & 0x20 {
+ match self.pin_bank() >> 5 {
#[cfg(feature = "qspi-as-gpio")]
1 => Bank::Qspi,
_ => Bank::Bank0,
From dd9f0d9d9e73feffce371ab7fda714b09b268715 Mon Sep 17 00:00:00 2001
From: Zach <zachvv11@gmail.com>
Date: Sat, 17 Feb 2024 12:04:53 -0600
Subject: [PATCH 258/392] support u5 flash
---
embassy-stm32/src/flash/mod.rs | 3 +-
embassy-stm32/src/flash/u5.rs | 105 ++++++++++++++++++++++++++++++
examples/stm32u5/src/bin/flash.rs | 55 ++++++++++++++++
3 files changed, 162 insertions(+), 1 deletion(-)
create mode 100644 embassy-stm32/src/flash/u5.rs
create mode 100644 examples/stm32u5/src/bin/flash.rs
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 47232f4a4..4f43a7a48 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -101,10 +101,11 @@ pub enum FlashBank {
#[cfg_attr(any(flash_g0, flash_g4), path = "g.rs")]
#[cfg_attr(flash_h7, path = "h7.rs")]
#[cfg_attr(flash_h7ab, path = "h7.rs")]
+#[cfg_attr(flash_u5, path = "u5.rs")]
#[cfg_attr(
not(any(
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f1, flash_f3, flash_f4, flash_f7, flash_g0,
- flash_g4, flash_h7, flash_h7ab
+ flash_g4, flash_h7, flash_h7ab, flash_u5
)),
path = "other.rs"
)]
diff --git a/embassy-stm32/src/flash/u5.rs b/embassy-stm32/src/flash/u5.rs
new file mode 100644
index 000000000..3787082f9
--- /dev/null
+++ b/embassy-stm32/src/flash/u5.rs
@@ -0,0 +1,105 @@
+use core::convert::TryInto;
+use core::ptr::write_volatile;
+use core::sync::atomic::{fence, Ordering};
+
+use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+
+pub(crate) const fn is_default_layout() -> bool {
+ true
+}
+
+pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
+ &FLASH_REGIONS
+}
+
+pub(crate) unsafe fn lock() {
+ pac::FLASH.seccr().modify(|w| w.set_lock(true));
+}
+
+pub(crate) unsafe fn unlock() {
+ if pac::FLASH.seccr().read().lock() {
+ pac::FLASH.seckeyr().write_value(0x4567_0123);
+ pac::FLASH.seckeyr().write_value(0xCDEF_89AB);
+ }
+}
+
+pub(crate) unsafe fn enable_blocking_write() {
+ assert_eq!(0, WRITE_SIZE % 4);
+
+ pac::FLASH.seccr().write(|w| {
+ w.set_pg(pac::flash::vals::SeccrPg::B_0X1);
+ });
+}
+
+pub(crate) unsafe fn disable_blocking_write() {
+ pac::FLASH.seccr().write(|w| w.set_pg(pac::flash::vals::SeccrPg::B_0X0));
+}
+
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+ let mut address = start_address;
+ for val in buf.chunks(4) {
+ write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
+ address += val.len() as u32;
+
+ // prevents parallelism errors
+ fence(Ordering::SeqCst);
+ }
+
+ blocking_wait_ready()
+}
+
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+ pac::FLASH.seccr().modify(|w| {
+ w.set_per(pac::flash::vals::SeccrPer::B_0X1);
+ w.set_pnb(sector.index_in_bank)
+ });
+
+ pac::FLASH.seccr().modify(|w| {
+ w.set_strt(true);
+ });
+
+ let ret: Result<(), Error> = blocking_wait_ready();
+ pac::FLASH
+ .seccr()
+ .modify(|w| w.set_per(pac::flash::vals::SeccrPer::B_0X0));
+ clear_all_err();
+ ret
+}
+
+pub(crate) unsafe fn clear_all_err() {
+ // read and write back the same value.
+ // This clears all "write 1 to clear" bits.
+ pac::FLASH.secsr().modify(|_| {});
+}
+
+unsafe fn blocking_wait_ready() -> Result<(), Error> {
+ loop {
+ let sr = pac::FLASH.secsr().read();
+
+ if !sr.bsy() {
+ if sr.pgserr() {
+ return Err(Error::Seq);
+ }
+
+ if sr.sizerr() {
+ return Err(Error::Size);
+ }
+
+ if sr.pgaerr() {
+ return Err(Error::Unaligned);
+ }
+
+ if sr.wrperr() {
+ return Err(Error::Protected);
+ }
+
+ if sr.progerr() {
+ return Err(Error::Prog);
+ }
+
+ return Ok(());
+ }
+ }
+}
diff --git a/examples/stm32u5/src/bin/flash.rs b/examples/stm32u5/src/bin/flash.rs
new file mode 100644
index 000000000..e4fd6bb9c
--- /dev/null
+++ b/examples/stm32u5/src/bin/flash.rs
@@ -0,0 +1,55 @@
+#![no_std]
+#![no_main]
+
+use defmt::{info, unwrap};
+use embassy_executor::Spawner;
+use embassy_stm32::flash::Flash;
+use embassy_time::Timer;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p = embassy_stm32::init(Default::default());
+ info!("Hello Flash!");
+
+ const ADDR: u32 = 0x8_0000; // This is the offset into the third region, the absolute address is 4x32K + 128K + 0x8_0000.
+
+ // wait a bit before accessing the flash
+ Timer::after_millis(300).await;
+
+ let mut f = Flash::new_blocking(p.FLASH).into_blocking_regions().bank1_region;
+
+ info!("Reading...");
+ let mut buf = [0u8; 32];
+ unwrap!(f.blocking_read(ADDR, &mut buf));
+ info!("Read: {=[u8]:x}", buf);
+
+ info!("Erasing...");
+ unwrap!(f.blocking_erase(ADDR, ADDR + 256 * 1024));
+
+ info!("Reading...");
+ let mut buf = [0u8; 32];
+ unwrap!(f.blocking_read(ADDR, &mut buf));
+ info!("Read after erase: {=[u8]:x}", buf);
+
+ info!("Writing...");
+ unwrap!(f.blocking_write(
+ ADDR,
+ &[
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31, 32
+ ]
+ ));
+
+ info!("Reading...");
+ let mut buf = [0u8; 32];
+ unwrap!(f.blocking_read(ADDR, &mut buf));
+ info!("Read: {=[u8]:x}", buf);
+ assert_eq!(
+ &buf[..],
+ &[
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31, 32
+ ]
+ );
+}
From f9e7fc6e5e3a8c50fb425735a48e65040185413b Mon Sep 17 00:00:00 2001
From: Zach <zachvv11@gmail.com>
Date: Sat, 17 Feb 2024 14:00:03 -0600
Subject: [PATCH 259/392] u5 - add working rng example
---
examples/stm32u5/src/bin/rng.rs | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 examples/stm32u5/src/bin/rng.rs
diff --git a/examples/stm32u5/src/bin/rng.rs b/examples/stm32u5/src/bin/rng.rs
new file mode 100644
index 000000000..3a5bce097
--- /dev/null
+++ b/examples/stm32u5/src/bin/rng.rs
@@ -0,0 +1,25 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::rng::Rng;
+use embassy_stm32::{bind_interrupts, peripherals, rng};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ RNG => rng::InterruptHandler<peripherals::RNG>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p = embassy_stm32::init(Default::default());
+
+ info!("Hello World!");
+
+ let mut rng = Rng::new(p.RNG, Irqs);
+
+ let mut buf = [0u8; 16];
+ unwrap!(rng.async_fill_bytes(&mut buf).await);
+ info!("random bytes: {:02x}", buf);
+}
From eafa90cd0707298f354d5d1e496f8364117bd781 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sun, 18 Feb 2024 13:09:37 +1000
Subject: [PATCH 260/392] Remove the OperatingMode typestates
Instead have two explcit types(without the mode generic arg)types:
- One for config
- One for all operating modes
---
embassy-stm32/src/can/fd/peripheral.rs | 13 ++
embassy-stm32/src/can/fdcan.rs | 265 +++++++++++--------------
examples/stm32g4/src/bin/can.rs | 9 +-
examples/stm32h5/src/bin/can.rs | 3 +-
examples/stm32h7/src/bin/can.rs | 3 +-
tests/stm32/src/bin/fdcan.rs | 2 +-
6 files changed, 133 insertions(+), 162 deletions(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 487b8f413..0771d6fbb 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -481,6 +481,19 @@ impl Registers {
while self.regs.cccr().read().init() == true {}
}
+ /// Moves out of ConfigMode and into specified mode
+ #[inline]
+ pub fn into_mode(mut self, config: FdCanConfig, mode: crate::can::_version::FdcanOperatingMode) {
+ match mode {
+ crate::can::FdcanOperatingMode::InternalLoopbackMode => self.set_loopback_mode(LoopbackMode::Internal),
+ crate::can::FdcanOperatingMode::ExternalLoopbackMode => self.set_loopback_mode(LoopbackMode::External),
+ crate::can::FdcanOperatingMode::NormalOperationMode => self.set_normal_operations(true),
+ crate::can::FdcanOperatingMode::RestrictedOperationMode => self.set_restricted_operations(true),
+ crate::can::FdcanOperatingMode::BusMonitoringMode => self.set_bus_monitoring_mode(true),
+ }
+ self.leave_init_mode(config);
+ }
+
/// Moves out of ConfigMode and into InternalLoopbackMode
#[inline]
pub fn into_internal_loopback(mut self, config: FdCanConfig) {
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 3ae330e14..f1f6f935e 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -100,75 +100,50 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT1Interrupt> for IT1Interrup
unsafe fn on_interrupt() {}
}
-/// Allows for Transmit Operations
-pub trait Transmit {}
-/// Allows for Receive Operations
-pub trait Receive {}
-
-/// Allows for the FdCan Instance to be released or to enter ConfigMode
-pub struct PoweredDownMode;
-/// Allows for the configuration for the Instance
-pub struct ConfigMode;
-/// This mode can be used for a “Hot Selftest”, meaning the FDCAN can be tested without
-/// affecting a running CAN system connected to the FDCAN_TX and FDCAN_RX pins. In this
-/// mode, FDCAN_RX pin is disconnected from the FDCAN and FDCAN_TX pin is held
-/// recessive.
-pub struct InternalLoopbackMode;
-impl Transmit for InternalLoopbackMode {}
-impl Receive for InternalLoopbackMode {}
-/// This mode is provided for hardware self-test. To be independent from external stimulation,
-/// the FDCAN ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a
-/// data / remote frame) in Loop Back mode. In this mode the FDCAN performs an internal
-/// feedback from its transmit output to its receive input. The actual value of the FDCAN_RX
-/// input pin is disregarded by the FDCAN. The transmitted messages can be monitored at the
-/// FDCAN_TX transmit pin.
-pub struct ExternalLoopbackMode;
-impl Transmit for ExternalLoopbackMode {}
-impl Receive for ExternalLoopbackMode {}
-/// The normal use of the FdCan instance after configurations
-pub struct NormalOperationMode;
-impl Transmit for NormalOperationMode {}
-impl Receive for NormalOperationMode {}
-/// In Restricted operation mode the node is able to receive data and remote frames and to give
-/// acknowledge to valid frames, but it does not send data frames, remote frames, active error
-/// frames, or overload frames. In case of an error condition or overload condition, it does not
-/// send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize
-/// itself to the CAN communication. The error counters for transmit and receive are frozen while
-/// error logging (can_errors) is active. TODO: automatically enter in this mode?
-pub struct RestrictedOperationMode;
-impl Receive for RestrictedOperationMode {}
-/// In Bus monitoring mode (for more details refer to ISO11898-1, 10.12 Bus monitoring),
-/// the FDCAN is able to receive valid data frames and valid remote frames, but cannot start a
-/// transmission. In this mode, it sends only recessive bits on the CAN bus. If the FDCAN is
-/// required to send a dominant bit (ACK bit, overload flag, active error flag), the bit is
-/// rerouted internally so that the FDCAN can monitor it, even if the CAN bus remains in recessive
-/// state. In Bus monitoring mode the TXBRP register is held in reset state. The Bus monitoring
-/// mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
-/// of dominant bits.
-pub struct BusMonitoringMode;
-impl Receive for BusMonitoringMode {}
-/// Test mode must be used for production tests or self test only. The software control for
-/// FDCAN_TX pin interferes with all CAN protocol functions. It is not recommended to use test
-/// modes for application.
-pub struct TestMode;
-
-/// Operating modes trait
-pub trait FdcanOperatingMode {}
-impl FdcanOperatingMode for PoweredDownMode {}
-impl FdcanOperatingMode for ConfigMode {}
-impl FdcanOperatingMode for InternalLoopbackMode {}
-impl FdcanOperatingMode for ExternalLoopbackMode {}
-impl FdcanOperatingMode for NormalOperationMode {}
-impl FdcanOperatingMode for RestrictedOperationMode {}
-impl FdcanOperatingMode for BusMonitoringMode {}
-impl FdcanOperatingMode for TestMode {}
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Different operating modes
+pub enum FdcanOperatingMode {
+ //PoweredDownMode,
+ //ConfigMode,
+ /// This mode can be used for a “Hot Selftest”, meaning the FDCAN can be tested without
+ /// affecting a running CAN system connected to the FDCAN_TX and FDCAN_RX pins. In this
+ /// mode, FDCAN_RX pin is disconnected from the FDCAN and FDCAN_TX pin is held
+ /// recessive.
+ InternalLoopbackMode,
+ /// This mode is provided for hardware self-test. To be independent from external stimulation,
+ /// the FDCAN ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a
+ /// data / remote frame) in Loop Back mode. In this mode the FDCAN performs an internal
+ /// feedback from its transmit output to its receive input. The actual value of the FDCAN_RX
+ /// input pin is disregarded by the FDCAN. The transmitted messages can be monitored at the
+ /// FDCAN_TX transmit pin.
+ ExternalLoopbackMode,
+ /// The normal use of the Fdcan instance after configurations
+ NormalOperationMode,
+ /// In Restricted operation mode the node is able to receive data and remote frames and to give
+ /// acknowledge to valid frames, but it does not send data frames, remote frames, active error
+ /// frames, or overload frames. In case of an error condition or overload condition, it does not
+ /// send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize
+ /// itself to the CAN communication. The error counters for transmit and receive are frozen while
+ /// error logging (can_errors) is active. TODO: automatically enter in this mode?
+ RestrictedOperationMode,
+ /// In Bus monitoring mode (for more details refer to ISO11898-1, 10.12 Bus monitoring),
+ /// the FDCAN is able to receive valid data frames and valid remote frames, but cannot start a
+ /// transmission. In this mode, it sends only recessive bits on the CAN bus. If the FDCAN is
+ /// required to send a dominant bit (ACK bit, overload flag, active error flag), the bit is
+ /// rerouted internally so that the FDCAN can monitor it, even if the CAN bus remains in recessive
+ /// state. In Bus monitoring mode the TXBRP register is held in reset state. The Bus monitoring
+ /// mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission
+ /// of dominant bits.
+ BusMonitoringMode,
+ //TestMode,
+}
/// FDCAN Instance
-pub struct Fdcan<'d, T: Instance, M: FdcanOperatingMode> {
+pub struct FdcanConfigurator<'d, T: Instance> {
config: crate::can::fd::config::FdCanConfig,
/// Reference to internals.
instance: FdcanInstance<'d, T>,
- _mode: PhantomData<M>,
}
fn calc_ns_per_timer_tick<T: Instance>(mode: crate::can::fd::config::FrameTransmissionConfig) -> u64 {
@@ -186,7 +161,7 @@ fn calc_ns_per_timer_tick<T: Instance>(mode: crate::can::fd::config::FrameTransm
}
}
-impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
+impl<'d, T: Instance> FdcanConfigurator<'d, T> {
/// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
/// You must call [Fdcan::enable_non_blocking] to use the peripheral.
pub fn new(
@@ -196,7 +171,7 @@ impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
_irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
+ interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
+ 'd,
- ) -> Fdcan<'d, T, ConfigMode> {
+ ) -> FdcanConfigurator<'d, T> {
into_ref!(peri, rx, tx);
rx.set_as_af(rx.af_num(), AFType::Input);
@@ -245,7 +220,6 @@ impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
Self {
config,
instance: FdcanInstance(peri),
- _mode: PhantomData::<ConfigMode>,
}
}
@@ -272,7 +246,7 @@ impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
self.config = self.config.set_nominal_bit_timing(nbtr);
}
- /// Configures the bit timings for VBR data calculated from supplied bitrate.
+ /// Configures the bit timings for VBR data calculated from supplied bitrate. This also sets confit to allow can FD and VBR
pub fn set_fd_data_bitrate(&mut self, bitrate: u32, transceiver_delay_compensation: bool) {
let bit_timing = util::calc_can_timings(T::frequency(), bitrate).unwrap();
// Note, used existing calcluation for normal(non-VBR) bitrate, appears to work for 250k/1M
@@ -312,51 +286,47 @@ impl<'d, T: Instance> Fdcan<'d, T, ConfigMode> {
T::registers().msg_ram_mut().filters.flesa[i].activate(*f);
}
}
+
+ /// Start in mode.
+ pub fn start(self, mode: FdcanOperatingMode) -> Fdcan<'d, T> {
+ let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(self.config.frame_transmit);
+ critical_section::with(|_| unsafe {
+ T::mut_state().ns_per_timer_tick = ns_per_timer_tick;
+ });
+ T::registers().into_mode(self.config, mode);
+ let ret = Fdcan {
+ config: self.config,
+ instance: self.instance,
+ _mode: mode,
+ };
+ ret
+ }
+
+ /// Start, entering mode. Does same as start(mode)
+ pub fn into_normal_mode(self) -> Fdcan<'d, T> {
+ self.start(FdcanOperatingMode::NormalOperationMode)
+ }
+
+ /// Start, entering mode. Does same as start(mode)
+ pub fn into_internal_loopback_mode(self) -> Fdcan<'d, T> {
+ self.start(FdcanOperatingMode::InternalLoopbackMode)
+ }
+
+ /// Start, entering mode. Does same as start(mode)
+ pub fn into_external_loopback_mode(self) -> Fdcan<'d, T> {
+ self.start(FdcanOperatingMode::ExternalLoopbackMode)
+ }
}
-macro_rules! impl_transition {
- ($from_mode:ident, $to_mode:ident, $name:ident, $func: ident) => {
- impl<'d, T: Instance> Fdcan<'d, T, $from_mode> {
- /// Transition from $from_mode:ident mode to $to_mode:ident mode
- pub fn $name(self) -> Fdcan<'d, T, $to_mode> {
- let ns_per_timer_tick = calc_ns_per_timer_tick::<T>(self.config.frame_transmit);
- critical_section::with(|_| unsafe {
- T::mut_state().ns_per_timer_tick = ns_per_timer_tick;
- });
- T::registers().$func(self.config);
- let ret = Fdcan {
- config: self.config,
- instance: self.instance,
- _mode: PhantomData::<$to_mode>,
- };
- ret
- }
- }
- };
+/// FDCAN Instance
+pub struct Fdcan<'d, T: Instance> {
+ config: crate::can::fd::config::FdCanConfig,
+ /// Reference to internals.
+ instance: FdcanInstance<'d, T>,
+ _mode: FdcanOperatingMode,
}
-impl_transition!(PoweredDownMode, ConfigMode, into_config_mode, into_config_mode);
-impl_transition!(InternalLoopbackMode, ConfigMode, into_config_mode, into_config_mode);
-
-impl_transition!(ConfigMode, NormalOperationMode, into_normal_mode, into_normal);
-impl_transition!(
- ConfigMode,
- ExternalLoopbackMode,
- into_external_loopback_mode,
- into_external_loopback
-);
-impl_transition!(
- ConfigMode,
- InternalLoopbackMode,
- into_internal_loopback_mode,
- into_internal_loopback
-);
-
-impl<'d, T: Instance, M: FdcanOperatingMode> Fdcan<'d, T, M>
-where
- M: Transmit,
- M: Receive,
-{
+impl<'d, T: Instance> Fdcan<'d, T> {
/// Flush one of the TX mailboxes.
pub async fn flush(&self, idx: usize) {
poll_fn(|cx| {
@@ -401,18 +371,8 @@ where
T::state().rx_mode.read_fd::<T>().await
}
- /// Join split rx and tx portions back together
- pub fn join(tx: FdcanTx<'d, T, M>, rx: FdcanRx<'d, T, M>) -> Self {
- Fdcan {
- config: tx.config,
- //_instance2: T::regs(),
- instance: tx._instance,
- _mode: rx._mode,
- }
- }
-
/// Split instance into separate Tx(write) and Rx(read) portions
- pub fn split(self) -> (FdcanTx<'d, T, M>, FdcanRx<'d, T, M>) {
+ pub fn split(self) -> (FdcanTx<'d, T>, FdcanRx<'d, T>) {
(
FdcanTx {
config: self.config,
@@ -427,12 +387,22 @@ where
)
}
+ /// Join split rx and tx portions back together
+ pub fn join(tx: FdcanTx<'d, T>, rx: FdcanRx<'d, T>) -> Self {
+ Fdcan {
+ config: tx.config,
+ //_instance2: T::regs(),
+ instance: tx._instance,
+ _mode: rx._mode,
+ }
+ }
+
/// Return a buffered instance of driver without CAN FD support. User must supply Buffers
pub fn buffered<const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>(
&self,
tx_buf: &'static mut TxBuf<TX_BUF_SIZE>,
rxb: &'static mut RxBuf<RX_BUF_SIZE>,
- ) -> BufferedCan<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE> {
+ ) -> BufferedCan<'d, T, TX_BUF_SIZE, RX_BUF_SIZE> {
BufferedCan::new(PhantomData::<T>, T::regs(), self._mode, tx_buf, rxb)
}
@@ -441,7 +411,7 @@ where
&self,
tx_buf: &'static mut TxFdBuf<TX_BUF_SIZE>,
rxb: &'static mut RxFdBuf<RX_BUF_SIZE>,
- ) -> BufferedCanFd<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE> {
+ ) -> BufferedCanFd<'d, T, TX_BUF_SIZE, RX_BUF_SIZE> {
BufferedCanFd::new(PhantomData::<T>, T::regs(), self._mode, tx_buf, rxb)
}
}
@@ -453,24 +423,21 @@ pub type RxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, (Classi
pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, ClassicFrame, BUF_SIZE>;
/// Buffered FDCAN Instance
-#[allow(dead_code)]
-pub struct BufferedCan<'d, T: Instance, M: FdcanOperatingMode, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
+pub struct BufferedCan<'d, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
_instance1: PhantomData<T>,
_instance2: &'d crate::pac::can::Fdcan,
- _mode: PhantomData<M>,
+ _mode: FdcanOperatingMode,
tx_buf: &'static TxBuf<TX_BUF_SIZE>,
rx_buf: &'static RxBuf<RX_BUF_SIZE>,
}
-impl<'c, 'd, T: Instance, M: Transmit, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
- BufferedCan<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
-where
- M: FdcanOperatingMode,
+impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
+ BufferedCan<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
{
fn new(
_instance1: PhantomData<T>,
_instance2: &'d crate::pac::can::Fdcan,
- _mode: PhantomData<M>,
+ _mode: FdcanOperatingMode,
tx_buf: &'static TxBuf<TX_BUF_SIZE>,
rx_buf: &'static RxBuf<RX_BUF_SIZE>,
) -> Self {
@@ -511,10 +478,8 @@ where
}
}
-impl<'c, 'd, T: Instance, M, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
- for BufferedCan<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
-where
- M: FdcanOperatingMode,
+impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
+ for BufferedCan<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
{
fn drop(&mut self) {
critical_section::with(|_| unsafe {
@@ -531,24 +496,21 @@ pub type RxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, (FdFr
pub type TxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, FdFrame, BUF_SIZE>;
/// Buffered FDCAN Instance
-#[allow(dead_code)]
-pub struct BufferedCanFd<'d, T: Instance, M: FdcanOperatingMode, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
+pub struct BufferedCanFd<'d, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
_instance1: PhantomData<T>,
_instance2: &'d crate::pac::can::Fdcan,
- _mode: PhantomData<M>,
+ _mode: FdcanOperatingMode,
tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
}
-impl<'c, 'd, T: Instance, M: Transmit, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
- BufferedCanFd<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
-where
- M: FdcanOperatingMode,
+impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
+ BufferedCanFd<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
{
fn new(
_instance1: PhantomData<T>,
_instance2: &'d crate::pac::can::Fdcan,
- _mode: PhantomData<M>,
+ _mode: FdcanOperatingMode,
tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
) -> Self {
@@ -589,10 +551,8 @@ where
}
}
-impl<'c, 'd, T: Instance, M, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
- for BufferedCanFd<'d, T, M, TX_BUF_SIZE, RX_BUF_SIZE>
-where
- M: FdcanOperatingMode,
+impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
+ for BufferedCanFd<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
{
fn drop(&mut self) {
critical_section::with(|_| unsafe {
@@ -603,21 +563,20 @@ where
}
/// FDCAN Rx only Instance
-#[allow(dead_code)]
-pub struct FdcanRx<'d, T: Instance, M: Receive> {
+pub struct FdcanRx<'d, T: Instance> {
_instance1: PhantomData<T>,
_instance2: &'d crate::pac::can::Fdcan,
- _mode: PhantomData<M>,
+ _mode: FdcanOperatingMode,
}
/// FDCAN Tx only Instance
-pub struct FdcanTx<'d, T: Instance, M: Transmit> {
+pub struct FdcanTx<'d, T: Instance> {
config: crate::can::fd::config::FdCanConfig,
_instance: FdcanInstance<'d, T>, //(PeripheralRef<'a, T>);
- _mode: PhantomData<M>,
+ _mode: FdcanOperatingMode,
}
-impl<'c, 'd, T: Instance, M: Transmit> FdcanTx<'d, T, M> {
+impl<'c, 'd, T: Instance> FdcanTx<'d, T> {
/// Queues the message to be sent but exerts backpressure. If a lower-priority
/// frame is dropped from the mailbox, it is returned. If no lower-priority frames
/// can be replaced, this call asynchronously waits for a frame to be successfully
@@ -635,7 +594,7 @@ impl<'c, 'd, T: Instance, M: Transmit> FdcanTx<'d, T, M> {
}
}
-impl<'c, 'd, T: Instance, M: Receive> FdcanRx<'d, T, M> {
+impl<'c, 'd, T: Instance> FdcanRx<'d, T> {
/// Returns the next received message frame
pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
T::state().rx_mode.read::<T>().await
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
index 043ca7144..affa97039 100644
--- a/examples/stm32g4/src/bin/can.rs
+++ b/examples/stm32g4/src/bin/can.rs
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
let peripherals = embassy_stm32::init(config);
- let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
+ let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
can.set_extended_filter(
can::fd::filter::ExtendedFilterSlot::_0,
@@ -38,8 +38,10 @@ async fn main(_spawner: Spawner) {
info!("Configured");
- let mut can = can.into_normal_mode();
- //let mut can = can.into_internal_loopback_mode();
+ let mut can = can.start(match use_fd {
+ true => can::FdcanOperatingMode::InternalLoopbackMode,
+ false => can::FdcanOperatingMode::NormalOperationMode,
+ });
let mut i = 0;
let mut last_read_ts = embassy_time::Instant::now();
@@ -106,7 +108,6 @@ async fn main(_spawner: Spawner) {
break;
}
}
-
i = 0;
let (mut tx, mut rx) = can.split();
// With split
diff --git a/examples/stm32h5/src/bin/can.rs b/examples/stm32h5/src/bin/can.rs
index 4b29a0d21..e5ccfe4f7 100644
--- a/examples/stm32h5/src/bin/can.rs
+++ b/examples/stm32h5/src/bin/can.rs
@@ -24,8 +24,7 @@ async fn main(_spawner: Spawner) {
let peripherals = embassy_stm32::init(config);
- //let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
- let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
+ let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
// 250k bps
can.set_bitrate(250_000);
diff --git a/examples/stm32h7/src/bin/can.rs b/examples/stm32h7/src/bin/can.rs
index 4b29a0d21..e5ccfe4f7 100644
--- a/examples/stm32h7/src/bin/can.rs
+++ b/examples/stm32h7/src/bin/can.rs
@@ -24,8 +24,7 @@ async fn main(_spawner: Spawner) {
let peripherals = embassy_stm32::init(config);
- //let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
- let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
+ let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
// 250k bps
can.set_bitrate(250_000);
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
index 76c27d091..398e31ffc 100644
--- a/tests/stm32/src/bin/fdcan.rs
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -75,7 +75,7 @@ async fn main(_spawner: Spawner) {
let options = options();
let peripherals = embassy_stm32::init(options.config);
- let mut can = can::Fdcan::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
+ let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PB8, peripherals.PB9, Irqs);
// 250k bps
can.set_bitrate(250_000);
From 20cd7d09f429be84481a314f6eb174bcfb82612a Mon Sep 17 00:00:00 2001
From: Scott Mabin <scott@mabez.dev>
Date: Sun, 18 Feb 2024 17:01:09 +0000
Subject: [PATCH 261/392] time: cloneable delay
---
embassy-time/src/delay.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/embassy-time/src/delay.rs b/embassy-time/src/delay.rs
index 7ef5961f0..f77859d4a 100644
--- a/embassy-time/src/delay.rs
+++ b/embassy-time/src/delay.rs
@@ -13,6 +13,7 @@ pub fn block_for(duration: Duration) {
/// the amount provided, but accuracy can be affected by many factors, including interrupt usage.
/// Make sure to use a suitable tick rate for your use case. The tick rate is defined by the currently
/// active driver.
+#[derive(Clone)]
pub struct Delay;
impl embedded_hal_1::delay::DelayNs for Delay {
From f12bba8a6db167582b072b007927b1a9920e86ba Mon Sep 17 00:00:00 2001
From: Zach <zachvv11@gmail.com>
Date: Sun, 18 Feb 2024 16:23:01 -0600
Subject: [PATCH 262/392] Add simple i2c example for u5
---
examples/stm32u5/src/bin/i2c.rs | 41 +++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 examples/stm32u5/src/bin/i2c.rs
diff --git a/examples/stm32u5/src/bin/i2c.rs b/examples/stm32u5/src/bin/i2c.rs
new file mode 100644
index 000000000..e376c6bc8
--- /dev/null
+++ b/examples/stm32u5/src/bin/i2c.rs
@@ -0,0 +1,41 @@
+#![no_std]
+#![no_main]
+
+use defmt::{info, unwrap};
+use embassy_executor::Spawner;
+use embassy_stm32::dma::NoDma;
+use embassy_stm32::i2c::I2c;
+use embassy_stm32::time::Hertz;
+use embassy_stm32::{bind_interrupts, i2c, peripherals};
+use {defmt_rtt as _, panic_probe as _};
+
+const HTS221_ADDRESS: u8 = 0x5F;
+const WHOAMI: u8 = 0x0F;
+
+bind_interrupts!(struct Irqs {
+ I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
+ I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p = embassy_stm32::init(Default::default());
+ let mut i2c = I2c::new(
+ p.I2C2,
+ p.PH4,
+ p.PH5,
+ Irqs,
+ NoDma,
+ NoDma,
+ Hertz(100_000),
+ Default::default(),
+ );
+
+ let mut data = [0u8; 1];
+ unwrap!(i2c.blocking_write_read(HTS221_ADDRESS, &[WHOAMI], &mut data));
+
+ // HTS221 data sheet is here: https://www.st.com/resource/en/datasheet/hts221.pdf
+ // 7.1 WHO_AM_I command is x0F which expected response xBC.
+ info!("Whoami: 0x{:02x}", data[0]);
+ assert_eq!(0xBC, data[0]);
+}
From 3f93105e9fe7c5cbdada46a4367b01448fd61c62 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Mon, 19 Feb 2024 08:33:19 +1000
Subject: [PATCH 263/392] Add dep for static_cell to example.
---
examples/stm32g4/Cargo.toml | 1 +
1 file changed, 1 insertion(+)
diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index fdb325f06..74ccfa3b0 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -24,6 +24,7 @@ embedded-can = { version = "0.4" }
panic-probe = { version = "0.3", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
heapless = { version = "0.8", default-features = false }
+static_cell = "2.0.0"
[profile.release]
debug = 2
From 6ecac3bc950212eba68d579c83ce5b52a17b8806 Mon Sep 17 00:00:00 2001
From: NBonaparte <nbonaparte@protonmail.com>
Date: Thu, 15 Feb 2024 22:33:23 -0800
Subject: [PATCH 264/392] feat(nrf/spim): allow specifying drive of SPI pins
---
embassy-nrf/src/spim.rs | 42 ++++++++++++++++++++++++++++++++++++++---
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index 8937159df..0de35490b 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -50,6 +50,15 @@ pub struct Config {
/// When doing bidirectional transfers, if the TX buffer is shorter than the RX buffer,
/// this byte will be transmitted in the MOSI line for the left-over bytes.
pub orc: u8,
+
+ /// Enable high drive for the SCK line.
+ pub sck_high_drive: bool,
+
+ /// Enable high drive for the MOSI line.
+ pub mosi_high_drive: bool,
+
+ /// Enable high drive for the MISO line.
+ pub miso_high_drive: bool,
}
impl Default for Config {
@@ -59,6 +68,9 @@ impl Default for Config {
mode: MODE_0,
bit_order: BitOrder::MSB_FIRST,
orc: 0x00,
+ sck_high_drive: false,
+ mosi_high_drive: false,
+ miso_high_drive: false,
}
}
}
@@ -159,13 +171,37 @@ impl<'d, T: Instance> Spim<'d, T> {
// Configure pins
if let Some(sck) = &sck {
- sck.conf().write(|w| w.dir().output().drive().h0h1());
+ sck.conf().write(|w| {
+ w.dir().output();
+ if config.sck_high_drive {
+ w.drive().h0h1();
+ } else {
+ w.drive().s0s1();
+ }
+ w
+ });
}
if let Some(mosi) = &mosi {
- mosi.conf().write(|w| w.dir().output().drive().h0h1());
+ mosi.conf().write(|w| {
+ w.dir().output();
+ if config.mosi_high_drive {
+ w.drive().h0h1();
+ } else {
+ w.drive().s0s1();
+ }
+ w
+ });
}
if let Some(miso) = &miso {
- miso.conf().write(|w| w.input().connect().drive().h0h1());
+ miso.conf().write(|w| {
+ w.input().connect();
+ if config.miso_high_drive {
+ w.drive().h0h1();
+ } else {
+ w.drive().s0s1();
+ }
+ w
+ });
}
match config.mode.polarity {
From 5b7e2d88265b5633fa53047961598fbc38bffed0 Mon Sep 17 00:00:00 2001
From: fe1es <157477981+fe1es@users.noreply.github.com>
Date: Mon, 19 Feb 2024 15:25:24 +0900
Subject: [PATCH 265/392] stm32/rcc: reset RTC on stm32l0
---
embassy-stm32/src/rcc/bd.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index d20f58185..d381ec1bd 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -206,7 +206,7 @@ impl LsConfig {
bdcr().modify(|w| w.set_vswrst(true));
bdcr().modify(|w| w.set_vswrst(false));
}
- #[cfg(any(stm32c0))]
+ #[cfg(any(stm32c0, stm32l0))]
{
bdcr().modify(|w| w.set_rtcrst(true));
bdcr().modify(|w| w.set_rtcrst(false));
From 67230dc4443d82aac14b590ba873fa647e5fc548 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Mon, 19 Feb 2024 15:49:43 +0000
Subject: [PATCH 266/392] flash: h50: first pass at implementation
---
embassy-stm32/src/flash/h50.rs | 124 +++++++++++++++++++++++++++++++++
embassy-stm32/src/flash/mod.rs | 3 +-
2 files changed, 126 insertions(+), 1 deletion(-)
create mode 100644 embassy-stm32/src/flash/h50.rs
diff --git a/embassy-stm32/src/flash/h50.rs b/embassy-stm32/src/flash/h50.rs
new file mode 100644
index 000000000..db05bef5d
--- /dev/null
+++ b/embassy-stm32/src/flash/h50.rs
@@ -0,0 +1,124 @@
+/// STM32H50 series flash impl. See RM0492
+use core::{
+ ptr::write_volatile,
+ sync::atomic::{fence, Ordering},
+};
+
+use cortex_m::interrupt;
+use pac::flash::regs::Nssr;
+use pac::flash::vals::Bksel;
+
+use super::{Error, FlashBank, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use crate::pac;
+
+pub(crate) const fn is_default_layout() -> bool {
+ true
+}
+
+pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
+ &FLASH_REGIONS
+}
+
+pub(crate) unsafe fn lock() {
+ pac::FLASH.nscr().modify(|w| w.set_lock(true));
+}
+
+pub(crate) unsafe fn unlock() {
+ while busy() {}
+
+ if pac::FLASH.nscr().read().lock() {
+ pac::FLASH.nskeyr().write_value(0x4567_0123);
+ pac::FLASH.nskeyr().write_value(0xCDEF_89AB);
+ }
+}
+
+pub(crate) unsafe fn enable_blocking_write() {
+ assert_eq!(0, WRITE_SIZE % 4);
+ pac::FLASH.nscr().write(|w| w.set_pg(true));
+}
+
+pub(crate) unsafe fn disable_blocking_write() {
+ pac::FLASH.nscr().write(|w| w.set_pg(false));
+}
+
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+ let mut address = start_address;
+ for val in buf.chunks(4) {
+ write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
+ address += val.len() as u32;
+
+ // prevents parallelism errors
+ fence(Ordering::SeqCst);
+ }
+
+ wait_ready_blocking()
+}
+
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+ assert!(sector.bank != FlashBank::Otp);
+ assert!(sector.index_in_bank < 8);
+
+ while busy() {}
+
+ interrupt::free(|_| {
+ pac::FLASH.nscr().modify(|w| {
+ w.set_bksel(match sector.bank {
+ FlashBank::Bank1 => Bksel::B_0X0,
+ FlashBank::Bank2 => Bksel::B_0X1,
+ _ => unreachable!(),
+ });
+ w.set_snb(sector.index_in_bank);
+ w.set_ser(true);
+ w.set_strt(true);
+ })
+ });
+
+ let ret = wait_ready_blocking();
+ pac::FLASH.nscr().modify(|w| w.set_ser(false));
+ ret
+}
+
+pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
+ loop {
+ let sr = pac::FLASH.nssr().read();
+
+ if !sr_busy(sr) {
+ if sr.wrperr() {
+ return Err(Error::Protected);
+ }
+ if sr.pgserr() {
+ return Err(Error::Seq);
+ }
+ if sr.strberr() {
+ // writing several times to the same byte in the write buffer
+ return Err(Error::Prog);
+ }
+ if sr.incerr() {
+ // attempting write operation before completion of previous
+ // write operation
+ return Err(Error::Seq);
+ }
+
+ return Ok(());
+ }
+ }
+}
+
+pub(crate) unsafe fn clear_all_err() {
+ pac::FLASH.nsccr().modify(|w| {
+ w.set_clr_wrperr(true);
+ w.set_clr_pgserr(true);
+ w.set_clr_strberr(true);
+ w.set_clr_incerr(true);
+ })
+}
+
+fn sr_busy(sr: Nssr) -> bool {
+ // Note: RM0492 sometimes incorrectly refers to WBNE as NSWBNE
+ sr.bsy() || sr.dbne() || sr.wbne()
+}
+
+fn busy() -> bool {
+ let sr = pac::FLASH.nssr().read();
+ sr_busy(sr)
+}
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 4f43a7a48..1d8031e82 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -102,10 +102,11 @@ pub enum FlashBank {
#[cfg_attr(flash_h7, path = "h7.rs")]
#[cfg_attr(flash_h7ab, path = "h7.rs")]
#[cfg_attr(flash_u5, path = "u5.rs")]
+#[cfg_attr(flash_h50, path = "h50.rs")]
#[cfg_attr(
not(any(
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f1, flash_f3, flash_f4, flash_f7, flash_g0,
- flash_g4, flash_h7, flash_h7ab, flash_u5
+ flash_g4, flash_h7, flash_h7ab, flash_u5, flash_h50
)),
path = "other.rs"
)]
From f3b96d8ba0d5143035a03679d94a4ba14f9652ac Mon Sep 17 00:00:00 2001
From: Mick Chanthaseth <mchant@users.noreply.github.com>
Date: Mon, 19 Feb 2024 15:14:28 -0800
Subject: [PATCH 267/392] Updated formatting in usb_hid_mouse.rs.
---
examples/rp/src/bin/usb_hid_mouse.rs | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/examples/rp/src/bin/usb_hid_mouse.rs b/examples/rp/src/bin/usb_hid_mouse.rs
index a812b22c3..d2c63605a 100644
--- a/examples/rp/src/bin/usb_hid_mouse.rs
+++ b/examples/rp/src/bin/usb_hid_mouse.rs
@@ -10,8 +10,8 @@ use embassy_rp::bind_interrupts;
use embassy_rp::clocks::RoscRng;
use embassy_rp::gpio::{Input, Pull};
use embassy_rp::peripherals::USB;
-use embassy_time::Timer;
use embassy_rp::usb::{Driver, InterruptHandler};
+use embassy_time::Timer;
use embassy_usb::class::hid::{HidReaderWriter, ReportId, RequestHandler, State};
use embassy_usb::control::OutResponse;
use embassy_usb::{Builder, Config, Handler};
@@ -92,18 +92,18 @@ async fn main(_spawner: Spawner) {
loop {
// every 1 second
_ = Timer::after_secs(1).await;
- let report = MouseReport{
+ let report = MouseReport {
buttons: 0,
x: rng.gen_range(-100..100), // random small x movement
y: rng.gen_range(-100..100), // random small y movement
wheel: 0,
pan: 0,
};
- match writer.write_serialize(&report).await{
- Ok(())=>{},
- Err(e)=>{
+ match writer.write_serialize(&report).await {
+ Ok(()) => {},
+ Err(e) => {
warn!("Failed to send report: {:?}", e);
- },
+ }
}
}
};
From 9c870981e3696c8afb16951c806cc6678073f7ca Mon Sep 17 00:00:00 2001
From: Mick Chanthaseth <mchant@users.noreply.github.com>
Date: Mon, 19 Feb 2024 15:28:57 -0800
Subject: [PATCH 268/392] fixed formatting in usb_hid_mouse.rs
---
examples/rp/src/bin/usb_hid_mouse.rs | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/examples/rp/src/bin/usb_hid_mouse.rs b/examples/rp/src/bin/usb_hid_mouse.rs
index d2c63605a..3a5201b59 100644
--- a/examples/rp/src/bin/usb_hid_mouse.rs
+++ b/examples/rp/src/bin/usb_hid_mouse.rs
@@ -99,11 +99,10 @@ async fn main(_spawner: Spawner) {
wheel: 0,
pan: 0,
};
+ // Send the report.
match writer.write_serialize(&report).await {
- Ok(()) => {},
- Err(e) => {
- warn!("Failed to send report: {:?}", e);
- }
+ Ok(()) => {}
+ Err(e) => warn!("Failed to send report: {:?}", e),
}
}
};
From bae30fb3973e0c35613422b1ecff299961b0dda4 Mon Sep 17 00:00:00 2001
From: Mick Chanthaseth <mchant@users.noreply.github.com>
Date: Mon, 19 Feb 2024 15:41:15 -0800
Subject: [PATCH 269/392] removed extra spaces.
---
examples/rp/src/bin/usb_hid_mouse.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/rp/src/bin/usb_hid_mouse.rs b/examples/rp/src/bin/usb_hid_mouse.rs
index 3a5201b59..afebd8813 100644
--- a/examples/rp/src/bin/usb_hid_mouse.rs
+++ b/examples/rp/src/bin/usb_hid_mouse.rs
@@ -88,7 +88,7 @@ async fn main(_spawner: Spawner) {
// Do stuff with the class!
let in_fut = async {
let mut rng = RoscRng;
-
+
loop {
// every 1 second
_ = Timer::after_secs(1).await;
From e8474426d8c0ca60ac222845b9c6f7befe3f6a4a Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Tue, 20 Feb 2024 01:02:15 +0100
Subject: [PATCH 270/392] hal-internal: remove impl DerefMut for PeripheralRef.
if you have `PeripheralRef<'a, AnyPIn>` for pin A, and `AnyPin` (owned) for pin B, you can `mem::swap` them.
so, getting access forever to pin A, just by "sacrificing" pin B
this defeats the point of PeripheralRef, which is if you got a `PeripheralRef<'a, T>` then you're only allowed to use the peripheral for `'a`.
Also some drivers rely on the fact only one instance of a singleton exists for soundness, so this is a soundness fix for those.
---
embassy-hal-internal/src/peripheral.rs | 11 +----
embassy-stm32/src/dma/bdma.rs | 6 +--
embassy-stm32/src/dma/dma.rs | 8 ++--
embassy-stm32/src/dma/dmamux.rs | 2 +-
embassy-stm32/src/dma/gpdma.rs | 2 +-
embassy-stm32/src/timer/mod.rs | 64 +++++++++++++-------------
6 files changed, 43 insertions(+), 50 deletions(-)
diff --git a/embassy-hal-internal/src/peripheral.rs b/embassy-hal-internal/src/peripheral.rs
index 16d49edfb..f03f41507 100644
--- a/embassy-hal-internal/src/peripheral.rs
+++ b/embassy-hal-internal/src/peripheral.rs
@@ -1,5 +1,5 @@
use core::marker::PhantomData;
-use core::ops::{Deref, DerefMut};
+use core::ops::Deref;
/// An exclusive reference to a peripheral.
///
@@ -86,13 +86,6 @@ impl<'a, T> Deref for PeripheralRef<'a, T> {
}
}
-impl<'a, T> DerefMut for PeripheralRef<'a, T> {
- #[inline]
- fn deref_mut(&mut self) -> &mut Self::Target {
- &mut self.inner
- }
-}
-
/// Trait for any type that can be used as a peripheral of type `P`.
///
/// This is used in driver constructors, to allow passing either owned peripherals (e.g. `TWISPI0`),
@@ -162,7 +155,7 @@ pub trait Peripheral: Sized {
}
}
-impl<'b, T: DerefMut> Peripheral for T
+impl<'b, T: Deref> Peripheral for T
where
T::Target: Peripheral,
{
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
index 077cfdcd9..994bdb1e6 100644
--- a/embassy-stm32/src/dma/bdma.rs
+++ b/embassy-stm32/src/dma/bdma.rs
@@ -299,7 +299,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
STATE.complete_count[this.channel.index()].store(0, Ordering::Release);
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, _request);
+ super::dmamux::configure_dmamux(&*this.channel, _request);
ch.par().write_value(peri_addr as u32);
ch.mar().write_value(mem_addr as u32);
@@ -483,7 +483,7 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
this.clear_irqs();
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, _request);
+ super::dmamux::configure_dmamux(&*this.channel, _request);
let ch = dma.ch(channel_number);
ch.par().write_value(peri_addr as u32);
@@ -641,7 +641,7 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
this.clear_irqs();
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, _request);
+ super::dmamux::configure_dmamux(&*this.channel, _request);
let ch = dma.ch(channel_number);
ch.par().write_value(peri_addr as u32);
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
index ef9bb3d78..e762b1bde 100644
--- a/embassy-stm32/src/dma/dma.rs
+++ b/embassy-stm32/src/dma/dma.rs
@@ -366,7 +366,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
this.clear_irqs();
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, _request);
+ super::dmamux::configure_dmamux(&*this.channel, _request);
ch.par().write_value(peri_addr as u32);
ch.m0ar().write_value(mem_addr as u32);
@@ -522,7 +522,7 @@ impl<'a, C: Channel, W: Word> DoubleBuffered<'a, C, W> {
this.clear_irqs();
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, _request);
+ super::dmamux::configure_dmamux(&*this.channel, _request);
let ch = dma.st(channel_number);
ch.par().write_value(peri_addr as u32);
@@ -726,7 +726,7 @@ impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
this.clear_irqs();
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, _request);
+ super::dmamux::configure_dmamux(&*this.channel, _request);
let ch = dma.st(channel_number);
ch.par().write_value(peri_addr as u32);
@@ -901,7 +901,7 @@ impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
this.clear_irqs();
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, _request);
+ super::dmamux::configure_dmamux(&*this.channel, _request);
let ch = dma.st(channel_number);
ch.par().write_value(peri_addr as u32);
diff --git a/embassy-stm32/src/dma/dmamux.rs b/embassy-stm32/src/dma/dmamux.rs
index 9cd494724..ac6f44107 100644
--- a/embassy-stm32/src/dma/dmamux.rs
+++ b/embassy-stm32/src/dma/dmamux.rs
@@ -2,7 +2,7 @@
use crate::{pac, peripherals};
-pub(crate) fn configure_dmamux<M: MuxChannel>(channel: &mut M, request: u8) {
+pub(crate) fn configure_dmamux<M: MuxChannel>(channel: &M, request: u8) {
let ch_mux_regs = channel.mux_regs().ccr(channel.mux_num());
ch_mux_regs.write(|reg| {
reg.set_nbreq(0);
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index 34b2426b9..337e7b309 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -259,7 +259,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
let this = Self { channel };
#[cfg(dmamux)]
- super::dmamux::configure_dmamux(&mut *this.channel, request);
+ super::dmamux::configure_dmamux(&*this.channel, request);
ch.cr().write(|w| w.set_reset(true));
ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 9480d6972..9397da2a1 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -65,17 +65,17 @@ pub(crate) mod sealed {
fn regs_core() -> crate::pac::timer::TimCore;
/// Start the timer.
- fn start(&mut self) {
+ fn start(&self) {
Self::regs_core().cr1().modify(|r| r.set_cen(true));
}
/// Stop the timer.
- fn stop(&mut self) {
+ fn stop(&self) {
Self::regs_core().cr1().modify(|r| r.set_cen(false));
}
/// Reset the counter value to 0
- fn reset(&mut self) {
+ fn reset(&self) {
Self::regs_core().cnt().write(|r| r.set_cnt(0));
}
@@ -85,7 +85,7 @@ pub(crate) mod sealed {
/// the timer counter will wrap around at the same frequency as is being set.
/// In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved
/// because it needs to count up and down.
- fn set_frequency(&mut self, frequency: Hertz) {
+ fn set_frequency(&self, frequency: Hertz) {
let f = frequency.0;
let timer_f = Self::frequency().0;
assert!(f > 0);
@@ -108,7 +108,7 @@ pub(crate) mod sealed {
/// Clear update interrupt.
///
/// Returns whether the update interrupt flag was set.
- fn clear_update_interrupt(&mut self) -> bool {
+ fn clear_update_interrupt(&self) -> bool {
let regs = Self::regs_core();
let sr = regs.sr().read();
if sr.uif() {
@@ -122,12 +122,12 @@ pub(crate) mod sealed {
}
/// Enable/disable the update interrupt.
- fn enable_update_interrupt(&mut self, enable: bool) {
+ fn enable_update_interrupt(&self, enable: bool) {
Self::regs_core().dier().modify(|r| r.set_uie(enable));
}
/// Enable/disable autoreload preload.
- fn set_autoreload_preload(&mut self, enable: bool) {
+ fn set_autoreload_preload(&self, enable: bool) {
Self::regs_core().cr1().modify(|r| r.set_arpe(enable));
}
@@ -154,7 +154,7 @@ pub(crate) mod sealed {
fn regs_basic_no_cr2() -> crate::pac::timer::TimBasicNoCr2;
/// Enable/disable the update dma.
- fn enable_update_dma(&mut self, enable: bool) {
+ fn enable_update_dma(&self, enable: bool) {
Self::regs_basic_no_cr2().dier().modify(|r| r.set_ude(enable));
}
@@ -186,7 +186,7 @@ pub(crate) mod sealed {
fn regs_1ch() -> crate::pac::timer::Tim1ch;
/// Set clock divider.
- fn set_clock_division(&mut self, ckd: vals::Ckd) {
+ fn set_clock_division(&self, ckd: vals::Ckd) {
Self::regs_1ch().cr1().modify(|r| r.set_ckd(ckd));
}
@@ -218,7 +218,7 @@ pub(crate) mod sealed {
fn regs_gp16() -> crate::pac::timer::TimGp16;
/// Set counting mode.
- fn set_counting_mode(&mut self, mode: CountingMode) {
+ fn set_counting_mode(&self, mode: CountingMode) {
let (cms, dir) = mode.into();
let timer_enabled = Self::regs_core().cr1().read().cen();
@@ -237,7 +237,7 @@ pub(crate) mod sealed {
}
/// Set input capture filter.
- fn set_input_capture_filter(&mut self, channel: Channel, icf: vals::FilterValue) {
+ fn set_input_capture_filter(&self, channel: Channel, icf: vals::FilterValue) {
let raw_channel = channel.index();
Self::regs_gp16()
.ccmr_input(raw_channel / 2)
@@ -245,17 +245,17 @@ pub(crate) mod sealed {
}
/// Clear input interrupt.
- fn clear_input_interrupt(&mut self, channel: Channel) {
+ fn clear_input_interrupt(&self, channel: Channel) {
Self::regs_gp16().sr().modify(|r| r.set_ccif(channel.index(), false));
}
/// Enable input interrupt.
- fn enable_input_interrupt(&mut self, channel: Channel, enable: bool) {
+ fn enable_input_interrupt(&self, channel: Channel, enable: bool) {
Self::regs_gp16().dier().modify(|r| r.set_ccie(channel.index(), enable));
}
/// Set input capture prescaler.
- fn set_input_capture_prescaler(&mut self, channel: Channel, factor: u8) {
+ fn set_input_capture_prescaler(&self, channel: Channel, factor: u8) {
let raw_channel = channel.index();
Self::regs_gp16()
.ccmr_input(raw_channel / 2)
@@ -263,7 +263,7 @@ pub(crate) mod sealed {
}
/// Set input TI selection.
- fn set_input_ti_selection(&mut self, channel: Channel, tisel: InputTISelection) {
+ fn set_input_ti_selection(&self, channel: Channel, tisel: InputTISelection) {
let raw_channel = channel.index();
Self::regs_gp16()
.ccmr_input(raw_channel / 2)
@@ -271,7 +271,7 @@ pub(crate) mod sealed {
}
/// Set input capture mode.
- fn set_input_capture_mode(&mut self, channel: Channel, mode: InputCaptureMode) {
+ fn set_input_capture_mode(&self, channel: Channel, mode: InputCaptureMode) {
Self::regs_gp16().ccer().modify(|r| match mode {
InputCaptureMode::Rising => {
r.set_ccnp(channel.index(), false);
@@ -289,7 +289,7 @@ pub(crate) mod sealed {
}
/// Set output compare mode.
- fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
+ fn set_output_compare_mode(&self, channel: Channel, mode: OutputCompareMode) {
let raw_channel: usize = channel.index();
Self::regs_gp16()
.ccmr_output(raw_channel / 2)
@@ -297,14 +297,14 @@ pub(crate) mod sealed {
}
/// Set output polarity.
- fn set_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+ fn set_output_polarity(&self, channel: Channel, polarity: OutputPolarity) {
Self::regs_gp16()
.ccer()
.modify(|w| w.set_ccp(channel.index(), polarity.into()));
}
/// Enable/disable a channel.
- fn enable_channel(&mut self, channel: Channel, enable: bool) {
+ fn enable_channel(&self, channel: Channel, enable: bool) {
Self::regs_gp16().ccer().modify(|w| w.set_cce(channel.index(), enable));
}
@@ -314,12 +314,12 @@ pub(crate) mod sealed {
}
/// Set compare value for a channel.
- fn set_compare_value(&mut self, channel: Channel, value: u16) {
+ fn set_compare_value(&self, channel: Channel, value: u16) {
Self::regs_gp16().ccr(channel.index()).modify(|w| w.set_ccr(value));
}
/// Get capture value for a channel.
- fn get_capture_value(&mut self, channel: Channel) -> u16 {
+ fn get_capture_value(&self, channel: Channel) -> u16 {
Self::regs_gp16().ccr(channel.index()).read().ccr()
}
@@ -329,7 +329,7 @@ pub(crate) mod sealed {
}
/// Set output compare preload.
- fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
+ fn set_output_compare_preload(&self, channel: Channel, preload: bool) {
let channel_index = channel.index();
Self::regs_gp16()
.ccmr_output(channel_index / 2)
@@ -342,7 +342,7 @@ pub(crate) mod sealed {
}
/// Set capture compare DMA selection
- fn set_cc_dma_selection(&mut self, ccds: super::vals::Ccds) {
+ fn set_cc_dma_selection(&self, ccds: super::vals::Ccds) {
Self::regs_gp16().cr2().modify(|w| w.set_ccds(ccds))
}
@@ -352,7 +352,7 @@ pub(crate) mod sealed {
}
/// Set capture compare DMA enable state
- fn set_cc_dma_enable_state(&mut self, channel: Channel, ccde: bool) {
+ fn set_cc_dma_enable_state(&self, channel: Channel, ccde: bool) {
Self::regs_gp16().dier().modify(|w| w.set_ccde(channel.index(), ccde))
}
}
@@ -369,7 +369,7 @@ pub(crate) mod sealed {
fn regs_gp32() -> crate::pac::timer::TimGp32;
/// Set timer frequency.
- fn set_frequency(&mut self, frequency: Hertz) {
+ fn set_frequency(&self, frequency: Hertz) {
let f = frequency.0;
assert!(f > 0);
let timer_f = Self::frequency().0;
@@ -398,12 +398,12 @@ pub(crate) mod sealed {
}
/// Set comapre value for a channel.
- fn set_compare_value(&mut self, channel: Channel, value: u32) {
+ fn set_compare_value(&self, channel: Channel, value: u32) {
Self::regs_gp32().ccr(channel.index()).modify(|w| w.set_ccr(value));
}
/// Get capture value for a channel.
- fn get_capture_value(&mut self, channel: Channel) -> u32 {
+ fn get_capture_value(&self, channel: Channel) -> u32 {
Self::regs_gp32().ccr(channel.index()).read().ccr()
}
@@ -430,17 +430,17 @@ pub(crate) mod sealed {
fn regs_1ch_cmp() -> crate::pac::timer::Tim1chCmp;
/// Set clock divider for the dead time.
- fn set_dead_time_clock_division(&mut self, value: vals::Ckd) {
+ fn set_dead_time_clock_division(&self, value: vals::Ckd) {
Self::regs_1ch_cmp().cr1().modify(|w| w.set_ckd(value));
}
/// Set dead time, as a fraction of the max duty value.
- fn set_dead_time_value(&mut self, value: u8) {
+ fn set_dead_time_value(&self, value: u8) {
Self::regs_1ch_cmp().bdtr().modify(|w| w.set_dtg(value));
}
/// Enable timer outputs.
- fn enable_outputs(&mut self) {
+ fn enable_outputs(&self) {
Self::regs_1ch_cmp().bdtr().modify(|w| w.set_moe(true));
}
}
@@ -468,14 +468,14 @@ pub(crate) mod sealed {
fn regs_advanced() -> crate::pac::timer::TimAdv;
/// Set complementary output polarity.
- fn set_complementary_output_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
+ fn set_complementary_output_polarity(&self, channel: Channel, polarity: OutputPolarity) {
Self::regs_advanced()
.ccer()
.modify(|w| w.set_ccnp(channel.index(), polarity.into()));
}
/// Enable/disable a complementary channel.
- fn enable_complementary_channel(&mut self, channel: Channel, enable: bool) {
+ fn enable_complementary_channel(&self, channel: Channel, enable: bool) {
Self::regs_advanced()
.ccer()
.modify(|w| w.set_ccne(channel.index(), enable));
From ba2b4aad81c37727e05d2ddfbcc77ce247787b35 Mon Sep 17 00:00:00 2001
From: NBonaparte <nbonaparte@protonmail.com>
Date: Mon, 19 Feb 2024 17:46:25 -0800
Subject: [PATCH 271/392] fix(nrf/spim): use `OutputDrive` to set pin drives
---
embassy-nrf/src/gpio.rs | 2 +-
embassy-nrf/src/spim.rs | 53 +++++++++++++----------------------------
2 files changed, 17 insertions(+), 38 deletions(-)
diff --git a/embassy-nrf/src/gpio.rs b/embassy-nrf/src/gpio.rs
index b2f987109..3649ea61a 100644
--- a/embassy-nrf/src/gpio.rs
+++ b/embassy-nrf/src/gpio.rs
@@ -189,7 +189,7 @@ impl<'d> Output<'d> {
}
}
-fn convert_drive(drive: OutputDrive) -> DRIVE_A {
+pub(crate) fn convert_drive(drive: OutputDrive) -> DRIVE_A {
match drive {
OutputDrive::Standard => DRIVE_A::S0S1,
OutputDrive::HighDrive0Standard1 => DRIVE_A::H0S1,
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index 0de35490b..a4ab7e9da 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -15,7 +15,7 @@ pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::sealed::Pin as _;
-use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
+use crate::gpio::{self, convert_drive, AnyPin, OutputDrive, Pin as GpioPin, PselBits};
use crate::interrupt::typelevel::Interrupt;
use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
use crate::{interrupt, pac, Peripheral};
@@ -51,14 +51,14 @@ pub struct Config {
/// this byte will be transmitted in the MOSI line for the left-over bytes.
pub orc: u8,
- /// Enable high drive for the SCK line.
- pub sck_high_drive: bool,
+ /// Drive strength for the SCK line.
+ pub sck_drive: OutputDrive,
- /// Enable high drive for the MOSI line.
- pub mosi_high_drive: bool,
+ /// Drive strength for the MOSI line.
+ pub mosi_drive: OutputDrive,
- /// Enable high drive for the MISO line.
- pub miso_high_drive: bool,
+ /// Drive strength for the MISO line.
+ pub miso_drive: OutputDrive,
}
impl Default for Config {
@@ -68,9 +68,9 @@ impl Default for Config {
mode: MODE_0,
bit_order: BitOrder::MSB_FIRST,
orc: 0x00,
- sck_high_drive: false,
- mosi_high_drive: false,
- miso_high_drive: false,
+ sck_drive: OutputDrive::HighDrive,
+ mosi_drive: OutputDrive::HighDrive,
+ miso_drive: OutputDrive::HighDrive,
}
}
}
@@ -171,37 +171,16 @@ impl<'d, T: Instance> Spim<'d, T> {
// Configure pins
if let Some(sck) = &sck {
- sck.conf().write(|w| {
- w.dir().output();
- if config.sck_high_drive {
- w.drive().h0h1();
- } else {
- w.drive().s0s1();
- }
- w
- });
+ sck.conf()
+ .write(|w| w.dir().output().drive().variant(convert_drive(config.sck_drive)));
}
if let Some(mosi) = &mosi {
- mosi.conf().write(|w| {
- w.dir().output();
- if config.mosi_high_drive {
- w.drive().h0h1();
- } else {
- w.drive().s0s1();
- }
- w
- });
+ mosi.conf()
+ .write(|w| w.dir().output().drive().variant(convert_drive(config.mosi_drive)));
}
if let Some(miso) = &miso {
- miso.conf().write(|w| {
- w.input().connect();
- if config.miso_high_drive {
- w.drive().h0h1();
- } else {
- w.drive().s0s1();
- }
- w
- });
+ miso.conf()
+ .write(|w| w.input().connect().drive().variant(convert_drive(config.miso_drive)));
}
match config.mode.polarity {
From 9b2d096f4f8b8db3747a29fb96f7b2a228dd571f Mon Sep 17 00:00:00 2001
From: Joonas Javanainen <joonas.javanainen@gmail.com>
Date: Tue, 20 Feb 2024 21:33:03 +0200
Subject: [PATCH 272/392] USB needs PWR_CR2 USV set on STM32L4
Confirmed to be needed on an STM32L422, and based on a quick look at
L4/L4+ reference manuals, this bit is present and required to be set on
all L4 chips that have some kind of USB peripheral (USB or OTG_FS).
The `usb_otg` driver already sets it for `cfg(stm32l4)` and we should do
the same thing here.
---
embassy-stm32/src/usb/usb.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 34d6b52fd..be321a19b 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -264,7 +264,7 @@ impl<'d, T: Instance> Driver<'d, T> {
let regs = T::regs();
- #[cfg(any(stm32l5, stm32wb))]
+ #[cfg(any(stm32l4, stm32l5, stm32wb))]
crate::pac::PWR.cr2().modify(|w| w.set_usv(true));
#[cfg(pwr_h5)]
From 2ee9b373738cf78cf784bf8753a7f55568f85d9b Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Tue, 20 Feb 2024 17:54:35 -0800
Subject: [PATCH 273/392] Move to a single Mux Struct.
---
embassy-stm32/build.rs | 26 ++++++++++----------------
embassy-stm32/src/rcc/f013.rs | 12 ++++++------
embassy-stm32/src/rcc/mod.rs | 2 ++
3 files changed, 18 insertions(+), 22 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index f45a571f2..2ffbadfc3 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -430,7 +430,7 @@ fn main() {
let mut clock_names = BTreeSet::new();
- let mut rcc_cfgr_regs = BTreeMap::new();
+ let mut rcc_cfgr_regs = BTreeSet::new();
for p in METADATA.peripherals {
if !singletons.contains(&p.name.to_string()) {
@@ -510,11 +510,7 @@ fn main() {
let field_name = format_ident!("{}", field_name);
let enum_name = format_ident!("{}", enum_name);
- if !rcc_cfgr_regs.contains_key(mux.register) {
- rcc_cfgr_regs.insert(mux.register, Vec::new());
- }
-
- rcc_cfgr_regs.get_mut(mux.register).unwrap().push((
+ rcc_cfgr_regs.insert((
fieldset_name.clone(),
field_name.clone(),
enum_name.clone(),
@@ -602,10 +598,10 @@ fn main() {
}
}
- for (rcc_cfgr_reg, fields) in rcc_cfgr_regs {
- println!("cargo:rustc-cfg={}", rcc_cfgr_reg.to_ascii_lowercase());
+ if !rcc_cfgr_regs.is_empty() {
+ println!("cargo:rustc-cfg=clock_mux");
- let struct_fields: Vec<_> = fields
+ let struct_fields: Vec<_> = rcc_cfgr_regs
.iter()
.map(|(_fieldset, fieldname, enum_name)| {
quote! {
@@ -614,12 +610,12 @@ fn main() {
})
.collect();
- let field_names: Vec<_> = fields
+ let field_names: Vec<_> = rcc_cfgr_regs
.iter()
.map(|(_fieldset, fieldname, _enum_name)| fieldname)
.collect();
- let inits: Vec<_> = fields
+ let inits: Vec<_> = rcc_cfgr_regs
.iter()
.map(|(fieldset, fieldname, _enum_name)| {
let setter = format_ident!("set_{}", fieldname);
@@ -635,15 +631,13 @@ fn main() {
})
.collect();
- let cfgr_reg = format_ident!("{}", rcc_cfgr_reg);
-
g.extend(quote! {
#[derive(Clone, Copy)]
- pub struct #cfgr_reg {
+ pub struct ClockMux {
#( #struct_fields, )*
}
- impl Default for #cfgr_reg {
+ impl Default for ClockMux {
fn default() -> Self {
Self {
#( #field_names: None, )*
@@ -651,7 +645,7 @@ fn main() {
}
}
- impl #cfgr_reg {
+ impl ClockMux {
pub fn init(self) {
#( #inits )*
}
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index a61aae0e8..86af4bd68 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -99,8 +99,8 @@ pub struct Config {
pub adc34: AdcClockSource,
#[cfg(stm32f334)]
pub hrtim: HrtimClockSource,
- #[cfg(cfgr3)]
- pub cfgr3: crate::_generated::CFGR3,
+ #[cfg(clock_mux)]
+ pub mux: crate::rcc::ClockMux,
pub ls: super::LsConfig,
}
@@ -130,8 +130,8 @@ impl Default for Config {
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(stm32f334)]
hrtim: HrtimClockSource::BusClk,
- #[cfg(cfgr3)]
- cfgr3: Default::default(),
+ #[cfg(clock_mux)]
+ mux: Default::default(),
}
}
}
@@ -367,8 +367,8 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(cfgr3)]
- config.cfgr3.init();
+ #[cfg(clock_mux)]
+ config.mux.init();
set_clocks!(
hsi: hsi,
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 0f3467151..f71211925 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -32,6 +32,8 @@ mod _version;
pub use _version::*;
pub use crate::_generated::Clocks;
+#[cfg(clock_mux)]
+pub use crate::_generated::ClockMux;
#[cfg(feature = "low-power")]
/// Must be written within a critical section
From 95056958300d92b34d5f8f77c7429894efbc0fa1 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Tue, 20 Feb 2024 17:55:05 -0800
Subject: [PATCH 274/392] Move compile test to the STM32F334 example.
---
examples/stm32f3/src/bin/usart_dma.rs | 4 +---
examples/stm32f334/src/bin/pwm.rs | 1 +
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/examples/stm32f3/src/bin/usart_dma.rs b/examples/stm32f3/src/bin/usart_dma.rs
index 7dc905adc..5234e53b9 100644
--- a/examples/stm32f3/src/bin/usart_dma.rs
+++ b/examples/stm32f3/src/bin/usart_dma.rs
@@ -17,9 +17,7 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
- let mut init_config = embassy_stm32::Config::default();
- init_config.rcc.cfgr3.usart1sw = Some(embassy_stm32::pac::rcc::vals::Usart1sw::HSI);
- let p = embassy_stm32::init(init_config);
+ let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let config = Config::default();
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index 7fc1ea926..24606b9b6 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -28,6 +28,7 @@ async fn main(_spawner: Spawner) {
config.rcc.apb1_pre = APBPrescaler::DIV2;
config.rcc.apb2_pre = APBPrescaler::DIV1;
config.rcc.hrtim = HrtimClockSource::PllClk;
+ config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P); // TODO: The two lines here do the same thing
}
let p = embassy_stm32::init(config);
From 88e29608ed5425f5dbc3edf56acff1654d587a5e Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Tue, 20 Feb 2024 17:59:51 -0800
Subject: [PATCH 275/392] Rust fmt
---
embassy-stm32/build.rs | 6 +-----
embassy-stm32/src/rcc/mod.rs | 2 +-
examples/stm32f334/src/bin/pwm.rs | 4 +++-
3 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 2ffbadfc3..a0b74c0b9 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -510,11 +510,7 @@ fn main() {
let field_name = format_ident!("{}", field_name);
let enum_name = format_ident!("{}", enum_name);
- rcc_cfgr_regs.insert((
- fieldset_name.clone(),
- field_name.clone(),
- enum_name.clone(),
- ));
+ rcc_cfgr_regs.insert((fieldset_name.clone(), field_name.clone(), enum_name.clone()));
let match_arms: TokenStream = enumm
.variants
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index f71211925..24516d426 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -31,9 +31,9 @@ mod _version;
pub use _version::*;
-pub use crate::_generated::Clocks;
#[cfg(clock_mux)]
pub use crate::_generated::ClockMux;
+pub use crate::_generated::Clocks;
#[cfg(feature = "low-power")]
/// Must be written within a critical section
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index 24606b9b6..cf5eb7b26 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -27,8 +27,10 @@ async fn main(_spawner: Spawner) {
config.rcc.ahb_pre = AHBPrescaler::DIV1;
config.rcc.apb1_pre = APBPrescaler::DIV2;
config.rcc.apb2_pre = APBPrescaler::DIV1;
+
+ // TODO: The two lines here do the same thing
config.rcc.hrtim = HrtimClockSource::PllClk;
- config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P); // TODO: The two lines here do the same thing
+ config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P);
}
let p = embassy_stm32::init(config);
From 111306ac0c93b2a7f12545067d23466f6f976742 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 21 Feb 2024 19:09:58 +0100
Subject: [PATCH 276/392] nrf/buffered_uart: simplify split lifetimes.
---
embassy-nrf/src/buffered_uarte.rs | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index fb72422bd..e0916f775 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -426,7 +426,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
/// Split the UART in reader and writer parts.
///
/// This allows reading and writing concurrently from independent tasks.
- pub fn split<'u>(&'u mut self) -> (BufferedUarteRx<'u, 'd, U, T>, BufferedUarteTx<'u, 'd, U, T>) {
+ pub fn split(&mut self) -> (BufferedUarteRx<'_, U, T>, BufferedUarteTx<'_, U, T>) {
(BufferedUarteRx { inner: self }, BufferedUarteTx { inner: self })
}
@@ -570,11 +570,11 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
}
/// Reader part of the buffered UARTE driver.
-pub struct BufferedUarteTx<'u, 'd, U: UarteInstance, T: TimerInstance> {
- inner: &'u BufferedUarte<'d, U, T>,
+pub struct BufferedUarteTx<'d, U: UarteInstance, T: TimerInstance> {
+ inner: &'d BufferedUarte<'d, U, T>,
}
-impl<'u, 'd, U: UarteInstance, T: TimerInstance> BufferedUarteTx<'u, 'd, U, T> {
+impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteTx<'d, U, T> {
/// Write a buffer into this writer, returning how many bytes were written.
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
self.inner.inner_write(buf).await
@@ -587,11 +587,11 @@ impl<'u, 'd, U: UarteInstance, T: TimerInstance> BufferedUarteTx<'u, 'd, U, T> {
}
/// Writer part of the buffered UARTE driver.
-pub struct BufferedUarteRx<'u, 'd, U: UarteInstance, T: TimerInstance> {
- inner: &'u BufferedUarte<'d, U, T>,
+pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
+ inner: &'d BufferedUarte<'d, U, T>,
}
-impl<'u, 'd, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'u, 'd, U, T> {
+impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
self.inner.inner_read(buf).await
@@ -621,11 +621,11 @@ mod _embedded_io {
type Error = Error;
}
- impl<'u, 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteRx<'u, 'd, U, T> {
+ impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteRx<'d, U, T> {
type Error = Error;
}
- impl<'u, 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteTx<'u, 'd, U, T> {
+ impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteTx<'d, U, T> {
type Error = Error;
}
@@ -635,7 +635,7 @@ mod _embedded_io {
}
}
- impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarteRx<'u, 'd, U, T> {
+ impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarteRx<'d, U, T> {
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
self.inner.inner_read(buf).await
}
@@ -651,7 +651,7 @@ mod _embedded_io {
}
}
- impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarteRx<'u, 'd, U, T> {
+ impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarteRx<'d, U, T> {
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
self.inner.inner_fill_buf().await
}
@@ -671,7 +671,7 @@ mod _embedded_io {
}
}
- impl<'u, 'd: 'u, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarteTx<'u, 'd, U, T> {
+ impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarteTx<'d, U, T> {
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
self.inner.inner_write(buf).await
}
From 250cfa5f5f97107fc6c7b8beaa52c61c3a4423df Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 21 Feb 2024 21:07:10 +0100
Subject: [PATCH 277/392] net/tcp: fix flush() not waiting for ACK of FIN.
---
embassy-net/src/tcp.rs | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/embassy-net/src/tcp.rs b/embassy-net/src/tcp.rs
index c508ff97a..57c9b7a04 100644
--- a/embassy-net/src/tcp.rs
+++ b/embassy-net/src/tcp.rs
@@ -491,10 +491,16 @@ impl<'d> TcpIo<'d> {
async fn flush(&mut self) -> Result<(), Error> {
poll_fn(move |cx| {
self.with_mut(|s, _| {
- let waiting_close = s.state() == tcp::State::Closed && s.remote_endpoint().is_some();
+ let data_pending = s.send_queue() > 0;
+ let fin_pending = matches!(
+ s.state(),
+ tcp::State::FinWait1 | tcp::State::Closing | tcp::State::LastAck
+ );
+ let rst_pending = s.state() == tcp::State::Closed && s.remote_endpoint().is_some();
+
// If there are outstanding send operations, register for wake up and wait
// smoltcp issues wake-ups when octets are dequeued from the send buffer
- if s.send_queue() > 0 || waiting_close {
+ if data_pending || fin_pending || rst_pending {
s.register_send_waker(cx.waker());
Poll::Pending
// No outstanding sends, socket is flushed
From c2e429205d2834f255e065475cefd123448d156a Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 21 Feb 2024 21:48:48 +0100
Subject: [PATCH 278/392] nrf/uart: add split_by_ref.
---
embassy-nrf/src/uarte.rs | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 9e5b85dea..90820acab 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -242,6 +242,14 @@ impl<'d, T: Instance> Uarte<'d, T> {
(self.tx, self.rx)
}
+ /// Split the UART in reader and writer parts, by reference.
+ ///
+ /// The returned halves borrow from `self`, so you can drop them and go back to using
+ /// the "un-split" `self`. This allows temporarily splitting the UART.
+ pub fn split_by_ref(&mut self) -> (&mut UarteTx<'d, T>, &mut UarteRx<'d, T>) {
+ (&mut self.tx, &mut self.rx)
+ }
+
/// Split the Uarte into the transmitter and receiver with idle support parts.
///
/// This is useful to concurrently transmit and receive from independent tasks.
From 1f17fdf84ee30f989a1a5bd8945a76a9f5edac4b Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 21 Feb 2024 21:51:43 +0100
Subject: [PATCH 279/392] nrf/buffered_uart: refactor so rx/tx halves are
independent.
---
.../src/atomic_ring_buffer.rs | 33 +-
embassy-nrf/src/buffered_uarte.rs | 463 +++++++++---------
tests/nrf52840/src/bin/buffered_uart.rs | 2 +-
tests/nrf52840/src/bin/buffered_uart_full.rs | 2 +-
4 files changed, 269 insertions(+), 231 deletions(-)
diff --git a/embassy-hal-internal/src/atomic_ring_buffer.rs b/embassy-hal-internal/src/atomic_ring_buffer.rs
index b4f2cec28..34ceac852 100644
--- a/embassy-hal-internal/src/atomic_ring_buffer.rs
+++ b/embassy-hal-internal/src/atomic_ring_buffer.rs
@@ -1,6 +1,6 @@
//! Atomic reusable ringbuffer.
-use core::slice;
use core::sync::atomic::{AtomicPtr, AtomicUsize, Ordering};
+use core::{ptr, slice};
/// Atomic reusable ringbuffer
///
@@ -73,6 +73,7 @@ impl RingBuffer {
pub unsafe fn deinit(&self) {
// Ordering: it's OK to use `Relaxed` because this is not called
// concurrently with other methods.
+ self.buf.store(ptr::null_mut(), Ordering::Relaxed);
self.len.store(0, Ordering::Relaxed);
self.start.store(0, Ordering::Relaxed);
self.end.store(0, Ordering::Relaxed);
@@ -82,20 +83,46 @@ impl RingBuffer {
///
/// # Safety
///
- /// Only one reader can exist at a time.
+ /// - Only one reader can exist at a time.
+ /// - Ringbuffer must be initialized.
pub unsafe fn reader(&self) -> Reader<'_> {
Reader(self)
}
+ /// Try creating a reader, fails if not initialized.
+ ///
+ /// # Safety
+ ///
+ /// Only one reader can exist at a time.
+ pub unsafe fn try_reader(&self) -> Option<Reader<'_>> {
+ if self.buf.load(Ordering::Relaxed).is_null() {
+ return None;
+ }
+ Some(Reader(self))
+ }
+
/// Create a writer.
///
/// # Safety
///
- /// Only one writer can exist at a time.
+ /// - Only one writer can exist at a time.
+ /// - Ringbuffer must be initialized.
pub unsafe fn writer(&self) -> Writer<'_> {
Writer(self)
}
+ /// Try creating a writer, fails if not initialized.
+ ///
+ /// # Safety
+ ///
+ /// Only one writer can exist at a time.
+ pub unsafe fn try_writer(&self) -> Option<Writer<'_>> {
+ if self.buf.load(Ordering::Relaxed).is_null() {
+ return None;
+ }
+ Some(Writer(self))
+ }
+
/// Return length of buffer.
pub fn len(&self) -> usize {
self.len.load(Ordering::Relaxed)
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index e0916f775..b1b639f10 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -22,13 +22,13 @@ use embassy_sync::waitqueue::AtomicWaker;
pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
use crate::gpio::sealed::Pin;
-use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
+use crate::gpio::{AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::typelevel::Interrupt;
use crate::ppi::{
self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
};
use crate::timer::{Instance as TimerInstance, Timer};
-use crate::uarte::{apply_workaround_for_enable_anomaly, Config, Instance as UarteInstance};
+use crate::uarte::{apply_workaround_for_enable_anomaly, drop_tx_rx, Config, Instance as UarteInstance};
use crate::{interrupt, pac, Peripheral};
mod sealed {
@@ -86,126 +86,128 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
let r = U::regs();
let s = U::buffered_state();
- let buf_len = s.rx_buf.len();
- let half_len = buf_len / 2;
- let mut tx = unsafe { s.tx_buf.reader() };
- let mut rx = unsafe { s.rx_buf.writer() };
+ if let Some(mut rx) = unsafe { s.rx_buf.try_writer() } {
+ let buf_len = s.rx_buf.len();
+ let half_len = buf_len / 2;
- if r.events_error.read().bits() != 0 {
- r.events_error.reset();
- let errs = r.errorsrc.read();
- r.errorsrc.write(|w| unsafe { w.bits(errs.bits()) });
+ if r.events_error.read().bits() != 0 {
+ r.events_error.reset();
+ let errs = r.errorsrc.read();
+ r.errorsrc.write(|w| unsafe { w.bits(errs.bits()) });
- if errs.overrun().bit() {
- panic!("BufferedUarte overrun");
+ if errs.overrun().bit() {
+ panic!("BufferedUarte overrun");
+ }
}
- }
- // Received some bytes, wake task.
- if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
- r.intenclr.write(|w| w.rxdrdy().clear());
- r.events_rxdrdy.reset();
- s.rx_waker.wake();
- }
+ // Received some bytes, wake task.
+ if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
+ r.intenclr.write(|w| w.rxdrdy().clear());
+ r.events_rxdrdy.reset();
+ s.rx_waker.wake();
+ }
- if r.events_endrx.read().bits() != 0 {
- //trace!(" irq_rx: endrx");
- r.events_endrx.reset();
+ if r.events_endrx.read().bits() != 0 {
+ //trace!(" irq_rx: endrx");
+ r.events_endrx.reset();
- let val = s.rx_ended_count.load(Ordering::Relaxed);
- s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
- }
+ let val = s.rx_ended_count.load(Ordering::Relaxed);
+ s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
+ }
- if r.events_rxstarted.read().bits() != 0 || !s.rx_started.load(Ordering::Relaxed) {
- //trace!(" irq_rx: rxstarted");
- let (ptr, len) = rx.push_buf();
- if len >= half_len {
- r.events_rxstarted.reset();
+ if r.events_rxstarted.read().bits() != 0 || !s.rx_started.load(Ordering::Relaxed) {
+ //trace!(" irq_rx: rxstarted");
+ let (ptr, len) = rx.push_buf();
+ if len >= half_len {
+ r.events_rxstarted.reset();
- //trace!(" irq_rx: starting second {:?}", half_len);
+ //trace!(" irq_rx: starting second {:?}", half_len);
- // Set up the DMA read
- r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
- r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
+ // Set up the DMA read
+ r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
+ r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
- let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
+ let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
- // Enable endrx -> startrx PPI channel.
- // From this point on, if endrx happens, startrx is automatically fired.
- ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
+ // Enable endrx -> startrx PPI channel.
+ // From this point on, if endrx happens, startrx is automatically fired.
+ ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
- // It is possible that endrx happened BEFORE enabling the PPI. In this case
- // the PPI channel doesn't trigger, and we'd hang. We have to detect this
- // and manually start.
+ // It is possible that endrx happened BEFORE enabling the PPI. In this case
+ // the PPI channel doesn't trigger, and we'd hang. We have to detect this
+ // and manually start.
- // check again in case endrx has happened between the last check and now.
- if r.events_endrx.read().bits() != 0 {
- //trace!(" irq_rx: endrx");
- r.events_endrx.reset();
+ // check again in case endrx has happened between the last check and now.
+ if r.events_endrx.read().bits() != 0 {
+ //trace!(" irq_rx: endrx");
+ r.events_endrx.reset();
- let val = s.rx_ended_count.load(Ordering::Relaxed);
- s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
+ let val = s.rx_ended_count.load(Ordering::Relaxed);
+ s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
+ }
+
+ let rx_ended = s.rx_ended_count.load(Ordering::Relaxed);
+ let rx_started = s.rx_started_count.load(Ordering::Relaxed);
+
+ // If we started the same amount of transfers as ended, the last rxend has
+ // already occured.
+ let rxend_happened = rx_started == rx_ended;
+
+ // Check if the PPI channel is still enabled. The PPI channel disables itself
+ // when it fires, so if it's still enabled it hasn't fired.
+ let ppi_ch_enabled = ppi::regs().chen.read().bits() & (1 << chn) != 0;
+
+ // if rxend happened, and the ppi channel hasn't fired yet, the rxend got missed.
+ // this condition also naturally matches if `!started`, needed to kickstart the DMA.
+ if rxend_happened && ppi_ch_enabled {
+ //trace!("manually starting.");
+
+ // disable the ppi ch, it's of no use anymore.
+ ppi::regs().chenclr.write(|w| unsafe { w.bits(1 << chn) });
+
+ // manually start
+ r.tasks_startrx.write(|w| unsafe { w.bits(1) });
+ }
+
+ rx.push_done(half_len);
+
+ s.rx_started_count.store(rx_started.wrapping_add(1), Ordering::Relaxed);
+ s.rx_started.store(true, Ordering::Relaxed);
+ } else {
+ //trace!(" irq_rx: rxstarted no buf");
+ r.intenclr.write(|w| w.rxstarted().clear());
}
-
- let rx_ended = s.rx_ended_count.load(Ordering::Relaxed);
- let rx_started = s.rx_started_count.load(Ordering::Relaxed);
-
- // If we started the same amount of transfers as ended, the last rxend has
- // already occured.
- let rxend_happened = rx_started == rx_ended;
-
- // Check if the PPI channel is still enabled. The PPI channel disables itself
- // when it fires, so if it's still enabled it hasn't fired.
- let ppi_ch_enabled = ppi::regs().chen.read().bits() & (1 << chn) != 0;
-
- // if rxend happened, and the ppi channel hasn't fired yet, the rxend got missed.
- // this condition also naturally matches if `!started`, needed to kickstart the DMA.
- if rxend_happened && ppi_ch_enabled {
- //trace!("manually starting.");
-
- // disable the ppi ch, it's of no use anymore.
- ppi::regs().chenclr.write(|w| unsafe { w.bits(1 << chn) });
-
- // manually start
- r.tasks_startrx.write(|w| unsafe { w.bits(1) });
- }
-
- rx.push_done(half_len);
-
- s.rx_started_count.store(rx_started.wrapping_add(1), Ordering::Relaxed);
- s.rx_started.store(true, Ordering::Relaxed);
- } else {
- //trace!(" irq_rx: rxstarted no buf");
- r.intenclr.write(|w| w.rxstarted().clear());
}
}
// =============================
- // TX end
- if r.events_endtx.read().bits() != 0 {
- r.events_endtx.reset();
+ if let Some(mut tx) = unsafe { s.tx_buf.try_reader() } {
+ // TX end
+ if r.events_endtx.read().bits() != 0 {
+ r.events_endtx.reset();
- let n = s.tx_count.load(Ordering::Relaxed);
- //trace!(" irq_tx: endtx {:?}", n);
- tx.pop_done(n);
- s.tx_waker.wake();
- s.tx_count.store(0, Ordering::Relaxed);
- }
+ let n = s.tx_count.load(Ordering::Relaxed);
+ //trace!(" irq_tx: endtx {:?}", n);
+ tx.pop_done(n);
+ s.tx_waker.wake();
+ s.tx_count.store(0, Ordering::Relaxed);
+ }
- // If not TXing, start.
- if s.tx_count.load(Ordering::Relaxed) == 0 {
- let (ptr, len) = tx.pop_buf();
- if len != 0 {
- //trace!(" irq_tx: starting {:?}", len);
- s.tx_count.store(len, Ordering::Relaxed);
+ // If not TXing, start.
+ if s.tx_count.load(Ordering::Relaxed) == 0 {
+ let (ptr, len) = tx.pop_buf();
+ if len != 0 {
+ //trace!(" irq_tx: starting {:?}", len);
+ s.tx_count.store(len, Ordering::Relaxed);
- // Set up the DMA write
- r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
- r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
+ // Set up the DMA write
+ r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
+ r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
- // Start UARTE Transmit transaction
- r.tasks_starttx.write(|w| unsafe { w.bits(1) });
+ // Start UARTE Transmit transaction
+ r.tasks_starttx.write(|w| unsafe { w.bits(1) });
+ }
}
}
@@ -215,11 +217,8 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
/// Buffered UARTE driver.
pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
- _peri: PeripheralRef<'d, U>,
- timer: Timer<'d, T>,
- _ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
- _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
- _ppi_group: PpiGroup<'d, AnyGroup>,
+ tx: BufferedUarteTx<'d, U>,
+ rx: BufferedUarteRx<'d, U, T>,
}
impl<'d, U: UarteInstance, T: TimerInstance> Unpin for BufferedUarte<'d, U, T> {}
@@ -404,17 +403,21 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
U::Interrupt::pend();
unsafe { U::Interrupt::enable() };
- Self {
- _peri: peri,
- timer,
- _ppi_ch1: ppi_ch1,
- _ppi_ch2: ppi_ch2,
- _ppi_group: ppi_group,
- }
- }
+ let s = U::state();
+ s.tx_rx_refcount.store(2, Ordering::Relaxed);
- fn pend_irq() {
- U::Interrupt::pend()
+ Self {
+ tx: BufferedUarteTx {
+ _peri: unsafe { peri.clone_unchecked() },
+ },
+ rx: BufferedUarteRx {
+ _peri: peri,
+ timer,
+ _ppi_ch1: ppi_ch1,
+ _ppi_ch2: ppi_ch2,
+ _ppi_group: ppi_group,
+ },
+ }
}
/// Adjust the baud rate to the provided value.
@@ -426,19 +429,52 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
/// Split the UART in reader and writer parts.
///
/// This allows reading and writing concurrently from independent tasks.
- pub fn split(&mut self) -> (BufferedUarteRx<'_, U, T>, BufferedUarteTx<'_, U, T>) {
- (BufferedUarteRx { inner: self }, BufferedUarteTx { inner: self })
+ pub fn split(self) -> (BufferedUarteRx<'d, U, T>, BufferedUarteTx<'d, U>) {
+ (self.rx, self.tx)
}
- async fn inner_read(&self, buf: &mut [u8]) -> Result<usize, Error> {
- let data = self.inner_fill_buf().await?;
- let n = data.len().min(buf.len());
- buf[..n].copy_from_slice(&data[..n]);
- self.inner_consume(n);
- Ok(n)
+ /// Split the UART in reader and writer parts, by reference.
+ ///
+ /// The returned halves borrow from `self`, so you can drop them and go back to using
+ /// the "un-split" `self`. This allows temporarily splitting the UART.
+ pub fn split_by_ref(&mut self) -> (&mut BufferedUarteRx<'d, U, T>, &mut BufferedUarteTx<'d, U>) {
+ (&mut self.rx, &mut self.tx)
}
- async fn inner_write<'a>(&'a self, buf: &'a [u8]) -> Result<usize, Error> {
+ /// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
+ pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
+ self.rx.read(buf).await
+ }
+
+ /// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
+ pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
+ self.rx.fill_buf().await
+ }
+
+ /// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
+ pub fn consume(&mut self, amt: usize) {
+ self.rx.consume(amt)
+ }
+
+ /// Write a buffer into this writer, returning how many bytes were written.
+ pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
+ self.tx.write(buf).await
+ }
+
+ /// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
+ pub async fn flush(&mut self) -> Result<(), Error> {
+ self.tx.flush().await
+ }
+}
+
+/// Reader part of the buffered UARTE driver.
+pub struct BufferedUarteTx<'d, U: UarteInstance> {
+ _peri: PeripheralRef<'d, U>,
+}
+
+impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
+ /// Write a buffer into this writer, returning how many bytes were written.
+ pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
poll_fn(move |cx| {
//trace!("poll_write: {:?}", buf.len());
let s = U::buffered_state();
@@ -458,14 +494,15 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
//trace!("poll_write: queued {:?}", n);
compiler_fence(Ordering::SeqCst);
- Self::pend_irq();
+ U::Interrupt::pend();
Poll::Ready(Ok(n))
})
.await
}
- async fn inner_flush<'a>(&'a self) -> Result<(), Error> {
+ /// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
+ pub async fn flush(&mut self) -> Result<(), Error> {
poll_fn(move |cx| {
//trace!("poll_flush");
let s = U::buffered_state();
@@ -479,8 +516,51 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
})
.await
}
+}
- async fn inner_fill_buf<'a>(&'a self) -> Result<&'a [u8], Error> {
+impl<'a, U: UarteInstance> Drop for BufferedUarteTx<'a, U> {
+ fn drop(&mut self) {
+ let r = U::regs();
+
+ r.intenclr.write(|w| {
+ w.txdrdy().set_bit();
+ w.txstarted().set_bit();
+ w.txstopped().set_bit();
+ w
+ });
+ r.events_txstopped.reset();
+ r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
+ while r.events_txstopped.read().bits() == 0 {}
+
+ let s = U::buffered_state();
+ unsafe { s.tx_buf.deinit() }
+
+ let s = U::state();
+ drop_tx_rx(r, s);
+ }
+}
+
+/// Reader part of the buffered UARTE driver.
+pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
+ _peri: PeripheralRef<'d, U>,
+ timer: Timer<'d, T>,
+ _ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 1>,
+ _ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 2>,
+ _ppi_group: PpiGroup<'d, AnyGroup>,
+}
+
+impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
+ /// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
+ pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
+ let data = self.fill_buf().await?;
+ let n = data.len().min(buf.len());
+ buf[..n].copy_from_slice(&data[..n]);
+ self.consume(n);
+ Ok(n)
+ }
+
+ /// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
+ pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
poll_fn(move |cx| {
compiler_fence(Ordering::SeqCst);
//trace!("poll_read");
@@ -532,7 +612,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
.await
}
- fn inner_consume(&self, amt: usize) {
+ /// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
+ pub fn consume(&mut self, amt: usize) {
if amt == 0 {
return;
}
@@ -542,69 +623,31 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
rx.pop_done(amt);
U::regs().intenset.write(|w| w.rxstarted().set());
}
-
- /// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
- pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
- self.inner_read(buf).await
- }
-
- /// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
- pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
- self.inner_fill_buf().await
- }
-
- /// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
- pub fn consume(&mut self, amt: usize) {
- self.inner_consume(amt)
- }
-
- /// Write a buffer into this writer, returning how many bytes were written.
- pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
- self.inner_write(buf).await
- }
-
- /// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
- pub async fn flush(&mut self) -> Result<(), Error> {
- self.inner_flush().await
- }
}
-/// Reader part of the buffered UARTE driver.
-pub struct BufferedUarteTx<'d, U: UarteInstance, T: TimerInstance> {
- inner: &'d BufferedUarte<'d, U, T>,
-}
+impl<'a, U: UarteInstance, T: TimerInstance> Drop for BufferedUarteRx<'a, U, T> {
+ fn drop(&mut self) {
+ self._ppi_group.disable_all();
-impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteTx<'d, U, T> {
- /// Write a buffer into this writer, returning how many bytes were written.
- pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
- self.inner.inner_write(buf).await
- }
+ let r = U::regs();
- /// Flush this output stream, ensuring that all intermediately buffered contents reach their destination.
- pub async fn flush(&mut self) -> Result<(), Error> {
- self.inner.inner_flush().await
- }
-}
+ self.timer.stop();
-/// Writer part of the buffered UARTE driver.
-pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
- inner: &'d BufferedUarte<'d, U, T>,
-}
+ r.intenclr.write(|w| {
+ w.rxdrdy().set_bit();
+ w.rxstarted().set_bit();
+ w.rxto().set_bit();
+ w
+ });
+ r.events_rxto.reset();
+ r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
+ while r.events_rxto.read().bits() == 0 {}
-impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
- /// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
- pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
- self.inner.inner_read(buf).await
- }
+ let s = U::buffered_state();
+ unsafe { s.rx_buf.deinit() }
- /// Return the contents of the internal buffer, filling it with more data from the inner reader if it is empty.
- pub async fn fill_buf(&mut self) -> Result<&[u8], Error> {
- self.inner.inner_fill_buf().await
- }
-
- /// Tell this buffer that `amt` bytes have been consumed from the buffer, so they should no longer be returned in calls to `fill_buf`.
- pub fn consume(&mut self, amt: usize) {
- self.inner.inner_consume(amt)
+ let s = U::state();
+ drop_tx_rx(r, s);
}
}
@@ -625,91 +668,59 @@ mod _embedded_io {
type Error = Error;
}
- impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::ErrorType for BufferedUarteTx<'d, U, T> {
+ impl<'d, U: UarteInstance> embedded_io_async::ErrorType for BufferedUarteTx<'d, U> {
type Error = Error;
}
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarte<'d, U, T> {
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
- self.inner_read(buf).await
+ self.read(buf).await
}
}
impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::Read for BufferedUarteRx<'d, U, T> {
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
- self.inner.inner_read(buf).await
+ self.read(buf).await
}
}
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarte<'d, U, T> {
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
- self.inner_fill_buf().await
+ self.fill_buf().await
}
fn consume(&mut self, amt: usize) {
- self.inner_consume(amt)
+ self.consume(amt)
}
}
impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::BufRead for BufferedUarteRx<'d, U, T> {
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
- self.inner.inner_fill_buf().await
+ self.fill_buf().await
}
fn consume(&mut self, amt: usize) {
- self.inner.inner_consume(amt)
+ self.consume(amt)
}
}
impl<'d, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarte<'d, U, T> {
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
- self.inner_write(buf).await
+ self.write(buf).await
}
async fn flush(&mut self) -> Result<(), Self::Error> {
- self.inner_flush().await
+ self.flush().await
}
}
- impl<'d: 'd, U: UarteInstance, T: TimerInstance> embedded_io_async::Write for BufferedUarteTx<'d, U, T> {
+ impl<'d: 'd, U: UarteInstance> embedded_io_async::Write for BufferedUarteTx<'d, U> {
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
- self.inner.inner_write(buf).await
+ self.write(buf).await
}
async fn flush(&mut self) -> Result<(), Self::Error> {
- self.inner.inner_flush().await
- }
- }
-}
-
-impl<'a, U: UarteInstance, T: TimerInstance> Drop for BufferedUarte<'a, U, T> {
- fn drop(&mut self) {
- self._ppi_group.disable_all();
-
- let r = U::regs();
-
- self.timer.stop();
-
- r.inten.reset();
- r.events_rxto.reset();
- r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
- r.events_txstopped.reset();
- r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
-
- while r.events_txstopped.read().bits() == 0 {}
- while r.events_rxto.read().bits() == 0 {}
-
- r.enable.write(|w| w.enable().disabled());
-
- gpio::deconfigure_pin(r.psel.rxd.read().bits());
- gpio::deconfigure_pin(r.psel.txd.read().bits());
- gpio::deconfigure_pin(r.psel.rts.read().bits());
- gpio::deconfigure_pin(r.psel.cts.read().bits());
-
- let s = U::buffered_state();
- unsafe {
- s.rx_buf.deinit();
- s.tx_buf.deinit();
+ self.flush().await
}
}
}
diff --git a/tests/nrf52840/src/bin/buffered_uart.rs b/tests/nrf52840/src/bin/buffered_uart.rs
index 354d787b4..721751136 100644
--- a/tests/nrf52840/src/bin/buffered_uart.rs
+++ b/tests/nrf52840/src/bin/buffered_uart.rs
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
let mut tx_buffer = [0u8; 1024];
let mut rx_buffer = [0u8; 1024];
- let mut u = BufferedUarte::new(
+ let u = BufferedUarte::new(
p.UARTE0,
p.TIMER0,
p.PPI_CH0,
diff --git a/tests/nrf52840/src/bin/buffered_uart_full.rs b/tests/nrf52840/src/bin/buffered_uart_full.rs
index e59c75ba9..62edaed25 100644
--- a/tests/nrf52840/src/bin/buffered_uart_full.rs
+++ b/tests/nrf52840/src/bin/buffered_uart_full.rs
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
let mut tx_buffer = [0u8; 1024];
let mut rx_buffer = [0u8; 1024];
- let mut u = BufferedUarte::new(
+ let u = BufferedUarte::new(
p.UARTE0,
p.TIMER0,
p.PPI_CH0,
From 4fbe18f82134567af4766d161e8385c7dd919a0b Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 21 Feb 2024 22:29:37 +0100
Subject: [PATCH 280/392] nrf/uart: share waker state between buffered and
nonbuffered.
---
embassy-nrf/src/buffered_uarte.rs | 19 +++++++++----------
embassy-nrf/src/uarte.rs | 18 +++++++++---------
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index b1b639f10..18416483f 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -17,7 +17,6 @@ use core::task::Poll;
use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
use embassy_hal_internal::{into_ref, PeripheralRef};
-use embassy_sync::waitqueue::AtomicWaker;
// Re-export SVD variants to allow user to directly set values
pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
@@ -35,11 +34,9 @@ mod sealed {
use super::*;
pub struct State {
- pub tx_waker: AtomicWaker,
pub tx_buf: RingBuffer,
pub tx_count: AtomicUsize,
- pub rx_waker: AtomicWaker,
pub rx_buf: RingBuffer,
pub rx_started: AtomicBool,
pub rx_started_count: AtomicU8,
@@ -61,11 +58,9 @@ pub(crate) use sealed::State;
impl State {
pub(crate) const fn new() -> Self {
Self {
- tx_waker: AtomicWaker::new(),
tx_buf: RingBuffer::new(),
tx_count: AtomicUsize::new(0),
- rx_waker: AtomicWaker::new(),
rx_buf: RingBuffer::new(),
rx_started: AtomicBool::new(false),
rx_started_count: AtomicU8::new(0),
@@ -84,6 +79,7 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
unsafe fn on_interrupt() {
//trace!("irq: start");
let r = U::regs();
+ let ss = U::state();
let s = U::buffered_state();
if let Some(mut rx) = unsafe { s.rx_buf.try_writer() } {
@@ -104,7 +100,7 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
if r.inten.read().rxdrdy().bit_is_set() && r.events_rxdrdy.read().bits() != 0 {
r.intenclr.write(|w| w.rxdrdy().clear());
r.events_rxdrdy.reset();
- s.rx_waker.wake();
+ ss.rx_waker.wake();
}
if r.events_endrx.read().bits() != 0 {
@@ -190,7 +186,7 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
let n = s.tx_count.load(Ordering::Relaxed);
//trace!(" irq_tx: endtx {:?}", n);
tx.pop_done(n);
- s.tx_waker.wake();
+ ss.tx_waker.wake();
s.tx_count.store(0, Ordering::Relaxed);
}
@@ -477,13 +473,14 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
poll_fn(move |cx| {
//trace!("poll_write: {:?}", buf.len());
+ let ss = U::state();
let s = U::buffered_state();
let mut tx = unsafe { s.tx_buf.writer() };
let tx_buf = tx.push_slice();
if tx_buf.is_empty() {
//trace!("poll_write: pending");
- s.tx_waker.register(cx.waker());
+ ss.tx_waker.register(cx.waker());
return Poll::Pending;
}
@@ -505,10 +502,11 @@ impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
pub async fn flush(&mut self) -> Result<(), Error> {
poll_fn(move |cx| {
//trace!("poll_flush");
+ let ss = U::state();
let s = U::buffered_state();
if !s.tx_buf.is_empty() {
//trace!("poll_flush: pending");
- s.tx_waker.register(cx.waker());
+ ss.tx_waker.register(cx.waker());
return Poll::Pending;
}
@@ -567,6 +565,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
let r = U::regs();
let s = U::buffered_state();
+ let ss = U::state();
// Read the RXDRDY counter.
T::regs().tasks_capture[0].write(|w| unsafe { w.bits(1) });
@@ -590,7 +589,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
let len = s.rx_buf.len();
if start == end {
//trace!(" empty");
- s.rx_waker.register(cx.waker());
+ ss.rx_waker.register(cx.waker());
r.intenset.write(|w| w.rxdrdy().set_bit());
return Poll::Pending;
}
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 90820acab..cd14c718a 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -115,7 +115,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
let endrx = r.events_endrx.read().bits();
let error = r.events_error.read().bits();
if endrx != 0 || error != 0 {
- s.endrx_waker.wake();
+ s.rx_waker.wake();
if endrx != 0 {
r.intenclr.write(|w| w.endrx().clear());
}
@@ -124,7 +124,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
}
}
if r.events_endtx.read().bits() != 0 {
- s.endtx_waker.wake();
+ s.tx_waker.wake();
r.intenclr.write(|w| w.endtx().clear());
}
}
@@ -433,7 +433,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
r.tasks_starttx.write(|w| unsafe { w.bits(1) });
poll_fn(|cx| {
- s.endtx_waker.register(cx.waker());
+ s.tx_waker.register(cx.waker());
if r.events_endtx.read().bits() != 0 {
return Poll::Ready(());
}
@@ -680,7 +680,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
let result = poll_fn(|cx| {
- s.endrx_waker.register(cx.waker());
+ s.rx_waker.register(cx.waker());
if let Err(e) = self.check_and_clear_errors() {
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
@@ -827,7 +827,7 @@ impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
let result = poll_fn(|cx| {
- s.endrx_waker.register(cx.waker());
+ s.rx_waker.register(cx.waker());
if let Err(e) = self.rx.check_and_clear_errors() {
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
@@ -970,15 +970,15 @@ pub(crate) mod sealed {
use super::*;
pub struct State {
- pub endrx_waker: AtomicWaker,
- pub endtx_waker: AtomicWaker,
+ pub rx_waker: AtomicWaker,
+ pub tx_waker: AtomicWaker,
pub tx_rx_refcount: AtomicU8,
}
impl State {
pub const fn new() -> Self {
Self {
- endrx_waker: AtomicWaker::new(),
- endtx_waker: AtomicWaker::new(),
+ rx_waker: AtomicWaker::new(),
+ tx_waker: AtomicWaker::new(),
tx_rx_refcount: AtomicU8::new(0),
}
}
From 2feed96c91e2bd3846452e87b575b3d57ae3cde8 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 21 Feb 2024 23:23:04 +0100
Subject: [PATCH 281/392] nrf/uart: Add support for rx-only or tx-only
BufferedUart.
---
embassy-nrf/src/buffered_uarte.rs | 361 +++++++++++++++++++++---------
embassy-nrf/src/uarte.rs | 2 +-
2 files changed, 255 insertions(+), 108 deletions(-)
diff --git a/embassy-nrf/src/buffered_uarte.rs b/embassy-nrf/src/buffered_uarte.rs
index 18416483f..b04c96e09 100644
--- a/embassy-nrf/src/buffered_uarte.rs
+++ b/embassy-nrf/src/buffered_uarte.rs
@@ -27,7 +27,7 @@ use crate::ppi::{
self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
};
use crate::timer::{Instance as TimerInstance, Timer};
-use crate::uarte::{apply_workaround_for_enable_anomaly, drop_tx_rx, Config, Instance as UarteInstance};
+use crate::uarte::{configure, drop_tx_rx, Config, Instance as UarteInstance};
use crate::{interrupt, pac, Peripheral};
mod sealed {
@@ -238,7 +238,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
rx_buffer: &'d mut [u8],
tx_buffer: &'d mut [u8],
) -> Self {
- into_ref!(rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
+ into_ref!(uarte, timer, rxd, txd, ppi_ch1, ppi_ch2, ppi_group);
Self::new_inner(
uarte,
timer,
@@ -275,7 +275,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
rx_buffer: &'d mut [u8],
tx_buffer: &'d mut [u8],
) -> Self {
- into_ref!(rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
+ into_ref!(uarte, timer, rxd, txd, cts, rts, ppi_ch1, ppi_ch2, ppi_group);
Self::new_inner(
uarte,
timer,
@@ -293,8 +293,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
}
fn new_inner(
- peri: impl Peripheral<P = U> + 'd,
- timer: impl Peripheral<P = T> + 'd,
+ peri: PeripheralRef<'d, U>,
+ timer: PeripheralRef<'d, T>,
ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
ppi_group: PeripheralRef<'d, AnyGroup>,
@@ -306,114 +306,17 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
rx_buffer: &'d mut [u8],
tx_buffer: &'d mut [u8],
) -> Self {
- into_ref!(peri, timer);
+ configure(U::regs(), config, cts.is_some());
- assert!(rx_buffer.len() % 2 == 0);
-
- let r = U::regs();
-
- let hwfc = cts.is_some();
-
- rxd.conf().write(|w| w.input().connect().drive().h0h1());
- r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
-
- txd.set_high();
- txd.conf().write(|w| w.dir().output().drive().h0h1());
- r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
-
- if let Some(pin) = &cts {
- pin.conf().write(|w| w.input().connect().drive().h0h1());
- }
- r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
-
- if let Some(pin) = &rts {
- pin.set_high();
- pin.conf().write(|w| w.dir().output().drive().h0h1());
- }
- r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
-
- // Initialize state
- let s = U::buffered_state();
- s.tx_count.store(0, Ordering::Relaxed);
- s.rx_started_count.store(0, Ordering::Relaxed);
- s.rx_ended_count.store(0, Ordering::Relaxed);
- s.rx_started.store(false, Ordering::Relaxed);
- let len = tx_buffer.len();
- unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
- let len = rx_buffer.len();
- unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
-
- // Configure
- r.config.write(|w| {
- w.hwfc().bit(hwfc);
- w.parity().variant(config.parity);
- w
- });
- r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
-
- // clear errors
- let errors = r.errorsrc.read().bits();
- r.errorsrc.write(|w| unsafe { w.bits(errors) });
-
- r.events_rxstarted.reset();
- r.events_txstarted.reset();
- r.events_error.reset();
- r.events_endrx.reset();
- r.events_endtx.reset();
-
- // Enable interrupts
- r.intenclr.write(|w| unsafe { w.bits(!0) });
- r.intenset.write(|w| {
- w.endtx().set();
- w.rxstarted().set();
- w.error().set();
- w.endrx().set();
- w
- });
-
- // Enable UARTE instance
- apply_workaround_for_enable_anomaly(r);
- r.enable.write(|w| w.enable().enabled());
-
- // Configure byte counter.
- let timer = Timer::new_counter(timer);
- timer.cc(1).write(rx_buffer.len() as u32 * 2);
- timer.cc(1).short_compare_clear();
- timer.clear();
- timer.start();
-
- let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_rxdrdy), timer.task_count());
- ppi_ch1.enable();
-
- s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
- let mut ppi_group = PpiGroup::new(ppi_group);
- let mut ppi_ch2 = Ppi::new_one_to_two(
- ppi_ch2,
- Event::from_reg(&r.events_endrx),
- Task::from_reg(&r.tasks_startrx),
- ppi_group.task_disable_all(),
- );
- ppi_ch2.disable();
- ppi_group.add_channel(&ppi_ch2);
+ let tx = BufferedUarteTx::new_innerer(unsafe { peri.clone_unchecked() }, txd, cts, tx_buffer);
+ let rx = BufferedUarteRx::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
U::Interrupt::pend();
unsafe { U::Interrupt::enable() };
- let s = U::state();
- s.tx_rx_refcount.store(2, Ordering::Relaxed);
+ U::state().tx_rx_refcount.store(2, Ordering::Relaxed);
- Self {
- tx: BufferedUarteTx {
- _peri: unsafe { peri.clone_unchecked() },
- },
- rx: BufferedUarteRx {
- _peri: peri,
- timer,
- _ppi_ch1: ppi_ch1,
- _ppi_ch2: ppi_ch2,
- _ppi_group: ppi_group,
- },
- }
+ Self { tx, rx }
}
/// Adjust the baud rate to the provided value.
@@ -469,6 +372,88 @@ pub struct BufferedUarteTx<'d, U: UarteInstance> {
}
impl<'d, U: UarteInstance> BufferedUarteTx<'d, U> {
+ /// Create a new BufferedUarteTx without hardware flow control.
+ pub fn new(
+ uarte: impl Peripheral<P = U> + 'd,
+ _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
+ txd: impl Peripheral<P = impl GpioPin> + 'd,
+ config: Config,
+ tx_buffer: &'d mut [u8],
+ ) -> Self {
+ into_ref!(uarte, txd);
+ Self::new_inner(uarte, txd.map_into(), None, config, tx_buffer)
+ }
+
+ /// Create a new BufferedUarte with hardware flow control (RTS/CTS)
+ ///
+ /// # Panics
+ ///
+ /// Panics if `rx_buffer.len()` is odd.
+ pub fn new_with_cts(
+ uarte: impl Peripheral<P = U> + 'd,
+ _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
+ txd: impl Peripheral<P = impl GpioPin> + 'd,
+ cts: impl Peripheral<P = impl GpioPin> + 'd,
+ config: Config,
+ tx_buffer: &'d mut [u8],
+ ) -> Self {
+ into_ref!(uarte, txd, cts);
+ Self::new_inner(uarte, txd.map_into(), Some(cts.map_into()), config, tx_buffer)
+ }
+
+ fn new_inner(
+ peri: PeripheralRef<'d, U>,
+ txd: PeripheralRef<'d, AnyPin>,
+ cts: Option<PeripheralRef<'d, AnyPin>>,
+ config: Config,
+ tx_buffer: &'d mut [u8],
+ ) -> Self {
+ configure(U::regs(), config, cts.is_some());
+
+ let this = Self::new_innerer(peri, txd, cts, tx_buffer);
+
+ U::Interrupt::pend();
+ unsafe { U::Interrupt::enable() };
+
+ U::state().tx_rx_refcount.store(1, Ordering::Relaxed);
+
+ this
+ }
+
+ fn new_innerer(
+ peri: PeripheralRef<'d, U>,
+ txd: PeripheralRef<'d, AnyPin>,
+ cts: Option<PeripheralRef<'d, AnyPin>>,
+ tx_buffer: &'d mut [u8],
+ ) -> Self {
+ let r = U::regs();
+
+ txd.set_high();
+ txd.conf().write(|w| w.dir().output().drive().h0h1());
+ r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
+
+ if let Some(pin) = &cts {
+ pin.conf().write(|w| w.input().connect().drive().h0h1());
+ }
+ r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
+
+ // Initialize state
+ let s = U::buffered_state();
+ s.tx_count.store(0, Ordering::Relaxed);
+ let len = tx_buffer.len();
+ unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
+
+ r.events_txstarted.reset();
+
+ // Enable interrupts
+ r.intenset.write(|w| {
+ w.endtx().set();
+ w
+ });
+
+ Self { _peri: peri }
+ }
+
/// Write a buffer into this writer, returning how many bytes were written.
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
poll_fn(move |cx| {
@@ -548,6 +533,168 @@ pub struct BufferedUarteRx<'d, U: UarteInstance, T: TimerInstance> {
}
impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarteRx<'d, U, T> {
+ /// Create a new BufferedUarte without hardware flow control.
+ ///
+ /// # Panics
+ ///
+ /// Panics if `rx_buffer.len()` is odd.
+ pub fn new(
+ uarte: impl Peripheral<P = U> + 'd,
+ timer: impl Peripheral<P = T> + 'd,
+ ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
+ ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
+ ppi_group: impl Peripheral<P = impl Group> + 'd,
+ _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
+ rxd: impl Peripheral<P = impl GpioPin> + 'd,
+ config: Config,
+ rx_buffer: &'d mut [u8],
+ ) -> Self {
+ into_ref!(uarte, timer, rxd, ppi_ch1, ppi_ch2, ppi_group);
+ Self::new_inner(
+ uarte,
+ timer,
+ ppi_ch1.map_into(),
+ ppi_ch2.map_into(),
+ ppi_group.map_into(),
+ rxd.map_into(),
+ None,
+ config,
+ rx_buffer,
+ )
+ }
+
+ /// Create a new BufferedUarte with hardware flow control (RTS/CTS)
+ ///
+ /// # Panics
+ ///
+ /// Panics if `rx_buffer.len()` is odd.
+ pub fn new_with_rts(
+ uarte: impl Peripheral<P = U> + 'd,
+ timer: impl Peripheral<P = T> + 'd,
+ ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
+ ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
+ ppi_group: impl Peripheral<P = impl Group> + 'd,
+ _irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
+ rxd: impl Peripheral<P = impl GpioPin> + 'd,
+ rts: impl Peripheral<P = impl GpioPin> + 'd,
+ config: Config,
+ rx_buffer: &'d mut [u8],
+ ) -> Self {
+ into_ref!(uarte, timer, rxd, rts, ppi_ch1, ppi_ch2, ppi_group);
+ Self::new_inner(
+ uarte,
+ timer,
+ ppi_ch1.map_into(),
+ ppi_ch2.map_into(),
+ ppi_group.map_into(),
+ rxd.map_into(),
+ Some(rts.map_into()),
+ config,
+ rx_buffer,
+ )
+ }
+
+ fn new_inner(
+ peri: PeripheralRef<'d, U>,
+ timer: PeripheralRef<'d, T>,
+ ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
+ ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
+ ppi_group: PeripheralRef<'d, AnyGroup>,
+ rxd: PeripheralRef<'d, AnyPin>,
+ rts: Option<PeripheralRef<'d, AnyPin>>,
+ config: Config,
+ rx_buffer: &'d mut [u8],
+ ) -> Self {
+ configure(U::regs(), config, rts.is_some());
+
+ let this = Self::new_innerer(peri, timer, ppi_ch1, ppi_ch2, ppi_group, rxd, rts, rx_buffer);
+
+ U::Interrupt::pend();
+ unsafe { U::Interrupt::enable() };
+
+ U::state().tx_rx_refcount.store(1, Ordering::Relaxed);
+
+ this
+ }
+
+ fn new_innerer(
+ peri: PeripheralRef<'d, U>,
+ timer: PeripheralRef<'d, T>,
+ ppi_ch1: PeripheralRef<'d, AnyConfigurableChannel>,
+ ppi_ch2: PeripheralRef<'d, AnyConfigurableChannel>,
+ ppi_group: PeripheralRef<'d, AnyGroup>,
+ rxd: PeripheralRef<'d, AnyPin>,
+ rts: Option<PeripheralRef<'d, AnyPin>>,
+ rx_buffer: &'d mut [u8],
+ ) -> Self {
+ assert!(rx_buffer.len() % 2 == 0);
+
+ let r = U::regs();
+
+ rxd.conf().write(|w| w.input().connect().drive().h0h1());
+ r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
+
+ if let Some(pin) = &rts {
+ pin.set_high();
+ pin.conf().write(|w| w.dir().output().drive().h0h1());
+ }
+ r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
+
+ // Initialize state
+ let s = U::buffered_state();
+ s.rx_started_count.store(0, Ordering::Relaxed);
+ s.rx_ended_count.store(0, Ordering::Relaxed);
+ s.rx_started.store(false, Ordering::Relaxed);
+ let len = rx_buffer.len();
+ unsafe { s.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
+
+ // clear errors
+ let errors = r.errorsrc.read().bits();
+ r.errorsrc.write(|w| unsafe { w.bits(errors) });
+
+ r.events_rxstarted.reset();
+ r.events_error.reset();
+ r.events_endrx.reset();
+
+ // Enable interrupts
+ r.intenset.write(|w| {
+ w.endtx().set();
+ w.rxstarted().set();
+ w.error().set();
+ w.endrx().set();
+ w
+ });
+
+ // Configure byte counter.
+ let timer = Timer::new_counter(timer);
+ timer.cc(1).write(rx_buffer.len() as u32 * 2);
+ timer.cc(1).short_compare_clear();
+ timer.clear();
+ timer.start();
+
+ let mut ppi_ch1 = Ppi::new_one_to_one(ppi_ch1, Event::from_reg(&r.events_rxdrdy), timer.task_count());
+ ppi_ch1.enable();
+
+ s.rx_ppi_ch.store(ppi_ch2.number() as u8, Ordering::Relaxed);
+ let mut ppi_group = PpiGroup::new(ppi_group);
+ let mut ppi_ch2 = Ppi::new_one_to_two(
+ ppi_ch2,
+ Event::from_reg(&r.events_endrx),
+ Task::from_reg(&r.tasks_startrx),
+ ppi_group.task_disable_all(),
+ );
+ ppi_ch2.disable();
+ ppi_group.add_channel(&ppi_ch2);
+
+ Self {
+ _peri: peri,
+ timer,
+ _ppi_ch1: ppi_ch1,
+ _ppi_ch2: ppi_ch2,
+ _ppi_group: ppi_group,
+ }
+ }
+
/// Pull some bytes from this source into the specified buffer, returning how many bytes were read.
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
let data = self.fill_buf().await?;
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index cd14c718a..7fd34453a 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -299,7 +299,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
}
}
-fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
+pub(crate) fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
r.config.write(|w| {
w.hwfc().bit(hardware_flow_control);
w.parity().variant(config.parity);
From 036f703a4a42ae67d2b0fdc6b5268ac04d5066f7 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 21 Feb 2024 23:38:51 +0100
Subject: [PATCH 282/392] nrf/uart: add buffereduart drop, rxonly, txonly
tests.
---
tests/nrf52840/src/bin/buffered_uart.rs | 87 ++++++++++---------
.../nrf52840/src/bin/buffered_uart_halves.rs | 82 +++++++++++++++++
2 files changed, 127 insertions(+), 42 deletions(-)
create mode 100644 tests/nrf52840/src/bin/buffered_uart_halves.rs
diff --git a/tests/nrf52840/src/bin/buffered_uart.rs b/tests/nrf52840/src/bin/buffered_uart.rs
index 721751136..a01d66d85 100644
--- a/tests/nrf52840/src/bin/buffered_uart.rs
+++ b/tests/nrf52840/src/bin/buffered_uart.rs
@@ -15,7 +15,7 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
- let p = embassy_nrf::init(Default::default());
+ let mut p = embassy_nrf::init(Default::default());
let mut config = uarte::Config::default();
config.parity = uarte::Parity::EXCLUDED;
config.baudrate = uarte::Baudrate::BAUD1M;
@@ -23,55 +23,58 @@ async fn main(_spawner: Spawner) {
let mut tx_buffer = [0u8; 1024];
let mut rx_buffer = [0u8; 1024];
- let u = BufferedUarte::new(
- p.UARTE0,
- p.TIMER0,
- p.PPI_CH0,
- p.PPI_CH1,
- p.PPI_GROUP0,
- Irqs,
- p.P1_03,
- p.P1_02,
- config.clone(),
- &mut rx_buffer,
- &mut tx_buffer,
- );
+ // test teardown + recreate of the buffereduarte works fine.
+ for _ in 0..2 {
+ let u = BufferedUarte::new(
+ &mut p.UARTE0,
+ &mut p.TIMER0,
+ &mut p.PPI_CH0,
+ &mut p.PPI_CH1,
+ &mut p.PPI_GROUP0,
+ Irqs,
+ &mut p.P1_03,
+ &mut p.P1_02,
+ config.clone(),
+ &mut rx_buffer,
+ &mut tx_buffer,
+ );
- info!("uarte initialized!");
+ info!("uarte initialized!");
- let (mut rx, mut tx) = u.split();
+ let (mut rx, mut tx) = u.split();
- const COUNT: usize = 40_000;
+ const COUNT: usize = 40_000;
- let tx_fut = async {
- let mut tx_buf = [0; 215];
- let mut i = 0;
- while i < COUNT {
- let n = tx_buf.len().min(COUNT - i);
- let tx_buf = &mut tx_buf[..n];
- for (j, b) in tx_buf.iter_mut().enumerate() {
- *b = (i + j) as u8;
+ let tx_fut = async {
+ let mut tx_buf = [0; 215];
+ let mut i = 0;
+ while i < COUNT {
+ let n = tx_buf.len().min(COUNT - i);
+ let tx_buf = &mut tx_buf[..n];
+ for (j, b) in tx_buf.iter_mut().enumerate() {
+ *b = (i + j) as u8;
+ }
+ let n = unwrap!(tx.write(tx_buf).await);
+ i += n;
}
- let n = unwrap!(tx.write(tx_buf).await);
- i += n;
- }
- };
- let rx_fut = async {
- let mut i = 0;
- while i < COUNT {
- let buf = unwrap!(rx.fill_buf().await);
+ };
+ let rx_fut = async {
+ let mut i = 0;
+ while i < COUNT {
+ let buf = unwrap!(rx.fill_buf().await);
- for &b in buf {
- assert_eq!(b, i as u8);
- i = i + 1;
+ for &b in buf {
+ assert_eq!(b, i as u8);
+ i = i + 1;
+ }
+
+ let n = buf.len();
+ rx.consume(n);
}
+ };
- let n = buf.len();
- rx.consume(n);
- }
- };
-
- join(rx_fut, tx_fut).await;
+ join(rx_fut, tx_fut).await;
+ }
info!("Test OK");
cortex_m::asm::bkpt();
diff --git a/tests/nrf52840/src/bin/buffered_uart_halves.rs b/tests/nrf52840/src/bin/buffered_uart_halves.rs
new file mode 100644
index 000000000..54a9fef5b
--- /dev/null
+++ b/tests/nrf52840/src/bin/buffered_uart_halves.rs
@@ -0,0 +1,82 @@
+#![no_std]
+#![no_main]
+teleprobe_meta::target!(b"nrf52840-dk");
+
+use defmt::{assert_eq, *};
+use embassy_executor::Spawner;
+use embassy_futures::join::join;
+use embassy_nrf::buffered_uarte::{self, BufferedUarteRx, BufferedUarteTx};
+use embassy_nrf::{bind_interrupts, peripherals, uarte};
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;
+ UARTE1 => buffered_uarte::InterruptHandler<peripherals::UARTE1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let mut p = embassy_nrf::init(Default::default());
+ let mut config = uarte::Config::default();
+ config.parity = uarte::Parity::EXCLUDED;
+ config.baudrate = uarte::Baudrate::BAUD1M;
+
+ let mut tx_buffer = [0u8; 1024];
+ let mut rx_buffer = [0u8; 1024];
+
+ // test teardown + recreate of the buffereduarte works fine.
+ for _ in 0..2 {
+ const COUNT: usize = 40_000;
+
+ let mut tx = BufferedUarteTx::new(&mut p.UARTE1, Irqs, &mut p.P1_02, config.clone(), &mut tx_buffer);
+
+ let mut rx = BufferedUarteRx::new(
+ &mut p.UARTE0,
+ &mut p.TIMER0,
+ &mut p.PPI_CH0,
+ &mut p.PPI_CH1,
+ &mut p.PPI_GROUP0,
+ Irqs,
+ &mut p.P1_03,
+ config.clone(),
+ &mut rx_buffer,
+ );
+
+ let tx_fut = async {
+ info!("tx initialized!");
+
+ let mut tx_buf = [0; 215];
+ let mut i = 0;
+ while i < COUNT {
+ let n = tx_buf.len().min(COUNT - i);
+ let tx_buf = &mut tx_buf[..n];
+ for (j, b) in tx_buf.iter_mut().enumerate() {
+ *b = (i + j) as u8;
+ }
+ let n = unwrap!(tx.write(tx_buf).await);
+ i += n;
+ }
+ };
+ let rx_fut = async {
+ info!("rx initialized!");
+
+ let mut i = 0;
+ while i < COUNT {
+ let buf = unwrap!(rx.fill_buf().await);
+
+ for &b in buf {
+ assert_eq!(b, i as u8);
+ i = i + 1;
+ }
+
+ let n = buf.len();
+ rx.consume(n);
+ }
+ };
+
+ join(rx_fut, tx_fut).await;
+ }
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
From 6a977d2ae937c835401c46aad9f5cbe79962266f Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Thu, 22 Feb 2024 00:07:09 +0100
Subject: [PATCH 283/392] nrf/uarte: prevent accidentally driving tx pin on
rxonly uart if it was left in PSEL.
---
embassy-nrf/src/uarte.rs | 60 +++++++++++++++++-----------------------
1 file changed, 26 insertions(+), 34 deletions(-)
diff --git a/embassy-nrf/src/uarte.rs b/embassy-nrf/src/uarte.rs
index 7fd34453a..cbd5dccbc 100644
--- a/embassy-nrf/src/uarte.rs
+++ b/embassy-nrf/src/uarte.rs
@@ -159,7 +159,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
txd: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
- into_ref!(rxd, txd);
+ into_ref!(uarte, rxd, txd);
Self::new_inner(uarte, rxd.map_into(), txd.map_into(), None, None, config)
}
@@ -173,7 +173,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
rts: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
- into_ref!(rxd, txd, cts, rts);
+ into_ref!(uarte, rxd, txd, cts, rts);
Self::new_inner(
uarte,
rxd.map_into(),
@@ -185,17 +185,22 @@ impl<'d, T: Instance> Uarte<'d, T> {
}
fn new_inner(
- uarte: impl Peripheral<P = T> + 'd,
+ uarte: PeripheralRef<'d, T>,
rxd: PeripheralRef<'d, AnyPin>,
txd: PeripheralRef<'d, AnyPin>,
cts: Option<PeripheralRef<'d, AnyPin>>,
rts: Option<PeripheralRef<'d, AnyPin>>,
config: Config,
) -> Self {
- into_ref!(uarte);
-
let r = T::regs();
+ let hardware_flow_control = match (rts.is_some(), cts.is_some()) {
+ (false, false) => false,
+ (true, true) => true,
+ _ => panic!("RTS and CTS pins must be either both set or none set."),
+ };
+ configure(r, config, hardware_flow_control);
+
rxd.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
@@ -217,13 +222,6 @@ impl<'d, T: Instance> Uarte<'d, T> {
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
- let hardware_flow_control = match (rts.is_some(), cts.is_some()) {
- (false, false) => false,
- (true, true) => true,
- _ => panic!("RTS and CTS pins must be either both set or none set."),
- };
- configure(r, config, hardware_flow_control);
-
let s = T::state();
s.tx_rx_refcount.store(2, Ordering::Relaxed);
@@ -315,6 +313,12 @@ pub(crate) fn configure(r: &RegisterBlock, config: Config, hardware_flow_control
r.events_rxstarted.reset();
r.events_txstarted.reset();
+ // reset all pins
+ r.psel.txd.write(|w| w.connect().disconnected());
+ r.psel.rxd.write(|w| w.connect().disconnected());
+ r.psel.cts.write(|w| w.connect().disconnected());
+ r.psel.rts.write(|w| w.connect().disconnected());
+
// Enable
apply_workaround_for_enable_anomaly(r);
r.enable.write(|w| w.enable().enabled());
@@ -328,7 +332,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
txd: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
- into_ref!(txd);
+ into_ref!(uarte, txd);
Self::new_inner(uarte, txd.map_into(), None, config)
}
@@ -340,20 +344,20 @@ impl<'d, T: Instance> UarteTx<'d, T> {
cts: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
- into_ref!(txd, cts);
+ into_ref!(uarte, txd, cts);
Self::new_inner(uarte, txd.map_into(), Some(cts.map_into()), config)
}
fn new_inner(
- uarte: impl Peripheral<P = T> + 'd,
+ uarte: PeripheralRef<'d, T>,
txd: PeripheralRef<'d, AnyPin>,
cts: Option<PeripheralRef<'d, AnyPin>>,
config: Config,
) -> Self {
- into_ref!(uarte);
-
let r = T::regs();
+ configure(r, config, cts.is_some());
+
txd.set_high();
txd.conf().write(|w| w.dir().output().drive().s0s1());
r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
@@ -363,12 +367,6 @@ impl<'d, T: Instance> UarteTx<'d, T> {
}
r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
- r.psel.rxd.write(|w| w.connect().disconnected());
- r.psel.rts.write(|w| w.connect().disconnected());
-
- let hardware_flow_control = cts.is_some();
- configure(r, config, hardware_flow_control);
-
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
@@ -524,7 +522,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
rxd: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
- into_ref!(rxd);
+ into_ref!(uarte, rxd);
Self::new_inner(uarte, rxd.map_into(), None, config)
}
@@ -536,7 +534,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
rts: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
- into_ref!(rxd, rts);
+ into_ref!(uarte, rxd, rts);
Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config)
}
@@ -549,15 +547,15 @@ impl<'d, T: Instance> UarteRx<'d, T> {
}
fn new_inner(
- uarte: impl Peripheral<P = T> + 'd,
+ uarte: PeripheralRef<'d, T>,
rxd: PeripheralRef<'d, AnyPin>,
rts: Option<PeripheralRef<'d, AnyPin>>,
config: Config,
) -> Self {
- into_ref!(uarte);
-
let r = T::regs();
+ configure(r, config, rts.is_some());
+
rxd.conf().write(|w| w.input().connect().drive().h0h1());
r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
@@ -567,15 +565,9 @@ impl<'d, T: Instance> UarteRx<'d, T> {
}
r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
- r.psel.txd.write(|w| w.connect().disconnected());
- r.psel.cts.write(|w| w.connect().disconnected());
-
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
- let hardware_flow_control = rts.is_some();
- configure(r, config, hardware_flow_control);
-
let s = T::state();
s.tx_rx_refcount.store(1, Ordering::Relaxed);
From 0c6d3ea05116c2798529ae68136f0e29f04f92e1 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Thu, 22 Feb 2024 06:05:51 -0500
Subject: [PATCH 284/392] Add SetConfig impl to rp2040 i2c
Also expand test to cover 1kHz, 100kHz, 400kHz, and 1MHz speeds.
---
embassy-rp/src/i2c.rs | 86 +++++++++++++++++++++++-------------
tests/rp/Cargo.toml | 1 +
tests/rp/src/bin/i2c.rs | 96 +++++++++++++++++++++++++----------------
3 files changed, 115 insertions(+), 68 deletions(-)
diff --git a/embassy-rp/src/i2c.rs b/embassy-rp/src/i2c.rs
index 74d015792..85636f5fe 100644
--- a/embassy-rp/src/i2c.rs
+++ b/embassy-rp/src/i2c.rs
@@ -43,6 +43,18 @@ pub enum Error {
AddressReserved(u16),
}
+/// I2C Config error
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ConfigError {
+ /// Max i2c speed is 1MHz
+ FrequencyTooHigh,
+ /// The sys clock is too slow to support given frequency
+ ClockTooSlow,
+ /// The sys clock is too fast to support given frequency
+ ClockTooFast,
+}
+
/// I2C config.
#[non_exhaustive]
#[derive(Copy, Clone)]
@@ -365,37 +377,32 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
) -> Self {
into_ref!(_peri);
- assert!(config.frequency <= 1_000_000);
- assert!(config.frequency > 0);
-
- let p = T::regs();
-
let reset = T::reset();
crate::reset::reset(reset);
crate::reset::unreset_wait(reset);
- p.ic_enable().write(|w| w.set_enable(false));
-
- // Select controller mode & speed
- p.ic_con().modify(|w| {
- // Always use "fast" mode (<= 400 kHz, works fine for standard
- // mode too)
- w.set_speed(i2c::vals::Speed::FAST);
- w.set_master_mode(true);
- w.set_ic_slave_disable(true);
- w.set_ic_restart_en(true);
- w.set_tx_empty_ctrl(true);
- });
-
- // Set FIFO watermarks to 1 to make things simpler. This is encoded
- // by a register value of 0.
- p.ic_tx_tl().write(|w| w.set_tx_tl(0));
- p.ic_rx_tl().write(|w| w.set_rx_tl(0));
-
// Configure SCL & SDA pins
set_up_i2c_pin(&scl);
set_up_i2c_pin(&sda);
+ let mut me = Self { phantom: PhantomData };
+
+ if let Err(e) = me.set_config_inner(&config) {
+ panic!("Error configuring i2c: {}", e);
+ }
+
+ me
+ }
+
+ fn set_config_inner(&mut self, config: &Config) -> Result<(), ConfigError> {
+ if config.frequency > 1_000_000 {
+ return Err(ConfigError::FrequencyTooHigh);
+ }
+
+ let p = T::regs();
+
+ p.ic_enable().write(|w| w.set_enable(false));
+
// Configure baudrate
// There are some subtleties to I2C timing which we are completely
@@ -407,11 +414,14 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
let lcnt = period * 3 / 5; // spend 3/5 (60%) of the period low
let hcnt = period - lcnt; // and 2/5 (40%) of the period high
+ warn!("cb:{} h:{:x} l:{:x}", clk_base, hcnt, lcnt);
// Check for out-of-range divisors:
- assert!(hcnt <= 0xffff);
- assert!(lcnt <= 0xffff);
- assert!(hcnt >= 8);
- assert!(lcnt >= 8);
+ if hcnt > 0xffff || lcnt > 0xffff {
+ return Err(ConfigError::ClockTooFast);
+ }
+ if hcnt < 8 || lcnt < 8 {
+ return Err(ConfigError::ClockTooSlow);
+ }
// Per I2C-bus specification a device in standard or fast mode must
// internally provide a hold time of at least 300ns for the SDA
@@ -424,14 +434,20 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
((clk_base * 3) / 10_000_000) + 1
} else {
// fast mode plus requires a clk_base > 32MHz
- assert!(clk_base >= 32_000_000);
+ if clk_base <= 32_000_000 {
+ return Err(ConfigError::ClockTooSlow);
+ }
// sda_tx_hold_count = clk_base [cycles/s] * 120ns * (1s /
// 1e9ns) Reduce 120/1e9 to 3/25e6 to avoid numbers that don't
// fit in uint. Add 1 to avoid division truncation.
((clk_base * 3) / 25_000_000) + 1
};
- assert!(sda_tx_hold_count <= lcnt - 2);
+ /*
+ if sda_tx_hold_count <= lcnt - 2 {
+ return Err(ConfigError::HoldCountOutOfRange);
+ }
+ */
p.ic_fs_scl_hcnt().write(|w| w.set_ic_fs_scl_hcnt(hcnt as u16));
p.ic_fs_scl_lcnt().write(|w| w.set_ic_fs_scl_lcnt(lcnt as u16));
@@ -440,10 +456,9 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
p.ic_sda_hold()
.modify(|w| w.set_ic_sda_tx_hold(sda_tx_hold_count as u16));
- // Enable I2C block
p.ic_enable().write(|w| w.set_enable(true));
- Self { phantom: PhantomData }
+ Ok(())
}
fn setup(addr: u16) -> Result<(), Error> {
@@ -757,6 +772,15 @@ where
}
}
+impl<'d, T: Instance, M: Mode> embassy_embedded_hal::SetConfig for I2c<'d, T, M> {
+ type Config = Config;
+ type ConfigError = ConfigError;
+
+ fn set_config(&mut self, config: &Self::Config) -> Result<(), Self::ConfigError> {
+ self.set_config_inner(config)
+ }
+}
+
/// Check if address is reserved.
pub fn i2c_reserved_addr(addr: u16) -> bool {
((addr & 0x78) == 0 || (addr & 0x78) == 0x78) && addr != 0
diff --git a/tests/rp/Cargo.toml b/tests/rp/Cargo.toml
index 46e1e9a5f..e67f2117d 100644
--- a/tests/rp/Cargo.toml
+++ b/tests/rp/Cargo.toml
@@ -14,6 +14,7 @@ embassy-rp = { version = "0.1.0", path = "../../embassy-rp", features = [ "defmt
embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
embassy-net = { version = "0.4.0", path = "../../embassy-net", features = ["defmt", "tcp", "udp", "dhcpv4", "medium-ethernet"] }
embassy-net-wiznet = { version = "0.1.0", path = "../../embassy-net-wiznet", features = ["defmt"] }
+embassy-embedded-hal = { version = "0.1.0", path = "../../embassy-embedded-hal/"}
cyw43 = { path = "../../cyw43", features = ["defmt", "firmware-logs"] }
cyw43-pio = { path = "../../cyw43-pio", features = ["defmt", "overclock"] }
perf-client = { path = "../perf-client" }
diff --git a/tests/rp/src/bin/i2c.rs b/tests/rp/src/bin/i2c.rs
index a0aed1a42..153b37999 100644
--- a/tests/rp/src/bin/i2c.rs
+++ b/tests/rp/src/bin/i2c.rs
@@ -3,7 +3,10 @@
teleprobe_meta::target!(b"rpi-pico");
use defmt::{assert_eq, info, panic, unwrap};
-use embassy_executor::Executor;
+use embassy_embedded_hal::SetConfig;
+use embassy_executor::{Executor, Spawner};
+use embassy_rp::clocks::{PllConfig, XoscConfig};
+use embassy_rp::config::Config as rpConfig;
use embassy_rp::multicore::{spawn_core1, Stack};
use embassy_rp::peripherals::{I2C0, I2C1};
use embassy_rp::{bind_interrupts, i2c, i2c_slave};
@@ -13,7 +16,6 @@ use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _, panic_probe as _, panic_probe as _};
static mut CORE1_STACK: Stack<1024> = Stack::new();
-static EXECUTOR0: StaticCell<Executor> = StaticCell::new();
static EXECUTOR1: StaticCell<Executor> = StaticCell::new();
use crate::i2c::AbortReason;
@@ -44,10 +46,7 @@ async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
Ok(x) => match x {
i2c_slave::ReadStatus::Done => break,
i2c_slave::ReadStatus::NeedMoreBytes => count += 1,
- i2c_slave::ReadStatus::LeftoverBytes(x) => {
- info!("tried to write {} extra bytes", x);
- break;
- }
+ i2c_slave::ReadStatus::LeftoverBytes(x) => panic!("tried to write {} extra bytes", x),
},
Err(e) => match e {
embassy_rp::i2c_slave::Error::Abort(AbortReason::Other(n)) => panic!("Other {:b}", n),
@@ -92,6 +91,8 @@ async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
resp_buff[i] = i as u8;
}
dev.respond_to_read(&resp_buff).await.unwrap();
+ // reset count for next round of tests
+ count = 0xD0;
}
x => panic!("Invalid Write Read {:x}", x),
}
@@ -104,8 +105,7 @@ async fn device_task(mut dev: i2c_slave::I2cSlave<'static, I2C1>) -> ! {
}
}
-#[embassy_executor::task]
-async fn controller_task(mut con: i2c::I2c<'static, I2C0, i2c::Async>) {
+async fn controller_task(con: &mut i2c::I2c<'static, I2C0, i2c::Async>) {
info!("Device start");
{
@@ -179,33 +179,55 @@ async fn controller_task(mut con: i2c::I2c<'static, I2C0, i2c::Async>) {
info!("large write_read - OK")
}
- info!("Test OK");
- cortex_m::asm::bkpt();
-}
-
-#[cortex_m_rt::entry]
-fn main() -> ! {
- let p = embassy_rp::init(Default::default());
- info!("Hello World!");
-
- let d_sda = p.PIN_19;
- let d_scl = p.PIN_18;
- let mut config = i2c_slave::Config::default();
- config.addr = DEV_ADDR as u16;
- let device = i2c_slave::I2cSlave::new(p.I2C1, d_sda, d_scl, Irqs, config);
-
- spawn_core1(p.CORE1, unsafe { &mut CORE1_STACK }, move || {
- let executor1 = EXECUTOR1.init(Executor::new());
- executor1.run(|spawner| unwrap!(spawner.spawn(device_task(device))));
- });
-
- let executor0 = EXECUTOR0.init(Executor::new());
-
- let c_sda = p.PIN_21;
- let c_scl = p.PIN_20;
- let mut config = i2c::Config::default();
- config.frequency = 5_000;
- let controller = i2c::I2c::new_async(p.I2C0, c_sda, c_scl, Irqs, config);
-
- executor0.run(|spawner| unwrap!(spawner.spawn(controller_task(controller))));
+ #[embassy_executor::main]
+ async fn main(_core0_spawner: Spawner) {
+ let mut config = rpConfig::default();
+ // Configure clk_sys to 48MHz to support 1kHz scl.
+ // In theory it can go lower, but we won't bother to test below 1kHz.
+ config.clocks.xosc = Some(XoscConfig {
+ hz: 12_000_000,
+ delay_multiplier: 128,
+ sys_pll: Some(PllConfig {
+ refdiv: 1,
+ fbdiv: 120,
+ post_div1: 6,
+ post_div2: 5,
+ }),
+ usb_pll: Some(PllConfig {
+ refdiv: 1,
+ fbdiv: 120,
+ post_div1: 6,
+ post_div2: 5,
+ }),
+ });
+
+ let p = embassy_rp::init(config);
+ info!("Hello World!");
+
+ let d_sda = p.PIN_19;
+ let d_scl = p.PIN_18;
+ let mut config = i2c_slave::Config::default();
+ config.addr = DEV_ADDR as u16;
+ let device = i2c_slave::I2cSlave::new(p.I2C1, d_sda, d_scl, Irqs, config);
+
+ spawn_core1(p.CORE1, unsafe { &mut CORE1_STACK }, move || {
+ let executor1 = EXECUTOR1.init(Executor::new());
+ executor1.run(|spawner| unwrap!(spawner.spawn(device_task(device))));
+ });
+
+ let c_sda = p.PIN_21;
+ let c_scl = p.PIN_20;
+ let mut controller = i2c::I2c::new_async(p.I2C0, c_sda, c_scl, Irqs, Default::default());
+
+ for freq in [1000, 100_000, 400_000, 1_000_000] {
+ info!("testing at {}hz", freq);
+ let mut config = i2c::Config::default();
+ config.frequency = freq;
+ controller.set_config(&config).unwrap();
+ controller_task(&mut controller).await;
+ }
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+ }
}
From 5ddee8586a3d98b4996278fefc1ef047f1367280 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Thu, 22 Feb 2024 06:12:41 -0500
Subject: [PATCH 285/392] rp2040 i2c_slave improvements
Fix race condition that appears on fast repeated transfers.
Add public reset function. Because application code can stall the bus,
we need to give application code a way to fix itself.
---
embassy-rp/src/i2c_slave.rs | 117 ++++++++++++++++++++----------------
1 file changed, 66 insertions(+), 51 deletions(-)
diff --git a/embassy-rp/src/i2c_slave.rs b/embassy-rp/src/i2c_slave.rs
index 979686627..caebb0257 100644
--- a/embassy-rp/src/i2c_slave.rs
+++ b/embassy-rp/src/i2c_slave.rs
@@ -83,6 +83,7 @@ impl Default for Config {
pub struct I2cSlave<'d, T: Instance> {
phantom: PhantomData<&'d mut T>,
pending_byte: Option<u8>,
+ config: Config,
}
impl<'d, T: Instance> I2cSlave<'d, T> {
@@ -99,6 +100,25 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
assert!(!i2c_reserved_addr(config.addr));
assert!(config.addr != 0);
+ // Configure SCL & SDA pins
+ set_up_i2c_pin(&scl);
+ set_up_i2c_pin(&sda);
+
+ let mut ret = Self {
+ phantom: PhantomData,
+ pending_byte: None,
+ config,
+ };
+
+ ret.reset();
+
+ ret
+ }
+
+ /// Reset the i2c peripheral. If you cancel a respond_to_read, you may stall the bus.
+ /// You can recover the bus by calling this function, but doing so will almost certainly cause
+ /// an i/o error in the master.
+ pub fn reset(&mut self) {
let p = T::regs();
let reset = T::reset();
@@ -107,7 +127,7 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
p.ic_enable().write(|w| w.set_enable(false));
- p.ic_sar().write(|w| w.set_ic_sar(config.addr));
+ p.ic_sar().write(|w| w.set_ic_sar(self.config.addr));
p.ic_con().modify(|w| {
w.set_master_mode(false);
w.set_ic_slave_disable(false);
@@ -121,10 +141,10 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
// Generate stop interrupts for general calls
// This also causes stop interrupts for other devices on the bus but those will not be
// propagated up to the application.
- w.set_stop_det_ifaddressed(!config.general_call);
+ w.set_stop_det_ifaddressed(!self.config.general_call);
});
p.ic_ack_general_call()
- .write(|w| w.set_ack_gen_call(config.general_call));
+ .write(|w| w.set_ack_gen_call(self.config.general_call));
// Set FIFO watermarks to 1 to make things simpler. This is encoded
// by a register value of 0. Rx watermark should never change, but Tx watermark will be
@@ -132,10 +152,6 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
p.ic_tx_tl().write(|w| w.set_tx_tl(0));
p.ic_rx_tl().write(|w| w.set_rx_tl(0));
- // Configure SCL & SDA pins
- set_up_i2c_pin(&scl);
- set_up_i2c_pin(&sda);
-
// Clear interrupts
p.ic_clr_intr().read();
@@ -146,11 +162,6 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
p.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0));
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
-
- Self {
- phantom: PhantomData,
- pending_byte: None,
- }
}
/// Calls `f` to check if we are ready or not.
@@ -178,15 +189,13 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
fn drain_fifo(&mut self, buffer: &mut [u8], offset: &mut usize) {
let p = T::regs();
- for b in &mut buffer[*offset..] {
- if let Some(pending) = self.pending_byte.take() {
- *b = pending;
- *offset += 1;
- continue;
- }
+ if let Some(pending) = self.pending_byte.take() {
+ buffer[*offset] = pending;
+ *offset += 1;
+ }
- let status = p.ic_status().read();
- if !status.rfne() {
+ for b in &mut buffer[*offset..] {
+ if !p.ic_status().read().rfne() {
break;
}
@@ -207,14 +216,6 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
}
}
- #[inline(always)]
- fn write_to_fifo(&mut self, buffer: &[u8]) {
- let p = T::regs();
- for byte in buffer {
- p.ic_data_cmd().write(|w| w.set_dat(*byte));
- }
- }
-
/// Wait asynchronously for commands from an I2C master.
/// `buffer` is provided in case master does a 'write', 'write read', or 'general call' and is unused for 'read'.
pub async fn listen(&mut self, buffer: &mut [u8]) -> Result<Command, Error> {
@@ -227,8 +228,9 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
self.wait_on(
|me| {
let stat = p.ic_raw_intr_stat().read();
+ trace!("ls:{:013b} len:{}", stat.0, len);
- if p.ic_rxflr().read().rxflr() > 0 {
+ if p.ic_rxflr().read().rxflr() > 0 || me.pending_byte.is_some() {
me.drain_fifo(buffer, &mut len);
// we're recieving data, set rx fifo watermark to 12 bytes (3/4 full) to reduce interrupt noise
p.ic_rx_tl().write(|w| w.set_rx_tl(11));
@@ -241,6 +243,10 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
return Poll::Ready(Err(Error::PartialWrite(buffer.len())));
}
}
+ trace!("len:{}, pend:{}", len, me.pending_byte);
+ if me.pending_byte.is_some() {
+ warn!("pending")
+ }
if stat.restart_det() && stat.rd_req() {
p.ic_clr_restart_det().read();
@@ -257,12 +263,17 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
p.ic_clr_restart_det().read();
p.ic_clr_gen_call().read();
Poll::Ready(Ok(Command::Read))
+ } else if stat.stop_det() {
+ // clear stuck stop bit
+ // This can happen if the SDA/SCL pullups are enabled after calling this func
+ p.ic_clr_stop_det().read();
+ Poll::Pending
} else {
Poll::Pending
}
},
|_me| {
- p.ic_intr_mask().modify(|w| {
+ p.ic_intr_mask().write(|w| {
w.set_m_stop_det(true);
w.set_m_restart_det(true);
w.set_m_gen_call(true);
@@ -286,27 +297,30 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
self.wait_on(
|me| {
- if let Err(abort_reason) = me.read_and_clear_abort_reason() {
- if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
- p.ic_clr_intr().read();
- return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
- } else {
- return Poll::Ready(Err(abort_reason));
+ let stat = p.ic_raw_intr_stat().read();
+ trace!("rs:{:013b}", stat.0);
+
+ if stat.tx_abrt() {
+ if let Err(abort_reason) = me.read_and_clear_abort_reason() {
+ if let Error::Abort(AbortReason::TxNotEmpty(bytes)) = abort_reason {
+ p.ic_clr_intr().read();
+ return Poll::Ready(Ok(ReadStatus::LeftoverBytes(bytes)));
+ } else {
+ return Poll::Ready(Err(abort_reason));
+ }
}
}
if let Some(chunk) = chunks.next() {
- me.write_to_fifo(chunk);
-
- p.ic_clr_rd_req().read();
+ for byte in chunk {
+ p.ic_clr_rd_req().read();
+ p.ic_data_cmd().write(|w| w.set_dat(*byte));
+ }
Poll::Pending
} else {
- let stat = p.ic_raw_intr_stat().read();
-
- if stat.rx_done() && stat.stop_det() {
+ if stat.rx_done() {
p.ic_clr_rx_done().read();
- p.ic_clr_stop_det().read();
Poll::Ready(Ok(ReadStatus::Done))
} else if stat.rd_req() && stat.tx_empty() {
Poll::Ready(Ok(ReadStatus::NeedMoreBytes))
@@ -316,11 +330,10 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
}
},
|_me| {
- p.ic_intr_mask().modify(|w| {
- w.set_m_stop_det(true);
- w.set_m_rx_done(true);
+ p.ic_intr_mask().write(|w| {
w.set_m_tx_empty(true);
w.set_m_tx_abrt(true);
+ w.set_m_rx_done(true);
})
},
)
@@ -329,9 +342,14 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
/// Respond to reads with the fill byte until the controller stops asking
pub async fn respond_till_stop(&mut self, fill: u8) -> Result<(), Error> {
+ // Send fill bytes a full fifo at a time, to reduce interrupt noise.
+ // This does mean we'll almost certainly abort the write, but since these are fill bytes,
+ // we don't care.
+ let buff = [fill; FIFO_SIZE as usize];
loop {
- match self.respond_to_read(&[fill]).await {
+ match self.respond_to_read(&buff).await {
Ok(ReadStatus::NeedMoreBytes) => (),
+ Ok(ReadStatus::LeftoverBytes(_)) => break Ok(()),
Ok(_) => break Ok(()),
Err(e) => break Err(e),
}
@@ -353,10 +371,7 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
#[inline(always)]
fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> {
let p = T::regs();
- let mut abort_reason = p.ic_tx_abrt_source().read();
-
- // Mask off master_dis
- abort_reason.set_abrt_master_dis(false);
+ let abort_reason = p.ic_tx_abrt_source().read();
if abort_reason.0 != 0 {
// Note clearing the abort flag also clears the reason, and this
From 89986fe967da4b1f94c57a11e57928b574536c92 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Thu, 22 Feb 2024 06:21:40 -0500
Subject: [PATCH 286/392] Fixup display -> debug
---
embassy-rp/src/i2c.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-rp/src/i2c.rs b/embassy-rp/src/i2c.rs
index 85636f5fe..3b74d8501 100644
--- a/embassy-rp/src/i2c.rs
+++ b/embassy-rp/src/i2c.rs
@@ -388,7 +388,7 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
let mut me = Self { phantom: PhantomData };
if let Err(e) = me.set_config_inner(&config) {
- panic!("Error configuring i2c: {}", e);
+ panic!("Error configuring i2c: {:?}", e);
}
me
From 25bff1d0b946a59d099aec88917759340124c931 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Thu, 22 Feb 2024 06:34:58 -0500
Subject: [PATCH 287/392] Fixup comments from James
---
embassy-rp/src/i2c.rs | 8 +++-----
embassy-rp/src/i2c_slave.rs | 2 +-
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/embassy-rp/src/i2c.rs b/embassy-rp/src/i2c.rs
index 3b74d8501..ac0eac96d 100644
--- a/embassy-rp/src/i2c.rs
+++ b/embassy-rp/src/i2c.rs
@@ -414,7 +414,6 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
let lcnt = period * 3 / 5; // spend 3/5 (60%) of the period low
let hcnt = period - lcnt; // and 2/5 (40%) of the period high
- warn!("cb:{} h:{:x} l:{:x}", clk_base, hcnt, lcnt);
// Check for out-of-range divisors:
if hcnt > 0xffff || lcnt > 0xffff {
return Err(ConfigError::ClockTooFast);
@@ -443,11 +442,10 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
// fit in uint. Add 1 to avoid division truncation.
((clk_base * 3) / 25_000_000) + 1
};
- /*
- if sda_tx_hold_count <= lcnt - 2 {
- return Err(ConfigError::HoldCountOutOfRange);
+
+ if sda_tx_hold_count > lcnt - 2 {
+ return Err(ConfigError::ClockTooSlow);
}
- */
p.ic_fs_scl_hcnt().write(|w| w.set_ic_fs_scl_hcnt(hcnt as u16));
p.ic_fs_scl_lcnt().write(|w| w.set_ic_fs_scl_lcnt(lcnt as u16));
diff --git a/embassy-rp/src/i2c_slave.rs b/embassy-rp/src/i2c_slave.rs
index caebb0257..e1441947f 100644
--- a/embassy-rp/src/i2c_slave.rs
+++ b/embassy-rp/src/i2c_slave.rs
@@ -331,9 +331,9 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
},
|_me| {
p.ic_intr_mask().write(|w| {
+ w.set_m_rx_done(true);
w.set_m_tx_empty(true);
w.set_m_tx_abrt(true);
- w.set_m_rx_done(true);
})
},
)
From f1bf9319202635ddf1d271bb4d0480afffffbe38 Mon Sep 17 00:00:00 2001
From: Caleb Jamison <caleb@cbjamo.com>
Date: Thu, 22 Feb 2024 06:40:39 -0500
Subject: [PATCH 288/392] fixup another display -> debug
---
embassy-rp/src/i2c_slave.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-rp/src/i2c_slave.rs b/embassy-rp/src/i2c_slave.rs
index e1441947f..97ca17295 100644
--- a/embassy-rp/src/i2c_slave.rs
+++ b/embassy-rp/src/i2c_slave.rs
@@ -243,7 +243,7 @@ impl<'d, T: Instance> I2cSlave<'d, T> {
return Poll::Ready(Err(Error::PartialWrite(buffer.len())));
}
}
- trace!("len:{}, pend:{}", len, me.pending_byte);
+ trace!("len:{}, pend:{:?}", len, me.pending_byte);
if me.pending_byte.is_some() {
warn!("pending")
}
From 5d2ccc8fa78af78d905c2593306d80f0f621f3bb Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Thu, 22 Feb 2024 13:14:39 +0000
Subject: [PATCH 289/392] adc: basic H5 support
---
embassy-stm32/src/adc/mod.rs | 6 +-
embassy-stm32/src/adc/resolution.rs | 8 +-
embassy-stm32/src/adc/sample_time.rs | 2 +-
embassy-stm32/src/adc/v3.rs | 123 ++++++++++++++++++---------
4 files changed, 93 insertions(+), 46 deletions(-)
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 51b4b5fcc..b273c6394 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -10,7 +10,7 @@
#[cfg_attr(adc_v1, path = "v1.rs")]
#[cfg_attr(adc_l0, path = "v1.rs")]
#[cfg_attr(adc_v2, path = "v2.rs")]
-#[cfg_attr(any(adc_v3, adc_g0), path = "v3.rs")]
+#[cfg_attr(any(adc_v3, adc_g0, adc_h5), path = "v3.rs")]
#[cfg_attr(adc_v4, path = "v4.rs")]
mod _version;
@@ -79,10 +79,10 @@ pub(crate) mod sealed {
}
/// ADC instance.
-#[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0)))]
+#[cfg(not(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0, adc_h5)))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
/// ADC instance.
-#[cfg(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0))]
+#[cfg(any(adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_f3, adc_f3_v1_1, adc_g0, adc_h5))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
/// ADC pin.
diff --git a/embassy-stm32/src/adc/resolution.rs b/embassy-stm32/src/adc/resolution.rs
index 0e6c45c65..37788cd77 100644
--- a/embassy-stm32/src/adc/resolution.rs
+++ b/embassy-stm32/src/adc/resolution.rs
@@ -1,6 +1,6 @@
/// ADC resolution
#[allow(missing_docs)]
-#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
+#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Resolution {
@@ -25,7 +25,7 @@ pub enum Resolution {
impl Default for Resolution {
fn default() -> Self {
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
+ #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
{
Self::TwelveBit
}
@@ -46,7 +46,7 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
+ #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
}
}
@@ -65,7 +65,7 @@ impl Resolution {
Resolution::TwelveBit => (1 << 12) - 1,
Resolution::TenBit => (1 << 10) - 1,
Resolution::EightBit => (1 << 8) - 1,
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1))]
+ #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
Resolution::SixBit => (1 << 6) - 1,
}
}
diff --git a/embassy-stm32/src/adc/sample_time.rs b/embassy-stm32/src/adc/sample_time.rs
index f4b22b462..19bc22938 100644
--- a/embassy-stm32/src/adc/sample_time.rs
+++ b/embassy-stm32/src/adc/sample_time.rs
@@ -67,7 +67,7 @@ impl_sample_time!(
)
);
-#[cfg(adc_v3)]
+#[cfg(any(adc_v3, adc_h5))]
impl_sample_time!(
"2.5",
Cycles2_5,
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 281a99f72..0c44e4400 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,3 +1,4 @@
+use cfg_if::cfg_if;
use embassy_hal_internal::into_ref;
use embedded_hal_02::blocking::delay::DelayUs;
@@ -13,10 +14,15 @@ pub struct VrefInt;
impl<T: Instance> AdcPin<T> for VrefInt {}
impl<T: Instance> super::sealed::AdcPin<T> for VrefInt {
fn channel(&self) -> u8 {
- #[cfg(not(adc_g0))]
- let val = 0;
- #[cfg(adc_g0)]
- let val = 13;
+ cfg_if! {
+ if #[cfg(adc_g0)] {
+ let val = 13;
+ } else if #[cfg(adc_h5)] {
+ let val = 17;
+ } else {
+ let val = 0;
+ }
+ }
val
}
}
@@ -25,10 +31,15 @@ pub struct Temperature;
impl<T: Instance> AdcPin<T> for Temperature {}
impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
fn channel(&self) -> u8 {
- #[cfg(not(adc_g0))]
- let val = 17;
- #[cfg(adc_g0)]
- let val = 12;
+ cfg_if! {
+ if #[cfg(adc_g0)] {
+ let val = 12;
+ } else if #[cfg(adc_h5)] {
+ let val = 16;
+ } else {
+ let val = 17;
+ }
+ }
val
}
}
@@ -37,14 +48,31 @@ pub struct Vbat;
impl<T: Instance> AdcPin<T> for Vbat {}
impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
fn channel(&self) -> u8 {
- #[cfg(not(adc_g0))]
- let val = 18;
- #[cfg(adc_g0)]
- let val = 14;
+ cfg_if! {
+ if #[cfg(adc_g0)] {
+ let val = 14;
+ } else if #[cfg(adc_h5)] {
+ let val = 2;
+ } else {
+ let val = 18;
+ }
+ }
val
}
}
+cfg_if! {
+ if #[cfg(adc_h5)] {
+ pub struct VddCore;
+ impl<T: Instance> AdcPin<T> for VddCore {}
+ impl<T: Instance> super::sealed::AdcPin<T> for VddCore {
+ fn channel(&self) -> u8 {
+ 6
+ }
+ }
+ }
+}
+
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
@@ -98,27 +126,41 @@ impl<'d, T: Instance> Adc<'d, T> {
}
pub fn enable_temperature(&self) -> Temperature {
- #[cfg(not(adc_g0))]
- T::common_regs().ccr().modify(|reg| {
- reg.set_ch17sel(true);
- });
- #[cfg(adc_g0)]
- T::regs().ccr().modify(|reg| {
- reg.set_tsen(true);
- });
+ cfg_if! {
+ if #[cfg(adc_g0)] {
+ T::regs().ccr().modify(|reg| {
+ reg.set_tsen(true);
+ });
+ } else if #[cfg(adc_h5)] {
+ T::common_regs().ccr().modify(|reg| {
+ reg.set_tsen(true);
+ });
+ } else {
+ T::common_regs().ccr().modify(|reg| {
+ reg.set_ch17sel(true);
+ });
+ }
+ }
Temperature {}
}
pub fn enable_vbat(&self) -> Vbat {
- #[cfg(not(adc_g0))]
- T::common_regs().ccr().modify(|reg| {
- reg.set_ch18sel(true);
- });
- #[cfg(adc_g0)]
- T::regs().ccr().modify(|reg| {
- reg.set_vbaten(true);
- });
+ cfg_if! {
+ if #[cfg(adc_g0)] {
+ T::regs().ccr().modify(|reg| {
+ reg.set_vbaten(true);
+ });
+ } else if #[cfg(adc_h5)] {
+ T::common_regs().ccr().modify(|reg| {
+ reg.set_vbaten(true);
+ });
+ } else {
+ T::common_regs().ccr().modify(|reg| {
+ reg.set_ch18sel(true);
+ });
+ }
+ }
Vbat {}
}
@@ -205,16 +247,21 @@ impl<'d, T: Instance> Adc<'d, T> {
val
}
- #[cfg(adc_g0)]
fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
- T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
- }
-
- #[cfg(not(adc_g0))]
- fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
- let sample_time = sample_time.into();
- T::regs()
- .smpr(ch as usize / 10)
- .modify(|reg| reg.set_smp(ch as usize % 10, sample_time));
+ cfg_if! {
+ if #[cfg(adc_g0)] {
+ T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+ } else if #[cfg(adc_h5)] {
+ match _ch {
+ 0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
+ _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
+ }
+ } else {
+ let sample_time = sample_time.into();
+ T::regs()
+ .smpr(ch as usize / 10)
+ .modify(|reg| reg.set_smp(ch as usize % 10, sample_time));
+ }
+ }
}
}
From 475dea0208954453f935ddb8713fcf9155d3bd22 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Fri, 23 Feb 2024 00:18:24 +0100
Subject: [PATCH 290/392] stm32/rcc: workaround nonsense RAM suicide errata on
backup domain reset.
---
embassy-stm32/src/rcc/bd.rs | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index d20f58185..cb10a9a3f 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -201,11 +201,18 @@ impl LsConfig {
bdcr().modify(|w| w.set_bdrst(true));
bdcr().modify(|w| w.set_bdrst(false));
}
- #[cfg(any(stm32h5))]
- {
- bdcr().modify(|w| w.set_vswrst(true));
- bdcr().modify(|w| w.set_vswrst(false));
- }
+ // H5 has a terrible, terrible errata: 'SRAM2 is erased when the backup domain is reset'
+ // pending a more sane sane way to handle this, just don't reset BD for now.
+ // This means the RTCSEL write below will have no effect, only if it has already been written
+ // after last power-on. Since it's uncommon to dynamically change RTCSEL, this is better than
+ // letting half our RAM go magically *poof*.
+ // STM32H503CB/EB/KB/RB device errata - 2.2.8 SRAM2 unduly erased upon a backup domain reset
+ // STM32H562xx/563xx/573xx device errata - 2.2.14 SRAM2 is erased when the backup domain is reset
+ //#[cfg(any(stm32h5))]
+ //{
+ // bdcr().modify(|w| w.set_vswrst(true));
+ // bdcr().modify(|w| w.set_vswrst(false));
+ //}
#[cfg(any(stm32c0))]
{
bdcr().modify(|w| w.set_rtcrst(true));
From 0665e0d452627b5fe3c0b52981c7f4ef380de83f Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Fri, 23 Feb 2024 01:22:11 +0100
Subject: [PATCH 291/392] stm32/rcc: port U5 to new API, add all PLLs, all HSE
modes.
---
embassy-stm32/src/rcc/u5.rs | 637 +++++++++++--------------
examples/stm32u5/src/bin/usb_serial.rs | 27 +-
tests/stm32/src/common.rs | 13 +-
3 files changed, 314 insertions(+), 363 deletions(-)
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 20cc3112a..72613f0f3 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -1,134 +1,83 @@
-pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange, Plldiv, Pllm, Plln, Ppre as APBPrescaler};
-use crate::pac::rcc::vals::{Msirgsel, Pllmboost, Pllrge, Pllsrc, Sw};
+pub use crate::pac::pwr::vals::Vos as VoltageScale;
+pub use crate::pac::rcc::vals::{
+ Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
+ Pllsrc as PllSource, Ppre as APBPrescaler, Sw as ClockSrc,
+};
+use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge};
use crate::pac::{FLASH, PWR, RCC};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-pub use crate::pac::pwr::vals::Vos as VoltageScale;
-
-#[derive(Copy, Clone)]
-#[allow(non_camel_case_types)]
-pub enum ClockSrc {
- /// Use an internal medium speed oscillator (MSIS) as the system clock.
- MSI(Msirange),
- /// Use the external high speed clock as the system clock.
- ///
- /// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
- /// never exceed 50 MHz.
- HSE(Hertz),
- /// Use the 16 MHz internal high speed oscillator as the system clock.
- HSI,
- /// Use PLL1 as the system clock.
- PLL1_R(PllConfig),
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+ /// crystal/ceramic oscillator (HSEBYP=0)
+ Oscillator,
+ /// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
+ Bypass,
+ /// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
+ BypassDigital,
}
-impl Default for ClockSrc {
- fn default() -> Self {
- // The default system clock source is MSIS @ 4 MHz, per RM0456 § 11.4.9
- ClockSrc::MSI(Msirange::RANGE_4MHZ)
- }
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+ /// HSE frequency.
+ pub freq: Hertz,
+ /// HSE mode.
+ pub mode: HseMode,
}
#[derive(Clone, Copy)]
-pub struct PllConfig {
+pub struct Pll {
/// The clock source for the PLL.
pub source: PllSource,
- /// The PLL prescaler.
+ /// The PLL pre-divider.
///
/// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
- pub m: Pllm,
+ pub prediv: PllPreDiv,
/// The PLL multiplier.
///
/// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
/// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
- pub n: Plln,
+ pub mul: PllMul,
/// The divider for the P output.
///
/// The P output is one of several options
/// that can be used to feed the SAI/MDF/ADF Clock mux's.
- pub p: Plldiv,
+ pub divp: Option<PllDiv>,
/// The divider for the Q output.
///
/// The Q ouput is one of severals options that can be used to feed the 48MHz clocks
/// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's.
- pub q: Plldiv,
+ pub divq: Option<PllDiv>,
/// The divider for the R output.
///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
/// `Config { voltage_range }`.
- pub r: Plldiv,
-}
-
-impl PllConfig {
- /// A configuration for HSI / 1 * 10 / 1 = 160 MHz
- pub const fn hsi_160mhz() -> Self {
- PllConfig {
- source: PllSource::HSI,
- m: Pllm::DIV1,
- n: Plln::MUL10,
- p: Plldiv::DIV3,
- q: Plldiv::DIV2,
- r: Plldiv::DIV1,
- }
- }
-
- /// A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz
- pub const fn msis_160mhz() -> Self {
- PllConfig {
- source: PllSource::MSIS(Msirange::RANGE_48MHZ),
- m: Pllm::DIV3,
- n: Plln::MUL10,
- p: Plldiv::DIV3,
- q: Plldiv::DIV2,
- r: Plldiv::DIV1,
- }
- }
-}
-
-#[derive(Clone, Copy)]
-pub enum PllSource {
- /// Use an internal medium speed oscillator as the PLL source.
- MSIS(Msirange),
- /// Use the external high speed clock as the system PLL source.
- ///
- /// HSE clocks faster than 25 MHz require at least `VoltageScale::RANGE3`, and HSE clocks must
- /// never exceed 50 MHz.
- HSE(Hertz),
- /// Use the 16 MHz internal high speed oscillator as the PLL source.
- HSI,
-}
-
-impl Into<Pllsrc> for PllSource {
- fn into(self) -> Pllsrc {
- match self {
- PllSource::MSIS(..) => Pllsrc::MSIS,
- PllSource::HSE(..) => Pllsrc::HSE,
- PllSource::HSI => Pllsrc::HSI,
- }
- }
-}
-
-impl Into<Sw> for ClockSrc {
- fn into(self) -> Sw {
- match self {
- ClockSrc::MSI(..) => Sw::MSIS,
- ClockSrc::HSE(..) => Sw::HSE,
- ClockSrc::HSI => Sw::HSI,
- ClockSrc::PLL1_R(..) => Sw::PLL1_R,
- }
- }
+ pub divr: Option<PllDiv>,
}
pub struct Config {
+ // base clock sources
+ pub msi: Option<MSIRange>,
+ pub hsi: bool,
+ pub hse: Option<Hse>,
+ pub hsi48: Option<super::Hsi48Config>,
+
+ // pll
+ pub pll1: Option<Pll>,
+ pub pll2: Option<Pll>,
+ pub pll3: Option<Pll>,
+
+ // sysclk, buses.
pub mux: ClockSrc,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub apb3_pre: APBPrescaler,
- pub hsi48: Option<super::Hsi48Config>,
+
/// The voltage range influences the maximum clock frequencies for different parts of the
/// device. In particular, system clocks exceeding 110 MHz require `RANGE1`, and system clocks
/// exceeding 55 MHz require at least `RANGE2`.
@@ -138,35 +87,35 @@ pub struct Config {
pub ls: super::LsConfig,
}
-impl Config {
- unsafe fn init_hsi(&self) -> Hertz {
- RCC.cr().write(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
-
- HSI_FREQ
- }
-
- unsafe fn init_hse(&self, frequency: Hertz) -> Hertz {
- // Check frequency limits per RM456 § 11.4.10
- match self.voltage_range {
- VoltageScale::RANGE1 | VoltageScale::RANGE2 | VoltageScale::RANGE3 => {
- assert!(frequency.0 <= 50_000_000);
- }
- VoltageScale::RANGE4 => {
- assert!(frequency.0 <= 25_000_000);
- }
+impl Default for Config {
+ fn default() -> Self {
+ Self {
+ msi: Some(Msirange::RANGE_4MHZ),
+ hse: None,
+ hsi: false,
+ hsi48: Some(Default::default()),
+ pll1: None,
+ pll2: None,
+ pll3: None,
+ mux: ClockSrc::MSIS,
+ ahb_pre: AHBPrescaler::DIV1,
+ apb1_pre: APBPrescaler::DIV1,
+ apb2_pre: APBPrescaler::DIV1,
+ apb3_pre: APBPrescaler::DIV1,
+ voltage_range: VoltageScale::RANGE1,
+ ls: Default::default(),
}
-
- // Enable HSE, and wait for it to stabilize
- RCC.cr().write(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
-
- frequency
}
+}
- unsafe fn init_msis(&self, range: Msirange) -> Hertz {
+pub(crate) unsafe fn init(config: Config) {
+ // Set the requested power mode
+ PWR.vosr().modify(|w| w.set_vos(config.voltage_range));
+ while !PWR.vosr().read().vosrdy() {}
+
+ let msi = config.msi.map(|range| {
// Check MSI output per RM0456 § 11.4.10
- match self.voltage_range {
+ match config.voltage_range {
VoltageScale::RANGE4 => {
assert!(msirange_to_hertz(range).0 <= 24_000_000);
}
@@ -191,223 +140,98 @@ impl Config {
});
while !RCC.cr().read().msisrdy() {}
msirange_to_hertz(range)
- }
-}
-
-impl Default for Config {
- fn default() -> Self {
- Self {
- mux: ClockSrc::default(),
- ahb_pre: AHBPrescaler::DIV1,
- apb1_pre: APBPrescaler::DIV1,
- apb2_pre: APBPrescaler::DIV1,
- apb3_pre: APBPrescaler::DIV1,
- hsi48: Some(Default::default()),
- voltage_range: VoltageScale::RANGE3,
- ls: Default::default(),
- }
- }
-}
-
-pub(crate) unsafe fn init(config: Config) {
- // Ensure PWR peripheral clock is enabled
- RCC.ahb3enr().modify(|w| {
- w.set_pwren(true);
});
- RCC.ahb3enr().read(); // synchronize
- // Set the requested power mode
- PWR.vosr().modify(|w| {
- w.set_vos(config.voltage_range);
+ let hsi = config.hsi.then(|| {
+ RCC.cr().write(|w| w.set_hsion(true));
+ while !RCC.cr().read().hsirdy() {}
+
+ HSI_FREQ
});
- while !PWR.vosr().read().vosrdy() {}
- let sys_clk = match config.mux {
- ClockSrc::MSI(range) => config.init_msis(range),
- ClockSrc::HSE(freq) => config.init_hse(freq),
- ClockSrc::HSI => config.init_hsi(),
- ClockSrc::PLL1_R(pll) => {
- // Configure the PLL source
- let source_clk = match pll.source {
- PllSource::MSIS(range) => config.init_msis(range),
- PllSource::HSE(hertz) => config.init_hse(hertz),
- PllSource::HSI => config.init_hsi(),
- };
-
- // Calculate the reference clock, which is the source divided by m
- let reference_clk = source_clk / pll.m;
-
- // Check limits per RM0456 § 11.4.6
- assert!(Hertz::mhz(4) <= reference_clk && reference_clk <= Hertz::mhz(16));
-
- // Calculate the PLL1 VCO clock and PLL1 R output clock
- let pll1_clk = reference_clk * pll.n;
- let pll1r_clk = pll1_clk / pll.r;
-
- // Check system clock per RM0456 § 11.4.9
- assert!(pll1r_clk <= Hertz::mhz(160));
-
- // Check PLL clocks per RM0456 § 11.4.10
- match config.voltage_range {
- VoltageScale::RANGE1 => {
- assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
- assert!(pll1r_clk <= Hertz::mhz(208));
- }
- VoltageScale::RANGE2 => {
- assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(544));
- assert!(pll1r_clk <= Hertz::mhz(110));
- }
- VoltageScale::RANGE3 => {
- assert!(pll1_clk >= Hertz::mhz(128) && pll1_clk <= Hertz::mhz(330));
- assert!(pll1r_clk <= Hertz::mhz(55));
- }
- VoltageScale::RANGE4 => {
- panic!("PLL is unavailable in voltage range 4");
- }
+ let hse = config.hse.map(|hse| {
+ // Check frequency limits per RM456 § 11.4.10
+ match config.voltage_range {
+ VoltageScale::RANGE1 | VoltageScale::RANGE2 | VoltageScale::RANGE3 => {
+ assert!(hse.freq.0 <= 50_000_000);
}
-
- // § 10.5.4: if we're targeting >= 55 MHz, we must configure PLL1MBOOST to a prescaler
- // value that results in an output between 4 and 16 MHz for the PWR EPOD boost
- let mboost = if pll1r_clk >= Hertz::mhz(55) {
- // source_clk can be up to 50 MHz, so there's just a few cases:
- if source_clk > Hertz::mhz(32) {
- // Divide by 4, giving EPOD 8-12.5 MHz
- Pllmboost::DIV4
- } else if source_clk > Hertz::mhz(16) {
- // Divide by 2, giving EPOD 8-16 MHz
- Pllmboost::DIV2
- } else {
- // Bypass, giving EPOD 4-16 MHz
- Pllmboost::DIV1
- }
- } else {
- // Nothing to do
- Pllmboost::DIV1
- };
-
- // Disable the PLL, and wait for it to disable
- RCC.cr().modify(|w| w.set_pllon(0, false));
- while RCC.cr().read().pllrdy(0) {}
-
- // Configure the PLL
- RCC.pll1cfgr().write(|w| {
- // Configure PLL1 source and prescaler
- w.set_pllsrc(pll.source.into());
- w.set_pllm(pll.m);
-
- // Configure PLL1 input frequncy range
- let input_range = if reference_clk <= Hertz::mhz(8) {
- Pllrge::FREQ_4TO8MHZ
- } else {
- Pllrge::FREQ_8TO16MHZ
- };
- w.set_pllrge(input_range);
-
- // Set the prescaler for PWR EPOD
- w.set_pllmboost(mboost);
-
- // Enable PLL1_R output
- w.set_pllren(true);
- });
-
- // Configure the PLL divisors
- RCC.pll1divr().modify(|w| {
- // Set the VCO multiplier
- w.set_plln(pll.n);
- w.set_pllp(pll.p);
- w.set_pllq(pll.q);
- // Set the R output divisor
- w.set_pllr(pll.r);
- });
-
- // Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
- if pll1r_clk >= Hertz::mhz(55) {
- // Enable the booster
- PWR.vosr().modify(|w| {
- w.set_boosten(true);
- });
- while !PWR.vosr().read().boostrdy() {}
+ VoltageScale::RANGE4 => {
+ assert!(hse.freq.0 <= 25_000_000);
}
-
- // Enable the PLL
- RCC.cr().modify(|w| w.set_pllon(0, true));
- while !RCC.cr().read().pllrdy(0) {}
-
- pll1r_clk
}
- };
+
+ // Enable HSE, and wait for it to stabilize
+ RCC.cr().write(|w| {
+ w.set_hseon(true);
+ w.set_hsebyp(hse.mode != HseMode::Oscillator);
+ w.set_hseext(match hse.mode {
+ HseMode::Oscillator | HseMode::Bypass => Hseext::ANALOG,
+ HseMode::BypassDigital => Hseext::DIGITAL,
+ });
+ });
+ while !RCC.cr().read().hserdy() {}
+
+ hse.freq
+ });
let hsi48 = config.hsi48.map(super::init_hsi48);
+ let pll_input = PllInput { hse, hsi, msi };
+ let pll1 = init_pll(PllInstance::Pll1, config.pll1, &pll_input, config.voltage_range);
+ let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range);
+ let pll3 = init_pll(PllInstance::Pll3, config.pll3, &pll_input, config.voltage_range);
+
+ let sys_clk = match config.mux {
+ ClockSrc::HSE => hse.unwrap(),
+ ClockSrc::HSI => hsi.unwrap(),
+ ClockSrc::MSIS => msi.unwrap(),
+ ClockSrc::PLL1_R => pll1.r.unwrap(),
+ };
+
+ // Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
+ if sys_clk >= Hertz::mhz(55) {
+ // Enable the booster
+ PWR.vosr().modify(|w| w.set_boosten(true));
+ while !PWR.vosr().read().boostrdy() {}
+ }
+
// The clock source is ready
// Calculate and set the flash wait states
let wait_states = match config.voltage_range {
// VOS 1 range VCORE 1.26V - 1.40V
- VoltageScale::RANGE1 => {
- if sys_clk.0 < 32_000_000 {
- 0
- } else if sys_clk.0 < 64_000_000 {
- 1
- } else if sys_clk.0 < 96_000_000 {
- 2
- } else if sys_clk.0 < 128_000_000 {
- 3
- } else {
- 4
- }
- }
+ VoltageScale::RANGE1 => match sys_clk.0 {
+ ..=32_000_000 => 0,
+ ..=64_000_000 => 1,
+ ..=96_000_000 => 2,
+ ..=128_000_000 => 3,
+ _ => 4,
+ },
// VOS 2 range VCORE 1.15V - 1.26V
- VoltageScale::RANGE2 => {
- if sys_clk.0 < 30_000_000 {
- 0
- } else if sys_clk.0 < 60_000_000 {
- 1
- } else if sys_clk.0 < 90_000_000 {
- 2
- } else {
- 3
- }
- }
+ VoltageScale::RANGE2 => match sys_clk.0 {
+ ..=30_000_000 => 0,
+ ..=60_000_000 => 1,
+ ..=90_000_000 => 2,
+ _ => 3,
+ },
// VOS 3 range VCORE 1.05V - 1.15V
- VoltageScale::RANGE3 => {
- if sys_clk.0 < 24_000_000 {
- 0
- } else if sys_clk.0 < 48_000_000 {
- 1
- } else {
- 2
- }
- }
+ VoltageScale::RANGE3 => match sys_clk.0 {
+ ..=24_000_000 => 0,
+ ..=48_000_000 => 1,
+ _ => 2,
+ },
// VOS 4 range VCORE 0.95V - 1.05V
- VoltageScale::RANGE4 => {
- if sys_clk.0 < 12_000_000 {
- 0
- } else {
- 1
- }
- }
+ VoltageScale::RANGE4 => match sys_clk.0 {
+ ..=12_000_000 => 0,
+ _ => 1,
+ },
};
FLASH.acr().modify(|w| {
w.set_latency(wait_states);
});
// Switch the system clock source
- RCC.cfgr1().modify(|w| {
- w.set_sw(config.mux.into());
- });
-
- // RM0456 § 11.4.9 specifies maximum bus frequencies per voltage range, but the maximum bus
- // frequency for each voltage range exactly matches the maximum permitted PLL output frequency.
- // Given that:
- //
- // 1. Any bus frequency can never exceed the system clock frequency;
- // 2. We checked the PLL output frequency if we're using it as a system clock;
- // 3. The maximum HSE frequencies at each voltage range are lower than the bus limits, and
- // we checked the HSE frequency if configured as a system clock; and
- // 4. The maximum frequencies from the other clock sources are lower than the lowest bus
- // frequency limit
- //
- // ...then we do not need to perform additional bus-related frequency checks.
+ RCC.cfgr1().modify(|w| w.set_sw(config.mux));
+ while RCC.cfgr1().read().sws() != config.mux {}
// Configure the bus prescalers
RCC.cfgr2().modify(|w| {
@@ -419,64 +243,52 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre3(config.apb3_pre);
});
- let ahb_freq = sys_clk / config.ahb_pre;
+ let hclk = sys_clk / config.ahb_pre;
- let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
+ let hclk_max = match config.voltage_range {
+ VoltageScale::RANGE1 => Hertz::mhz(160),
+ VoltageScale::RANGE2 => Hertz::mhz(110),
+ VoltageScale::RANGE3 => Hertz::mhz(55),
+ VoltageScale::RANGE4 => Hertz::mhz(25),
};
+ assert!(hclk <= hclk_max);
- let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
-
- let (apb3_freq, _apb3_tim_freq) = match config.apb3_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+ let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
+ let (pclk3, _) = super::util::calc_pclk(hclk, config.apb3_pre);
let rtc = config.ls.init();
set_clocks!(
sys: Some(sys_clk),
- hclk1: Some(ahb_freq),
- hclk2: Some(ahb_freq),
- hclk3: Some(ahb_freq),
- pclk1: Some(apb1_freq),
- pclk2: Some(apb2_freq),
- pclk3: Some(apb3_freq),
- pclk1_tim: Some(apb1_tim_freq),
- pclk2_tim: Some(apb2_tim_freq),
+ hclk1: Some(hclk),
+ hclk2: Some(hclk),
+ hclk3: Some(hclk),
+ pclk1: Some(pclk1),
+ pclk2: Some(pclk2),
+ pclk3: Some(pclk3),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2_tim: Some(pclk2_tim),
hsi48: hsi48,
rtc: rtc,
+ hse: hse,
+ hsi: hsi,
+ pll1_p: pll1.p,
+ pll1_q: pll1.q,
+ pll1_r: pll1.r,
+ pll2_p: pll2.p,
+ pll2_q: pll2.q,
+ pll2_r: pll2.r,
+ pll3_p: pll3.p,
+ pll3_q: pll3.q,
+ pll3_r: pll3.r,
// TODO
- hse: None,
- hsi: None,
audioclk: None,
hsi48_div_2: None,
lse: None,
lsi: None,
msik: None,
- pll1_p: None,
- pll1_q: None,
- pll1_r: None,
- pll2_p: None,
- pll2_q: None,
- pll2_r: None,
- pll3_p: None,
- pll3_q: None,
- pll3_r: None,
iclk: None,
);
}
@@ -501,3 +313,126 @@ fn msirange_to_hertz(range: Msirange) -> Hertz {
Msirange::RANGE_100KHZ => Hertz(100_000),
}
}
+
+pub(super) struct PllInput {
+ pub hsi: Option<Hertz>,
+ pub hse: Option<Hertz>,
+ pub msi: Option<Hertz>,
+}
+
+#[allow(unused)]
+#[derive(Default)]
+pub(super) struct PllOutput {
+ pub p: Option<Hertz>,
+ pub q: Option<Hertz>,
+ pub r: Option<Hertz>,
+}
+
+#[derive(PartialEq, Eq, Clone, Copy)]
+enum PllInstance {
+ Pll1 = 0,
+ Pll2 = 1,
+ Pll3 = 2,
+}
+
+fn pll_enable(instance: PllInstance, enabled: bool) {
+ RCC.cr().modify(|w| w.set_pllon(instance as _, enabled));
+ while RCC.cr().read().pllrdy(instance as _) != enabled {}
+}
+
+fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput, voltage_range: VoltageScale) -> PllOutput {
+ // Disable PLL
+ pll_enable(instance, false);
+
+ let Some(pll) = config else { return PllOutput::default() };
+
+ let src_freq = match pll.source {
+ PllSource::DISABLE => panic!("must not select PLL source as DISABLE"),
+ PllSource::HSE => unwrap!(input.hse),
+ PllSource::HSI => unwrap!(input.hsi),
+ PllSource::MSIS => unwrap!(input.msi),
+ };
+
+ // Calculate the reference clock, which is the source divided by m
+ let ref_freq = src_freq / pll.prediv;
+ // Check limits per RM0456 § 11.4.6
+ assert!(Hertz::mhz(4) <= ref_freq && ref_freq <= Hertz::mhz(16));
+
+ // Check PLL clocks per RM0456 § 11.4.10
+ let (vco_min, vco_max, out_max) = match voltage_range {
+ VoltageScale::RANGE1 => (Hertz::mhz(128), Hertz::mhz(544), Hertz::mhz(208)),
+ VoltageScale::RANGE2 => (Hertz::mhz(128), Hertz::mhz(544), Hertz::mhz(110)),
+ VoltageScale::RANGE3 => (Hertz::mhz(128), Hertz::mhz(330), Hertz::mhz(55)),
+ VoltageScale::RANGE4 => panic!("PLL is unavailable in voltage range 4"),
+ };
+
+ // Calculate the PLL VCO clock
+ let vco_freq = ref_freq * pll.mul;
+ assert!(vco_freq >= vco_min && vco_freq <= vco_max);
+
+ // Calculate output clocks.
+ let p = pll.divp.map(|div| vco_freq / div);
+ let q = pll.divq.map(|div| vco_freq / div);
+ let r = pll.divr.map(|div| vco_freq / div);
+ for freq in [p, q, r] {
+ if let Some(freq) = freq {
+ assert!(freq <= out_max);
+ }
+ }
+
+ let divr = match instance {
+ PllInstance::Pll1 => RCC.pll1divr(),
+ PllInstance::Pll2 => RCC.pll2divr(),
+ PllInstance::Pll3 => RCC.pll3divr(),
+ };
+ divr.write(|w| {
+ w.set_plln(pll.mul);
+ w.set_pllp(pll.divp.unwrap_or(PllDiv::DIV1));
+ w.set_pllq(pll.divq.unwrap_or(PllDiv::DIV1));
+ w.set_pllr(pll.divr.unwrap_or(PllDiv::DIV1));
+ });
+
+ let input_range = match ref_freq.0 {
+ ..=8_000_000 => Pllrge::FREQ_4TO8MHZ,
+ _ => Pllrge::FREQ_8TO16MHZ,
+ };
+
+ macro_rules! write_fields {
+ ($w:ident) => {
+ $w.set_pllpen(pll.divp.is_some());
+ $w.set_pllqen(pll.divq.is_some());
+ $w.set_pllren(pll.divr.is_some());
+ $w.set_pllm(pll.prediv);
+ $w.set_pllsrc(pll.source);
+ $w.set_pllrge(input_range);
+ };
+ }
+
+ match instance {
+ PllInstance::Pll1 => RCC.pll1cfgr().write(|w| {
+ // § 10.5.4: if we're targeting >= 55 MHz, we must configure PLL1MBOOST to a prescaler
+ // value that results in an output between 4 and 16 MHz for the PWR EPOD boost
+ if r.unwrap() >= Hertz::mhz(55) {
+ // source_clk can be up to 50 MHz, so there's just a few cases:
+ let mboost = match src_freq.0 {
+ ..=16_000_000 => Pllmboost::DIV1, // Bypass, giving EPOD 4-16 MHz
+ ..=32_000_000 => Pllmboost::DIV2, // Divide by 2, giving EPOD 8-16 MHz
+ _ => Pllmboost::DIV4, // Divide by 4, giving EPOD 8-12.5 MHz
+ };
+ w.set_pllmboost(mboost);
+ }
+ write_fields!(w);
+ }),
+ PllInstance::Pll2 => RCC.pll2cfgr().write(|w| {
+ write_fields!(w);
+ }),
+ PllInstance::Pll3 => RCC.pll3cfgr().write(|w| {
+ write_fields!(w);
+ }),
+ }
+
+ // Enable PLL
+ pll_enable(instance, true);
+
+ PllOutput { p, q, r }
+}
diff --git a/examples/stm32u5/src/bin/usb_serial.rs b/examples/stm32u5/src/bin/usb_serial.rs
index dca34fd0e..99cdeacc9 100644
--- a/examples/stm32u5/src/bin/usb_serial.rs
+++ b/examples/stm32u5/src/bin/usb_serial.rs
@@ -4,7 +4,6 @@
use defmt::{panic, *};
use defmt_rtt as _; // global logger
use embassy_executor::Spawner;
-use embassy_stm32::rcc::*;
use embassy_stm32::usb_otg::{Driver, Instance};
use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
@@ -22,22 +21,28 @@ async fn main(_spawner: Spawner) {
info!("Hello World!");
let mut config = Config::default();
- config.rcc.mux = ClockSrc::PLL1_R(PllConfig {
- source: PllSource::HSI,
- m: Pllm::DIV2,
- n: Plln::MUL10,
- p: Plldiv::DIV1,
- q: Plldiv::DIV1,
- r: Plldiv::DIV1,
- });
- config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hsi = true;
+ config.rcc.pll1 = Some(Pll {
+ source: PllSource::HSI, // 16 MHz
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL10,
+ divp: None,
+ divq: None,
+ divr: Some(PllDiv::DIV1), // 160 MHz
+ });
+ config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.voltage_range = VoltageScale::RANGE1;
+ config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
+ }
let p = embassy_stm32::init(config);
// Create the driver, from the HAL.
let mut ep_out_buffer = [0u8; 256];
let mut config = embassy_stm32::usb_otg::Config::default();
- config.vbus_detection = true;
+ config.vbus_detection = false;
let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer, config);
// Create embassy-usb Config
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 50a7f9bae..1e6b1cce9 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -577,7 +577,18 @@ pub fn config() -> Config {
#[cfg(any(feature = "stm32u585ai", feature = "stm32u5a5zj"))]
{
use embassy_stm32::rcc::*;
- config.rcc.mux = ClockSrc::MSI(Msirange::RANGE_48MHZ);
+ config.rcc.hsi = true;
+ config.rcc.pll1 = Some(Pll {
+ source: PllSource::HSI, // 16 MHz
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL10,
+ divp: None,
+ divq: None,
+ divr: Some(PllDiv::DIV1), // 160 MHz
+ });
+ config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.voltage_range = VoltageScale::RANGE1;
+ config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
}
#[cfg(feature = "stm32wba52cg")]
From d24349f57ce7435e70fcf1cd9aac20d1740995d4 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Fri, 23 Feb 2024 01:33:37 +0100
Subject: [PATCH 292/392] stm32/tests: run stm32u5a5zj from flash due to wrong
RAM size in stm32-data.
---
tests/stm32/Cargo.toml | 2 +-
tests/stm32/build.rs | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 5b28b5849..828a28e2c 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -26,7 +26,7 @@ stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng", "hash"
stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"]
stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash"]
stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng", "hash"]
-stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
+stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng", "hash"]
stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"]
stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
diff --git a/tests/stm32/build.rs b/tests/stm32/build.rs
index bc5589164..176adff62 100644
--- a/tests/stm32/build.rs
+++ b/tests/stm32/build.rs
@@ -16,6 +16,7 @@ fn main() -> Result<(), Box<dyn Error>> {
feature = "stm32l073rz",
// wrong ram size in stm32-data
feature = "stm32wl55jc",
+ feature = "stm32u5a5zj",
// no VTOR, so interrupts can't work when running from RAM
feature = "stm32f091rc",
)) {
From b091ffcb55840a1349c62f1e4218746d9d51b6c3 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Fri, 23 Feb 2024 01:59:24 +0100
Subject: [PATCH 293/392] [embassy-stm32] G4 RCC refactor amendments and
additions
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
* Added assertions for a variety of clock frequencies, based on the reference manual and
stm32g474 datasheet. The family and numbers are consistent enough that I’m assuming
these numbers will work for the other chips.
* Corrected value of pll1_q in set_clocks call, added pll1_r value
---
embassy-stm32/src/rcc/g4.rs | 52 +++++++++++++++++++++++++------------
1 file changed, 35 insertions(+), 17 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 382ffbead..6ed266284 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -176,7 +176,7 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};
- // TODO: check PLL input, internal and output frequencies for validity
+ assert!(max::PLL_IN.contains(&src_freq));
// Disable PLL before configuration
RCC.cr().modify(|w| w.set_pllon(false));
@@ -184,6 +184,8 @@ pub(crate) unsafe fn init(config: Config) {
let internal_freq = src_freq / pll_config.prediv * pll_config.mul;
+ assert!(max::PLL_VCO.contains(&internal_freq));
+
RCC.pllcfgr().write(|w| {
w.set_plln(pll_config.mul);
w.set_pllm(pll_config.prediv);
@@ -195,7 +197,9 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllp(div_p);
w.set_pllpen(true);
});
- internal_freq / div_p
+ let freq = internal_freq / div_p;
+ assert!(max::PCLK.contains(&freq));
+ freq
});
let pll_q_freq = pll_config.divq.map(|div_q| {
@@ -203,7 +207,9 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllq(div_q);
w.set_pllqen(true);
});
- internal_freq / div_q
+ let freq = internal_freq / div_q;
+ assert!(max::PCLK.contains(&freq));
+ freq
});
let pll_r_freq = pll_config.divr.map(|div_r| {
@@ -211,7 +217,9 @@ pub(crate) unsafe fn init(config: Config) {
w.set_pllr(div_r);
w.set_pllren(true);
});
- internal_freq / div_r
+ let freq = internal_freq / div_r;
+ assert!(max::PCLK.contains(&freq));
+ freq
});
// Enable the PLL
@@ -234,7 +242,7 @@ pub(crate) unsafe fn init(config: Config) {
let freq = pll_freq.as_ref().unwrap().pll_r.unwrap().0;
- assert!(freq <= 170_000_000);
+ assert!(max::SYSCLK.contains(&Hertz(freq)));
(Hertz(freq), Sw::PLL1_R)
}
@@ -244,6 +252,8 @@ pub(crate) unsafe fn init(config: Config) {
// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
let hclk = sys_clk / config.ahb_pre;
+ assert!(max::HCLK.contains(&hclk));
+
// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
if config.boost {
// RM0440 p235
@@ -346,32 +356,40 @@ pub(crate) unsafe fn init(config: Config) {
adc: adc12_ck,
adc34: adc345_ck,
pll1_p: pll_freq.as_ref().and_then(|pll| pll.pll_p),
- pll1_q: pll_freq.as_ref().and_then(|pll| pll.pll_p),
+ pll1_q: pll_freq.as_ref().and_then(|pll| pll.pll_q),
+ pll1_r: pll_freq.as_ref().and_then(|pll| pll.pll_r),
hse: hse,
rtc: rtc,
);
}
-// TODO: if necessary, make more of these, gated behind cfg attrs
+/// Acceptable Frequency Ranges
+/// Currently assuming voltage scaling range 1 boost mode.
+/// Where not specified in the generic G4 reference manual (RM0440), values taken from the STM32G474 datasheet.
+/// If acceptable ranges for other G4-family chips differ, make additional max modules gated behind cfg attrs.
mod max {
use core::ops::RangeInclusive;
use crate::time::Hertz;
- /// HSE 4-48MHz (RM0440 p280)
+ /// HSE Frequency Range (RM0440 p280)
pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(48_000_000);
- /// External Clock ?-48MHz (RM0440 p280)
+ /// External Clock Frequency Range (RM0440 p280)
pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
- // SYSCLK ?-170MHz (RM0440 p282)
- //pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
+ /// SYSCLK Frequency Range (RM0440 p282)
+ pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
- // PLL Output frequency ?-170MHz (RM0440 p281)
- //pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
+ /// PLL Output Frequency Range (RM0440 p281, STM32G474 Datasheet p123, Table 46)
+ pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(8)..=Hertz(170_000_000);
- // Left over from f.rs, remove if not necessary
- //pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(12_500_000)..=Hertz(216_000_000);
- //pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
- //pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
+ /// HCLK (AHB) Clock Frequency Range (STM32G474 Datasheet)
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
+
+ /// PLL Source Frequency Range (STM32G474 Datasheet p123, Table 46)
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(2_660_000)..=Hertz(16_000_000);
+
+ /// PLL VCO (internal) Frequency Range (STM32G474 Datasheet p123, Table 46)
+ pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(96_000_000)..=Hertz(344_000_000);
}
From a11e3146f8f5c00c770c6ef913bca676bbc9a685 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Thu, 22 Feb 2024 16:55:00 +0000
Subject: [PATCH 294/392] stm32: time_driver: allow use of TIM1 for driver
---
embassy-stm32/Cargo.toml | 2 ++
embassy-stm32/src/time_driver.rs | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index d585d2cd6..0defde033 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -130,6 +130,8 @@ _time-driver = ["dep:embassy-time-driver", "time"]
## Use any time driver
time-driver-any = ["_time-driver"]
+## Use TIM1 as time driver
+time-driver-tim1 = ["_time-driver"]
## Use TIM2 as time driver
time-driver-tim2 = ["_time-driver"]
## Use TIM3 as time driver
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index a1f54307d..4129e4f30 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -38,7 +38,7 @@ cfg_if::cfg_if! {
}
}
-#[cfg(time_drvier_tim1)]
+#[cfg(time_driver_tim1)]
type T = peripherals::TIM1;
#[cfg(time_driver_tim2)]
type T = peripherals::TIM2;
From 44534abf32f556533c1183640e87bc2d45161d54 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Thu, 22 Feb 2024 17:26:44 +0000
Subject: [PATCH 295/392] stm32: sync available TIMs in Cargo.toml, build.rs
---
embassy-stm32/Cargo.toml | 8 ++++++++
embassy-stm32/build.rs | 1 +
2 files changed, 9 insertions(+)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 0defde033..c4b3ece1a 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -140,6 +140,8 @@ time-driver-tim3 = ["_time-driver"]
time-driver-tim4 = ["_time-driver"]
## Use TIM5 as time driver
time-driver-tim5 = ["_time-driver"]
+## Use TIM8 as time driver
+time-driver-tim8 = ["_time-driver"]
## Use TIM9 as time driver
time-driver-tim9 = ["_time-driver"]
## Use TIM11 as time driver
@@ -148,10 +150,16 @@ time-driver-tim11 = ["_time-driver"]
time-driver-tim12 = ["_time-driver"]
## Use TIM15 as time driver
time-driver-tim15 = ["_time-driver"]
+## Use TIM20 as time driver
+time-driver-tim20 = ["_time-driver"]
## Use TIM21 as time driver
time-driver-tim21 = ["_time-driver"]
## Use TIM22 as time driver
time-driver-tim22 = ["_time-driver"]
+## Use TIM23 as time driver
+time-driver-tim23 = ["_time-driver"]
+## Use TIM24 as time driver
+time-driver-tim24 = ["_time-driver"]
#! ## Analog Switch Pins (Pxy_C) on STM32H7 series
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 068a74733..75a2055eb 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -189,6 +189,7 @@ fn main() {
Some("tim5") => "TIM5",
Some("tim8") => "TIM8",
Some("tim9") => "TIM9",
+ Some("tim11") => "TIM11",
Some("tim12") => "TIM12",
Some("tim15") => "TIM15",
Some("tim20") => "TIM20",
From 86ccf0bc3e0a9908402405aebde6755df0e1b4f6 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Thu, 22 Feb 2024 17:42:08 +0000
Subject: [PATCH 296/392] stm32: remove TIM11 as time driver candidate (only 1
CC channel)
---
embassy-stm32/Cargo.toml | 2 --
embassy-stm32/build.rs | 1 -
embassy-stm32/src/time_driver.rs | 2 --
3 files changed, 5 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index c4b3ece1a..abcc8ac4e 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -144,8 +144,6 @@ time-driver-tim5 = ["_time-driver"]
time-driver-tim8 = ["_time-driver"]
## Use TIM9 as time driver
time-driver-tim9 = ["_time-driver"]
-## Use TIM11 as time driver
-time-driver-tim11 = ["_time-driver"]
## Use TIM12 as time driver
time-driver-tim12 = ["_time-driver"]
## Use TIM15 as time driver
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 75a2055eb..068a74733 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -189,7 +189,6 @@ fn main() {
Some("tim5") => "TIM5",
Some("tim8") => "TIM8",
Some("tim9") => "TIM9",
- Some("tim11") => "TIM11",
Some("tim12") => "TIM12",
Some("tim15") => "TIM15",
Some("tim20") => "TIM20",
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 4129e4f30..8e4e606a4 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -52,8 +52,6 @@ type T = peripherals::TIM5;
type T = peripherals::TIM8;
#[cfg(time_driver_tim9)]
type T = peripherals::TIM9;
-#[cfg(time_driver_tim11)]
-type T = peripherals::TIM11;
#[cfg(time_driver_tim12)]
type T = peripherals::TIM12;
#[cfg(time_driver_tim15)]
From e67dfcb04f79aebed52a357b867d418e0ff476af Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sat, 24 Feb 2024 02:38:31 +0100
Subject: [PATCH 297/392] stm32/dma: add AnyChannel, add support for BDMA on
H7.
---
embassy-stm32/build.rs | 181 ++--
embassy-stm32/src/dcmi.rs | 122 ---
embassy-stm32/src/dma/bdma.rs | 740 -------------
embassy-stm32/src/dma/dma.rs | 1012 ------------------
embassy-stm32/src/dma/dma_bdma.rs | 913 ++++++++++++++++
embassy-stm32/src/dma/dmamux.rs | 34 +-
embassy-stm32/src/dma/gpdma.rs | 170 ++-
embassy-stm32/src/dma/mod.rs | 104 +-
embassy-stm32/src/sai/mod.rs | 49 +-
embassy-stm32/src/sdmmc/mod.rs | 15 +-
embassy-stm32/src/usart/ringbuffered.rs | 20 +-
tests/stm32/src/bin/usart_rx_ringbuffered.rs | 2 +-
12 files changed, 1210 insertions(+), 2152 deletions(-)
delete mode 100644 embassy-stm32/src/dma/bdma.rs
delete mode 100644 embassy-stm32/src/dma/dma.rs
create mode 100644 embassy-stm32/src/dma/dma_bdma.rs
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 068a74733..4ecc97536 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -353,50 +353,6 @@ fn main() {
g.extend(quote! { pub mod flash_regions { #flash_regions } });
- // ========
- // Generate DMA IRQs.
-
- let mut dma_irqs: BTreeMap<&str, Vec<(&str, &str, &str)>> = BTreeMap::new();
-
- for p in METADATA.peripherals {
- if let Some(r) = &p.registers {
- if r.kind == "dma" || r.kind == "bdma" || r.kind == "gpdma" {
- if p.name == "BDMA1" {
- // BDMA1 in H7 doesn't use DMAMUX, which breaks
- continue;
- }
- for irq in p.interrupts {
- dma_irqs
- .entry(irq.interrupt)
- .or_default()
- .push((r.kind, p.name, irq.signal));
- }
- }
- }
- }
-
- let dma_irqs: TokenStream = dma_irqs
- .iter()
- .map(|(irq, channels)| {
- let irq = format_ident!("{}", irq);
-
- let xdma = format_ident!("{}", channels[0].0);
- let channels = channels.iter().map(|(_, dma, ch)| format_ident!("{}_{}", dma, ch));
-
- quote! {
- #[cfg(feature = "rt")]
- #[crate::interrupt]
- unsafe fn #irq () {
- #(
- <crate::peripherals::#channels as crate::dma::#xdma::sealed::Channel>::on_irq();
- )*
- }
- }
- })
- .collect();
-
- g.extend(dma_irqs);
-
// ========
// Extract the rcc registers
let rcc_registers = METADATA
@@ -664,7 +620,7 @@ fn main() {
#[rustfmt::skip]
let signals: HashMap<_, _> = [
- // (kind, signal) => trait
+ // (kind, signal) => trait
(("usart", "TX"), quote!(crate::usart::TxPin)),
(("usart", "RX"), quote!(crate::usart::RxPin)),
(("usart", "CTS"), quote!(crate::usart::CtsPin)),
@@ -897,7 +853,7 @@ fn main() {
(("quadspi", "BK2_IO3"), quote!(crate::qspi::BK2D3Pin)),
(("quadspi", "BK2_NCS"), quote!(crate::qspi::BK2NSSPin)),
(("quadspi", "CLK"), quote!(crate::qspi::SckPin)),
- ].into();
+ ].into();
for p in METADATA.peripherals {
if let Some(regs) = &p.registers {
@@ -959,7 +915,7 @@ fn main() {
};
if let Some(ch) = ch {
g.extend(quote! {
- impl_adc_pin!( #peri, #pin_name, #ch);
+ impl_adc_pin!( #peri, #pin_name, #ch);
})
}
}
@@ -991,7 +947,7 @@ fn main() {
let ch: u8 = pin.signal.strip_prefix("OUT").unwrap().parse().unwrap();
g.extend(quote! {
- impl_dac_pin!( #peri, #pin_name, #ch);
+ impl_dac_pin!( #peri, #pin_name, #ch);
})
}
}
@@ -1189,7 +1145,6 @@ fn main() {
let mut interrupts_table: Vec<Vec<String>> = Vec::new();
let mut peripherals_table: Vec<Vec<String>> = Vec::new();
let mut pins_table: Vec<Vec<String>> = Vec::new();
- let mut dma_channels_table: Vec<Vec<String>> = Vec::new();
let mut adc_common_table: Vec<Vec<String>> = Vec::new();
/*
@@ -1283,51 +1238,108 @@ fn main() {
}
}
- let mut dma_channel_count: usize = 0;
- let mut bdma_channel_count: usize = 0;
- let mut gpdma_channel_count: usize = 0;
+ let mut dmas = TokenStream::new();
+ let has_dmamux = METADATA
+ .peripherals
+ .iter()
+ .flat_map(|p| &p.registers)
+ .any(|p| p.kind == "dmamux");
+
+ for (ch_idx, ch) in METADATA.dma_channels.iter().enumerate() {
+ // Some H7 chips have BDMA1 hardcoded for DFSDM, ie no DMAMUX. It's unsupported, skip it.
+ if has_dmamux && ch.dmamux.is_none() {
+ continue;
+ }
+
+ let name = format_ident!("{}", ch.name);
+ let idx = ch_idx as u8;
+ g.extend(quote!(dma_channel_impl!(#name, #idx);));
+
+ let dma = format_ident!("{}", ch.dma);
+ let ch_num = ch.channel as usize;
- for ch in METADATA.dma_channels {
- let mut row = Vec::new();
let dma_peri = METADATA.peripherals.iter().find(|p| p.name == ch.dma).unwrap();
let bi = dma_peri.registers.as_ref().unwrap();
- let num;
- match bi.kind {
- "dma" => {
- num = dma_channel_count;
- dma_channel_count += 1;
- }
- "bdma" => {
- num = bdma_channel_count;
- bdma_channel_count += 1;
- }
- "gpdma" => {
- num = gpdma_channel_count;
- gpdma_channel_count += 1;
- }
+ let dma_info = match bi.kind {
+ "dma" => quote!(crate::dma::DmaInfo::Dma(crate::pac::#dma)),
+ "bdma" => quote!(crate::dma::DmaInfo::Bdma(crate::pac::#dma)),
+ "gpdma" => quote!(crate::pac::#dma),
_ => panic!("bad dma channel kind {}", bi.kind),
- }
+ };
- row.push(ch.name.to_string());
- row.push(ch.dma.to_string());
- row.push(bi.kind.to_string());
- row.push(ch.channel.to_string());
- row.push(num.to_string());
- if let Some(dmamux) = &ch.dmamux {
- let dmamux_channel = ch.dmamux_channel.unwrap();
- row.push(format!("{{dmamux: {}, dmamux_channel: {}}}", dmamux, dmamux_channel));
- } else {
- row.push("{}".to_string());
- }
+ let dmamux = match &ch.dmamux {
+ Some(dmamux) => {
+ let dmamux = format_ident!("{}", dmamux);
+ let num = ch.dmamux_channel.unwrap() as usize;
- dma_channels_table.push(row);
+ g.extend(quote!(dmamux_channel_impl!(#name, #dmamux);));
+
+ quote! {
+ dmamux: crate::dma::DmamuxInfo {
+ mux: crate::pac::#dmamux,
+ num: #num,
+ },
+ }
+ }
+ None => quote!(),
+ };
+
+ dmas.extend(quote! {
+ crate::dma::ChannelInfo {
+ dma: #dma_info,
+ num: #ch_num,
+ #dmamux
+ },
+ });
}
+ // ========
+ // Generate DMA IRQs.
+
+ let mut dma_irqs: BTreeMap<&str, Vec<String>> = BTreeMap::new();
+
+ for p in METADATA.peripherals {
+ if let Some(r) = &p.registers {
+ if r.kind == "dma" || r.kind == "bdma" || r.kind == "gpdma" {
+ for irq in p.interrupts {
+ let ch_name = format!("{}_{}", p.name, irq.signal);
+ let ch = METADATA.dma_channels.iter().find(|c| c.name == ch_name).unwrap();
+
+ // Some H7 chips have BDMA1 hardcoded for DFSDM, ie no DMAMUX. It's unsupported, skip it.
+ if has_dmamux && ch.dmamux.is_none() {
+ continue;
+ }
+
+ dma_irqs.entry(irq.interrupt).or_default().push(ch_name);
+ }
+ }
+ }
+ }
+
+ let dma_irqs: TokenStream = dma_irqs
+ .iter()
+ .map(|(irq, channels)| {
+ let irq = format_ident!("{}", irq);
+
+ let channels = channels.iter().map(|c| format_ident!("{}", c));
+
+ quote! {
+ #[cfg(feature = "rt")]
+ #[crate::interrupt]
+ unsafe fn #irq () {
+ #(
+ <crate::peripherals::#channels as crate::dma::sealed::ChannelInterrupt>::on_irq();
+ )*
+ }
+ }
+ })
+ .collect();
+
+ g.extend(dma_irqs);
+
g.extend(quote! {
- pub(crate) const DMA_CHANNEL_COUNT: usize = #dma_channel_count;
- pub(crate) const BDMA_CHANNEL_COUNT: usize = #bdma_channel_count;
- pub(crate) const GPDMA_CHANNEL_COUNT: usize = #gpdma_channel_count;
+ pub(crate) const DMA_CHANNELS: &[crate::dma::ChannelInfo] = &[#dmas];
});
for irq in METADATA.interrupts {
@@ -1347,7 +1359,6 @@ fn main() {
make_table(&mut m, "foreach_interrupt", &interrupts_table);
make_table(&mut m, "foreach_peripheral", &peripherals_table);
make_table(&mut m, "foreach_pin", &pins_table);
- make_table(&mut m, "foreach_dma_channel", &dma_channels_table);
make_table(&mut m, "foreach_adc", &adc_common_table);
let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs
index 4d02284b2..826b04a4b 100644
--- a/embassy-stm32/src/dcmi.rs
+++ b/embassy-stm32/src/dcmi.rs
@@ -394,19 +394,7 @@ where
/// This method starts the capture and finishes when both the dma transfer and DCMI finish the frame transfer.
/// The implication is that the input buffer size must be exactly the size of the captured frame.
- ///
- /// Note that when `buffer.len() > 0xffff` the capture future requires some real-time guarantees to be upheld
- /// (must be polled fast enough so the buffers get switched before data is overwritten).
- /// It is therefore recommended that it is run on higher priority executor.
pub async fn capture(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
- if buffer.len() <= 0xffff {
- return self.capture_small(buffer).await;
- } else {
- return self.capture_giant(buffer).await;
- }
- }
-
- async fn capture_small(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
let r = self.inner.regs();
let src = r.dr().as_ptr() as *mut u32;
let request = self.dma.request();
@@ -441,116 +429,6 @@ where
result
}
-
- #[cfg(not(dma))]
- async fn capture_giant(&mut self, _buffer: &mut [u32]) -> Result<(), Error> {
- panic!("capturing to buffers larger than 0xffff is only supported on DMA for now, not on BDMA or GPDMA.");
- }
-
- #[cfg(dma)]
- async fn capture_giant(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
- use crate::dma::TransferOptions;
-
- let data_len = buffer.len();
- let chunk_estimate = data_len / 0xffff;
-
- let mut chunks = chunk_estimate + 1;
- while data_len % chunks != 0 {
- chunks += 1;
- }
-
- let chunk_size = data_len / chunks;
-
- let mut remaining_chunks = chunks - 2;
-
- let mut m0ar = buffer.as_mut_ptr();
- let mut m1ar = unsafe { buffer.as_mut_ptr().add(chunk_size) };
-
- let channel = &mut self.dma;
- let request = channel.request();
-
- let r = self.inner.regs();
- let src = r.dr().as_ptr() as *mut u32;
-
- let mut transfer = unsafe {
- crate::dma::DoubleBuffered::new_read(
- &mut self.dma,
- request,
- src,
- m0ar,
- m1ar,
- chunk_size,
- TransferOptions::default(),
- )
- };
-
- let mut last_chunk_set_for_transfer = false;
- let mut buffer0_last_accessible = false;
- let dma_result = poll_fn(|cx| {
- transfer.set_waker(cx.waker());
-
- let buffer0_currently_accessible = transfer.is_buffer0_accessible();
-
- // check if the accessible buffer changed since last poll
- if buffer0_last_accessible == buffer0_currently_accessible {
- return Poll::Pending;
- }
- buffer0_last_accessible = !buffer0_last_accessible;
-
- if remaining_chunks != 0 {
- if remaining_chunks % 2 == 0 && buffer0_currently_accessible {
- m0ar = unsafe { m0ar.add(2 * chunk_size) };
- unsafe { transfer.set_buffer0(m0ar) }
- remaining_chunks -= 1;
- } else if !buffer0_currently_accessible {
- m1ar = unsafe { m1ar.add(2 * chunk_size) };
- unsafe { transfer.set_buffer1(m1ar) };
- remaining_chunks -= 1;
- }
- } else {
- if buffer0_currently_accessible {
- unsafe { transfer.set_buffer0(buffer.as_mut_ptr()) }
- } else {
- unsafe { transfer.set_buffer1(buffer.as_mut_ptr()) }
- }
- if last_chunk_set_for_transfer {
- transfer.request_stop();
- return Poll::Ready(());
- }
- last_chunk_set_for_transfer = true;
- }
- Poll::Pending
- });
-
- Self::clear_interrupt_flags();
- Self::enable_irqs();
-
- let result = poll_fn(|cx| {
- STATE.waker.register(cx.waker());
-
- let ris = crate::pac::DCMI.ris().read();
- if ris.err_ris() {
- crate::pac::DCMI.icr().write(|r| r.set_err_isc(true));
- Poll::Ready(Err(Error::PeripheralError))
- } else if ris.ovr_ris() {
- crate::pac::DCMI.icr().write(|r| r.set_ovr_isc(true));
- Poll::Ready(Err(Error::Overrun))
- } else if ris.frame_ris() {
- crate::pac::DCMI.icr().write(|r| r.set_frame_isc(true));
- Poll::Ready(Ok(()))
- } else {
- Poll::Pending
- }
- });
-
- Self::toggle(true);
-
- let (_, result) = embassy_futures::join::join(dma_result, result).await;
-
- Self::toggle(false);
-
- result
- }
}
mod sealed {
diff --git a/embassy-stm32/src/dma/bdma.rs b/embassy-stm32/src/dma/bdma.rs
deleted file mode 100644
index 994bdb1e6..000000000
--- a/embassy-stm32/src/dma/bdma.rs
+++ /dev/null
@@ -1,740 +0,0 @@
-//! Basic Direct Memory Acccess (BDMA)
-
-use core::future::Future;
-use core::pin::Pin;
-use core::sync::atomic::{fence, AtomicUsize, Ordering};
-use core::task::{Context, Poll, Waker};
-
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
-use embassy_sync::waitqueue::AtomicWaker;
-
-use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
-use super::word::{Word, WordSize};
-use super::Dir;
-use crate::_generated::BDMA_CHANNEL_COUNT;
-use crate::interrupt::typelevel::Interrupt;
-use crate::interrupt::Priority;
-use crate::pac;
-use crate::pac::bdma::{regs, vals};
-
-/// BDMA transfer options.
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[non_exhaustive]
-pub struct TransferOptions {
- /// Enable circular DMA
- ///
- /// Note:
- /// If you enable circular mode manually, you may want to build and `.await` the `Transfer` in a separate task.
- /// Since DMA in circular mode need manually stop, `.await` in current task would block the task forever.
- pub circular: bool,
- /// Enable half transfer interrupt
- pub half_transfer_ir: bool,
- /// Enable transfer complete interrupt
- pub complete_transfer_ir: bool,
-}
-
-impl Default for TransferOptions {
- fn default() -> Self {
- Self {
- circular: false,
- half_transfer_ir: false,
- complete_transfer_ir: true,
- }
- }
-}
-
-impl From<WordSize> for vals::Size {
- fn from(raw: WordSize) -> Self {
- match raw {
- WordSize::OneByte => Self::BITS8,
- WordSize::TwoBytes => Self::BITS16,
- WordSize::FourBytes => Self::BITS32,
- }
- }
-}
-
-impl From<Dir> for vals::Dir {
- fn from(raw: Dir) -> Self {
- match raw {
- Dir::MemoryToPeripheral => Self::FROMMEMORY,
- Dir::PeripheralToMemory => Self::FROMPERIPHERAL,
- }
- }
-}
-
-struct State {
- ch_wakers: [AtomicWaker; BDMA_CHANNEL_COUNT],
- complete_count: [AtomicUsize; BDMA_CHANNEL_COUNT],
-}
-
-impl State {
- const fn new() -> Self {
- const ZERO: AtomicUsize = AtomicUsize::new(0);
- const AW: AtomicWaker = AtomicWaker::new();
- Self {
- ch_wakers: [AW; BDMA_CHANNEL_COUNT],
- complete_count: [ZERO; BDMA_CHANNEL_COUNT],
- }
- }
-}
-
-static STATE: State = State::new();
-
-/// safety: must be called only once
-pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: Priority) {
- foreach_interrupt! {
- ($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
- crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
- crate::interrupt::typelevel::$irq::enable();
- };
- }
- crate::_generated::init_bdma();
-}
-
-foreach_dma_channel! {
- ($channel_peri:ident, BDMA1, bdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
- // BDMA1 in H7 doesn't use DMAMUX, which breaks
- };
- ($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
- impl sealed::Channel for crate::peripherals::$channel_peri {
- fn regs(&self) -> pac::bdma::Dma {
- pac::$dma_peri
- }
- fn num(&self) -> usize {
- $channel_num
- }
- fn index(&self) -> usize {
- $index
- }
- fn on_irq() {
- unsafe { on_irq_inner(pac::$dma_peri, $channel_num, $index) }
- }
- }
-
- impl Channel for crate::peripherals::$channel_peri {}
- };
-}
-
-/// Safety: Must be called with a matching set of parameters for a valid dma channel
-pub(crate) unsafe fn on_irq_inner(dma: pac::bdma::Dma, channel_num: usize, index: usize) {
- let isr = dma.isr().read();
- let cr = dma.ch(channel_num).cr();
-
- if isr.teif(channel_num) {
- panic!("DMA: error on BDMA@{:08x} channel {}", dma.as_ptr() as u32, channel_num);
- }
-
- if isr.htif(channel_num) && cr.read().htie() {
- // Acknowledge half transfer complete interrupt
- dma.ifcr().write(|w| w.set_htif(channel_num, true));
- } else if isr.tcif(channel_num) && cr.read().tcie() {
- // Acknowledge transfer complete interrupt
- dma.ifcr().write(|w| w.set_tcif(channel_num, true));
- #[cfg(not(armv6m))]
- STATE.complete_count[index].fetch_add(1, Ordering::Release);
- #[cfg(armv6m)]
- critical_section::with(|_| {
- let x = STATE.complete_count[index].load(Ordering::Relaxed);
- STATE.complete_count[index].store(x + 1, Ordering::Release);
- })
- } else {
- return;
- }
-
- STATE.ch_wakers[index].wake();
-}
-
-/// DMA request type alias.
-#[cfg(any(bdma_v2, dmamux))]
-pub type Request = u8;
-/// DMA request type alias.
-#[cfg(not(any(bdma_v2, dmamux)))]
-pub type Request = ();
-
-/// DMA channel.
-#[cfg(dmamux)]
-pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
-/// DMA channel.
-#[cfg(not(dmamux))]
-pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
-
-pub(crate) mod sealed {
- use super::*;
-
- pub trait Channel {
- fn regs(&self) -> pac::bdma::Dma;
- fn num(&self) -> usize;
- fn index(&self) -> usize;
- fn on_irq();
- }
-}
-
-/// DMA transfer.
-#[must_use = "futures do nothing unless you `.await` or poll them"]
-pub struct Transfer<'a, C: Channel> {
- channel: PeripheralRef<'a, C>,
-}
-
-impl<'a, C: Channel> Transfer<'a, C> {
- /// Create a new read DMA transfer (peripheral to memory).
- pub unsafe fn new_read<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- peri_addr: *mut W,
- buf: &'a mut [W],
- options: TransferOptions,
- ) -> Self {
- Self::new_read_raw(channel, request, peri_addr, buf, options)
- }
-
- /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
- pub unsafe fn new_read_raw<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- peri_addr: *mut W,
- buf: *mut [W],
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let (ptr, len) = super::slice_ptr_parts_mut(buf);
- assert!(len > 0 && len <= 0xFFFF);
-
- Self::new_inner(
- channel,
- request,
- Dir::PeripheralToMemory,
- peri_addr as *const u32,
- ptr as *mut u32,
- len,
- true,
- W::size(),
- options,
- )
- }
-
- /// Create a new write DMA transfer (memory to peripheral).
- pub unsafe fn new_write<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- buf: &'a [W],
- peri_addr: *mut W,
- options: TransferOptions,
- ) -> Self {
- Self::new_write_raw(channel, request, buf, peri_addr, options)
- }
-
- /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
- pub unsafe fn new_write_raw<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- buf: *const [W],
- peri_addr: *mut W,
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let (ptr, len) = super::slice_ptr_parts(buf);
- assert!(len > 0 && len <= 0xFFFF);
-
- Self::new_inner(
- channel,
- request,
- Dir::MemoryToPeripheral,
- peri_addr as *const u32,
- ptr as *mut u32,
- len,
- true,
- W::size(),
- options,
- )
- }
-
- /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
- pub unsafe fn new_write_repeated<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- repeated: &'a W,
- count: usize,
- peri_addr: *mut W,
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- Self::new_inner(
- channel,
- request,
- Dir::MemoryToPeripheral,
- peri_addr as *const u32,
- repeated as *const W as *mut u32,
- count,
- false,
- W::size(),
- options,
- )
- }
-
- unsafe fn new_inner(
- channel: PeripheralRef<'a, C>,
- _request: Request,
- dir: Dir,
- peri_addr: *const u32,
- mem_addr: *mut u32,
- mem_len: usize,
- incr_mem: bool,
- data_size: WordSize,
- options: TransferOptions,
- ) -> Self {
- let ch = channel.regs().ch(channel.num());
-
- // "Preceding reads and writes cannot be moved past subsequent writes."
- fence(Ordering::SeqCst);
-
- #[cfg(bdma_v2)]
- critical_section::with(|_| channel.regs().cselr().modify(|w| w.set_cs(channel.num(), _request)));
-
- let mut this = Self { channel };
- this.clear_irqs();
- STATE.complete_count[this.channel.index()].store(0, Ordering::Release);
-
- #[cfg(dmamux)]
- super::dmamux::configure_dmamux(&*this.channel, _request);
-
- ch.par().write_value(peri_addr as u32);
- ch.mar().write_value(mem_addr as u32);
- ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
- ch.cr().write(|w| {
- w.set_psize(data_size.into());
- w.set_msize(data_size.into());
- w.set_minc(incr_mem);
- w.set_dir(dir.into());
- w.set_teie(true);
- w.set_tcie(options.complete_transfer_ir);
- w.set_htie(options.half_transfer_ir);
- w.set_circ(options.circular);
- if options.circular {
- debug!("Setting circular mode");
- }
- w.set_pl(vals::Pl::VERYHIGH);
- w.set_en(true);
- });
-
- this
- }
-
- fn clear_irqs(&mut self) {
- self.channel.regs().ifcr().write(|w| {
- w.set_tcif(self.channel.num(), true);
- w.set_teif(self.channel.num(), true);
- });
- }
-
- /// Request the transfer to stop.
- ///
- /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
- pub fn request_stop(&mut self) {
- let ch = self.channel.regs().ch(self.channel.num());
-
- // Disable the channel. Keep the IEs enabled so the irqs still fire.
- ch.cr().write(|w| {
- w.set_teie(true);
- w.set_tcie(true);
- });
- }
-
- /// Return whether this transfer is still running.
- ///
- /// If this returns `false`, it can be because either the transfer finished, or
- /// it was requested to stop early with [`request_stop`](Self::request_stop).
- pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().ch(self.channel.num());
- let en = ch.cr().read().en();
- let circular = ch.cr().read().circ();
- let tcif = STATE.complete_count[self.channel.index()].load(Ordering::Acquire) != 0;
- en && (circular || !tcif)
- }
-
- /// Get the total remaining transfers for the channel.
- ///
- /// This will be zero for transfers that completed instead of being canceled with [`request_stop`](Self::request_stop).
- pub fn get_remaining_transfers(&self) -> u16 {
- let ch = self.channel.regs().ch(self.channel.num());
- ch.ndtr().read().ndt()
- }
-
- /// Blocking wait until the transfer finishes.
- pub fn blocking_wait(mut self) {
- while self.is_running() {}
- self.request_stop();
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
-
- core::mem::forget(self);
- }
-}
-
-impl<'a, C: Channel> Drop for Transfer<'a, C> {
- fn drop(&mut self) {
- self.request_stop();
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
- }
-}
-
-impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
-impl<'a, C: Channel> Future for Transfer<'a, C> {
- type Output = ();
- fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
- STATE.ch_wakers[self.channel.index()].register(cx.waker());
-
- if self.is_running() {
- Poll::Pending
- } else {
- Poll::Ready(())
- }
- }
-}
-
-// ==============================
-
-struct DmaCtrlImpl<'a, C: Channel>(PeripheralRef<'a, C>);
-
-impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
- fn get_remaining_transfers(&self) -> usize {
- let ch = self.0.regs().ch(self.0.num());
- ch.ndtr().read().ndt() as usize
- }
-
- fn get_complete_count(&self) -> usize {
- STATE.complete_count[self.0.index()].load(Ordering::Acquire)
- }
-
- fn reset_complete_count(&mut self) -> usize {
- #[cfg(not(armv6m))]
- return STATE.complete_count[self.0.index()].swap(0, Ordering::AcqRel);
- #[cfg(armv6m)]
- return critical_section::with(|_| {
- let x = STATE.complete_count[self.0.index()].load(Ordering::Acquire);
- STATE.complete_count[self.0.index()].store(0, Ordering::Release);
- x
- });
- }
-
- fn set_waker(&mut self, waker: &Waker) {
- STATE.ch_wakers[self.0.index()].register(waker);
- }
-}
-
-/// Ringbuffer for reading data using DMA circular mode.
-pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
- cr: regs::Cr,
- channel: PeripheralRef<'a, C>,
- ringbuf: ReadableDmaRingBuffer<'a, W>,
-}
-
-impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
- /// Create a new ring buffer.
- pub unsafe fn new(
- channel: impl Peripheral<P = C> + 'a,
- _request: Request,
- peri_addr: *mut W,
- buffer: &'a mut [W],
- _options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let len = buffer.len();
- assert!(len > 0 && len <= 0xFFFF);
-
- let dir = Dir::PeripheralToMemory;
- let data_size = W::size();
-
- let channel_number = channel.num();
- let dma = channel.regs();
-
- // "Preceding reads and writes cannot be moved past subsequent writes."
- fence(Ordering::SeqCst);
-
- #[cfg(bdma_v2)]
- critical_section::with(|_| channel.regs().cselr().modify(|w| w.set_cs(channel.num(), _request)));
-
- let mut w = regs::Cr(0);
- w.set_psize(data_size.into());
- w.set_msize(data_size.into());
- w.set_minc(true);
- w.set_dir(dir.into());
- w.set_teie(true);
- w.set_htie(true);
- w.set_tcie(true);
- w.set_circ(true);
- w.set_pl(vals::Pl::VERYHIGH);
- w.set_en(true);
-
- let buffer_ptr = buffer.as_mut_ptr();
- let mut this = Self {
- channel,
- cr: w,
- ringbuf: ReadableDmaRingBuffer::new(buffer),
- };
- this.clear_irqs();
-
- #[cfg(dmamux)]
- super::dmamux::configure_dmamux(&*this.channel, _request);
-
- let ch = dma.ch(channel_number);
- ch.par().write_value(peri_addr as u32);
- ch.mar().write_value(buffer_ptr as u32);
- ch.ndtr().write(|w| w.set_ndt(len as u16));
-
- this
- }
-
- /// Start the ring buffer operation.
- ///
- /// You must call this after creating it for it to work.
- pub fn start(&mut self) {
- let ch = self.channel.regs().ch(self.channel.num());
- ch.cr().write_value(self.cr)
- }
-
- /// Clear all data in the ring buffer.
- pub fn clear(&mut self) {
- self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
- }
-
- /// Read elements from the ring buffer
- /// Return a tuple of the length read and the length remaining in the buffer
- /// If not all of the elements were read, then there will be some elements in the buffer remaining
- /// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
- /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
- pub fn read(&mut self, buf: &mut [W]) -> Result<(usize, usize), OverrunError> {
- self.ringbuf.read(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
- }
-
- /// Read an exact number of elements from the ringbuffer.
- ///
- /// Returns the remaining number of elements available for immediate reading.
- /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
- ///
- /// Async/Wake Behavior:
- /// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
- /// and when it wraps around. This means that when called with a buffer of length 'M', when this
- /// ring buffer was created with a buffer of size 'N':
- /// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
- /// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
- pub async fn read_exact(&mut self, buffer: &mut [W]) -> Result<usize, OverrunError> {
- self.ringbuf
- .read_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
- .await
- }
-
- /// The capacity of the ringbuffer.
- pub const fn capacity(&self) -> usize {
- self.ringbuf.cap()
- }
-
- /// Set a waker to be woken when at least one byte is received.
- pub fn set_waker(&mut self, waker: &Waker) {
- DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
- }
-
- fn clear_irqs(&mut self) {
- let dma = self.channel.regs();
- dma.ifcr().write(|w| {
- w.set_htif(self.channel.num(), true);
- w.set_tcif(self.channel.num(), true);
- w.set_teif(self.channel.num(), true);
- });
- }
-
- /// Request DMA to stop.
- ///
- /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
- pub fn request_stop(&mut self) {
- let ch = self.channel.regs().ch(self.channel.num());
-
- // Disable the channel. Keep the IEs enabled so the irqs still fire.
- // If the channel is enabled and transfer is not completed, we need to perform
- // two separate write access to the CR register to disable the channel.
- ch.cr().write(|w| {
- w.set_teie(true);
- w.set_htie(true);
- w.set_tcie(true);
- });
- }
-
- /// Return whether DMA is still running.
- ///
- /// If this returns `false`, it can be because either the transfer finished, or
- /// it was requested to stop early with [`request_stop`](Self::request_stop).
- pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().ch(self.channel.num());
- ch.cr().read().en()
- }
-}
-
-impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
- fn drop(&mut self) {
- self.request_stop();
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
- }
-}
-
-/// Ringbuffer for writing data using DMA circular mode.
-pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
- cr: regs::Cr,
- channel: PeripheralRef<'a, C>,
- ringbuf: WritableDmaRingBuffer<'a, W>,
-}
-
-impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
- /// Create a new ring buffer.
- pub unsafe fn new(
- channel: impl Peripheral<P = C> + 'a,
- _request: Request,
- peri_addr: *mut W,
- buffer: &'a mut [W],
- _options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let len = buffer.len();
- assert!(len > 0 && len <= 0xFFFF);
-
- let dir = Dir::MemoryToPeripheral;
- let data_size = W::size();
-
- let channel_number = channel.num();
- let dma = channel.regs();
-
- // "Preceding reads and writes cannot be moved past subsequent writes."
- fence(Ordering::SeqCst);
-
- #[cfg(bdma_v2)]
- critical_section::with(|_| channel.regs().cselr().modify(|w| w.set_cs(channel.num(), _request)));
-
- let mut w = regs::Cr(0);
- w.set_psize(data_size.into());
- w.set_msize(data_size.into());
- w.set_minc(true);
- w.set_dir(dir.into());
- w.set_teie(true);
- w.set_htie(true);
- w.set_tcie(true);
- w.set_circ(true);
- w.set_pl(vals::Pl::VERYHIGH);
- w.set_en(true);
-
- let buffer_ptr = buffer.as_mut_ptr();
- let mut this = Self {
- channel,
- cr: w,
- ringbuf: WritableDmaRingBuffer::new(buffer),
- };
- this.clear_irqs();
-
- #[cfg(dmamux)]
- super::dmamux::configure_dmamux(&*this.channel, _request);
-
- let ch = dma.ch(channel_number);
- ch.par().write_value(peri_addr as u32);
- ch.mar().write_value(buffer_ptr as u32);
- ch.ndtr().write(|w| w.set_ndt(len as u16));
-
- this
- }
-
- /// Start the ring buffer operation.
- ///
- /// You must call this after creating it for it to work.
- pub fn start(&mut self) {
- let ch = self.channel.regs().ch(self.channel.num());
- ch.cr().write_value(self.cr)
- }
-
- /// Clear all data in the ring buffer.
- pub fn clear(&mut self) {
- self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
- }
-
- /// Write elements directly to the raw buffer.
- /// This can be used to fill the buffer before starting the DMA transfer.
- #[allow(dead_code)]
- pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
- self.ringbuf.write_immediate(buf)
- }
-
- /// Write elements to the ring buffer
- /// Return a tuple of the length written and the length remaining in the buffer
- pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
- self.ringbuf.write(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
- }
-
- /// Write an exact number of elements to the ringbuffer.
- pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
- self.ringbuf
- .write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
- .await
- }
-
- /// The capacity of the ringbuffer.
- pub const fn capacity(&self) -> usize {
- self.ringbuf.cap()
- }
-
- /// Set a waker to be woken when at least one byte is sent.
- pub fn set_waker(&mut self, waker: &Waker) {
- DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
- }
-
- fn clear_irqs(&mut self) {
- let dma = self.channel.regs();
- dma.ifcr().write(|w| {
- w.set_htif(self.channel.num(), true);
- w.set_tcif(self.channel.num(), true);
- w.set_teif(self.channel.num(), true);
- });
- }
-
- /// Request DMA to stop.
- ///
- /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
- pub fn request_stop(&mut self) {
- let ch = self.channel.regs().ch(self.channel.num());
-
- // Disable the channel. Keep the IEs enabled so the irqs still fire.
- // If the channel is enabled and transfer is not completed, we need to perform
- // two separate write access to the CR register to disable the channel.
- ch.cr().write(|w| {
- w.set_teie(true);
- w.set_htie(true);
- w.set_tcie(true);
- });
- }
-
- /// Return whether DMA is still running.
- ///
- /// If this returns `false`, it can be because either the transfer finished, or
- /// it was requested to stop early with [`request_stop`](Self::request_stop).
- pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().ch(self.channel.num());
- ch.cr().read().en()
- }
-}
-
-impl<'a, C: Channel, W: Word> Drop for WritableRingBuffer<'a, C, W> {
- fn drop(&mut self) {
- self.request_stop();
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
- }
-}
diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs
deleted file mode 100644
index e762b1bde..000000000
--- a/embassy-stm32/src/dma/dma.rs
+++ /dev/null
@@ -1,1012 +0,0 @@
-use core::future::Future;
-use core::marker::PhantomData;
-use core::pin::Pin;
-use core::sync::atomic::{fence, AtomicUsize, Ordering};
-use core::task::{Context, Poll, Waker};
-
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
-use embassy_sync::waitqueue::AtomicWaker;
-
-use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
-use super::word::{Word, WordSize};
-use super::Dir;
-use crate::_generated::DMA_CHANNEL_COUNT;
-use crate::interrupt::typelevel::Interrupt;
-use crate::interrupt::Priority;
-use crate::pac::dma::{regs, vals};
-use crate::{interrupt, pac};
-
-/// DMA transfer options.
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[non_exhaustive]
-pub struct TransferOptions {
- /// Peripheral burst transfer configuration
- pub pburst: Burst,
- /// Memory burst transfer configuration
- pub mburst: Burst,
- /// Flow control configuration
- pub flow_ctrl: FlowControl,
- /// FIFO threshold for DMA FIFO mode. If none, direct mode is used.
- pub fifo_threshold: Option<FifoThreshold>,
- /// Enable circular DMA
- ///
- /// Note:
- /// If you enable circular mode manually, you may want to build and `.await` the `Transfer` in a separate task.
- /// Since DMA in circular mode need manually stop, `.await` in current task would block the task forever.
- pub circular: bool,
- /// Enable half transfer interrupt
- pub half_transfer_ir: bool,
- /// Enable transfer complete interrupt
- pub complete_transfer_ir: bool,
-}
-
-impl Default for TransferOptions {
- fn default() -> Self {
- Self {
- pburst: Burst::Single,
- mburst: Burst::Single,
- flow_ctrl: FlowControl::Dma,
- fifo_threshold: None,
- circular: false,
- half_transfer_ir: false,
- complete_transfer_ir: true,
- }
- }
-}
-
-impl From<WordSize> for vals::Size {
- fn from(raw: WordSize) -> Self {
- match raw {
- WordSize::OneByte => Self::BITS8,
- WordSize::TwoBytes => Self::BITS16,
- WordSize::FourBytes => Self::BITS32,
- }
- }
-}
-
-impl From<Dir> for vals::Dir {
- fn from(raw: Dir) -> Self {
- match raw {
- Dir::MemoryToPeripheral => Self::MEMORYTOPERIPHERAL,
- Dir::PeripheralToMemory => Self::PERIPHERALTOMEMORY,
- }
- }
-}
-
-/// DMA transfer burst setting.
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Burst {
- /// Single transfer
- Single,
- /// Incremental burst of 4 beats
- Incr4,
- /// Incremental burst of 8 beats
- Incr8,
- /// Incremental burst of 16 beats
- Incr16,
-}
-
-impl From<Burst> for vals::Burst {
- fn from(burst: Burst) -> Self {
- match burst {
- Burst::Single => vals::Burst::SINGLE,
- Burst::Incr4 => vals::Burst::INCR4,
- Burst::Incr8 => vals::Burst::INCR8,
- Burst::Incr16 => vals::Burst::INCR16,
- }
- }
-}
-
-/// DMA flow control setting.
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum FlowControl {
- /// Flow control by DMA
- Dma,
- /// Flow control by peripheral
- Peripheral,
-}
-
-impl From<FlowControl> for vals::Pfctrl {
- fn from(flow: FlowControl) -> Self {
- match flow {
- FlowControl::Dma => vals::Pfctrl::DMA,
- FlowControl::Peripheral => vals::Pfctrl::PERIPHERAL,
- }
- }
-}
-
-/// DMA FIFO threshold.
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum FifoThreshold {
- /// 1/4 full FIFO
- Quarter,
- /// 1/2 full FIFO
- Half,
- /// 3/4 full FIFO
- ThreeQuarters,
- /// Full FIFO
- Full,
-}
-
-impl From<FifoThreshold> for vals::Fth {
- fn from(value: FifoThreshold) -> Self {
- match value {
- FifoThreshold::Quarter => vals::Fth::QUARTER,
- FifoThreshold::Half => vals::Fth::HALF,
- FifoThreshold::ThreeQuarters => vals::Fth::THREEQUARTERS,
- FifoThreshold::Full => vals::Fth::FULL,
- }
- }
-}
-
-struct State {
- ch_wakers: [AtomicWaker; DMA_CHANNEL_COUNT],
- complete_count: [AtomicUsize; DMA_CHANNEL_COUNT],
-}
-
-impl State {
- const fn new() -> Self {
- const ZERO: AtomicUsize = AtomicUsize::new(0);
- const AW: AtomicWaker = AtomicWaker::new();
- Self {
- ch_wakers: [AW; DMA_CHANNEL_COUNT],
- complete_count: [ZERO; DMA_CHANNEL_COUNT],
- }
- }
-}
-
-static STATE: State = State::new();
-
-/// safety: must be called only once
-pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: Priority) {
- foreach_interrupt! {
- ($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
- interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
- interrupt::typelevel::$irq::enable();
- };
- }
- crate::_generated::init_dma();
-}
-
-foreach_dma_channel! {
- ($channel_peri:ident, $dma_peri:ident, dma, $channel_num:expr, $index:expr, $dmamux:tt) => {
- impl sealed::Channel for crate::peripherals::$channel_peri {
- fn regs(&self) -> pac::dma::Dma {
- pac::$dma_peri
- }
- fn num(&self) -> usize {
- $channel_num
- }
- fn index(&self) -> usize {
- $index
- }
- fn on_irq() {
- unsafe { on_irq_inner(pac::$dma_peri, $channel_num, $index) }
- }
- }
-
- impl Channel for crate::peripherals::$channel_peri {}
- };
-}
-
-/// Safety: Must be called with a matching set of parameters for a valid dma channel
-pub(crate) unsafe fn on_irq_inner(dma: pac::dma::Dma, channel_num: usize, index: usize) {
- let cr = dma.st(channel_num).cr();
- let isr = dma.isr(channel_num / 4).read();
-
- if isr.teif(channel_num % 4) {
- panic!("DMA: error on DMA@{:08x} channel {}", dma.as_ptr() as u32, channel_num);
- }
-
- if isr.htif(channel_num % 4) && cr.read().htie() {
- // Acknowledge half transfer complete interrupt
- dma.ifcr(channel_num / 4).write(|w| w.set_htif(channel_num % 4, true));
- } else if isr.tcif(channel_num % 4) && cr.read().tcie() {
- // Acknowledge transfer complete interrupt
- dma.ifcr(channel_num / 4).write(|w| w.set_tcif(channel_num % 4, true));
- STATE.complete_count[index].fetch_add(1, Ordering::Release);
- } else {
- return;
- }
-
- STATE.ch_wakers[index].wake();
-}
-
-/// DMA request type alias. (also known as DMA channel number in some chips)
-#[cfg(any(dma_v2, dmamux))]
-pub type Request = u8;
-/// DMA request type alias. (also known as DMA channel number in some chips)
-#[cfg(not(any(dma_v2, dmamux)))]
-pub type Request = ();
-
-/// DMA channel.
-#[cfg(dmamux)]
-pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
-/// DMA channel.
-#[cfg(not(dmamux))]
-pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
-
-pub(crate) mod sealed {
- use super::*;
-
- pub trait Channel {
- fn regs(&self) -> pac::dma::Dma;
- fn num(&self) -> usize;
- fn index(&self) -> usize;
- fn on_irq();
- }
-}
-
-/// DMA transfer.
-#[must_use = "futures do nothing unless you `.await` or poll them"]
-pub struct Transfer<'a, C: Channel> {
- channel: PeripheralRef<'a, C>,
-}
-
-impl<'a, C: Channel> Transfer<'a, C> {
- /// Create a new read DMA transfer (peripheral to memory).
- pub unsafe fn new_read<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- peri_addr: *mut W,
- buf: &'a mut [W],
- options: TransferOptions,
- ) -> Self {
- Self::new_read_raw(channel, request, peri_addr, buf, options)
- }
-
- /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
- pub unsafe fn new_read_raw<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- peri_addr: *mut W,
- buf: *mut [W],
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let (ptr, len) = super::slice_ptr_parts_mut(buf);
- assert!(len > 0 && len <= 0xFFFF);
-
- Self::new_inner(
- channel,
- request,
- Dir::PeripheralToMemory,
- peri_addr as *const u32,
- ptr as *mut u32,
- len,
- true,
- W::size(),
- options,
- )
- }
-
- /// Create a new write DMA transfer (memory to peripheral).
- pub unsafe fn new_write<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- buf: &'a [W],
- peri_addr: *mut W,
- options: TransferOptions,
- ) -> Self {
- Self::new_write_raw(channel, request, buf, peri_addr, options)
- }
-
- /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
- pub unsafe fn new_write_raw<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- buf: *const [W],
- peri_addr: *mut W,
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let (ptr, len) = super::slice_ptr_parts(buf);
- assert!(len > 0 && len <= 0xFFFF);
-
- Self::new_inner(
- channel,
- request,
- Dir::MemoryToPeripheral,
- peri_addr as *const u32,
- ptr as *mut u32,
- len,
- true,
- W::size(),
- options,
- )
- }
-
- /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
- pub unsafe fn new_write_repeated<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
- request: Request,
- repeated: &'a W,
- count: usize,
- peri_addr: *mut W,
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- Self::new_inner(
- channel,
- request,
- Dir::MemoryToPeripheral,
- peri_addr as *const u32,
- repeated as *const W as *mut u32,
- count,
- false,
- W::size(),
- options,
- )
- }
-
- unsafe fn new_inner(
- channel: PeripheralRef<'a, C>,
- _request: Request,
- dir: Dir,
- peri_addr: *const u32,
- mem_addr: *mut u32,
- mem_len: usize,
- incr_mem: bool,
- data_size: WordSize,
- options: TransferOptions,
- ) -> Self {
- let ch = channel.regs().st(channel.num());
-
- // "Preceding reads and writes cannot be moved past subsequent writes."
- fence(Ordering::SeqCst);
-
- let mut this = Self { channel };
- this.clear_irqs();
-
- #[cfg(dmamux)]
- super::dmamux::configure_dmamux(&*this.channel, _request);
-
- ch.par().write_value(peri_addr as u32);
- ch.m0ar().write_value(mem_addr as u32);
- ch.ndtr().write_value(regs::Ndtr(mem_len as _));
- ch.fcr().write(|w| {
- if let Some(fth) = options.fifo_threshold {
- // FIFO mode
- w.set_dmdis(vals::Dmdis::DISABLED);
- w.set_fth(fth.into());
- } else {
- // Direct mode
- w.set_dmdis(vals::Dmdis::ENABLED);
- }
- });
- ch.cr().write(|w| {
- w.set_dir(dir.into());
- w.set_msize(data_size.into());
- w.set_psize(data_size.into());
- w.set_pl(vals::Pl::VERYHIGH);
- w.set_minc(incr_mem);
- w.set_pinc(false);
- w.set_teie(true);
- w.set_tcie(options.complete_transfer_ir);
- w.set_circ(options.circular);
- if options.circular {
- debug!("Setting circular mode");
- }
- #[cfg(dma_v1)]
- w.set_trbuff(true);
-
- #[cfg(dma_v2)]
- w.set_chsel(_request);
-
- w.set_pburst(options.pburst.into());
- w.set_mburst(options.mburst.into());
- w.set_pfctrl(options.flow_ctrl.into());
-
- w.set_en(true);
- });
-
- this
- }
-
- fn clear_irqs(&mut self) {
- let isrn = self.channel.num() / 4;
- let isrbit = self.channel.num() % 4;
-
- self.channel.regs().ifcr(isrn).write(|w| {
- w.set_tcif(isrbit, true);
- w.set_teif(isrbit, true);
- });
- }
-
- /// Request the transfer to stop.
- ///
- /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
- pub fn request_stop(&mut self) {
- let ch = self.channel.regs().st(self.channel.num());
-
- // Disable the channel. Keep the IEs enabled so the irqs still fire.
- ch.cr().write(|w| {
- w.set_teie(true);
- w.set_tcie(true);
- });
- }
-
- /// Return whether this transfer is still running.
- ///
- /// If this returns `false`, it can be because either the transfer finished, or
- /// it was requested to stop early with [`request_stop`](Self::request_stop).
- pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().st(self.channel.num());
- ch.cr().read().en()
- }
-
- /// Gets the total remaining transfers for the channel
- /// Note: this will be zero for transfers that completed without cancellation.
- pub fn get_remaining_transfers(&self) -> u16 {
- let ch = self.channel.regs().st(self.channel.num());
- ch.ndtr().read().ndt()
- }
-
- /// Blocking wait until the transfer finishes.
- pub fn blocking_wait(mut self) {
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
-
- core::mem::forget(self);
- }
-}
-
-impl<'a, C: Channel> Drop for Transfer<'a, C> {
- fn drop(&mut self) {
- self.request_stop();
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
- }
-}
-
-impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
-impl<'a, C: Channel> Future for Transfer<'a, C> {
- type Output = ();
- fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
- STATE.ch_wakers[self.channel.index()].register(cx.waker());
-
- if self.is_running() {
- Poll::Pending
- } else {
- Poll::Ready(())
- }
- }
-}
-
-// ==================================
-
-/// Double-buffered DMA transfer.
-pub struct DoubleBuffered<'a, C: Channel, W: Word> {
- channel: PeripheralRef<'a, C>,
- _phantom: PhantomData<W>,
-}
-
-impl<'a, C: Channel, W: Word> DoubleBuffered<'a, C, W> {
- /// Create a new read DMA transfer (peripheral to memory).
- pub unsafe fn new_read(
- channel: impl Peripheral<P = C> + 'a,
- _request: Request,
- peri_addr: *mut W,
- buf0: *mut W,
- buf1: *mut W,
- len: usize,
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
- assert!(len > 0 && len <= 0xFFFF);
-
- let dir = Dir::PeripheralToMemory;
- let data_size = W::size();
-
- let channel_number = channel.num();
- let dma = channel.regs();
-
- // "Preceding reads and writes cannot be moved past subsequent writes."
- fence(Ordering::SeqCst);
-
- let mut this = Self {
- channel,
- _phantom: PhantomData,
- };
- this.clear_irqs();
-
- #[cfg(dmamux)]
- super::dmamux::configure_dmamux(&*this.channel, _request);
-
- let ch = dma.st(channel_number);
- ch.par().write_value(peri_addr as u32);
- ch.m0ar().write_value(buf0 as u32);
- ch.m1ar().write_value(buf1 as u32);
- ch.ndtr().write_value(regs::Ndtr(len as _));
- ch.fcr().write(|w| {
- if let Some(fth) = options.fifo_threshold {
- // FIFO mode
- w.set_dmdis(vals::Dmdis::DISABLED);
- w.set_fth(fth.into());
- } else {
- // Direct mode
- w.set_dmdis(vals::Dmdis::ENABLED);
- }
- });
- ch.cr().write(|w| {
- w.set_dir(dir.into());
- w.set_msize(data_size.into());
- w.set_psize(data_size.into());
- w.set_pl(vals::Pl::VERYHIGH);
- w.set_minc(true);
- w.set_pinc(false);
- w.set_teie(true);
- w.set_tcie(true);
- #[cfg(dma_v1)]
- w.set_trbuff(true);
-
- #[cfg(dma_v2)]
- w.set_chsel(_request);
-
- w.set_pburst(options.pburst.into());
- w.set_mburst(options.mburst.into());
- w.set_pfctrl(options.flow_ctrl.into());
-
- w.set_en(true);
- });
-
- this
- }
-
- fn clear_irqs(&mut self) {
- let channel_number = self.channel.num();
- let dma = self.channel.regs();
- let isrn = channel_number / 4;
- let isrbit = channel_number % 4;
-
- dma.ifcr(isrn).write(|w| {
- w.set_htif(isrbit, true);
- w.set_tcif(isrbit, true);
- w.set_teif(isrbit, true);
- });
- }
-
- /// Set the first buffer address.
- ///
- /// You may call this while DMA is transferring the other buffer.
- pub unsafe fn set_buffer0(&mut self, buffer: *mut W) {
- let ch = self.channel.regs().st(self.channel.num());
- ch.m0ar().write_value(buffer as _);
- }
-
- /// Set the second buffer address.
- ///
- /// You may call this while DMA is transferring the other buffer.
- pub unsafe fn set_buffer1(&mut self, buffer: *mut W) {
- let ch = self.channel.regs().st(self.channel.num());
- ch.m1ar().write_value(buffer as _);
- }
-
- /// Returh whether buffer0 is accessible (i.e. whether DMA is transferring buffer1 now)
- pub fn is_buffer0_accessible(&mut self) -> bool {
- let ch = self.channel.regs().st(self.channel.num());
- ch.cr().read().ct() == vals::Ct::MEMORY1
- }
-
- /// Set a waker to be woken when one of the buffers is being transferred.
- pub fn set_waker(&mut self, waker: &Waker) {
- STATE.ch_wakers[self.channel.index()].register(waker);
- }
-
- /// Request the transfer to stop.
- ///
- /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
- pub fn request_stop(&mut self) {
- let ch = self.channel.regs().st(self.channel.num());
-
- // Disable the channel. Keep the IEs enabled so the irqs still fire.
- ch.cr().write(|w| {
- w.set_teie(true);
- w.set_tcie(true);
- });
- }
-
- /// Return whether this transfer is still running.
- ///
- /// If this returns `false`, it can be because either the transfer finished, or
- /// it was requested to stop early with [`request_stop`](Self::request_stop).
- pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().st(self.channel.num());
- ch.cr().read().en()
- }
-
- /// Gets the total remaining transfers for the channel
- /// Note: this will be zero for transfers that completed without cancellation.
- pub fn get_remaining_transfers(&self) -> u16 {
- let ch = self.channel.regs().st(self.channel.num());
- ch.ndtr().read().ndt()
- }
-}
-
-impl<'a, C: Channel, W: Word> Drop for DoubleBuffered<'a, C, W> {
- fn drop(&mut self) {
- self.request_stop();
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
- }
-}
-
-// ==============================
-
-struct DmaCtrlImpl<'a, C: Channel>(PeripheralRef<'a, C>);
-
-impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
- fn get_remaining_transfers(&self) -> usize {
- let ch = self.0.regs().st(self.0.num());
- ch.ndtr().read().ndt() as usize
- }
-
- fn get_complete_count(&self) -> usize {
- STATE.complete_count[self.0.index()].load(Ordering::Acquire)
- }
-
- fn reset_complete_count(&mut self) -> usize {
- STATE.complete_count[self.0.index()].swap(0, Ordering::AcqRel)
- }
-
- fn set_waker(&mut self, waker: &Waker) {
- STATE.ch_wakers[self.0.index()].register(waker);
- }
-}
-
-/// Ringbuffer for receiving data using DMA circular mode.
-pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
- cr: regs::Cr,
- channel: PeripheralRef<'a, C>,
- ringbuf: ReadableDmaRingBuffer<'a, W>,
-}
-
-impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
- /// Create a new ring buffer.
- pub unsafe fn new(
- channel: impl Peripheral<P = C> + 'a,
- _request: Request,
- peri_addr: *mut W,
- buffer: &'a mut [W],
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let len = buffer.len();
- assert!(len > 0 && len <= 0xFFFF);
-
- let dir = Dir::PeripheralToMemory;
- let data_size = W::size();
-
- let channel_number = channel.num();
- let dma = channel.regs();
-
- // "Preceding reads and writes cannot be moved past subsequent writes."
- fence(Ordering::SeqCst);
-
- let mut w = regs::Cr(0);
- w.set_dir(dir.into());
- w.set_msize(data_size.into());
- w.set_psize(data_size.into());
- w.set_pl(vals::Pl::VERYHIGH);
- w.set_minc(true);
- w.set_pinc(false);
- w.set_teie(true);
- w.set_htie(options.half_transfer_ir);
- w.set_tcie(true);
- w.set_circ(true);
- #[cfg(dma_v1)]
- w.set_trbuff(true);
- #[cfg(dma_v2)]
- w.set_chsel(_request);
- w.set_pburst(options.pburst.into());
- w.set_mburst(options.mburst.into());
- w.set_pfctrl(options.flow_ctrl.into());
- w.set_en(true);
-
- let buffer_ptr = buffer.as_mut_ptr();
- let mut this = Self {
- channel,
- cr: w,
- ringbuf: ReadableDmaRingBuffer::new(buffer),
- };
- this.clear_irqs();
-
- #[cfg(dmamux)]
- super::dmamux::configure_dmamux(&*this.channel, _request);
-
- let ch = dma.st(channel_number);
- ch.par().write_value(peri_addr as u32);
- ch.m0ar().write_value(buffer_ptr as u32);
- ch.ndtr().write_value(regs::Ndtr(len as _));
- ch.fcr().write(|w| {
- if let Some(fth) = options.fifo_threshold {
- // FIFO mode
- w.set_dmdis(vals::Dmdis::DISABLED);
- w.set_fth(fth.into());
- } else {
- // Direct mode
- w.set_dmdis(vals::Dmdis::ENABLED);
- }
- });
-
- this
- }
-
- /// Start the ring buffer operation.
- ///
- /// You must call this after creating it for it to work.
- pub fn start(&mut self) {
- let ch = self.channel.regs().st(self.channel.num());
- ch.cr().write_value(self.cr);
- }
-
- /// Clear all data in the ring buffer.
- pub fn clear(&mut self) {
- self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
- }
-
- /// Read elements from the ring buffer
- /// Return a tuple of the length read and the length remaining in the buffer
- /// If not all of the elements were read, then there will be some elements in the buffer remaining
- /// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
- /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
- pub fn read(&mut self, buf: &mut [W]) -> Result<(usize, usize), OverrunError> {
- self.ringbuf.read(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
- }
-
- /// Read an exact number of elements from the ringbuffer.
- ///
- /// Returns the remaining number of elements available for immediate reading.
- /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
- ///
- /// Async/Wake Behavior:
- /// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
- /// and when it wraps around. This means that when called with a buffer of length 'M', when this
- /// ring buffer was created with a buffer of size 'N':
- /// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
- /// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
- pub async fn read_exact(&mut self, buffer: &mut [W]) -> Result<usize, OverrunError> {
- self.ringbuf
- .read_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
- .await
- }
-
- /// The capacity of the ringbuffer
- pub const fn capacity(&self) -> usize {
- self.ringbuf.cap()
- }
-
- /// Set a waker to be woken when at least one byte is received.
- pub fn set_waker(&mut self, waker: &Waker) {
- DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
- }
-
- fn clear_irqs(&mut self) {
- let channel_number = self.channel.num();
- let dma = self.channel.regs();
- let isrn = channel_number / 4;
- let isrbit = channel_number % 4;
-
- dma.ifcr(isrn).write(|w| {
- w.set_htif(isrbit, true);
- w.set_tcif(isrbit, true);
- w.set_teif(isrbit, true);
- });
- }
-
- /// Request DMA to stop.
- ///
- /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
- pub fn request_stop(&mut self) {
- let ch = self.channel.regs().st(self.channel.num());
-
- // Disable the channel. Keep the IEs enabled so the irqs still fire.
- ch.cr().write(|w| {
- w.set_teie(true);
- w.set_htie(true);
- w.set_tcie(true);
- });
- }
-
- /// Return whether DMA is still running.
- ///
- /// If this returns `false`, it can be because either the transfer finished, or
- /// it was requested to stop early with [`request_stop`](Self::request_stop).
- pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().st(self.channel.num());
- ch.cr().read().en()
- }
-}
-
-impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
- fn drop(&mut self) {
- self.request_stop();
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
- }
-}
-
-/// Ringbuffer for writing data using DMA circular mode.
-pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
- cr: regs::Cr,
- channel: PeripheralRef<'a, C>,
- ringbuf: WritableDmaRingBuffer<'a, W>,
-}
-
-impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
- /// Create a new ring buffer.
- pub unsafe fn new(
- channel: impl Peripheral<P = C> + 'a,
- _request: Request,
- peri_addr: *mut W,
- buffer: &'a mut [W],
- options: TransferOptions,
- ) -> Self {
- into_ref!(channel);
-
- let len = buffer.len();
- assert!(len > 0 && len <= 0xFFFF);
-
- let dir = Dir::MemoryToPeripheral;
- let data_size = W::size();
-
- let channel_number = channel.num();
- let dma = channel.regs();
-
- // "Preceding reads and writes cannot be moved past subsequent writes."
- fence(Ordering::SeqCst);
-
- let mut w = regs::Cr(0);
- w.set_dir(dir.into());
- w.set_msize(data_size.into());
- w.set_psize(data_size.into());
- w.set_pl(vals::Pl::VERYHIGH);
- w.set_minc(true);
- w.set_pinc(false);
- w.set_teie(true);
- w.set_htie(options.half_transfer_ir);
- w.set_tcie(true);
- w.set_circ(true);
- #[cfg(dma_v1)]
- w.set_trbuff(true);
- #[cfg(dma_v2)]
- w.set_chsel(_request);
- w.set_pburst(options.pburst.into());
- w.set_mburst(options.mburst.into());
- w.set_pfctrl(options.flow_ctrl.into());
- w.set_en(true);
-
- let buffer_ptr = buffer.as_mut_ptr();
- let mut this = Self {
- channel,
- cr: w,
- ringbuf: WritableDmaRingBuffer::new(buffer),
- };
- this.clear_irqs();
-
- #[cfg(dmamux)]
- super::dmamux::configure_dmamux(&*this.channel, _request);
-
- let ch = dma.st(channel_number);
- ch.par().write_value(peri_addr as u32);
- ch.m0ar().write_value(buffer_ptr as u32);
- ch.ndtr().write_value(regs::Ndtr(len as _));
- ch.fcr().write(|w| {
- if let Some(fth) = options.fifo_threshold {
- // FIFO mode
- w.set_dmdis(vals::Dmdis::DISABLED);
- w.set_fth(fth.into());
- } else {
- // Direct mode
- w.set_dmdis(vals::Dmdis::ENABLED);
- }
- });
-
- this
- }
-
- /// Start the ring buffer operation.
- ///
- /// You must call this after creating it for it to work.
- pub fn start(&mut self) {
- let ch = self.channel.regs().st(self.channel.num());
- ch.cr().write_value(self.cr);
- }
-
- /// Clear all data in the ring buffer.
- pub fn clear(&mut self) {
- self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
- }
-
- /// Write elements directly to the raw buffer.
- /// This can be used to fill the buffer before starting the DMA transfer.
- #[allow(dead_code)]
- pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
- self.ringbuf.write_immediate(buf)
- }
-
- /// Write elements from the ring buffer
- /// Return a tuple of the length written and the length remaining in the buffer
- pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
- self.ringbuf.write(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
- }
-
- /// Write an exact number of elements to the ringbuffer.
- pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
- self.ringbuf
- .write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
- .await
- }
-
- /// The capacity of the ringbuffer
- pub const fn capacity(&self) -> usize {
- self.ringbuf.cap()
- }
-
- /// Set a waker to be woken when at least one byte is received.
- pub fn set_waker(&mut self, waker: &Waker) {
- DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
- }
-
- fn clear_irqs(&mut self) {
- let channel_number = self.channel.num();
- let dma = self.channel.regs();
- let isrn = channel_number / 4;
- let isrbit = channel_number % 4;
-
- dma.ifcr(isrn).write(|w| {
- w.set_htif(isrbit, true);
- w.set_tcif(isrbit, true);
- w.set_teif(isrbit, true);
- });
- }
-
- /// Request DMA to stop.
- ///
- /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
- pub fn request_stop(&mut self) {
- let ch = self.channel.regs().st(self.channel.num());
-
- // Disable the channel. Keep the IEs enabled so the irqs still fire.
- ch.cr().write(|w| {
- w.set_teie(true);
- w.set_htie(true);
- w.set_tcie(true);
- });
- }
-
- /// Return whether DMA is still running.
- ///
- /// If this returns `false`, it can be because either the transfer finished, or
- /// it was requested to stop early with [`request_stop`](Self::request_stop).
- pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().st(self.channel.num());
- ch.cr().read().en()
- }
-}
-
-impl<'a, C: Channel, W: Word> Drop for WritableRingBuffer<'a, C, W> {
- fn drop(&mut self) {
- self.request_stop();
- while self.is_running() {}
-
- // "Subsequent reads and writes cannot be moved ahead of preceding reads."
- fence(Ordering::SeqCst);
- }
-}
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
new file mode 100644
index 000000000..08aba2795
--- /dev/null
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -0,0 +1,913 @@
+use core::future::Future;
+use core::pin::Pin;
+use core::sync::atomic::{fence, AtomicUsize, Ordering};
+use core::task::{Context, Poll, Waker};
+
+use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_sync::waitqueue::AtomicWaker;
+
+use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
+use super::word::{Word, WordSize};
+use super::{AnyChannel, Channel, Dir, Request, STATE};
+use crate::interrupt::typelevel::Interrupt;
+use crate::interrupt::Priority;
+use crate::pac;
+
+pub(crate) struct ChannelInfo {
+ pub(crate) dma: DmaInfo,
+ pub(crate) num: usize,
+ #[cfg(dmamux)]
+ pub(crate) dmamux: super::DmamuxInfo,
+}
+
+#[derive(Clone, Copy)]
+pub(crate) enum DmaInfo {
+ #[cfg(dma)]
+ Dma(pac::dma::Dma),
+ #[cfg(bdma)]
+ Bdma(pac::bdma::Dma),
+}
+
+/// DMA transfer options.
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub struct TransferOptions {
+ /// Peripheral burst transfer configuration
+ #[cfg(dma)]
+ pub pburst: Burst,
+ /// Memory burst transfer configuration
+ #[cfg(dma)]
+ pub mburst: Burst,
+ /// Flow control configuration
+ #[cfg(dma)]
+ pub flow_ctrl: FlowControl,
+ /// FIFO threshold for DMA FIFO mode. If none, direct mode is used.
+ #[cfg(dma)]
+ pub fifo_threshold: Option<FifoThreshold>,
+ /// Enable circular DMA
+ ///
+ /// Note:
+ /// If you enable circular mode manually, you may want to build and `.await` the `Transfer` in a separate task.
+ /// Since DMA in circular mode need manually stop, `.await` in current task would block the task forever.
+ pub circular: bool,
+ /// Enable half transfer interrupt
+ pub half_transfer_ir: bool,
+ /// Enable transfer complete interrupt
+ pub complete_transfer_ir: bool,
+}
+
+impl Default for TransferOptions {
+ fn default() -> Self {
+ Self {
+ #[cfg(dma)]
+ pburst: Burst::Single,
+ #[cfg(dma)]
+ mburst: Burst::Single,
+ #[cfg(dma)]
+ flow_ctrl: FlowControl::Dma,
+ #[cfg(dma)]
+ fifo_threshold: None,
+ circular: false,
+ half_transfer_ir: false,
+ complete_transfer_ir: true,
+ }
+ }
+}
+
+#[cfg(dma)]
+pub use dma_only::*;
+#[cfg(dma)]
+mod dma_only {
+ use pac::dma::vals;
+
+ use super::*;
+
+ impl From<WordSize> for vals::Size {
+ fn from(raw: WordSize) -> Self {
+ match raw {
+ WordSize::OneByte => Self::BITS8,
+ WordSize::TwoBytes => Self::BITS16,
+ WordSize::FourBytes => Self::BITS32,
+ }
+ }
+ }
+
+ impl From<Dir> for vals::Dir {
+ fn from(raw: Dir) -> Self {
+ match raw {
+ Dir::MemoryToPeripheral => Self::MEMORYTOPERIPHERAL,
+ Dir::PeripheralToMemory => Self::PERIPHERALTOMEMORY,
+ }
+ }
+ }
+
+ /// DMA transfer burst setting.
+ #[derive(Debug, Copy, Clone, PartialEq, Eq)]
+ #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+ pub enum Burst {
+ /// Single transfer
+ Single,
+ /// Incremental burst of 4 beats
+ Incr4,
+ /// Incremental burst of 8 beats
+ Incr8,
+ /// Incremental burst of 16 beats
+ Incr16,
+ }
+
+ impl From<Burst> for vals::Burst {
+ fn from(burst: Burst) -> Self {
+ match burst {
+ Burst::Single => vals::Burst::SINGLE,
+ Burst::Incr4 => vals::Burst::INCR4,
+ Burst::Incr8 => vals::Burst::INCR8,
+ Burst::Incr16 => vals::Burst::INCR16,
+ }
+ }
+ }
+
+ /// DMA flow control setting.
+ #[derive(Debug, Copy, Clone, PartialEq, Eq)]
+ #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+ pub enum FlowControl {
+ /// Flow control by DMA
+ Dma,
+ /// Flow control by peripheral
+ Peripheral,
+ }
+
+ impl From<FlowControl> for vals::Pfctrl {
+ fn from(flow: FlowControl) -> Self {
+ match flow {
+ FlowControl::Dma => vals::Pfctrl::DMA,
+ FlowControl::Peripheral => vals::Pfctrl::PERIPHERAL,
+ }
+ }
+ }
+
+ /// DMA FIFO threshold.
+ #[derive(Debug, Copy, Clone, PartialEq, Eq)]
+ #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+ pub enum FifoThreshold {
+ /// 1/4 full FIFO
+ Quarter,
+ /// 1/2 full FIFO
+ Half,
+ /// 3/4 full FIFO
+ ThreeQuarters,
+ /// Full FIFO
+ Full,
+ }
+
+ impl From<FifoThreshold> for vals::Fth {
+ fn from(value: FifoThreshold) -> Self {
+ match value {
+ FifoThreshold::Quarter => vals::Fth::QUARTER,
+ FifoThreshold::Half => vals::Fth::HALF,
+ FifoThreshold::ThreeQuarters => vals::Fth::THREEQUARTERS,
+ FifoThreshold::Full => vals::Fth::FULL,
+ }
+ }
+ }
+}
+
+#[cfg(bdma)]
+mod bdma_only {
+ use pac::bdma::vals;
+
+ use super::*;
+
+ impl From<WordSize> for vals::Size {
+ fn from(raw: WordSize) -> Self {
+ match raw {
+ WordSize::OneByte => Self::BITS8,
+ WordSize::TwoBytes => Self::BITS16,
+ WordSize::FourBytes => Self::BITS32,
+ }
+ }
+ }
+
+ impl From<Dir> for vals::Dir {
+ fn from(raw: Dir) -> Self {
+ match raw {
+ Dir::MemoryToPeripheral => Self::FROMMEMORY,
+ Dir::PeripheralToMemory => Self::FROMPERIPHERAL,
+ }
+ }
+ }
+}
+
+pub(crate) struct ChannelState {
+ waker: AtomicWaker,
+ complete_count: AtomicUsize,
+}
+
+impl ChannelState {
+ pub(crate) const NEW: Self = Self {
+ waker: AtomicWaker::new(),
+ complete_count: AtomicUsize::new(0),
+ };
+}
+
+/// safety: must be called only once
+pub(crate) unsafe fn init(
+ cs: critical_section::CriticalSection,
+ #[cfg(dma)] dma_priority: Priority,
+ #[cfg(bdma)] bdma_priority: Priority,
+) {
+ foreach_interrupt! {
+ ($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
+ crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, dma_priority);
+ crate::interrupt::typelevel::$irq::enable();
+ };
+ ($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
+ crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, bdma_priority);
+ crate::interrupt::typelevel::$irq::enable();
+ };
+ }
+ crate::_generated::init_dma();
+ crate::_generated::init_bdma();
+}
+
+impl AnyChannel {
+ /// Safety: Must be called with a matching set of parameters for a valid dma channel
+ pub(crate) unsafe fn on_irq(&self) {
+ let info = self.info();
+ let state = &STATE[self.id as usize];
+ match self.info().dma {
+ #[cfg(dma)]
+ DmaInfo::Dma(r) => {
+ let cr = r.st(info.num).cr();
+ let isr = r.isr(info.num / 4).read();
+
+ if isr.teif(info.num % 4) {
+ panic!("DMA: error on DMA@{:08x} channel {}", r.as_ptr() as u32, info.num);
+ }
+
+ if isr.htif(info.num % 4) && cr.read().htie() {
+ // Acknowledge half transfer complete interrupt
+ r.ifcr(info.num / 4).write(|w| w.set_htif(info.num % 4, true));
+ } else if isr.tcif(info.num % 4) && cr.read().tcie() {
+ // Acknowledge transfer complete interrupt
+ r.ifcr(info.num / 4).write(|w| w.set_tcif(info.num % 4, true));
+ state.complete_count.fetch_add(1, Ordering::Release);
+ } else {
+ return;
+ }
+
+ state.waker.wake();
+ }
+ #[cfg(bdma)]
+ DmaInfo::Bdma(r) => {
+ let isr = r.isr().read();
+ let cr = r.ch(info.num).cr();
+
+ if isr.teif(info.num) {
+ panic!("DMA: error on BDMA@{:08x} channel {}", r.as_ptr() as u32, info.num);
+ }
+
+ if isr.htif(info.num) && cr.read().htie() {
+ // Acknowledge half transfer complete interrupt
+ r.ifcr().write(|w| w.set_htif(info.num, true));
+ } else if isr.tcif(info.num) && cr.read().tcie() {
+ // Acknowledge transfer complete interrupt
+ r.ifcr().write(|w| w.set_tcif(info.num, true));
+ #[cfg(not(armv6m))]
+ state.complete_count.fetch_add(1, Ordering::Release);
+ #[cfg(armv6m)]
+ critical_section::with(|_| {
+ let x = state.complete_count.load(Ordering::Relaxed);
+ state.complete_count.store(x + 1, Ordering::Release);
+ })
+ } else {
+ return;
+ }
+
+ state.waker.wake();
+ }
+ }
+ }
+
+ unsafe fn configure(
+ &self,
+ _request: Request,
+ dir: Dir,
+ peri_addr: *const u32,
+ mem_addr: *mut u32,
+ mem_len: usize,
+ incr_mem: bool,
+ data_size: WordSize,
+ options: TransferOptions,
+ ) {
+ let info = self.info();
+
+ #[cfg(dmamux)]
+ super::dmamux::configure_dmamux(&info.dmamux, _request);
+
+ assert!(mem_len > 0 && mem_len <= 0xFFFF);
+
+ match self.info().dma {
+ #[cfg(dma)]
+ DmaInfo::Dma(r) => {
+ let ch = r.st(info.num);
+
+ // "Preceding reads and writes cannot be moved past subsequent writes."
+ fence(Ordering::SeqCst);
+
+ self.clear_irqs();
+
+ ch.par().write_value(peri_addr as u32);
+ ch.m0ar().write_value(mem_addr as u32);
+ ch.ndtr().write_value(pac::dma::regs::Ndtr(mem_len as _));
+ ch.fcr().write(|w| {
+ if let Some(fth) = options.fifo_threshold {
+ // FIFO mode
+ w.set_dmdis(pac::dma::vals::Dmdis::DISABLED);
+ w.set_fth(fth.into());
+ } else {
+ // Direct mode
+ w.set_dmdis(pac::dma::vals::Dmdis::ENABLED);
+ }
+ });
+ ch.cr().write(|w| {
+ w.set_dir(dir.into());
+ w.set_msize(data_size.into());
+ w.set_psize(data_size.into());
+ w.set_pl(pac::dma::vals::Pl::VERYHIGH);
+ w.set_minc(incr_mem);
+ w.set_pinc(false);
+ w.set_teie(true);
+ w.set_htie(options.half_transfer_ir);
+ w.set_tcie(options.complete_transfer_ir);
+ w.set_circ(options.circular);
+ #[cfg(dma_v1)]
+ w.set_trbuff(true);
+ #[cfg(dma_v2)]
+ w.set_chsel(_request);
+ w.set_pburst(options.pburst.into());
+ w.set_mburst(options.mburst.into());
+ w.set_pfctrl(options.flow_ctrl.into());
+ w.set_en(false); // don't start yet
+ });
+ }
+ #[cfg(bdma)]
+ DmaInfo::Bdma(r) => {
+ #[cfg(bdma_v2)]
+ critical_section::with(|_| r.cselr().modify(|w| w.set_cs(info.num, _request)));
+
+ let state: &ChannelState = &STATE[self.id as usize];
+ let ch = r.ch(info.num);
+
+ state.complete_count.store(0, Ordering::Release);
+ self.clear_irqs();
+
+ ch.par().write_value(peri_addr as u32);
+ ch.mar().write_value(mem_addr as u32);
+ ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
+ ch.cr().write(|w| {
+ w.set_psize(data_size.into());
+ w.set_msize(data_size.into());
+ w.set_minc(incr_mem);
+ w.set_dir(dir.into());
+ w.set_teie(true);
+ w.set_tcie(options.complete_transfer_ir);
+ w.set_htie(options.half_transfer_ir);
+ w.set_circ(options.circular);
+ w.set_pl(pac::bdma::vals::Pl::VERYHIGH);
+ w.set_en(false); // don't start yet
+ });
+ }
+ }
+ }
+
+ fn start(&self) {
+ let info = self.info();
+ match self.info().dma {
+ #[cfg(dma)]
+ DmaInfo::Dma(r) => {
+ let ch = r.st(info.num);
+ ch.cr().modify(|w| w.set_en(true))
+ }
+ #[cfg(bdma)]
+ DmaInfo::Bdma(r) => {
+ let ch = r.ch(info.num);
+ ch.cr().modify(|w| w.set_en(true));
+ }
+ }
+ }
+
+ fn clear_irqs(&self) {
+ let info = self.info();
+ match self.info().dma {
+ #[cfg(dma)]
+ DmaInfo::Dma(r) => {
+ let isrn = info.num / 4;
+ let isrbit = info.num % 4;
+
+ r.ifcr(isrn).write(|w| {
+ w.set_htif(isrbit, true);
+ w.set_tcif(isrbit, true);
+ w.set_teif(isrbit, true);
+ });
+ }
+ #[cfg(bdma)]
+ DmaInfo::Bdma(r) => {
+ r.ifcr().write(|w| {
+ w.set_htif(info.num, true);
+ w.set_tcif(info.num, true);
+ w.set_teif(info.num, true);
+ });
+ }
+ }
+ }
+
+ fn request_stop(&self) {
+ let info = self.info();
+ match self.info().dma {
+ #[cfg(dma)]
+ DmaInfo::Dma(r) => {
+ // Disable the channel. Keep the IEs enabled so the irqs still fire.
+ r.st(info.num).cr().write(|w| {
+ w.set_teie(true);
+ w.set_tcie(true);
+ });
+ }
+ #[cfg(bdma)]
+ DmaInfo::Bdma(r) => {
+ // Disable the channel. Keep the IEs enabled so the irqs still fire.
+ r.ch(info.num).cr().write(|w| {
+ w.set_teie(true);
+ w.set_tcie(true);
+ });
+ }
+ }
+ }
+
+ fn is_running(&self) -> bool {
+ let info = self.info();
+ match self.info().dma {
+ #[cfg(dma)]
+ DmaInfo::Dma(r) => r.st(info.num).cr().read().en(),
+ #[cfg(bdma)]
+ DmaInfo::Bdma(r) => {
+ let state: &ChannelState = &STATE[self.id as usize];
+ let ch = r.ch(info.num);
+ let en = ch.cr().read().en();
+ let circular = ch.cr().read().circ();
+ let tcif = state.complete_count.load(Ordering::Acquire) != 0;
+ en && (circular || !tcif)
+ }
+ }
+ }
+
+ fn get_remaining_transfers(&self) -> u16 {
+ let info = self.info();
+ match self.info().dma {
+ #[cfg(dma)]
+ DmaInfo::Dma(r) => r.st(info.num).ndtr().read().ndt(),
+ #[cfg(bdma)]
+ DmaInfo::Bdma(r) => r.ch(info.num).ndtr().read().ndt(),
+ }
+ }
+}
+
+/// DMA transfer.
+#[must_use = "futures do nothing unless you `.await` or poll them"]
+pub struct Transfer<'a> {
+ channel: PeripheralRef<'a, AnyChannel>,
+}
+
+impl<'a> Transfer<'a> {
+ /// Create a new read DMA transfer (peripheral to memory).
+ pub unsafe fn new_read<W: Word>(
+ channel: impl Peripheral<P = impl Channel> + 'a,
+ request: Request,
+ peri_addr: *mut W,
+ buf: &'a mut [W],
+ options: TransferOptions,
+ ) -> Self {
+ Self::new_read_raw(channel, request, peri_addr, buf, options)
+ }
+
+ /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
+ pub unsafe fn new_read_raw<W: Word>(
+ channel: impl Peripheral<P = impl Channel> + 'a,
+ request: Request,
+ peri_addr: *mut W,
+ buf: *mut [W],
+ options: TransferOptions,
+ ) -> Self {
+ into_ref!(channel);
+
+ let (ptr, len) = super::slice_ptr_parts_mut(buf);
+ assert!(len > 0 && len <= 0xFFFF);
+
+ Self::new_inner(
+ channel.map_into(),
+ request,
+ Dir::PeripheralToMemory,
+ peri_addr as *const u32,
+ ptr as *mut u32,
+ len,
+ true,
+ W::size(),
+ options,
+ )
+ }
+
+ /// Create a new write DMA transfer (memory to peripheral).
+ pub unsafe fn new_write<W: Word>(
+ channel: impl Peripheral<P = impl Channel> + 'a,
+ request: Request,
+ buf: &'a [W],
+ peri_addr: *mut W,
+ options: TransferOptions,
+ ) -> Self {
+ Self::new_write_raw(channel, request, buf, peri_addr, options)
+ }
+
+ /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
+ pub unsafe fn new_write_raw<W: Word>(
+ channel: impl Peripheral<P = impl Channel> + 'a,
+ request: Request,
+ buf: *const [W],
+ peri_addr: *mut W,
+ options: TransferOptions,
+ ) -> Self {
+ into_ref!(channel);
+
+ let (ptr, len) = super::slice_ptr_parts(buf);
+ assert!(len > 0 && len <= 0xFFFF);
+
+ Self::new_inner(
+ channel.map_into(),
+ request,
+ Dir::MemoryToPeripheral,
+ peri_addr as *const u32,
+ ptr as *mut u32,
+ len,
+ true,
+ W::size(),
+ options,
+ )
+ }
+
+ /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
+ pub unsafe fn new_write_repeated<W: Word>(
+ channel: impl Peripheral<P = impl Channel> + 'a,
+ request: Request,
+ repeated: &'a W,
+ count: usize,
+ peri_addr: *mut W,
+ options: TransferOptions,
+ ) -> Self {
+ into_ref!(channel);
+
+ Self::new_inner(
+ channel.map_into(),
+ request,
+ Dir::MemoryToPeripheral,
+ peri_addr as *const u32,
+ repeated as *const W as *mut u32,
+ count,
+ false,
+ W::size(),
+ options,
+ )
+ }
+
+ unsafe fn new_inner(
+ channel: PeripheralRef<'a, AnyChannel>,
+ _request: Request,
+ dir: Dir,
+ peri_addr: *const u32,
+ mem_addr: *mut u32,
+ mem_len: usize,
+ incr_mem: bool,
+ data_size: WordSize,
+ options: TransferOptions,
+ ) -> Self {
+ channel.configure(
+ _request, dir, peri_addr, mem_addr, mem_len, incr_mem, data_size, options,
+ );
+ channel.start();
+
+ Self { channel }
+ }
+
+ /// Request the transfer to stop.
+ ///
+ /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+ pub fn request_stop(&mut self) {
+ self.channel.request_stop()
+ }
+
+ /// Return whether this transfer is still running.
+ ///
+ /// If this returns `false`, it can be because either the transfer finished, or
+ /// it was requested to stop early with [`request_stop`](Self::request_stop).
+ pub fn is_running(&mut self) -> bool {
+ self.channel.is_running()
+ }
+
+ /// Gets the total remaining transfers for the channel
+ /// Note: this will be zero for transfers that completed without cancellation.
+ pub fn get_remaining_transfers(&self) -> u16 {
+ self.channel.get_remaining_transfers()
+ }
+
+ /// Blocking wait until the transfer finishes.
+ pub fn blocking_wait(mut self) {
+ while self.is_running() {}
+
+ // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+ fence(Ordering::SeqCst);
+
+ core::mem::forget(self);
+ }
+}
+
+impl<'a> Drop for Transfer<'a> {
+ fn drop(&mut self) {
+ self.request_stop();
+ while self.is_running() {}
+
+ // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+ fence(Ordering::SeqCst);
+ }
+}
+
+impl<'a> Unpin for Transfer<'a> {}
+impl<'a> Future for Transfer<'a> {
+ type Output = ();
+ fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+ let state: &ChannelState = &STATE[self.channel.id as usize];
+
+ state.waker.register(cx.waker());
+
+ if self.is_running() {
+ Poll::Pending
+ } else {
+ Poll::Ready(())
+ }
+ }
+}
+
+// ==============================
+
+struct DmaCtrlImpl<'a>(PeripheralRef<'a, AnyChannel>);
+
+impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
+ fn get_remaining_transfers(&self) -> usize {
+ self.0.get_remaining_transfers() as _
+ }
+
+ fn get_complete_count(&self) -> usize {
+ STATE[self.0.id as usize].complete_count.load(Ordering::Acquire)
+ }
+
+ fn reset_complete_count(&mut self) -> usize {
+ let state = &STATE[self.0.id as usize];
+ #[cfg(not(armv6m))]
+ return state.complete_count.swap(0, Ordering::AcqRel);
+ #[cfg(armv6m)]
+ return critical_section::with(|_| {
+ let x = state.complete_count.load(Ordering::Acquire);
+ state.complete_count.store(0, Ordering::Release);
+ x
+ });
+ }
+
+ fn set_waker(&mut self, waker: &Waker) {
+ STATE[self.0.id as usize].waker.register(waker);
+ }
+}
+
+/// Ringbuffer for receiving data using DMA circular mode.
+pub struct ReadableRingBuffer<'a, W: Word> {
+ channel: PeripheralRef<'a, AnyChannel>,
+ ringbuf: ReadableDmaRingBuffer<'a, W>,
+}
+
+impl<'a, W: Word> ReadableRingBuffer<'a, W> {
+ /// Create a new ring buffer.
+ pub unsafe fn new(
+ channel: impl Peripheral<P = impl Channel> + 'a,
+ _request: Request,
+ peri_addr: *mut W,
+ buffer: &'a mut [W],
+ mut options: TransferOptions,
+ ) -> Self {
+ into_ref!(channel);
+ let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
+
+ let buffer_ptr = buffer.as_mut_ptr();
+ let len = buffer.len();
+ let dir = Dir::PeripheralToMemory;
+ let data_size = W::size();
+
+ options.complete_transfer_ir = true;
+ options.circular = true;
+
+ channel.configure(
+ _request,
+ dir,
+ peri_addr as *mut u32,
+ buffer_ptr as *mut u32,
+ len,
+ true,
+ data_size,
+ options,
+ );
+
+ Self {
+ channel,
+ ringbuf: ReadableDmaRingBuffer::new(buffer),
+ }
+ }
+
+ /// Start the ring buffer operation.
+ ///
+ /// You must call this after creating it for it to work.
+ pub fn start(&mut self) {
+ self.channel.start()
+ }
+
+ /// Clear all data in the ring buffer.
+ pub fn clear(&mut self) {
+ self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
+ }
+
+ /// Read elements from the ring buffer
+ /// Return a tuple of the length read and the length remaining in the buffer
+ /// If not all of the elements were read, then there will be some elements in the buffer remaining
+ /// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
+ /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
+ pub fn read(&mut self, buf: &mut [W]) -> Result<(usize, usize), OverrunError> {
+ self.ringbuf.read(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
+ }
+
+ /// Read an exact number of elements from the ringbuffer.
+ ///
+ /// Returns the remaining number of elements available for immediate reading.
+ /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
+ ///
+ /// Async/Wake Behavior:
+ /// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
+ /// and when it wraps around. This means that when called with a buffer of length 'M', when this
+ /// ring buffer was created with a buffer of size 'N':
+ /// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
+ /// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
+ pub async fn read_exact(&mut self, buffer: &mut [W]) -> Result<usize, OverrunError> {
+ self.ringbuf
+ .read_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
+ .await
+ }
+
+ /// The capacity of the ringbuffer
+ pub const fn capacity(&self) -> usize {
+ self.ringbuf.cap()
+ }
+
+ /// Set a waker to be woken when at least one byte is received.
+ pub fn set_waker(&mut self, waker: &Waker) {
+ DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
+ }
+
+ /// Request DMA to stop.
+ ///
+ /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+ pub fn request_stop(&mut self) {
+ self.channel.request_stop()
+ }
+
+ /// Return whether DMA is still running.
+ ///
+ /// If this returns `false`, it can be because either the transfer finished, or
+ /// it was requested to stop early with [`request_stop`](Self::request_stop).
+ pub fn is_running(&mut self) -> bool {
+ self.channel.is_running()
+ }
+}
+
+impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
+ fn drop(&mut self) {
+ self.request_stop();
+ while self.is_running() {}
+
+ // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+ fence(Ordering::SeqCst);
+ }
+}
+
+/// Ringbuffer for writing data using DMA circular mode.
+pub struct WritableRingBuffer<'a, W: Word> {
+ channel: PeripheralRef<'a, AnyChannel>,
+ ringbuf: WritableDmaRingBuffer<'a, W>,
+}
+
+impl<'a, W: Word> WritableRingBuffer<'a, W> {
+ /// Create a new ring buffer.
+ pub unsafe fn new(
+ channel: impl Peripheral<P = impl Channel> + 'a,
+ _request: Request,
+ peri_addr: *mut W,
+ buffer: &'a mut [W],
+ mut options: TransferOptions,
+ ) -> Self {
+ into_ref!(channel);
+ let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
+
+ let len = buffer.len();
+ let dir = Dir::MemoryToPeripheral;
+ let data_size = W::size();
+ let buffer_ptr = buffer.as_mut_ptr();
+
+ options.complete_transfer_ir = true;
+ options.circular = true;
+
+ channel.configure(
+ _request,
+ dir,
+ peri_addr as *mut u32,
+ buffer_ptr as *mut u32,
+ len,
+ true,
+ data_size,
+ options,
+ );
+
+ Self {
+ channel,
+ ringbuf: WritableDmaRingBuffer::new(buffer),
+ }
+ }
+
+ /// Start the ring buffer operation.
+ ///
+ /// You must call this after creating it for it to work.
+ pub fn start(&mut self) {
+ self.channel.start()
+ }
+
+ /// Clear all data in the ring buffer.
+ pub fn clear(&mut self) {
+ self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
+ }
+
+ /// Write elements directly to the raw buffer.
+ /// This can be used to fill the buffer before starting the DMA transfer.
+ #[allow(dead_code)]
+ pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
+ self.ringbuf.write_immediate(buf)
+ }
+
+ /// Write elements from the ring buffer
+ /// Return a tuple of the length written and the length remaining in the buffer
+ pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
+ self.ringbuf.write(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
+ }
+
+ /// Write an exact number of elements to the ringbuffer.
+ pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
+ self.ringbuf
+ .write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
+ .await
+ }
+
+ /// The capacity of the ringbuffer
+ pub const fn capacity(&self) -> usize {
+ self.ringbuf.cap()
+ }
+
+ /// Set a waker to be woken when at least one byte is received.
+ pub fn set_waker(&mut self, waker: &Waker) {
+ DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
+ }
+
+ /// Request DMA to stop.
+ ///
+ /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+ pub fn request_stop(&mut self) {
+ self.channel.request_stop()
+ }
+
+ /// Return whether DMA is still running.
+ ///
+ /// If this returns `false`, it can be because either the transfer finished, or
+ /// it was requested to stop early with [`request_stop`](Self::request_stop).
+ pub fn is_running(&mut self) -> bool {
+ self.channel.is_running()
+ }
+}
+
+impl<'a, W: Word> Drop for WritableRingBuffer<'a, W> {
+ fn drop(&mut self) {
+ self.request_stop();
+ while self.is_running() {}
+
+ // "Subsequent reads and writes cannot be moved ahead of preceding reads."
+ fence(Ordering::SeqCst);
+ }
+}
diff --git a/embassy-stm32/src/dma/dmamux.rs b/embassy-stm32/src/dma/dmamux.rs
index ac6f44107..1e9ab5944 100644
--- a/embassy-stm32/src/dma/dmamux.rs
+++ b/embassy-stm32/src/dma/dmamux.rs
@@ -1,9 +1,14 @@
#![macro_use]
-use crate::{pac, peripherals};
+use crate::pac;
-pub(crate) fn configure_dmamux<M: MuxChannel>(channel: &M, request: u8) {
- let ch_mux_regs = channel.mux_regs().ccr(channel.mux_num());
+pub(crate) struct DmamuxInfo {
+ pub(crate) mux: pac::dmamux::Dmamux,
+ pub(crate) num: usize,
+}
+
+pub(crate) fn configure_dmamux(info: &DmamuxInfo, request: u8) {
+ let ch_mux_regs = info.mux.ccr(info.num);
ch_mux_regs.write(|reg| {
reg.set_nbreq(0);
reg.set_dmareq_id(request);
@@ -15,11 +20,7 @@ pub(crate) fn configure_dmamux<M: MuxChannel>(channel: &M, request: u8) {
}
pub(crate) mod dmamux_sealed {
- use super::*;
- pub trait MuxChannel {
- fn mux_regs(&self) -> pac::dmamux::Dmamux;
- fn mux_num(&self) -> usize;
- }
+ pub trait MuxChannel {}
}
/// DMAMUX1 instance.
@@ -34,18 +35,11 @@ pub trait MuxChannel: dmamux_sealed::MuxChannel {
type Mux;
}
-foreach_dma_channel! {
- ($channel_peri:ident, $dma_peri:ident, $version:ident, $channel_num:expr, $index:expr, {dmamux: $dmamux:ident, dmamux_channel: $dmamux_channel:expr}) => {
- impl dmamux_sealed::MuxChannel for peripherals::$channel_peri {
- fn mux_regs(&self) -> pac::dmamux::Dmamux {
- pac::$dmamux
- }
- fn mux_num(&self) -> usize {
- $dmamux_channel
- }
- }
- impl MuxChannel for peripherals::$channel_peri {
- type Mux = $dmamux;
+macro_rules! dmamux_channel_impl {
+ ($channel_peri:ident, $dmamux:ident) => {
+ impl crate::dma::dmamux_sealed::MuxChannel for crate::peripherals::$channel_peri {}
+ impl crate::dma::MuxChannel for crate::peripherals::$channel_peri {
+ type Mux = crate::dma::$dmamux;
}
};
}
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index 337e7b309..ef03970ef 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -9,13 +9,17 @@ use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use super::word::{Word, WordSize};
-use super::Dir;
-use crate::_generated::GPDMA_CHANNEL_COUNT;
+use super::{AnyChannel, Channel, Dir, Request, STATE};
use crate::interrupt::typelevel::Interrupt;
use crate::interrupt::Priority;
use crate::pac;
use crate::pac::gpdma::vals;
+pub(crate) struct ChannelInfo {
+ pub(crate) dma: pac::gpdma::Gpdma,
+ pub(crate) num: usize,
+}
+
/// GPDMA transfer options.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -38,21 +42,16 @@ impl From<WordSize> for vals::ChTr1Dw {
}
}
-struct State {
- ch_wakers: [AtomicWaker; GPDMA_CHANNEL_COUNT],
+pub(crate) struct ChannelState {
+ waker: AtomicWaker,
}
-impl State {
- const fn new() -> Self {
- const AW: AtomicWaker = AtomicWaker::new();
- Self {
- ch_wakers: [AW; GPDMA_CHANNEL_COUNT],
- }
- }
+impl ChannelState {
+ pub(crate) const NEW: Self = Self {
+ waker: AtomicWaker::new(),
+ };
}
-static STATE: State = State::new();
-
/// safety: must be called only once
pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: Priority) {
foreach_interrupt! {
@@ -64,87 +63,50 @@ pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: P
crate::_generated::init_gpdma();
}
-foreach_dma_channel! {
- ($channel_peri:ident, $dma_peri:ident, gpdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
- impl sealed::Channel for crate::peripherals::$channel_peri {
- fn regs(&self) -> pac::gpdma::Gpdma {
- pac::$dma_peri
- }
- fn num(&self) -> usize {
- $channel_num
- }
- fn index(&self) -> usize {
- $index
- }
- fn on_irq() {
- unsafe { on_irq_inner(pac::$dma_peri, $channel_num, $index) }
- }
+impl AnyChannel {
+ /// Safety: Must be called with a matching set of parameters for a valid dma channel
+ pub(crate) unsafe fn on_irq(&self) {
+ let info = self.info();
+ let state = &STATE[self.id as usize];
+
+ let ch = info.dma.ch(info.num);
+ let sr = ch.sr().read();
+
+ if sr.dtef() {
+ panic!(
+ "DMA: data transfer error on DMA@{:08x} channel {}",
+ info.dma.as_ptr() as u32,
+ info.num
+ );
+ }
+ if sr.usef() {
+ panic!(
+ "DMA: user settings error on DMA@{:08x} channel {}",
+ info.dma.as_ptr() as u32,
+ info.num
+ );
}
- impl Channel for crate::peripherals::$channel_peri {}
- };
-}
+ if sr.suspf() || sr.tcf() {
+ // disable all xxIEs to prevent the irq from firing again.
+ ch.cr().write(|_| {});
-/// Safety: Must be called with a matching set of parameters for a valid dma channel
-pub(crate) unsafe fn on_irq_inner(dma: pac::gpdma::Gpdma, channel_num: usize, index: usize) {
- let ch = dma.ch(channel_num);
- let sr = ch.sr().read();
-
- if sr.dtef() {
- panic!(
- "DMA: data transfer error on DMA@{:08x} channel {}",
- dma.as_ptr() as u32,
- channel_num
- );
- }
- if sr.usef() {
- panic!(
- "DMA: user settings error on DMA@{:08x} channel {}",
- dma.as_ptr() as u32,
- channel_num
- );
- }
-
- if sr.suspf() || sr.tcf() {
- // disable all xxIEs to prevent the irq from firing again.
- ch.cr().write(|_| {});
-
- // Wake the future. It'll look at tcf and see it's set.
- STATE.ch_wakers[index].wake();
- }
-}
-
-/// DMA request type alias. (also known as DMA channel number in some chips)
-pub type Request = u8;
-
-/// DMA channel.
-#[cfg(dmamux)]
-pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
-/// DMA channel.
-#[cfg(not(dmamux))]
-pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
-
-pub(crate) mod sealed {
- use super::*;
-
- pub trait Channel {
- fn regs(&self) -> pac::gpdma::Gpdma;
- fn num(&self) -> usize;
- fn index(&self) -> usize;
- fn on_irq();
+ // Wake the future. It'll look at tcf and see it's set.
+ state.waker.wake();
+ }
}
}
/// DMA transfer.
#[must_use = "futures do nothing unless you `.await` or poll them"]
-pub struct Transfer<'a, C: Channel> {
- channel: PeripheralRef<'a, C>,
+pub struct Transfer<'a> {
+ channel: PeripheralRef<'a, AnyChannel>,
}
-impl<'a, C: Channel> Transfer<'a, C> {
+impl<'a> Transfer<'a> {
/// Create a new read DMA transfer (peripheral to memory).
pub unsafe fn new_read<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
+ channel: impl Peripheral<P = impl Channel> + 'a,
request: Request,
peri_addr: *mut W,
buf: &'a mut [W],
@@ -155,7 +117,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
/// Create a new read DMA transfer (peripheral to memory), using raw pointers.
pub unsafe fn new_read_raw<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
+ channel: impl Peripheral<P = impl Channel> + 'a,
request: Request,
peri_addr: *mut W,
buf: *mut [W],
@@ -167,7 +129,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
assert!(len > 0 && len <= 0xFFFF);
Self::new_inner(
- channel,
+ channel.map_into(),
request,
Dir::PeripheralToMemory,
peri_addr as *const u32,
@@ -181,7 +143,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
/// Create a new write DMA transfer (memory to peripheral).
pub unsafe fn new_write<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
+ channel: impl Peripheral<P = impl Channel> + 'a,
request: Request,
buf: &'a [W],
peri_addr: *mut W,
@@ -192,7 +154,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
/// Create a new write DMA transfer (memory to peripheral), using raw pointers.
pub unsafe fn new_write_raw<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
+ channel: impl Peripheral<P = impl Channel> + 'a,
request: Request,
buf: *const [W],
peri_addr: *mut W,
@@ -204,7 +166,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
assert!(len > 0 && len <= 0xFFFF);
Self::new_inner(
- channel,
+ channel.map_into(),
request,
Dir::MemoryToPeripheral,
peri_addr as *const u32,
@@ -218,7 +180,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
/// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
pub unsafe fn new_write_repeated<W: Word>(
- channel: impl Peripheral<P = C> + 'a,
+ channel: impl Peripheral<P = impl Channel> + 'a,
request: Request,
repeated: &'a W,
count: usize,
@@ -228,7 +190,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
into_ref!(channel);
Self::new_inner(
- channel,
+ channel.map_into(),
request,
Dir::MemoryToPeripheral,
peri_addr as *const u32,
@@ -241,7 +203,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
}
unsafe fn new_inner(
- channel: PeripheralRef<'a, C>,
+ channel: PeripheralRef<'a, AnyChannel>,
request: Request,
dir: Dir,
peri_addr: *const u32,
@@ -251,7 +213,8 @@ impl<'a, C: Channel> Transfer<'a, C> {
data_size: WordSize,
_options: TransferOptions,
) -> Self {
- let ch = channel.regs().ch(channel.num());
+ let info = channel.info();
+ let ch = info.dma.ch(info.num);
// "Preceding reads and writes cannot be moved past subsequent writes."
fence(Ordering::SeqCst);
@@ -311,10 +274,10 @@ impl<'a, C: Channel> Transfer<'a, C> {
///
/// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
pub fn request_stop(&mut self) {
- let ch = self.channel.regs().ch(self.channel.num());
- ch.cr().modify(|w| {
- w.set_susp(true);
- })
+ let info = self.channel.info();
+ let ch = info.dma.ch(info.num);
+
+ ch.cr().modify(|w| w.set_susp(true))
}
/// Return whether this transfer is still running.
@@ -322,7 +285,9 @@ impl<'a, C: Channel> Transfer<'a, C> {
/// If this returns `false`, it can be because either the transfer finished, or
/// it was requested to stop early with [`request_stop`](Self::request_stop).
pub fn is_running(&mut self) -> bool {
- let ch = self.channel.regs().ch(self.channel.num());
+ let info = self.channel.info();
+ let ch = info.dma.ch(info.num);
+
let sr = ch.sr().read();
!sr.tcf() && !sr.suspf()
}
@@ -330,7 +295,9 @@ impl<'a, C: Channel> Transfer<'a, C> {
/// Gets the total remaining transfers for the channel
/// Note: this will be zero for transfers that completed without cancellation.
pub fn get_remaining_transfers(&self) -> u16 {
- let ch = self.channel.regs().ch(self.channel.num());
+ let info = self.channel.info();
+ let ch = info.dma.ch(info.num);
+
ch.br1().read().bndt()
}
@@ -345,7 +312,7 @@ impl<'a, C: Channel> Transfer<'a, C> {
}
}
-impl<'a, C: Channel> Drop for Transfer<'a, C> {
+impl<'a> Drop for Transfer<'a> {
fn drop(&mut self) {
self.request_stop();
while self.is_running() {}
@@ -355,11 +322,12 @@ impl<'a, C: Channel> Drop for Transfer<'a, C> {
}
}
-impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
-impl<'a, C: Channel> Future for Transfer<'a, C> {
+impl<'a> Unpin for Transfer<'a> {}
+impl<'a> Future for Transfer<'a> {
type Output = ();
fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
- STATE.ch_wakers[self.channel.index()].register(cx.waker());
+ let state = &STATE[self.channel.id as usize];
+ state.waker.register(cx.waker());
if self.is_running() {
Poll::Pending
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 38945ac33..6b1ac6207 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -1,19 +1,10 @@
//! Direct Memory Access (DMA)
+#![macro_use]
-#[cfg(dma)]
-pub(crate) mod dma;
-#[cfg(dma)]
-pub use dma::*;
-
-// stm32h7 has both dma and bdma. In that case, we export dma as "main" dma,
-// and bdma as "secondary", under `embassy_stm32::dma::bdma`.
-#[cfg(all(bdma, dma))]
-pub mod bdma;
-
-#[cfg(all(bdma, not(dma)))]
-pub(crate) mod bdma;
-#[cfg(all(bdma, not(dma)))]
-pub use bdma::*;
+#[cfg(any(bdma, dma))]
+mod dma_bdma;
+#[cfg(any(bdma, dma))]
+pub use dma_bdma::*;
#[cfg(gpdma)]
pub(crate) mod gpdma;
@@ -22,16 +13,16 @@ pub use gpdma::*;
#[cfg(dmamux)]
mod dmamux;
+#[cfg(dmamux)]
+pub use dmamux::*;
pub(crate) mod ringbuffer;
pub mod word;
use core::mem;
-use embassy_hal_internal::impl_peripheral;
+use embassy_hal_internal::{impl_peripheral, Peripheral};
-#[cfg(dmamux)]
-pub use self::dmamux::*;
use crate::interrupt::Priority;
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
@@ -41,6 +32,73 @@ enum Dir {
PeripheralToMemory,
}
+/// DMA request type alias. (also known as DMA channel number in some chips)
+#[cfg(any(dma_v2, bdma_v2, gpdma, dmamux))]
+pub type Request = u8;
+/// DMA request type alias. (also known as DMA channel number in some chips)
+#[cfg(not(any(dma_v2, bdma_v2, gpdma, dmamux)))]
+pub type Request = ();
+
+pub(crate) mod sealed {
+ pub trait Channel {
+ fn id(&self) -> u8;
+ }
+ pub trait ChannelInterrupt {
+ unsafe fn on_irq();
+ }
+}
+
+/// DMA channel.
+pub trait Channel: sealed::Channel + Peripheral<P = Self> + Into<AnyChannel> + 'static {
+ /// Type-erase (degrade) this pin into an `AnyChannel`.
+ ///
+ /// This converts DMA channel singletons (`DMA1_CH3`, `DMA2_CH1`, ...), which
+ /// are all different types, into the same type. It is useful for
+ /// creating arrays of channels, or avoiding generics.
+ #[inline]
+ fn degrade(self) -> AnyChannel {
+ AnyChannel { id: self.id() }
+ }
+}
+
+macro_rules! dma_channel_impl {
+ ($channel_peri:ident, $index:expr) => {
+ impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
+ fn id(&self) -> u8 {
+ $index
+ }
+ }
+ impl crate::dma::sealed::ChannelInterrupt for crate::peripherals::$channel_peri {
+ unsafe fn on_irq() {
+ crate::dma::AnyChannel { id: $index }.on_irq();
+ }
+ }
+
+ impl crate::dma::Channel for crate::peripherals::$channel_peri {}
+
+ impl From<crate::peripherals::$channel_peri> for crate::dma::AnyChannel {
+ fn from(x: crate::peripherals::$channel_peri) -> Self {
+ crate::dma::Channel::degrade(x)
+ }
+ }
+ };
+}
+
+/// Type-erased DMA channel.
+pub struct AnyChannel {
+ pub(crate) id: u8,
+}
+impl_peripheral!(AnyChannel);
+
+impl AnyChannel {
+ fn info(&self) -> &ChannelInfo {
+ &crate::_generated::DMA_CHANNELS[self.id as usize]
+ }
+}
+
+const CHANNEL_COUNT: usize = crate::_generated::DMA_CHANNELS.len();
+static STATE: [ChannelState; CHANNEL_COUNT] = [ChannelState::NEW; CHANNEL_COUNT];
+
/// "No DMA" placeholder.
///
/// You may pass this in place of a real DMA channel when creating a driver
@@ -70,10 +128,14 @@ pub(crate) unsafe fn init(
#[cfg(dma)] dma_priority: Priority,
#[cfg(gpdma)] gpdma_priority: Priority,
) {
- #[cfg(bdma)]
- bdma::init(cs, bdma_priority);
- #[cfg(dma)]
- dma::init(cs, dma_priority);
+ #[cfg(any(dma, bdma))]
+ dma_bdma::init(
+ cs,
+ #[cfg(dma)]
+ dma_priority,
+ #[cfg(bdma)]
+ bdma_priority,
+ );
#[cfg(gpdma)]
gpdma::init(cs, gpdma_priority);
#[cfg(dmamux)]
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index 5e647612c..b6c3e4028 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -501,9 +501,9 @@ impl Config {
}
}
-enum RingBuffer<'d, C: Channel, W: word::Word> {
- Writable(WritableRingBuffer<'d, C, W>),
- Readable(ReadableRingBuffer<'d, C, W>),
+enum RingBuffer<'d, W: word::Word> {
+ Writable(WritableRingBuffer<'d, W>),
+ Readable(ReadableRingBuffer<'d, W>),
}
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
@@ -528,13 +528,13 @@ fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AFType, AFType) {
)
}
-fn get_ring_buffer<'d, T: Instance, C: Channel, W: word::Word>(
- dma: impl Peripheral<P = C> + 'd,
+fn get_ring_buffer<'d, T: Instance, W: word::Word>(
+ dma: impl Peripheral<P = impl Channel> + 'd,
dma_buf: &'d mut [W],
request: Request,
sub_block: WhichSubBlock,
tx_rx: TxRx,
-) -> RingBuffer<'d, C, W> {
+) -> RingBuffer<'d, W> {
let opts = TransferOptions {
half_transfer_ir: true,
//the new_write() and new_read() always use circular mode
@@ -593,17 +593,17 @@ pub fn split_subblocks<'d, T: Instance>(peri: impl Peripheral<P = T> + 'd) -> (S
}
/// SAI sub-block driver.
-pub struct Sai<'d, T: Instance, C: Channel, W: word::Word> {
+pub struct Sai<'d, T: Instance, W: word::Word> {
_peri: PeripheralRef<'d, T>,
sd: Option<PeripheralRef<'d, AnyPin>>,
fs: Option<PeripheralRef<'d, AnyPin>>,
sck: Option<PeripheralRef<'d, AnyPin>>,
mclk: Option<PeripheralRef<'d, AnyPin>>,
- ring_buffer: RingBuffer<'d, C, W>,
+ ring_buffer: RingBuffer<'d, W>,
sub_block: WhichSubBlock,
}
-impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
+impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
/// Create a new SAI driver in asynchronous mode with MCLK.
///
/// You can obtain the [`SubBlock`] with [`split_subblocks`].
@@ -613,13 +613,10 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
fs: impl Peripheral<P = impl FsPin<T, S>> + 'd,
mclk: impl Peripheral<P = impl MclkPin<T, S>> + 'd,
- dma: impl Peripheral<P = C> + 'd,
+ dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
dma_buf: &'d mut [W],
mut config: Config,
- ) -> Self
- where
- C: Channel + Dma<T, S>,
- {
+ ) -> Self {
into_ref!(mclk);
let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
@@ -642,13 +639,10 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
sck: impl Peripheral<P = impl SckPin<T, S>> + 'd,
sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
fs: impl Peripheral<P = impl FsPin<T, S>> + 'd,
- dma: impl Peripheral<P = C> + 'd,
+ dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
dma_buf: &'d mut [W],
config: Config,
- ) -> Self
- where
- C: Channel + Dma<T, S>,
- {
+ ) -> Self {
let peri = peri.peri;
into_ref!(peri, dma, sck, sd, fs);
@@ -671,7 +665,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
None,
Some(sd.map_into()),
Some(fs.map_into()),
- get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
+ get_ring_buffer::<T, W>(dma, dma_buf, request, sub_block, config.tx_rx),
config,
)
}
@@ -682,13 +676,10 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
pub fn new_synchronous<S: SubBlockInstance>(
peri: SubBlock<'d, T, S>,
sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
- dma: impl Peripheral<P = C> + 'd,
+ dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
dma_buf: &'d mut [W],
mut config: Config,
- ) -> Self
- where
- C: Channel + Dma<T, S>,
- {
+ ) -> Self {
update_synchronous_config(&mut config);
let peri = peri.peri;
@@ -709,7 +700,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
None,
Some(sd.map_into()),
None,
- get_ring_buffer::<T, C, W>(dma, dma_buf, request, sub_block, config.tx_rx),
+ get_ring_buffer::<T, W>(dma, dma_buf, request, sub_block, config.tx_rx),
config,
)
}
@@ -721,7 +712,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
mclk: Option<PeripheralRef<'d, AnyPin>>,
sd: Option<PeripheralRef<'d, AnyPin>>,
fs: Option<PeripheralRef<'d, AnyPin>>,
- ring_buffer: RingBuffer<'d, C, W>,
+ ring_buffer: RingBuffer<'d, W>,
config: Config,
) -> Self {
#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
@@ -830,7 +821,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
}
}
- fn is_transmitter(ring_buffer: &RingBuffer<C, W>) -> bool {
+ fn is_transmitter(ring_buffer: &RingBuffer<W>) -> bool {
match ring_buffer {
RingBuffer::Writable(_) => true,
_ => false,
@@ -889,7 +880,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> Sai<'d, T, C, W> {
}
}
-impl<'d, T: Instance, C: Channel, W: word::Word> Drop for Sai<'d, T, C, W> {
+impl<'d, T: Instance, W: word::Word> Drop for Sai<'d, T, W> {
fn drop(&mut self) {
let ch = T::REGS.ch(self.sub_block as usize);
ch.cr1().modify(|w| w.set_saien(false));
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 61589a215..bf1d2ca9b 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -228,10 +228,10 @@ fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u16, Hertz), Error> {
}
#[cfg(sdmmc_v1)]
-type Transfer<'a, C> = crate::dma::Transfer<'a, C>;
+type Transfer<'a> = crate::dma::Transfer<'a>;
#[cfg(sdmmc_v2)]
-struct Transfer<'a, C> {
- _dummy: core::marker::PhantomData<&'a mut C>,
+struct Transfer<'a> {
+ _dummy: PhantomData<&'a ()>,
}
#[cfg(all(sdmmc_v1, dma))]
@@ -548,7 +548,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
buffer: &'a mut [u32],
length_bytes: u32,
block_size: u8,
- ) -> Transfer<'a, Dma> {
+ ) -> Transfer<'a> {
assert!(block_size <= 14, "Block size up to 2^14 bytes");
let regs = T::regs();
@@ -596,12 +596,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
/// # Safety
///
/// `buffer` must be valid for the whole transfer and word aligned
- fn prepare_datapath_write<'a>(
- &'a mut self,
- buffer: &'a [u32],
- length_bytes: u32,
- block_size: u8,
- ) -> Transfer<'a, Dma> {
+ fn prepare_datapath_write<'a>(&'a mut self, buffer: &'a [u32], length_bytes: u32, block_size: u8) -> Transfer<'a> {
assert!(block_size <= 14, "Block size up to 2^14 bytes");
let regs = T::regs();
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index a0ab060a3..b852f0176 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -7,19 +7,19 @@ use embassy_embedded_hal::SetConfig;
use embassy_hal_internal::PeripheralRef;
use futures::future::{select, Either};
-use super::{clear_interrupt_flags, rdr, reconfigure, sr, BasicInstance, Config, ConfigError, Error, RxDma, UartRx};
+use super::{clear_interrupt_flags, rdr, reconfigure, sr, BasicInstance, Config, ConfigError, Error, UartRx};
use crate::dma::ReadableRingBuffer;
use crate::usart::{Regs, Sr};
/// Rx-only Ring-buffered UART Driver
///
/// Created with [UartRx::into_ring_buffered]
-pub struct RingBufferedUartRx<'d, T: BasicInstance, RxDma: super::RxDma<T>> {
+pub struct RingBufferedUartRx<'d, T: BasicInstance> {
_peri: PeripheralRef<'d, T>,
- ring_buf: ReadableRingBuffer<'d, RxDma, u8>,
+ ring_buf: ReadableRingBuffer<'d, u8>,
}
-impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> SetConfig for RingBufferedUartRx<'d, T, RxDma> {
+impl<'d, T: BasicInstance> SetConfig for RingBufferedUartRx<'d, T> {
type Config = Config;
type ConfigError = ConfigError;
@@ -32,7 +32,7 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> UartRx<'d, T, RxDma> {
/// Turn the `UartRx` into a buffered uart which can continously receive in the background
/// without the possibility of losing bytes. The `dma_buf` is a buffer registered to the
/// DMA controller, and must be large enough to prevent overflows.
- pub fn into_ring_buffered(self, dma_buf: &'d mut [u8]) -> RingBufferedUartRx<'d, T, RxDma> {
+ pub fn into_ring_buffered(self, dma_buf: &'d mut [u8]) -> RingBufferedUartRx<'d, T> {
assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
let request = self.rx_dma.request();
@@ -51,7 +51,7 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> UartRx<'d, T, RxDma> {
}
}
-impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> RingBufferedUartRx<'d, T, RxDma> {
+impl<'d, T: BasicInstance> RingBufferedUartRx<'d, T> {
/// Clear the ring buffer and start receiving in the background
pub fn start(&mut self) -> Result<(), Error> {
// Clear the ring buffer so that it is ready to receive data
@@ -208,7 +208,7 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> RingBufferedUartRx<'d, T, RxD
}
}
-impl<T: BasicInstance, RxDma: super::RxDma<T>> Drop for RingBufferedUartRx<'_, T, RxDma> {
+impl<T: BasicInstance> Drop for RingBufferedUartRx<'_, T> {
fn drop(&mut self) {
self.teardown_uart();
@@ -245,18 +245,16 @@ fn clear_idle_flag(r: Regs) -> Sr {
sr
}
-impl<T, Rx> embedded_io_async::ErrorType for RingBufferedUartRx<'_, T, Rx>
+impl<T> embedded_io_async::ErrorType for RingBufferedUartRx<'_, T>
where
T: BasicInstance,
- Rx: RxDma<T>,
{
type Error = Error;
}
-impl<T, Rx> embedded_io_async::Read for RingBufferedUartRx<'_, T, Rx>
+impl<T> embedded_io_async::Read for RingBufferedUartRx<'_, T>
where
T: BasicInstance,
- Rx: RxDma<T>,
{
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
self.read(buf).await
diff --git a/tests/stm32/src/bin/usart_rx_ringbuffered.rs b/tests/stm32/src/bin/usart_rx_ringbuffered.rs
index f5d618db4..0c110421d 100644
--- a/tests/stm32/src/bin/usart_rx_ringbuffered.rs
+++ b/tests/stm32/src/bin/usart_rx_ringbuffered.rs
@@ -74,7 +74,7 @@ async fn transmit_task(mut tx: UartTx<'static, peris::UART, peris::UART_TX_DMA>)
}
#[embassy_executor::task]
-async fn receive_task(mut rx: RingBufferedUartRx<'static, peris::UART, peris::UART_RX_DMA>) {
+async fn receive_task(mut rx: RingBufferedUartRx<'static, peris::UART>) {
info!("Ready to receive...");
let mut rng = ChaCha8Rng::seed_from_u64(1337);
From e79d2dd7561c0acfb2eb81ea95929c1ca8ba1b77 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sat, 24 Feb 2024 12:54:58 -0800
Subject: [PATCH 298/392] Move to internal mod and re-export the enums
---
embassy-stm32/build.rs | 37 +++++++++++++++++++------------
embassy-stm32/src/rcc/f013.rs | 14 +++++-------
embassy-stm32/src/rcc/mod.rs | 2 +-
examples/stm32f334/src/bin/pwm.rs | 4 +---
4 files changed, 31 insertions(+), 26 deletions(-)
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index a0b74c0b9..64d8afa13 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -601,7 +601,7 @@ fn main() {
.iter()
.map(|(_fieldset, fieldname, enum_name)| {
quote! {
- pub #fieldname: Option<crate::pac::rcc::vals::#enum_name>
+ pub #fieldname: Option<#enum_name>
}
})
.collect();
@@ -627,23 +627,32 @@ fn main() {
})
.collect();
- g.extend(quote! {
- #[derive(Clone, Copy)]
- pub struct ClockMux {
- #( #struct_fields, )*
- }
+ let enum_names: BTreeSet<_> = rcc_cfgr_regs
+ .iter()
+ .map(|(_fieldset, _fieldname, enum_name)| enum_name)
+ .collect();
- impl Default for ClockMux {
- fn default() -> Self {
- Self {
- #( #field_names: None, )*
+ g.extend(quote! {
+ pub mod mux {
+ #(pub use crate::pac::rcc::vals::#enum_names as #enum_names; )*
+
+ #[derive(Clone, Copy)]
+ pub struct ClockMux {
+ #( #struct_fields, )*
+ }
+
+ impl Default for ClockMux {
+ fn default() -> Self {
+ Self {
+ #( #field_names: None, )*
+ }
}
}
- }
- impl ClockMux {
- pub fn init(self) {
- #( #inits )*
+ impl ClockMux {
+ pub fn init(self) {
+ #( #inits )*
+ }
}
}
});
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 86af4bd68..de209272d 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -97,10 +97,9 @@ pub struct Config {
pub adc: AdcClockSource,
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
pub adc34: AdcClockSource,
- #[cfg(stm32f334)]
- pub hrtim: HrtimClockSource,
+
#[cfg(clock_mux)]
- pub mux: crate::rcc::ClockMux,
+ pub mux: crate::rcc::mux::ClockMux,
pub ls: super::LsConfig,
}
@@ -128,8 +127,7 @@ impl Default for Config {
adc: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
- #[cfg(stm32f334)]
- hrtim: HrtimClockSource::BusClk,
+
#[cfg(clock_mux)]
mux: Default::default(),
}
@@ -350,7 +348,8 @@ pub(crate) unsafe fn init(config: Config) {
}
};
- #[cfg(stm32f334)]
+ /*
+ TODO: Maybe add something like this to clock_mux? How can we autogenerate the data for this?
let hrtim = match config.hrtim {
// Must be configured after the bus is ready, otherwise it won't work
HrtimClockSource::BusClk => None,
@@ -366,6 +365,7 @@ pub(crate) unsafe fn init(config: Config) {
Some(pll * 2u32)
}
};
+ */
#[cfg(clock_mux)]
config.mux.init();
@@ -384,8 +384,6 @@ pub(crate) unsafe fn init(config: Config) {
adc: Some(adc),
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
adc34: Some(adc34),
- #[cfg(stm32f334)]
- hrtim: hrtim,
rtc: rtc,
hsi48: hsi48,
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 24516d426..b5a8bc2a4 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -32,7 +32,7 @@ mod _version;
pub use _version::*;
#[cfg(clock_mux)]
-pub use crate::_generated::ClockMux;
+pub use crate::_generated::mux as mux;
pub use crate::_generated::Clocks;
#[cfg(feature = "low-power")]
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index cf5eb7b26..7c6d6cd71 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -28,9 +28,7 @@ async fn main(_spawner: Spawner) {
config.rcc.apb1_pre = APBPrescaler::DIV2;
config.rcc.apb2_pre = APBPrescaler::DIV1;
- // TODO: The two lines here do the same thing
- config.rcc.hrtim = HrtimClockSource::PllClk;
- config.rcc.mux.hrtim1sw = Some(embassy_stm32::pac::rcc::vals::Timsw::PLL1_P);
+ config.rcc.mux.hrtim1sw = Some(embassy_stm32::rcc::mux::Timsw::PLL1_P);
}
let p = embassy_stm32::init(config);
From 394abda092cac80c875998c429f629caa289f9d1 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sat, 24 Feb 2024 12:58:38 -0800
Subject: [PATCH 299/392] Fix report with the same name
---
embassy-stm32/src/rcc/mod.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index b5a8bc2a4..c8ca713de 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -32,7 +32,7 @@ mod _version;
pub use _version::*;
#[cfg(clock_mux)]
-pub use crate::_generated::mux as mux;
+pub use crate::_generated::mux;
pub use crate::_generated::Clocks;
#[cfg(feature = "low-power")]
From 2d634d07e08650caf2c2940343a1a63e0bc66f05 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <corey@schuhen.net>
Date: Sat, 24 Feb 2024 18:31:05 +1000
Subject: [PATCH 300/392] FDCAN: Remove extra traits from.
Comments
Fix.
---
embassy-stm32/src/can/fdcan.rs | 47 ++++++++++++++--------------------
1 file changed, 19 insertions(+), 28 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index f1f6f935e..fc5d47ab7 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -861,22 +861,13 @@ pub(crate) mod sealed {
}
}
-/// Trait for FDCAN interrupt channel 0
-pub trait IT0Instance {
- /// Type for FDCAN interrupt channel 0
+/// Instance trait
+pub trait Instance: sealed::Instance + RccPeripheral + 'static {
+ /// Interrupt 0
type IT0Interrupt: crate::interrupt::typelevel::Interrupt;
-}
-
-/// Trait for FDCAN interrupt channel 1
-pub trait IT1Instance {
- /// Type for FDCAN interrupt channel 1
+ /// Interrupt 0
type IT1Interrupt: crate::interrupt::typelevel::Interrupt;
}
-
-/// InterruptableInstance trait
-pub trait InterruptableInstance: IT0Instance + IT1Instance {}
-/// Instance trait
-pub trait Instance: sealed::Instance + RccPeripheral + InterruptableInstance + 'static {}
/// Fdcan Instance struct
pub struct FdcanInstance<'a, T>(PeripheralRef<'a, T>);
@@ -921,22 +912,22 @@ fn calc_timestamp(_ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
}
- impl Instance for peripherals::$inst {}
+ #[allow(non_snake_case)]
+ pub(crate) mod $inst {
- foreach_interrupt!(
- ($inst,can,FDCAN,IT0,$irq:ident) => {
- impl IT0Instance for peripherals::$inst {
- type IT0Interrupt = crate::interrupt::typelevel::$irq;
- }
- };
- ($inst,can,FDCAN,IT1,$irq:ident) => {
- impl IT1Instance for peripherals::$inst {
- type IT1Interrupt = crate::interrupt::typelevel::$irq;
- }
- };
- );
-
- impl InterruptableInstance for peripherals::$inst {}
+ foreach_interrupt!(
+ ($inst,can,FDCAN,IT0,$irq:ident) => {
+ pub type Interrupt0 = crate::interrupt::typelevel::$irq;
+ };
+ ($inst,can,FDCAN,IT1,$irq:ident) => {
+ pub type Interrupt1 = crate::interrupt::typelevel::$irq;
+ };
+ );
+ }
+ impl Instance for peripherals::$inst {
+ type IT0Interrupt = $inst::Interrupt0;
+ type IT1Interrupt = $inst::Interrupt1;
+ }
};
($inst:ident, $msg_ram_inst:ident) => {
From 779898c0e74d850f324528d2b2db3c9d76ec86d1 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <corey@schuhen.net>
Date: Sat, 24 Feb 2024 20:13:52 +1000
Subject: [PATCH 301/392] FDCAN: Expose some pub types in API
---
embassy-stm32/src/can/fdcan.rs | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index fc5d47ab7..817ee2115 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -18,16 +18,18 @@ use crate::{interrupt, peripherals, Peripheral};
pub mod enums;
use enums::*;
-pub mod util;
+mod util;
pub mod frame;
use frame::*;
+/// Timestamp for incoming packets. Use Embassy time when enabled.
#[cfg(feature = "time")]
-type Timestamp = embassy_time::Instant;
+pub type Timestamp = embassy_time::Instant;
+/// Timestamp for incoming packets.
#[cfg(not(feature = "time"))]
-type Timestamp = u16;
+pub type Timestamp = u16;
/// Interrupt handler channel 0.
pub struct IT0InterruptHandler<T: Instance> {
@@ -139,7 +141,8 @@ pub enum FdcanOperatingMode {
//TestMode,
}
-/// FDCAN Instance
+/// FDCAN Configuration instance instance
+/// Create instance of this first
pub struct FdcanConfigurator<'d, T: Instance> {
config: crate::can::fd::config::FdCanConfig,
/// Reference to internals.
@@ -868,6 +871,7 @@ pub trait Instance: sealed::Instance + RccPeripheral + 'static {
/// Interrupt 0
type IT1Interrupt: crate::interrupt::typelevel::Interrupt;
}
+
/// Fdcan Instance struct
pub struct FdcanInstance<'a, T>(PeripheralRef<'a, T>);
From a061cf31334d7c1912528edecb4738c84d98e17a Mon Sep 17 00:00:00 2001
From: Corey Schuhen <corey@schuhen.net>
Date: Sat, 24 Feb 2024 20:23:34 +1000
Subject: [PATCH 302/392] FDCAN: Allow access to buffered senders and
receivers.
---
embassy-stm32/src/can/fdcan.rs | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 817ee2115..d290295f5 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -434,6 +434,12 @@ pub struct BufferedCan<'d, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_S
rx_buf: &'static RxBuf<RX_BUF_SIZE>,
}
+/// Sender that can be used for sending CAN frames.
+pub type BufferedCanSender = embassy_sync::channel::DynamicSender<'static, ClassicFrame>;
+
+/// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
+pub type BufferedCanReceiver = embassy_sync::channel::DynamicReceiver<'static, (ClassicFrame, Timestamp)>;
+
impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
BufferedCan<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
{
@@ -479,6 +485,16 @@ impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
Ok(self.rx_buf.receive().await)
}
+
+ /// Returns a sender that can be used for sending CAN frames.
+ pub fn writer(&self) -> BufferedCanSender {
+ self.tx_buf.sender().into()
+ }
+
+ /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
+ pub fn reader(&self) -> BufferedCanReceiver {
+ self.rx_buf.receiver().into()
+ }
}
impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
@@ -507,6 +523,12 @@ pub struct BufferedCanFd<'d, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF
rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
}
+/// Sender that can be used for sending CAN frames.
+pub type BufferedFdCanSender = embassy_sync::channel::DynamicSender<'static, FdFrame>;
+
+/// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
+pub type BufferedFdCanReceiver = embassy_sync::channel::DynamicReceiver<'static, (FdFrame, Timestamp)>;
+
impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
BufferedCanFd<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
{
@@ -552,6 +574,16 @@ impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
pub async fn read(&mut self) -> Result<(FdFrame, Timestamp), BusError> {
Ok(self.rx_buf.receive().await)
}
+
+ /// Returns a sender that can be used for sending CAN frames.
+ pub fn writer(&self) -> BufferedFdCanSender {
+ self.tx_buf.sender().into()
+ }
+
+ /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
+ pub fn reader(&self) -> BufferedFdCanReceiver {
+ self.rx_buf.receiver().into()
+ }
}
impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop
From 0565098b06f73b542369c4d4f97f34c78e9bd058 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <corey@schuhen.net>
Date: Sun, 25 Feb 2024 08:57:18 +1000
Subject: [PATCH 303/392] FDCAN: Fix some indenting in macros
---
embassy-stm32/src/can/fdcan.rs | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index d290295f5..4b76cc34d 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -929,22 +929,22 @@ macro_rules! impl_fdcan {
unsafe { peripherals::$inst::mut_state() }
}
-#[cfg(feature = "time")]
-fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
- let now_embassy = embassy_time::Instant::now();
- if ns_per_timer_tick == 0 {
- return now_embassy;
- }
- let cantime = { Self::regs().tscv().read().tsc() };
- let delta = cantime.overflowing_sub(ts_val).0 as u64;
- let ns = ns_per_timer_tick * delta as u64;
- now_embassy - embassy_time::Duration::from_nanos(ns)
-}
+ #[cfg(feature = "time")]
+ fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
+ let now_embassy = embassy_time::Instant::now();
+ if ns_per_timer_tick == 0 {
+ return now_embassy;
+ }
+ let cantime = { Self::regs().tscv().read().tsc() };
+ let delta = cantime.overflowing_sub(ts_val).0 as u64;
+ let ns = ns_per_timer_tick * delta as u64;
+ now_embassy - embassy_time::Duration::from_nanos(ns)
+ }
-#[cfg(not(feature = "time"))]
-fn calc_timestamp(_ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
- ts_val
-}
+ #[cfg(not(feature = "time"))]
+ fn calc_timestamp(_ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
+ ts_val
+ }
}
From 1327a644b6194093e732372d2aab571214ef5717 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <corey@schuhen.net>
Date: Sun, 25 Feb 2024 09:57:30 +1000
Subject: [PATCH 304/392] FDCAN: Don't require internal module for public API.
---
embassy-stm32/src/can/fdcan.rs | 11 ++++++-----
examples/stm32g4/src/bin/can.rs | 4 ++--
tests/stm32/src/bin/fdcan.rs | 4 ++--
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 4b76cc34d..744d756f5 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -3,12 +3,9 @@ use core::future::poll_fn;
use core::marker::PhantomData;
use core::task::Poll;
-pub mod fd;
use embassy_hal_internal::{into_ref, PeripheralRef};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::channel::Channel;
-use fd::config::*;
-use fd::filter::*;
use crate::can::fd::peripheral::Registers;
use crate::gpio::sealed::AFType;
@@ -17,10 +14,14 @@ use crate::rcc::RccPeripheral;
use crate::{interrupt, peripherals, Peripheral};
pub mod enums;
-use enums::*;
+pub(crate) mod fd;
+pub mod frame;
mod util;
-pub mod frame;
+use enums::*;
+use fd::config::*;
+use fd::filter::*;
+pub use fd::{config, filter};
use frame::*;
/// Timestamp for incoming packets. Use Embassy time when enabled.
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
index affa97039..a41f765c1 100644
--- a/examples/stm32g4/src/bin/can.rs
+++ b/examples/stm32g4/src/bin/can.rs
@@ -22,8 +22,8 @@ async fn main(_spawner: Spawner) {
let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
can.set_extended_filter(
- can::fd::filter::ExtendedFilterSlot::_0,
- can::fd::filter::ExtendedFilter::accept_all_into_fifo1(),
+ can::filter::ExtendedFilterSlot::_0,
+ can::filter::ExtendedFilter::accept_all_into_fifo1(),
);
// 250k bps
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
index 398e31ffc..f21aa797c 100644
--- a/tests/stm32/src/bin/fdcan.rs
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -81,8 +81,8 @@ async fn main(_spawner: Spawner) {
can.set_bitrate(250_000);
can.set_extended_filter(
- can::fd::filter::ExtendedFilterSlot::_0,
- can::fd::filter::ExtendedFilter::accept_all_into_fifo1(),
+ can::filter::ExtendedFilterSlot::_0,
+ can::filter::ExtendedFilter::accept_all_into_fifo1(),
);
let mut can = can.into_internal_loopback_mode();
From a737a7350e6aa42b867679dbb21c2d6fb8b22b91 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <corey@schuhen.net>
Date: Sun, 25 Feb 2024 10:00:17 +1000
Subject: [PATCH 305/392] FDCAN: Remove history from comments.
---
embassy-stm32/src/can/fd/config.rs | 2 +-
embassy-stm32/src/can/fd/filter.rs | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index 38b409121..f2401d92f 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -1,5 +1,5 @@
//! Configuration for FDCAN Module
-//! Note: This file is copied and modified from fdcan crate by Richard Meadows
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
use core::num::{NonZeroU16, NonZeroU8};
diff --git a/embassy-stm32/src/can/fd/filter.rs b/embassy-stm32/src/can/fd/filter.rs
index 3e2129e6e..2023a2ef0 100644
--- a/embassy-stm32/src/can/fd/filter.rs
+++ b/embassy-stm32/src/can/fd/filter.rs
@@ -1,5 +1,5 @@
//! Definition of Filter structs for FDCAN Module
-//! Note: This file is copied and modified from fdcan crate by Richard Meadows
+// Note: This file is copied and modified from fdcan crate by Richard Meadows
use embedded_can::{ExtendedId, StandardId};
From 489d0be2a2971cfae7d6413b601bbd044d42e351 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 26 Feb 2024 00:00:17 +0100
Subject: [PATCH 306/392] stm32/rcc: unify naming sysclk field to `sys`, enum
to `Sysclk`.
---
embassy-stm32/src/rcc/c0.rs | 14 +++++-----
embassy-stm32/src/rcc/g0.rs | 16 ++++++------
embassy-stm32/src/rcc/l.rs | 26 +++++++++----------
embassy-stm32/src/rcc/u5.rs | 20 +++++++-------
embassy-stm32/src/rcc/wba.rs | 24 ++++++++---------
examples/stm32g0/src/bin/hf_timer.rs | 4 +--
examples/stm32l1/src/bin/usb_serial.rs | 2 +-
examples/stm32l4/src/bin/rng.rs | 4 +--
examples/stm32l4/src/bin/rtc.rs | 2 +-
.../src/bin/spe_adin1110_http_server.rs | 2 +-
examples/stm32l4/src/bin/usb_serial.rs | 2 +-
examples/stm32l5/src/bin/rng.rs | 4 +--
examples/stm32l5/src/bin/usb_ethernet.rs | 2 +-
examples/stm32l5/src/bin/usb_hid_mouse.rs | 2 +-
examples/stm32l5/src/bin/usb_serial.rs | 2 +-
examples/stm32u5/src/bin/usb_serial.rs | 2 +-
examples/stm32wl/src/bin/random.rs | 2 +-
examples/stm32wl/src/bin/rtc.rs | 2 +-
examples/stm32wl/src/bin/uart_async.rs | 2 +-
tests/stm32/src/common.rs | 14 +++++-----
20 files changed, 74 insertions(+), 74 deletions(-)
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index ca1222185..ec6ec34e8 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -9,7 +9,7 @@ pub const HSI_FREQ: Hertz = Hertz(48_000_000);
/// System clock mux source
#[derive(Clone, Copy)]
-pub enum ClockSrc {
+pub enum Sysclk {
HSE(Hertz),
HSI(HSIPrescaler),
LSI,
@@ -17,7 +17,7 @@ pub enum ClockSrc {
/// Clocks configutation
pub struct Config {
- pub mux: ClockSrc,
+ pub sys: Sysclk,
pub ahb_pre: AHBPrescaler,
pub apb_pre: APBPrescaler,
pub ls: super::LsConfig,
@@ -27,7 +27,7 @@ impl Default for Config {
#[inline]
fn default() -> Config {
Config {
- mux: ClockSrc::HSI(HSIPrescaler::DIV1),
+ sys: Sysclk::HSI(HSIPrescaler::DIV1),
ahb_pre: AHBPrescaler::DIV1,
apb_pre: APBPrescaler::DIV1,
ls: Default::default(),
@@ -36,8 +36,8 @@ impl Default for Config {
}
pub(crate) unsafe fn init(config: Config) {
- let (sys_clk, sw) = match config.mux {
- ClockSrc::HSI(div) => {
+ let (sys_clk, sw) = match config.sys {
+ Sysclk::HSI(div) => {
// Enable HSI
RCC.cr().write(|w| {
w.set_hsidiv(div);
@@ -47,14 +47,14 @@ pub(crate) unsafe fn init(config: Config) {
(HSI_FREQ / div, Sw::HSI)
}
- ClockSrc::HSE(freq) => {
+ Sysclk::HSE(freq) => {
// Enable HSE
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
(freq, Sw::HSE)
}
- ClockSrc::LSI => {
+ Sysclk::LSI => {
// Enable LSI
RCC.csr2().write(|w| w.set_lsion(true));
while !RCC.csr2().read().lsirdy() {}
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index e3cd46fb9..0b1f34a20 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -19,7 +19,7 @@ pub enum HseMode {
/// System clock mux source
#[derive(Clone, Copy)]
-pub enum ClockSrc {
+pub enum Sysclk {
HSE(Hertz, HseMode),
HSI(HSIPrescaler),
PLL(PllConfig),
@@ -89,7 +89,7 @@ pub enum UsbSrc {
/// Clocks configutation
pub struct Config {
- pub mux: ClockSrc,
+ pub sys: Sysclk,
pub ahb_pre: AHBPrescaler,
pub apb_pre: APBPrescaler,
pub low_power_run: bool,
@@ -102,7 +102,7 @@ impl Default for Config {
#[inline]
fn default() -> Config {
Config {
- mux: ClockSrc::HSI(HSIPrescaler::DIV1),
+ sys: Sysclk::HSI(HSIPrescaler::DIV1),
ahb_pre: AHBPrescaler::DIV1,
apb_pre: APBPrescaler::DIV1,
low_power_run: false,
@@ -202,8 +202,8 @@ pub(crate) unsafe fn init(config: Config) {
let mut pll1_q_freq = None;
let mut pll1_p_freq = None;
- let (sys_clk, sw) = match config.mux {
- ClockSrc::HSI(div) => {
+ let (sys_clk, sw) = match config.sys {
+ Sysclk::HSI(div) => {
// Enable HSI
RCC.cr().write(|w| {
w.set_hsidiv(div);
@@ -213,7 +213,7 @@ pub(crate) unsafe fn init(config: Config) {
(HSI_FREQ / div, Sw::HSI)
}
- ClockSrc::HSE(freq, mode) => {
+ Sysclk::HSE(freq, mode) => {
// Enable HSE
RCC.cr().write(|w| {
w.set_hseon(true);
@@ -223,7 +223,7 @@ pub(crate) unsafe fn init(config: Config) {
(freq, Sw::HSE)
}
- ClockSrc::PLL(pll) => {
+ Sysclk::PLL(pll) => {
let (r_freq, q_freq, p_freq) = pll.init();
pll1_q_freq = q_freq;
@@ -231,7 +231,7 @@ pub(crate) unsafe fn init(config: Config) {
(r_freq, Sw::PLL1_R)
}
- ClockSrc::LSI => {
+ Sysclk::LSI => {
// Enable LSI
RCC.csr().write(|w| w.set_lsion(true));
while !RCC.csr().read().lsirdy() {}
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 04ea81ec4..aa4245d4e 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -7,7 +7,7 @@ pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
#[cfg(any(stm32wb, stm32wl))]
pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
-pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc};
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as Sysclk};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
@@ -50,7 +50,7 @@ pub struct Config {
pub pllsai2: Option<Pll>,
// sysclk, buses.
- pub mux: ClockSrc,
+ pub sys: Sysclk,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
@@ -80,7 +80,7 @@ impl Default for Config {
hse: None,
hsi: false,
msi: Some(MSIRange::RANGE4M),
- mux: ClockSrc::MSI,
+ sys: Sysclk::MSI,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
@@ -113,7 +113,7 @@ pub const WPAN_DEFAULT: Config = Config {
mode: HseMode::Oscillator,
prescaler: HsePrescaler::DIV1,
}),
- mux: ClockSrc::PLL1_R,
+ sys: Sysclk::PLL1_R,
#[cfg(crs)]
hsi48: Some(super::Hsi48Config { sync_from_usb: false }),
msi: None,
@@ -161,11 +161,11 @@ pub(crate) unsafe fn init(config: Config) {
// Turn on MSI and configure it to 4MHz.
msi_enable(MSIRange::RANGE4M)
}
- if RCC.cfgr().read().sws() != ClockSrc::MSI {
+ if RCC.cfgr().read().sws() != Sysclk::MSI {
// Set MSI as a clock source, reset prescalers.
RCC.cfgr().write_value(Cfgr::default());
// Wait for clock switch status bits to change.
- while RCC.cfgr().read().sws() != ClockSrc::MSI {}
+ while RCC.cfgr().read().sws() != Sysclk::MSI {}
}
// Set voltage scale
@@ -260,11 +260,11 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
let pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
- let sys_clk = match config.mux {
- ClockSrc::HSE => hse.unwrap(),
- ClockSrc::HSI => hsi.unwrap(),
- ClockSrc::MSI => msi.unwrap(),
- ClockSrc::PLL1_R => pll.r.unwrap(),
+ let sys_clk = match config.sys {
+ Sysclk::HSE => hse.unwrap(),
+ Sysclk::HSI => hsi.unwrap(),
+ Sysclk::MSI => msi.unwrap(),
+ Sysclk::PLL1_R => pll.r.unwrap(),
};
#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
@@ -350,12 +350,12 @@ pub(crate) unsafe fn init(config: Config) {
while FLASH.acr().read().latency() != latency {}
RCC.cfgr().modify(|w| {
- w.set_sw(config.mux);
+ w.set_sw(config.sys);
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
- while RCC.cfgr().read().sws() != config.mux {}
+ while RCC.cfgr().read().sws() != config.sys {}
#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 72613f0f3..43138f05c 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -1,7 +1,7 @@
pub use crate::pac::pwr::vals::Vos as VoltageScale;
pub use crate::pac::rcc::vals::{
Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
- Pllsrc as PllSource, Ppre as APBPrescaler, Sw as ClockSrc,
+ Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
};
use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge};
use crate::pac::{FLASH, PWR, RCC};
@@ -72,7 +72,7 @@ pub struct Config {
pub pll3: Option<Pll>,
// sysclk, buses.
- pub mux: ClockSrc,
+ pub sys: Sysclk,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
@@ -97,7 +97,7 @@ impl Default for Config {
pll1: None,
pll2: None,
pll3: None,
- mux: ClockSrc::MSIS,
+ sys: Sysclk::MSIS,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
@@ -181,11 +181,11 @@ pub(crate) unsafe fn init(config: Config) {
let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range);
let pll3 = init_pll(PllInstance::Pll3, config.pll3, &pll_input, config.voltage_range);
- let sys_clk = match config.mux {
- ClockSrc::HSE => hse.unwrap(),
- ClockSrc::HSI => hsi.unwrap(),
- ClockSrc::MSIS => msi.unwrap(),
- ClockSrc::PLL1_R => pll1.r.unwrap(),
+ let sys_clk = match config.sys {
+ Sysclk::HSE => hse.unwrap(),
+ Sysclk::HSI => hsi.unwrap(),
+ Sysclk::MSIS => msi.unwrap(),
+ Sysclk::PLL1_R => pll1.r.unwrap(),
};
// Do we need the EPOD booster to reach the target clock speed per § 10.5.4?
@@ -230,8 +230,8 @@ pub(crate) unsafe fn init(config: Config) {
});
// Switch the system clock source
- RCC.cfgr1().modify(|w| w.set_sw(config.mux));
- while RCC.cfgr1().read().sws() != config.mux {}
+ RCC.cfgr1().modify(|w| w.set_sw(config.sys));
+ while RCC.cfgr1().read().sws() != config.sys {}
// Configure the bus prescalers
RCC.cfgr2().modify(|w| {
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index fbf2d1cf9..9d5dcfc4b 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -1,7 +1,7 @@
pub use crate::pac::pwr::vals::Vos as VoltageScale;
use crate::pac::rcc::regs::Cfgr1;
pub use crate::pac::rcc::vals::{
- Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as ClockSrc,
+ Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk,
};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
@@ -23,7 +23,7 @@ pub struct Config {
pub hse: Option<Hse>,
// sysclk, buses.
- pub mux: ClockSrc,
+ pub sys: Sysclk,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
@@ -43,7 +43,7 @@ impl Default for Config {
Config {
hse: None,
hsi: true,
- mux: ClockSrc::HSI,
+ sys: Sysclk::HSI,
ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
@@ -65,11 +65,11 @@ pub(crate) unsafe fn init(config: Config) {
if !RCC.cr().read().hsion() {
hsi_enable()
}
- if RCC.cfgr1().read().sws() != ClockSrc::HSI {
+ if RCC.cfgr1().read().sws() != Sysclk::HSI {
// Set HSI as a clock source, reset prescalers.
RCC.cfgr1().write_value(Cfgr1::default());
// Wait for clock switch status bits to change.
- while RCC.cfgr1().read().sws() != ClockSrc::HSI {}
+ while RCC.cfgr1().read().sws() != Sysclk::HSI {}
}
// Set voltage scale
@@ -94,11 +94,11 @@ pub(crate) unsafe fn init(config: Config) {
HSE_FREQ
});
- let sys_clk = match config.mux {
- ClockSrc::HSE => hse.unwrap(),
- ClockSrc::HSI => hsi.unwrap(),
- ClockSrc::_RESERVED_1 => unreachable!(),
- ClockSrc::PLL1_R => todo!(),
+ let sys_clk = match config.sys {
+ Sysclk::HSE => hse.unwrap(),
+ Sysclk::HSI => hsi.unwrap(),
+ Sysclk::_RESERVED_1 => unreachable!(),
+ Sysclk::PLL1_R => todo!(),
};
assert!(sys_clk.0 <= 100_000_000);
@@ -142,9 +142,9 @@ pub(crate) unsafe fn init(config: Config) {
// TODO: Set the SRAM wait states
RCC.cfgr1().modify(|w| {
- w.set_sw(config.mux);
+ w.set_sw(config.sys);
});
- while RCC.cfgr1().read().sws() != config.mux {}
+ while RCC.cfgr1().read().sws() != config.sys {}
RCC.cfgr2().modify(|w| {
w.set_hpre(config.ahb_pre);
diff --git a/examples/stm32g0/src/bin/hf_timer.rs b/examples/stm32g0/src/bin/hf_timer.rs
index 78a779e29..3f63d0dfd 100644
--- a/examples/stm32g0/src/bin/hf_timer.rs
+++ b/examples/stm32g0/src/bin/hf_timer.rs
@@ -5,7 +5,7 @@ use defmt::info;
use embassy_executor::Spawner;
use embassy_stm32::gpio::OutputType;
use embassy_stm32::pac::rcc::vals::Tim1sel;
-use embassy_stm32::rcc::{ClockSrc, Config as RccConfig, PllConfig, PllSource, Pllm, Plln, Pllq, Pllr};
+use embassy_stm32::rcc::{Config as RccConfig, PllConfig, PllSource, Pllm, Plln, Pllq, Pllr, Sysclk};
use embassy_stm32::time::khz;
use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, ComplementaryPwmPin};
use embassy_stm32::timer::simple_pwm::PwmPin;
@@ -16,7 +16,7 @@ use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut rcc_config = RccConfig::default();
- rcc_config.mux = ClockSrc::PLL(PllConfig {
+ rcc_config.sys = Sysclk::PLL(PllConfig {
source: PllSource::HSI,
m: Pllm::DIV1,
n: Plln::MUL16,
diff --git a/examples/stm32l1/src/bin/usb_serial.rs b/examples/stm32l1/src/bin/usb_serial.rs
index 7b1e84cbc..f738ea358 100644
--- a/examples/stm32l1/src/bin/usb_serial.rs
+++ b/examples/stm32l1/src/bin/usb_serial.rs
@@ -27,7 +27,7 @@ async fn main(_spawner: Spawner) {
mul: PllMul::MUL6, // PLLVCO = 16*6 = 96Mhz
div: PllDiv::DIV3, // 32Mhz clock (16 * 6 / 3)
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
}
let p = embassy_stm32::init(config);
diff --git a/examples/stm32l4/src/bin/rng.rs b/examples/stm32l4/src/bin/rng.rs
index 638b3e9e4..14d0e3c1e 100644
--- a/examples/stm32l4/src/bin/rng.rs
+++ b/examples/stm32l4/src/bin/rng.rs
@@ -3,7 +3,7 @@
use defmt::*;
use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, PllSource};
+use embassy_stm32::rcc::{Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, PllSource, Sysclk};
use embassy_stm32::rng::Rng;
use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
use {defmt_rtt as _, panic_probe as _};
@@ -15,7 +15,7 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PllSource::HSI,
diff --git a/examples/stm32l4/src/bin/rtc.rs b/examples/stm32l4/src/bin/rtc.rs
index 526620bfb..a8a375ab4 100644
--- a/examples/stm32l4/src/bin/rtc.rs
+++ b/examples/stm32l4/src/bin/rtc.rs
@@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
{
use embassy_stm32::rcc::*;
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.hse = Some(Hse {
freq: Hertz::mhz(8),
mode: HseMode::Oscillator,
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 026a3a477..32bfab6eb 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -75,7 +75,7 @@ async fn main(spawner: Spawner) {
use embassy_stm32::rcc::*;
// 80Mhz clock (Source: 8 / SrcDiv: 1 * PllMul 20 / ClkDiv 2)
// 80MHz highest frequency for flash 0 wait.
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.hse = Some(Hse {
freq: Hertz::mhz(8),
mode: HseMode::Oscillator,
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index 8cc9a7aed..9247e56a1 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/rng.rs b/examples/stm32l5/src/bin/rng.rs
index 50da6c946..0a644e73d 100644
--- a/examples/stm32l5/src/bin/rng.rs
+++ b/examples/stm32l5/src/bin/rng.rs
@@ -3,7 +3,7 @@
use defmt::*;
use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllRDiv, PllSource};
+use embassy_stm32::rcc::{Pll, PllMul, PllPreDiv, PllRDiv, PllSource, Sysclk};
use embassy_stm32::rng::Rng;
use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
use {defmt_rtt as _, panic_probe as _};
@@ -16,7 +16,7 @@ bind_interrupts!(struct Irqs {
async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.hsi = true;
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
// 64Mhz clock (16 / 1 * 8 / 2)
source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/usb_ethernet.rs b/examples/stm32l5/src/bin/usb_ethernet.rs
index 88060b6b0..f6d8b16d0 100644
--- a/examples/stm32l5/src/bin/usb_ethernet.rs
+++ b/examples/stm32l5/src/bin/usb_ethernet.rs
@@ -45,7 +45,7 @@ async fn net_task(stack: &'static Stack<Device<'static, MTU>>) -> ! {
async fn main(spawner: Spawner) {
let mut config = Config::default();
config.rcc.hsi = true;
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
// 80Mhz clock (16 / 1 * 10 / 2)
source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/usb_hid_mouse.rs b/examples/stm32l5/src/bin/usb_hid_mouse.rs
index 7c8a8ebfb..c51ed96e0 100644
--- a/examples/stm32l5/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32l5/src/bin/usb_hid_mouse.rs
@@ -22,7 +22,7 @@ bind_interrupts!(struct Irqs {
async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.hsi = true;
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
// 80Mhz clock (16 / 1 * 10 / 2)
source: PllSource::HSI,
diff --git a/examples/stm32l5/src/bin/usb_serial.rs b/examples/stm32l5/src/bin/usb_serial.rs
index 75053ce4b..87987f2ce 100644
--- a/examples/stm32l5/src/bin/usb_serial.rs
+++ b/examples/stm32l5/src/bin/usb_serial.rs
@@ -20,7 +20,7 @@ bind_interrupts!(struct Irqs {
async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.hsi = true;
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
// 80Mhz clock (16 / 1 * 10 / 2)
source: PllSource::HSI,
diff --git a/examples/stm32u5/src/bin/usb_serial.rs b/examples/stm32u5/src/bin/usb_serial.rs
index 99cdeacc9..61851e5a2 100644
--- a/examples/stm32u5/src/bin/usb_serial.rs
+++ b/examples/stm32u5/src/bin/usb_serial.rs
@@ -32,7 +32,7 @@ async fn main(_spawner: Spawner) {
divq: None,
divr: Some(PllDiv::DIV1), // 160 MHz
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.voltage_range = VoltageScale::RANGE1;
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
}
diff --git a/examples/stm32wl/src/bin/random.rs b/examples/stm32wl/src/bin/random.rs
index 3610392be..8e9fe02b2 100644
--- a/examples/stm32wl/src/bin/random.rs
+++ b/examples/stm32wl/src/bin/random.rs
@@ -22,7 +22,7 @@ async fn main(_spawner: Spawner) {
mode: HseMode::Bypass,
prescaler: HsePrescaler::DIV1,
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs
index 4738d5770..0c26426ef 100644
--- a/examples/stm32wl/src/bin/rtc.rs
+++ b/examples/stm32wl/src/bin/rtc.rs
@@ -21,7 +21,7 @@ async fn main(_spawner: Spawner) {
mode: HseMode::Bypass,
prescaler: HsePrescaler::DIV1,
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
diff --git a/examples/stm32wl/src/bin/uart_async.rs b/examples/stm32wl/src/bin/uart_async.rs
index 8e545834c..3637243a0 100644
--- a/examples/stm32wl/src/bin/uart_async.rs
+++ b/examples/stm32wl/src/bin/uart_async.rs
@@ -20,7 +20,7 @@ but can be surely changed for your needs.
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = embassy_stm32::Config::default();
- config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE;
+ config.rcc.sys = embassy_stm32::rcc::Sysclk::HSE;
let p = embassy_stm32::init(config);
defmt::info!("Starting system");
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 1e6b1cce9..7b9585afd 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -527,7 +527,7 @@ pub fn config() -> Config {
#[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
{
use embassy_stm32::rcc::*;
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PllSource::HSI,
@@ -547,7 +547,7 @@ pub fn config() -> Config {
mode: HseMode::Bypass,
prescaler: HsePrescaler::DIV1,
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
@@ -562,7 +562,7 @@ pub fn config() -> Config {
{
use embassy_stm32::rcc::*;
config.rcc.hsi = true;
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
// 110Mhz clock (16 / 4 * 55 / 2)
source: PllSource::HSI,
@@ -586,7 +586,7 @@ pub fn config() -> Config {
divq: None,
divr: Some(PllDiv::DIV1), // 160 MHz
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
config.rcc.voltage_range = VoltageScale::RANGE1;
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
}
@@ -594,7 +594,7 @@ pub fn config() -> Config {
#[cfg(feature = "stm32wba52cg")]
{
use embassy_stm32::rcc::*;
- config.rcc.mux = ClockSrc::HSI;
+ config.rcc.sys = Sysclk::HSI;
embassy_stm32::pac::RCC.ccipr2().write(|w| {
w.set_rngsel(embassy_stm32::pac::rcc::vals::Rngsel::HSI);
@@ -610,7 +610,7 @@ pub fn config() -> Config {
mul: PllMul::MUL4,
div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
}
#[cfg(any(feature = "stm32l152re"))]
@@ -622,7 +622,7 @@ pub fn config() -> Config {
mul: PllMul::MUL4,
div: PllDiv::DIV2, // 32Mhz clock (16 * 4 / 2)
});
- config.rcc.mux = ClockSrc::PLL1_R;
+ config.rcc.sys = Sysclk::PLL1_R;
}
config
From c23b59bdc82a766549f8ba83b7d3b678b5080a3f Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sun, 25 Feb 2024 16:12:32 -0800
Subject: [PATCH 307/392] Add `pll1_p_mul_2` clock.
---
embassy-stm32/src/rcc/f013.rs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index de209272d..bbc76d086 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -209,6 +209,9 @@ pub(crate) unsafe fn init(config: Config) {
out_freq
});
+ #[cfg(stm32f3)]
+ let pll_mul_2 = pll.map(|pll| { pll * 2u32 });
+
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
let usb = match pll {
Some(Hertz(72_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1_5),
@@ -374,6 +377,8 @@ pub(crate) unsafe fn init(config: Config) {
hsi: hsi,
hse: hse,
pll1_p: pll,
+ #[cfg(stm32f3)]
+ pll1_p_mul_2: pll_mul_2,
sys: Some(sys),
pclk1: Some(pclk1),
pclk2: Some(pclk2),
From 7dbae799dc708734af53494f54b0e6f46468daf3 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sun, 25 Feb 2024 16:24:52 -0800
Subject: [PATCH 308/392] Rust FMT
---
embassy-stm32/src/rcc/f013.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index bbc76d086..2e9540c6a 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -210,7 +210,7 @@ pub(crate) unsafe fn init(config: Config) {
});
#[cfg(stm32f3)]
- let pll_mul_2 = pll.map(|pll| { pll * 2u32 });
+ let pll_mul_2 = pll.map(|pll| pll * 2u32 );
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
let usb = match pll {
From 2dfd66b7c4098dbde3c5beafae9de527cb6644e6 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sun, 25 Feb 2024 16:25:42 -0800
Subject: [PATCH 309/392] :facepalm:
---
embassy-stm32/src/rcc/f013.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 2e9540c6a..56bb2a0d9 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -210,7 +210,7 @@ pub(crate) unsafe fn init(config: Config) {
});
#[cfg(stm32f3)]
- let pll_mul_2 = pll.map(|pll| pll * 2u32 );
+ let pll_mul_2 = pll.map(|pll| pll * 2u32);
#[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
let usb = match pll {
From abde7891e3f763b356f86d6f0619c971bf0ef055 Mon Sep 17 00:00:00 2001
From: Eli Orona <eliorona@live.com>
Date: Sun, 25 Feb 2024 16:44:46 -0800
Subject: [PATCH 310/392] Update metapac version
---
embassy-stm32/Cargo.toml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index d585d2cd6..e0bee6a92 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6097928f720646c73d6483a3245f922bd5faee2f" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6097928f720646c73d6483a3245f922bd5faee2f", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4", default-features = false, features = ["metadata"]}
[features]
From 79e5e8b052b56f8c6fc07d8407fcfc3aaf39bab3 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 13 Feb 2024 10:11:54 -0500
Subject: [PATCH 311/392] Add cryp configuration.
---
embassy-stm32/src/cryp/mod.rs | 227 ++++++++++++++++++++++++++++++++++
embassy-stm32/src/lib.rs | 2 +
2 files changed, 229 insertions(+)
create mode 100644 embassy-stm32/src/cryp/mod.rs
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
new file mode 100644
index 000000000..dedc6ddc5
--- /dev/null
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -0,0 +1,227 @@
+use embassy_hal_internal::{into_ref, PeripheralRef};
+use pac::cryp::Init;
+
+use crate::pac;
+use crate::peripherals::CRYP;
+use crate::rcc::sealed::RccPeripheral;
+use crate::{interrupt, peripherals, Peripheral};
+
+pub struct Context<'c> {
+ key: &'c [u8],
+}
+
+#[derive(PartialEq)]
+pub enum Algorithm {
+ AES,
+ DES,
+ TDES,
+}
+
+#[derive(PartialEq)]
+pub enum Mode {
+ ECB,
+ CBC,
+ CTR,
+ GCM,
+ GMAC,
+ CCM,
+}
+
+#[derive(PartialEq)]
+pub enum Direction {
+ Encrypt,
+ Decrypt,
+}
+
+/// Crypto Accelerator Driver
+pub struct Cryp<'d, T: Instance, In, Out> {
+ _peripheral: PeripheralRef<'d, T>,
+ indma: PeripheralRef<'d, In>,
+ outdma: PeripheralRef<'d, Out>,
+}
+
+type InitVector<'v> = Option<&'v [u8]>;
+
+impl<'d, T: Instance, In, Out> Cryp<'d, T, In, Out> {
+ /// Create a new CRYP driver.
+ pub fn new(
+ peri: impl Peripheral<P = T> + 'd,
+ indma: impl Peripheral<P = In> + 'd,
+ outdma: impl Peripheral<P = Out> + 'd,
+ ) -> Self {
+ CRYP::enable_and_reset();
+ into_ref!(peri, indma, outdma);
+ let instance = Self {
+ _peripheral: peri,
+ indma: indma,
+ outdma: outdma,
+ };
+ instance
+ }
+
+ /// Start a new cipher operation.
+ /// Key size must be 128, 192, or 256 bits.
+ pub fn start(key: &[u8], iv: InitVector, algo: Algorithm, mode: Mode, dir: Direction) -> Context {
+ T::regs().cr().modify(|w| w.set_crypen(false));
+
+ let keylen = key.len() * 8;
+ let ivlen;
+ if let Some(iv) = iv {
+ ivlen = iv.len() * 8;
+ } else {
+ ivlen = 0;
+ }
+
+ // Checks for correctness
+ if algo == Algorithm::AES {
+ match keylen {
+ 128 => T::regs().cr().write(|w| w.set_keysize(0)),
+ 192 => T::regs().cr().write(|w| w.set_keysize(1)),
+ 256 => T::regs().cr().write(|w| w.set_keysize(2)),
+ _ => panic!("Key length must be 128, 192, or 256 bits."),
+ }
+
+ if (mode == Mode::GCM) && (ivlen != 96) {
+ panic!("IV length must be 96 bits for GCM.");
+ } else if (mode == Mode::CBC) && (ivlen != 128) {
+ panic!("IV length must be 128 bits for CBC.");
+ } else if (mode == Mode::CCM) && (ivlen != 128) {
+ panic!("IV length must be 128 bits for CCM.");
+ } else if (mode == Mode::CTR) && (ivlen != 64) {
+ panic!("IV length must be 64 bits for CTR.");
+ } else if (mode == Mode::GCM) && (ivlen != 96) {
+ panic!("IV length must be 96 bits for GCM.");
+ } else if (mode == Mode::GMAC) && (ivlen != 96) {
+ panic!("IV length must be 96 bits for GMAC.");
+ }
+ }
+
+ // Load the key into the registers.
+ let mut keyidx = 0;
+ let mut keyword: [u8; 4] = [0; 4];
+ if keylen > 192 {
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(0).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(0).krr().write_value(u32::from_be_bytes(keyword));
+ }
+ if keylen > 128 {
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(1).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(1).krr().write_value(u32::from_be_bytes(keyword));
+ }
+ if keylen > 64 {
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(2).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(2).krr().write_value(u32::from_be_bytes(keyword));
+ }
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(3).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ T::regs().key(3).krr().write_value(u32::from_be_bytes(keyword));
+
+ // Set data type to 8-bit. This will match software implementations.
+ T::regs().cr().modify(|w| w.set_datatype(2));
+
+ if algo == Algorithm::AES {
+ if (mode == Mode::ECB) || (mode == Mode::CBC) {
+ T::regs().cr().modify(|w| w.set_algomode0(7));
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ while T::regs().sr().read().busy() {}
+ }
+
+ match mode {
+ Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(4)),
+ Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(5)),
+ Mode::CTR => T::regs().cr().modify(|w| w.set_algomode0(6)),
+ Mode::GCM => T::regs().cr().modify(|w| w.set_algomode0(8)),
+ Mode::GMAC => T::regs().cr().modify(|w| w.set_algomode0(8)),
+ Mode::CCM => T::regs().cr().modify(|w| w.set_algomode0(9)),
+ }
+ } else if algo == Algorithm::DES {
+ match mode {
+ Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(2)),
+ Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(3)),
+ _ => panic!("Only ECB and CBC modes are valid for DES."),
+ }
+ } else if algo == Algorithm::TDES {
+ match mode {
+ Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(0)),
+ Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(1)),
+ _ => panic!("Only ECB and CBC modes are valid for TDES."),
+ }
+ }
+
+ // Set encrypt/decrypt
+ if dir == Direction::Encrypt {
+ T::regs().cr().modify(|w| w.set_algodir(false));
+ } else {
+ T::regs().cr().modify(|w| w.set_algodir(true));
+ }
+
+ // Load the IV into the registers.
+ if let Some(iv) = iv {
+ let mut iv_idx = 0;
+ let mut iv_word: [u8; 4] = [0; 4];
+ iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
+ iv_idx += 4;
+ T::regs().init(0).ivlr().write_value(u32::from_be_bytes(iv_word));
+ iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
+ iv_idx += 4;
+ if iv.len() >= 12 {
+ T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
+ iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
+ iv_idx += 4;
+ }
+ if iv.len() >= 16 {
+ T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
+ iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
+ T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
+ }
+ }
+
+ // Flush in/out FIFOs
+ T::regs().cr().modify(|w| w.fflush());
+
+ let ctx = Context { key: key };
+
+ ctx
+ }
+}
+
+pub(crate) mod sealed {
+ use super::*;
+
+ pub trait Instance {
+ fn regs() -> pac::cryp::Cryp;
+ }
+}
+
+/// RNG instance trait.
+pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+ /// Interrupt for this RNG instance.
+ type Interrupt: interrupt::typelevel::Interrupt;
+}
+
+foreach_interrupt!(
+ ($inst:ident, rng, CRYP, GLOBAL, $irq:ident) => {
+ impl Instance for peripherals::$inst {
+ type Interrupt = crate::interrupt::typelevel::$irq;
+ }
+
+ impl sealed::Instance for peripherals::$inst {
+ fn regs() -> crate::pac::cryp::Cryp {
+ crate::pac::$inst
+ }
+ }
+ };
+);
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index cd1ede0fa..6859eef6c 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -34,6 +34,8 @@ pub mod adc;
pub mod can;
#[cfg(crc)]
pub mod crc;
+#[cfg(cryp)]
+pub mod cryp;
#[cfg(dac)]
pub mod dac;
#[cfg(dcmi)]
From a0a8a4ec864763948d4a965ccf8ec11ca91cb15f Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Wed, 14 Feb 2024 20:24:52 -0500
Subject: [PATCH 312/392] Support CBC, ECB, CTR modes.
---
embassy-stm32/src/cryp/mod.rs | 350 +++++++++++++++++++++++++++-------
1 file changed, 282 insertions(+), 68 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index dedc6ddc5..f266313c1 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1,23 +1,34 @@
use embassy_hal_internal::{into_ref, PeripheralRef};
-use pac::cryp::Init;
use crate::pac;
use crate::peripherals::CRYP;
use crate::rcc::sealed::RccPeripheral;
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, Peripheral};
+
+const DES_BLOCK_SIZE: usize = 8; // 64 bits
+const AES_BLOCK_SIZE: usize = 16; // 128 bits
pub struct Context<'c> {
+ algo: Algorithm,
+ mode: Mode,
+ dir: Direction,
+ last_block_processed: bool,
+ aad_complete: bool,
+ cr: u32,
+ iv: [u32; 4],
key: &'c [u8],
+ csgcmccm: [u32; 8],
+ csgcm: [u32; 8],
}
-#[derive(PartialEq)]
+#[derive(PartialEq, Clone, Copy)]
pub enum Algorithm {
AES,
DES,
TDES,
}
-#[derive(PartialEq)]
+#[derive(PartialEq, Clone, Copy)]
pub enum Mode {
ECB,
CBC,
@@ -27,53 +38,55 @@ pub enum Mode {
CCM,
}
-#[derive(PartialEq)]
+#[derive(PartialEq, Clone, Copy)]
pub enum Direction {
Encrypt,
Decrypt,
}
/// Crypto Accelerator Driver
-pub struct Cryp<'d, T: Instance, In, Out> {
+pub struct Cryp<'d, T: Instance> {
_peripheral: PeripheralRef<'d, T>,
- indma: PeripheralRef<'d, In>,
- outdma: PeripheralRef<'d, Out>,
}
type InitVector<'v> = Option<&'v [u8]>;
-impl<'d, T: Instance, In, Out> Cryp<'d, T, In, Out> {
+impl<'d, T: Instance> Cryp<'d, T> {
/// Create a new CRYP driver.
- pub fn new(
- peri: impl Peripheral<P = T> + 'd,
- indma: impl Peripheral<P = In> + 'd,
- outdma: impl Peripheral<P = Out> + 'd,
- ) -> Self {
+ pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
CRYP::enable_and_reset();
- into_ref!(peri, indma, outdma);
- let instance = Self {
- _peripheral: peri,
- indma: indma,
- outdma: outdma,
- };
+ into_ref!(peri);
+ let instance = Self { _peripheral: peri };
instance
}
/// Start a new cipher operation.
/// Key size must be 128, 192, or 256 bits.
- pub fn start(key: &[u8], iv: InitVector, algo: Algorithm, mode: Mode, dir: Direction) -> Context {
- T::regs().cr().modify(|w| w.set_crypen(false));
+ pub fn start<'c>(&self, key: &'c [u8], iv: InitVector, algo: Algorithm, mode: Mode, dir: Direction) -> Context<'c> {
+ let mut ctx = Context {
+ algo,
+ mode,
+ dir,
+ last_block_processed: false,
+ cr: 0,
+ iv: [0; 4],
+ key,
+ csgcmccm: [0; 8],
+ csgcm: [0; 8],
+ aad_complete: false,
+ };
- let keylen = key.len() * 8;
- let ivlen;
- if let Some(iv) = iv {
- ivlen = iv.len() * 8;
- } else {
- ivlen = 0;
- }
+ T::regs().cr().modify(|w| w.set_crypen(false));
// Checks for correctness
if algo == Algorithm::AES {
+ let keylen = key.len() * 8;
+ let ivlen;
+ if let Some(iv) = iv {
+ ivlen = iv.len() * 8;
+ } else {
+ ivlen = 0;
+ }
match keylen {
128 => T::regs().cr().write(|w| w.set_keysize(0)),
192 => T::regs().cr().write(|w| w.set_keysize(1)),
@@ -96,49 +109,14 @@ impl<'d, T: Instance, In, Out> Cryp<'d, T, In, Out> {
}
}
- // Load the key into the registers.
- let mut keyidx = 0;
- let mut keyword: [u8; 4] = [0; 4];
- if keylen > 192 {
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- keyidx += 4;
- T::regs().key(0).klr().write_value(u32::from_be_bytes(keyword));
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- keyidx += 4;
- T::regs().key(0).krr().write_value(u32::from_be_bytes(keyword));
- }
- if keylen > 128 {
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- keyidx += 4;
- T::regs().key(1).klr().write_value(u32::from_be_bytes(keyword));
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- keyidx += 4;
- T::regs().key(1).krr().write_value(u32::from_be_bytes(keyword));
- }
- if keylen > 64 {
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- keyidx += 4;
- T::regs().key(2).klr().write_value(u32::from_be_bytes(keyword));
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- keyidx += 4;
- T::regs().key(2).krr().write_value(u32::from_be_bytes(keyword));
- }
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- keyidx += 4;
- T::regs().key(3).klr().write_value(u32::from_be_bytes(keyword));
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
- T::regs().key(3).krr().write_value(u32::from_be_bytes(keyword));
+ self.load_key(key);
// Set data type to 8-bit. This will match software implementations.
T::regs().cr().modify(|w| w.set_datatype(2));
- if algo == Algorithm::AES {
- if (mode == Mode::ECB) || (mode == Mode::CBC) {
- T::regs().cr().modify(|w| w.set_algomode0(7));
- T::regs().cr().modify(|w| w.set_crypen(true));
- while T::regs().sr().read().busy() {}
- }
+ self.prepare_key(&ctx);
+ if algo == Algorithm::AES {
match mode {
Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(4)),
Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(5)),
@@ -192,10 +170,246 @@ impl<'d, T: Instance, In, Out> Cryp<'d, T, In, Out> {
// Flush in/out FIFOs
T::regs().cr().modify(|w| w.fflush());
- let ctx = Context { key: key };
+ if mode == Mode::GCM {
+ // GCM init phase
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(0));
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ while T::regs().cr().read().crypen() {}
+ }
+
+ self.store_context(&mut ctx);
ctx
}
+
+ // pub fn aad_blocking(&self, ctx: &mut Context, aad: &[u8]) {
+ // if ctx.aad_complete {
+ // panic!("Cannot update AAD after calling 'update'!")
+ // }
+ // if (ctx.mode != Mode::GCM) && (ctx.mode != Mode::GMAC) && (ctx.mode != Mode::CCM) {
+ // panic!("Associated data only valid for GCM, GMAC, and CCM modes.")
+ // }
+
+ // let mut header_size = 0;
+ // let mut header: [u8;]
+
+ // if aad.len() < 65280 {
+
+ // }
+
+ // // GCM header phase
+ // T::regs().cr().modify(|w| w.set_gcm_ccmph(1));
+ // T::regs().cr().modify(|w| w.set_crypen(true));
+ // }
+
+ pub fn update_blocking(&self, ctx: &mut Context, input: &[u8], output: &mut [u8], last_block: bool) {
+ self.load_context(ctx);
+
+ ctx.aad_complete = true;
+ if last_block {
+ ctx.last_block_processed = true;
+ }
+
+ let block_size;
+ if ctx.algo == Algorithm::DES {
+ block_size = 8;
+ } else {
+ block_size = 16;
+ }
+ let last_block_remainder = input.len() % block_size;
+
+ // Perform checks for correctness.
+
+ if ctx.mode == Mode::GMAC {
+ panic!("GMAC works on header data only. Do not call this function for GMAC.");
+ }
+ if ctx.last_block_processed {
+ panic!("The last block has already been processed!");
+ }
+ if input.len() != output.len() {
+ panic!("Output buffer length must match input length.");
+ }
+ if !last_block {
+ if last_block_remainder != 0 {
+ panic!("Input length must be a multiple of {block_size} bytes.");
+ }
+ }
+ if (ctx.mode == Mode::ECB) || (ctx.mode == Mode::CBC) {
+ if last_block_remainder != 0 {
+ panic!("Input must be a multiple of {block_size} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.");
+ }
+ }
+
+ // Load data into core, block by block.
+ let num_full_blocks = input.len() / block_size;
+ for block in 0..num_full_blocks {
+ let mut index = block * block_size;
+ let end_index = index + block_size;
+ // Write block in
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&input[index..index + 4]);
+ T::regs().din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ let mut index = block * block_size;
+ let end_index = index + block_size;
+ // Block until there is output to read.
+ while !T::regs().sr().read().ofne() {}
+ // Read block out
+ while index < end_index {
+ let out_word: u32 = T::regs().dout().read();
+ output[index..index + 4].copy_from_slice(u32::to_ne_bytes(out_word).as_slice());
+ index += 4;
+ }
+ }
+
+ // Handle the final block, which is incomplete.
+ if last_block_remainder > 0 {
+ if ctx.mode == Mode::GCM && ctx.dir == Direction::Encrypt {
+ //Handle special GCM partial block process.
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().write(|w| w.set_algomode0(6));
+ let iv1r = T::regs().csgcmccmr(7).read() - 1;
+ T::regs().init(1).ivrr().write_value(iv1r);
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ }
+
+ let mut intermediate_data: [u8; 16] = [0; 16];
+ let mut last_block: [u8; 16] = [0; 16];
+ last_block.copy_from_slice(&input[input.len() - last_block_remainder..input.len()]);
+ let mut index = 0;
+ let end_index = block_size;
+ // Write block in
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&last_block[index..index + 4]);
+ T::regs().din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ let mut index = 0;
+ let end_index = block_size;
+ // Block until there is output to read.
+ while !T::regs().sr().read().ofne() {}
+ // Read block out
+ while index < end_index {
+ let out_word: u32 = T::regs().dout().read();
+ intermediate_data[index..index + 4].copy_from_slice(u32::to_ne_bytes(out_word).as_slice());
+ index += 4;
+ }
+
+ // Handle the last block depending on mode.
+ output[output.len() - last_block_remainder..output.len()]
+ .copy_from_slice(&intermediate_data[0..last_block_remainder]);
+
+ if ctx.mode == Mode::GCM && ctx.dir == Direction::Encrypt {
+ //Handle special GCM partial block process.
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().write(|w| w.set_algomode0(8));
+ T::regs().init(1).ivrr().write_value(2);
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(3));
+ let mut index = 0;
+ let end_index = block_size;
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&intermediate_data[index..index + 4]);
+ T::regs().din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ for _ in 0..4 {
+ T::regs().dout().read();
+ }
+ }
+ }
+ }
+
+ fn prepare_key(&self, ctx: &Context) {
+ if ctx.algo == Algorithm::AES {
+ if (ctx.mode == Mode::ECB) || (ctx.mode == Mode::CBC) {
+ T::regs().cr().modify(|w| w.set_algomode0(7));
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ while T::regs().sr().read().busy() {}
+ }
+ }
+ }
+
+ fn load_key(&self, key: &[u8]) {
+ // Load the key into the registers.
+ let mut keyidx = 0;
+ let mut keyword: [u8; 4] = [0; 4];
+ let keylen = key.len() * 8;
+ if keylen > 192 {
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(0).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(0).krr().write_value(u32::from_be_bytes(keyword));
+ }
+ if keylen > 128 {
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(1).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(1).krr().write_value(u32::from_be_bytes(keyword));
+ }
+ if keylen > 64 {
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(2).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(2).krr().write_value(u32::from_be_bytes(keyword));
+ }
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyidx += 4;
+ T::regs().key(3).klr().write_value(u32::from_be_bytes(keyword));
+ keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ T::regs().key(3).krr().write_value(u32::from_be_bytes(keyword));
+ }
+
+ fn store_context(&self, ctx: &mut Context) {
+ // Wait for data block processing to finish.
+ while !T::regs().sr().read().ifem() {}
+ while T::regs().sr().read().ofne() {}
+ while T::regs().sr().read().busy() {}
+
+ // Disable crypto processor.
+ T::regs().cr().modify(|w| w.set_crypen(false));
+
+ // Save the peripheral state.
+ ctx.cr = T::regs().cr().read().0;
+ ctx.iv[0] = T::regs().init(0).ivlr().read();
+ ctx.iv[1] = T::regs().init(0).ivrr().read();
+ ctx.iv[2] = T::regs().init(1).ivlr().read();
+ ctx.iv[3] = T::regs().init(1).ivrr().read();
+ for i in 0..8 {
+ ctx.csgcmccm[i] = T::regs().csgcmccmr(i).read();
+ ctx.csgcm[i] = T::regs().csgcmr(i).read();
+ }
+ }
+
+ fn load_context(&self, ctx: &Context) {
+ // Reload state registers.
+ T::regs().cr().write(|w| w.0 = ctx.cr);
+ T::regs().init(0).ivlr().write_value(ctx.iv[0]);
+ T::regs().init(0).ivrr().write_value(ctx.iv[1]);
+ T::regs().init(1).ivlr().write_value(ctx.iv[2]);
+ T::regs().init(1).ivrr().write_value(ctx.iv[3]);
+ for i in 0..8 {
+ T::regs().csgcmccmr(i).write_value(ctx.csgcmccm[i]);
+ T::regs().csgcmr(i).write_value(ctx.csgcm[i]);
+ }
+ self.load_key(ctx.key);
+
+ // Prepare key if applicable.
+ self.prepare_key(ctx);
+
+ // Enable crypto processor.
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ }
}
pub(crate) mod sealed {
From 72e4cacd914195352c9760856e8b8e40a7851752 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Wed, 14 Feb 2024 22:11:38 -0500
Subject: [PATCH 313/392] CBC and ECB AES modes functional.
---
embassy-stm32/src/cryp/mod.rs | 39 +++++++++++++++++++----------------
1 file changed, 21 insertions(+), 18 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index f266313c1..b368930da 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -3,7 +3,7 @@ use embassy_hal_internal::{into_ref, PeripheralRef};
use crate::pac;
use crate::peripherals::CRYP;
use crate::rcc::sealed::RccPeripheral;
-use crate::{interrupt, Peripheral};
+use crate::{interrupt, peripherals, Peripheral};
const DES_BLOCK_SIZE: usize = 8; // 64 bits
const AES_BLOCK_SIZE: usize = 16; // 128 bits
@@ -49,7 +49,7 @@ pub struct Cryp<'d, T: Instance> {
_peripheral: PeripheralRef<'d, T>,
}
-type InitVector<'v> = Option<&'v [u8]>;
+pub type InitVector<'v> = Option<&'v [u8]>;
impl<'d, T: Instance> Cryp<'d, T> {
/// Create a new CRYP driver.
@@ -88,9 +88,9 @@ impl<'d, T: Instance> Cryp<'d, T> {
ivlen = 0;
}
match keylen {
- 128 => T::regs().cr().write(|w| w.set_keysize(0)),
- 192 => T::regs().cr().write(|w| w.set_keysize(1)),
- 256 => T::regs().cr().write(|w| w.set_keysize(2)),
+ 128 => T::regs().cr().modify(|w| w.set_keysize(0)),
+ 192 => T::regs().cr().modify(|w| w.set_keysize(1)),
+ 256 => T::regs().cr().modify(|w| w.set_keysize(2)),
_ => panic!("Key length must be 128, 192, or 256 bits."),
}
@@ -155,13 +155,13 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().init(0).ivlr().write_value(u32::from_be_bytes(iv_word));
iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
iv_idx += 4;
+ T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
if iv.len() >= 12 {
- T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
iv_idx += 4;
+ T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
}
if iv.len() >= 16 {
- T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
}
@@ -206,9 +206,6 @@ impl<'d, T: Instance> Cryp<'d, T> {
self.load_context(ctx);
ctx.aad_complete = true;
- if last_block {
- ctx.last_block_processed = true;
- }
let block_size;
if ctx.algo == Algorithm::DES {
@@ -231,15 +228,19 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
if !last_block {
if last_block_remainder != 0 {
- panic!("Input length must be a multiple of {block_size} bytes.");
+ panic!("Input length must be a multiple of {} bytes.", block_size);
}
}
if (ctx.mode == Mode::ECB) || (ctx.mode == Mode::CBC) {
if last_block_remainder != 0 {
- panic!("Input must be a multiple of {block_size} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.");
+ panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", block_size);
}
}
+ if last_block {
+ ctx.last_block_processed = true;
+ }
+
// Load data into core, block by block.
let num_full_blocks = input.len() / block_size;
for block in 0..num_full_blocks {
@@ -277,7 +278,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
let mut intermediate_data: [u8; 16] = [0; 16];
let mut last_block: [u8; 16] = [0; 16];
- last_block.copy_from_slice(&input[input.len() - last_block_remainder..input.len()]);
+ last_block[..last_block_remainder].copy_from_slice(&input[input.len() - last_block_remainder..input.len()]);
let mut index = 0;
let end_index = block_size;
// Write block in
@@ -299,7 +300,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
// Handle the last block depending on mode.
- output[output.len() - last_block_remainder..output.len()]
+ let output_len = output.len();
+ output[output_len - last_block_remainder..output_len]
.copy_from_slice(&intermediate_data[0..last_block_remainder]);
if ctx.mode == Mode::GCM && ctx.dir == Direction::Encrypt {
@@ -325,7 +327,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
fn prepare_key(&self, ctx: &Context) {
- if ctx.algo == Algorithm::AES {
+ if ctx.algo == Algorithm::AES && ctx.dir == Direction::Decrypt {
if (ctx.mode == Mode::ECB) || (ctx.mode == Mode::CBC) {
T::regs().cr().modify(|w| w.set_algomode0(7));
T::regs().cr().modify(|w| w.set_crypen(true));
@@ -406,6 +408,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Prepare key if applicable.
self.prepare_key(ctx);
+ T::regs().cr().write(|w| w.0 = ctx.cr);
// Enable crypto processor.
T::regs().cr().modify(|w| w.set_crypen(true));
@@ -420,14 +423,14 @@ pub(crate) mod sealed {
}
}
-/// RNG instance trait.
+/// CRYP instance trait.
pub trait Instance: sealed::Instance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
- /// Interrupt for this RNG instance.
+ /// Interrupt for this CRYP instance.
type Interrupt: interrupt::typelevel::Interrupt;
}
foreach_interrupt!(
- ($inst:ident, rng, CRYP, GLOBAL, $irq:ident) => {
+ ($inst:ident, cryp, CRYP, GLOBAL, $irq:ident) => {
impl Instance for peripherals::$inst {
type Interrupt = crate::interrupt::typelevel::$irq;
}
From 565acdf24301a72fe084aa18b7c55a6110609374 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Wed, 14 Feb 2024 22:38:05 -0500
Subject: [PATCH 314/392] CTR mode functional.
---
embassy-stm32/src/cryp/mod.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index b368930da..4db95d55c 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -100,8 +100,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
panic!("IV length must be 128 bits for CBC.");
} else if (mode == Mode::CCM) && (ivlen != 128) {
panic!("IV length must be 128 bits for CCM.");
- } else if (mode == Mode::CTR) && (ivlen != 64) {
- panic!("IV length must be 64 bits for CTR.");
+ } else if (mode == Mode::CTR) && (ivlen != 128) {
+ panic!("IV length must be 128 bits for CTR.");
} else if (mode == Mode::GCM) && (ivlen != 96) {
panic!("IV length must be 96 bits for GCM.");
} else if (mode == Mode::GMAC) && (ivlen != 96) {
From c2b03eff62245bd325a781e1e260c150e0a5040c Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Fri, 16 Feb 2024 13:15:14 -0500
Subject: [PATCH 315/392] GCM mode functional.
---
embassy-stm32/src/cryp/mod.rs | 244 +++++++++++++++++++++++++++-------
1 file changed, 198 insertions(+), 46 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 4db95d55c..447bcf2f8 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1,3 +1,4 @@
+//! Crypto Accelerator (CRYP)
use embassy_hal_internal::{into_ref, PeripheralRef};
use crate::pac;
@@ -8,6 +9,8 @@ use crate::{interrupt, peripherals, Peripheral};
const DES_BLOCK_SIZE: usize = 8; // 64 bits
const AES_BLOCK_SIZE: usize = 16; // 128 bits
+/// Holds the state information for a cipher operation.
+/// Allows suspending/resuming of cipher operations.
pub struct Context<'c> {
algo: Algorithm,
mode: Mode,
@@ -19,28 +22,44 @@ pub struct Context<'c> {
key: &'c [u8],
csgcmccm: [u32; 8],
csgcm: [u32; 8],
+ header_len: u64,
+ payload_len: u64,
}
+/// Selects the encryption algorithm.
#[derive(PartialEq, Clone, Copy)]
pub enum Algorithm {
+ /// Advanced Encryption Standard
AES,
+ /// Data Encryption Standard
DES,
+ /// Triple-DES
TDES,
}
+/// Selects the cipher mode.
#[derive(PartialEq, Clone, Copy)]
pub enum Mode {
+ /// Electronic Codebook
ECB,
+ /// Cipher Block Chaining
CBC,
+ /// Counter Mode
CTR,
+ /// Galois Counter Mode
GCM,
+ /// Galois Message Authentication Code
GMAC,
+ /// Counter with CBC-MAC
CCM,
}
+/// Selects whether the crypto processor operates in encryption or decryption mode.
#[derive(PartialEq, Clone, Copy)]
pub enum Direction {
+ /// Encryption mode
Encrypt,
+ /// Decryption mode
Decrypt,
}
@@ -49,6 +68,8 @@ pub struct Cryp<'d, T: Instance> {
_peripheral: PeripheralRef<'d, T>,
}
+/// Initialization vector of arbitrary length.
+/// When an initialization vector is not needed, `None` may be supplied.
pub type InitVector<'v> = Option<&'v [u8]>;
impl<'d, T: Instance> Cryp<'d, T> {
@@ -62,6 +83,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// Start a new cipher operation.
/// Key size must be 128, 192, or 256 bits.
+ /// Initialization vector must only be supplied if necessary.
+ /// Panics if there is any mismatch in parameters, such as an incorrect IV length or invalid mode.
pub fn start<'c>(&self, key: &'c [u8], iv: InitVector, algo: Algorithm, mode: Mode, dir: Direction) -> Context<'c> {
let mut ctx = Context {
algo,
@@ -74,6 +97,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
csgcmccm: [0; 8],
csgcm: [0; 8],
aad_complete: false,
+ header_len: 0,
+ payload_len: 0,
};
T::regs().cr().modify(|w| w.set_crypen(false));
@@ -102,8 +127,6 @@ impl<'d, T: Instance> Cryp<'d, T> {
panic!("IV length must be 128 bits for CCM.");
} else if (mode == Mode::CTR) && (ivlen != 128) {
panic!("IV length must be 128 bits for CTR.");
- } else if (mode == Mode::GCM) && (ivlen != 96) {
- panic!("IV length must be 96 bits for GCM.");
} else if (mode == Mode::GMAC) && (ivlen != 96) {
panic!("IV length must be 96 bits for GMAC.");
}
@@ -121,17 +144,27 @@ impl<'d, T: Instance> Cryp<'d, T> {
Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(4)),
Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(5)),
Mode::CTR => T::regs().cr().modify(|w| w.set_algomode0(6)),
- Mode::GCM => T::regs().cr().modify(|w| w.set_algomode0(8)),
- Mode::GMAC => T::regs().cr().modify(|w| w.set_algomode0(8)),
- Mode::CCM => T::regs().cr().modify(|w| w.set_algomode0(9)),
+ Mode::GCM => T::regs().cr().modify(|w| w.set_algomode0(0)),
+ Mode::GMAC => T::regs().cr().modify(|w| w.set_algomode0(0)),
+ Mode::CCM => T::regs().cr().modify(|w| w.set_algomode0(1)),
+ }
+ match mode {
+ Mode::ECB => T::regs().cr().modify(|w| w.set_algomode3(false)),
+ Mode::CBC => T::regs().cr().modify(|w| w.set_algomode3(false)),
+ Mode::CTR => T::regs().cr().modify(|w| w.set_algomode3(false)),
+ Mode::GCM => T::regs().cr().modify(|w| w.set_algomode3(true)),
+ Mode::GMAC => T::regs().cr().modify(|w| w.set_algomode3(true)),
+ Mode::CCM => T::regs().cr().modify(|w| w.set_algomode3(true)),
}
} else if algo == Algorithm::DES {
+ T::regs().cr().modify(|w| w.set_algomode3(false));
match mode {
Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(2)),
Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(3)),
_ => panic!("Only ECB and CBC modes are valid for DES."),
}
} else if algo == Algorithm::TDES {
+ T::regs().cr().modify(|w| w.set_algomode3(false));
match mode {
Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(0)),
Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(1)),
@@ -148,23 +181,26 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Load the IV into the registers.
if let Some(iv) = iv {
+ let mut full_iv: [u8; 16] = [0; 16];
+ full_iv[0..iv.len()].copy_from_slice(iv);
+
+ if (mode == Mode::GCM) || (mode == Mode::GMAC) {
+ full_iv[15] = 2;
+ }
+
let mut iv_idx = 0;
let mut iv_word: [u8; 4] = [0; 4];
- iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
iv_idx += 4;
T::regs().init(0).ivlr().write_value(u32::from_be_bytes(iv_word));
- iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
iv_idx += 4;
T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
- if iv.len() >= 12 {
- iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
- iv_idx += 4;
- T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
- }
- if iv.len() >= 16 {
- iv_word.copy_from_slice(&iv[iv_idx..iv_idx + 4]);
- T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
- }
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+ iv_idx += 4;
+ T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+ T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
}
// Flush in/out FIFOs
@@ -182,41 +218,116 @@ impl<'d, T: Instance> Cryp<'d, T> {
ctx
}
- // pub fn aad_blocking(&self, ctx: &mut Context, aad: &[u8]) {
- // if ctx.aad_complete {
- // panic!("Cannot update AAD after calling 'update'!")
- // }
- // if (ctx.mode != Mode::GCM) && (ctx.mode != Mode::GMAC) && (ctx.mode != Mode::CCM) {
- // panic!("Associated data only valid for GCM, GMAC, and CCM modes.")
- // }
-
- // let mut header_size = 0;
- // let mut header: [u8;]
-
- // if aad.len() < 65280 {
-
- // }
-
- // // GCM header phase
- // T::regs().cr().modify(|w| w.set_gcm_ccmph(1));
- // T::regs().cr().modify(|w| w.set_crypen(true));
- // }
-
- pub fn update_blocking(&self, ctx: &mut Context, input: &[u8], output: &mut [u8], last_block: bool) {
+ /// Controls the header phase of cipher processing.
+ /// This function is only valid for GCM, CCM, and GMAC modes.
+ /// It only needs to be called if using one of these modes and there is associated data.
+ /// All AAD must be supplied to this function prior to starting the payload phase with `payload_blocking`.
+ /// The AAD must be supplied in multiples of the block size (128 bits), except when supplying the last block.
+ /// When supplying the last block of AAD, `last_aad_block` must be `true`.
+ pub fn aad_blocking(&self, ctx: &mut Context, aad: &[u8], last_aad_block: bool) {
self.load_context(ctx);
- ctx.aad_complete = true;
-
let block_size;
if ctx.algo == Algorithm::DES {
- block_size = 8;
+ block_size = DES_BLOCK_SIZE;
} else {
- block_size = 16;
+ block_size = AES_BLOCK_SIZE;
+ }
+ let last_block_remainder = aad.len() % block_size;
+
+ // Perform checks for correctness.
+ if ctx.aad_complete {
+ panic!("Cannot update AAD after calling 'update'!")
+ }
+ if (ctx.mode != Mode::GCM) && (ctx.mode != Mode::GMAC) && (ctx.mode != Mode::CCM) {
+ panic!("Associated data only valid for GCM, GMAC, and CCM modes.")
+ }
+ if !last_aad_block {
+ if last_block_remainder != 0 {
+ panic!("Input length must be a multiple of {} bytes.", block_size);
+ }
+ }
+
+ ctx.header_len += aad.len() as u64;
+
+ // GCM header phase
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(1));
+ T::regs().cr().modify(|w| w.set_crypen(true));
+
+ // Load data into core, block by block.
+ let num_full_blocks = aad.len() / block_size;
+ for block in 0..num_full_blocks {
+ let mut index = block * block_size;
+ let end_index = index + block_size;
+ // Write block in
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&aad[index..index + 4]);
+ T::regs().din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ // Block until input FIFO is empty.
+ while !T::regs().sr().read().ifem() {}
+ }
+
+ // Handle the final block, which is incomplete.
+ if last_block_remainder > 0 {
+ let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
+ last_block[..last_block_remainder].copy_from_slice(&aad[aad.len() - last_block_remainder..aad.len()]);
+ let mut index = 0;
+ let end_index = block_size;
+ // Write block in
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&last_block[index..index + 4]);
+ T::regs().din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ // Block until input FIFO is empty
+ while !T::regs().sr().read().ifem() {}
+ }
+
+ if last_aad_block {
+ // Switch to payload phase.
+ ctx.aad_complete = true;
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
+ T::regs().cr().modify(|w| w.fflush());
+ }
+
+ self.store_context(ctx);
+ }
+
+ /// Performs encryption/decryption on the provided context.
+ /// The context determines algorithm, mode, and state of the crypto accelerator.
+ /// When the last piece of data is supplied, `last_block` should be `true`.
+ /// This function panics under various mismatches of parameters.
+ /// Input and output buffer lengths must match.
+ /// Data must be a multiple of block size (128-bits for AES, 64-bits for DES) for CBC and ECB modes.
+ /// Padding or ciphertext stealing must be managed by the application for these modes.
+ /// Data must also be a multiple of block size unless `last_block` is `true`.
+ pub fn payload_blocking(&self, ctx: &mut Context, input: &[u8], output: &mut [u8], last_block: bool) {
+ self.load_context(ctx);
+
+ let block_size;
+ if ctx.algo == Algorithm::DES {
+ block_size = DES_BLOCK_SIZE;
+ } else {
+ block_size = AES_BLOCK_SIZE;
}
let last_block_remainder = input.len() % block_size;
// Perform checks for correctness.
-
+ if !ctx.aad_complete && ctx.header_len > 0 {
+ panic!("Additional associated data must be processed first!");
+ } else if !ctx.aad_complete {
+ ctx.aad_complete = true;
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
+ T::regs().cr().modify(|w| w.fflush());
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ }
if ctx.mode == Mode::GMAC {
panic!("GMAC works on header data only. Do not call this function for GMAC.");
}
@@ -270,14 +381,15 @@ impl<'d, T: Instance> Cryp<'d, T> {
if ctx.mode == Mode::GCM && ctx.dir == Direction::Encrypt {
//Handle special GCM partial block process.
T::regs().cr().modify(|w| w.set_crypen(false));
- T::regs().cr().write(|w| w.set_algomode0(6));
+ T::regs().cr().modify(|w| w.set_algomode3(false));
+ T::regs().cr().modify(|w| w.set_algomode0(6));
let iv1r = T::regs().csgcmccmr(7).read() - 1;
T::regs().init(1).ivrr().write_value(iv1r);
T::regs().cr().modify(|w| w.set_crypen(true));
}
- let mut intermediate_data: [u8; 16] = [0; 16];
- let mut last_block: [u8; 16] = [0; 16];
+ let mut intermediate_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
+ let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
last_block[..last_block_remainder].copy_from_slice(&input[input.len() - last_block_remainder..input.len()]);
let mut index = 0;
let end_index = block_size;
@@ -307,7 +419,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
if ctx.mode == Mode::GCM && ctx.dir == Direction::Encrypt {
//Handle special GCM partial block process.
T::regs().cr().modify(|w| w.set_crypen(false));
- T::regs().cr().write(|w| w.set_algomode0(8));
+ T::regs().cr().write(|w| w.set_algomode3(true));
+ T::regs().cr().write(|w| w.set_algomode0(0));
T::regs().init(1).ivrr().write_value(2);
T::regs().cr().modify(|w| w.set_crypen(true));
T::regs().cr().modify(|w| w.set_gcm_ccmph(3));
@@ -324,12 +437,51 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
}
}
+
+ ctx.payload_len += input.len() as u64;
+ }
+
+ /// This function only needs to be called for GCM, CCM, and GMAC modes to
+ /// generate an authentication tag. Calling this function on any other mode
+ /// does nothing except consumes the context. A buffer for the authentication
+ /// tag must be supplied.
+ pub fn finish_blocking(&self, mut ctx: Context, tag: &mut [u8; 16]) {
+ // Just consume the context if called for any other mode.
+ if (ctx.mode != Mode::GCM) || (ctx.mode != Mode::CCM) || (ctx.mode != Mode::GMAC) {
+ return;
+ }
+
+ self.load_context(&mut ctx);
+
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(3));
+ T::regs().cr().modify(|w| w.set_crypen(true));
+
+ let headerlen1: u32 = (ctx.header_len >> 32) as u32;
+ let headerlen2: u32 = ctx.header_len as u32;
+ let payloadlen1: u32 = (ctx.payload_len >> 32) as u32;
+ let payloadlen2: u32 = ctx.payload_len as u32;
+
+ T::regs().din().write_value(headerlen1.swap_bytes());
+ T::regs().din().write_value(headerlen2.swap_bytes());
+ T::regs().din().write_value(payloadlen1.swap_bytes());
+ T::regs().din().write_value(payloadlen2.swap_bytes());
+
+ while !T::regs().sr().read().ofne() {}
+
+ tag[0..4].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ tag[4..8].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ tag[8..12].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ tag[12..16].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+
+ T::regs().cr().modify(|w| w.set_crypen(false));
}
fn prepare_key(&self, ctx: &Context) {
if ctx.algo == Algorithm::AES && ctx.dir == Direction::Decrypt {
if (ctx.mode == Mode::ECB) || (ctx.mode == Mode::CBC) {
T::regs().cr().modify(|w| w.set_algomode0(7));
+ T::regs().cr().modify(|w| w.set_algomode3(false));
T::regs().cr().modify(|w| w.set_crypen(true));
while T::regs().sr().read().busy() {}
}
From fec26e896052cc0eac6bfa6415a4ebad5352d1d9 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 18 Feb 2024 21:40:18 -0500
Subject: [PATCH 316/392] Refactored ciphers into traits.
---
embassy-stm32/src/cryp/mod.rs | 651 ++++++++++++++++++++++------------
1 file changed, 431 insertions(+), 220 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 447bcf2f8..29c1db12e 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1,4 +1,6 @@
//! Crypto Accelerator (CRYP)
+use core::marker::PhantomData;
+
use embassy_hal_internal::{into_ref, PeripheralRef};
use crate::pac;
@@ -9,51 +11,375 @@ use crate::{interrupt, peripherals, Peripheral};
const DES_BLOCK_SIZE: usize = 8; // 64 bits
const AES_BLOCK_SIZE: usize = 16; // 128 bits
+/// This trait encapsulates all cipher-specific behavior/
+pub trait Cipher<'c> {
+ /// Processing block size. Determined by the processor and the algorithm.
+ const BLOCK_SIZE: usize;
+
+ /// Indicates whether the cipher requires the application to provide padding.
+ /// If `true`, no partial blocks will be accepted (a panic will occur).
+ const REQUIRES_PADDING: bool = false;
+
+ /// Returns the symmetric key.
+ fn key(&self) -> &'c [u8];
+
+ /// Returns the initialization vector.
+ fn iv(&self) -> &[u8];
+
+ /// Sets the processor algorithm mode according to the associated cipher.
+ fn set_algomode(&self, p: &pac::cryp::Cryp);
+
+ /// Performs any key preparation within the processor, if necessary.
+ fn prepare_key(&self, _p: &pac::cryp::Cryp) {}
+
+ /// Performs any cipher-specific initialization.
+ fn init_phase(&self, _p: &pac::cryp::Cryp) {}
+
+ /// Called prior to processing the last data block for cipher-specific operations.
+ fn pre_final_block(&self, _p: &pac::cryp::Cryp) {}
+
+ /// Called after processing the last data block for cipher-specific operations.
+ fn post_final_block(&self, _p: &pac::cryp::Cryp, _dir: Direction, _int_data: &[u8; AES_BLOCK_SIZE]) {}
+}
+
+/// This trait enables restriction of ciphers to specific key sizes.
+pub trait CipherSized {}
+
+/// This trait enables restriction of a header phase to authenticated ciphers only.
+pub trait CipherAuthenticated {}
+
+/// AES-ECB Cipher Mode
+pub struct AesEcb<'c, const KEY_SIZE: usize> {
+ iv: &'c [u8; 0],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> AesEcb<'c, KEY_SIZE> {
+ /// Constructs a new AES-ECB cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE]) -> Self {
+ return Self { key: key, iv: &[0; 0] };
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
+ const REQUIRES_PADDING: bool = true;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &'c [u8] {
+ self.iv
+ }
+
+ fn prepare_key(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(7));
+ p.cr().modify(|w| w.set_algomode3(false));
+ p.cr().modify(|w| w.set_crypen(true));
+ while p.sr().read().busy() {}
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(4));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
+}
+
+impl<'c> CipherSized for AesEcb<'c, { 128 / 8 }> {}
+impl<'c> CipherSized for AesEcb<'c, { 192 / 8 }> {}
+impl<'c> CipherSized for AesEcb<'c, { 256 / 8 }> {}
+
+/// AES-CBC Cipher Mode
+pub struct AesCbc<'c, const KEY_SIZE: usize> {
+ iv: &'c [u8; 16],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> AesCbc<'c, KEY_SIZE> {
+ /// Constructs a new AES-CBC cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 16]) -> Self {
+ return Self { key: key, iv: iv };
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCbc<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
+ const REQUIRES_PADDING: bool = true;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &'c [u8] {
+ self.iv
+ }
+
+ fn prepare_key(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(7));
+ p.cr().modify(|w| w.set_algomode3(false));
+ p.cr().modify(|w| w.set_crypen(true));
+ while p.sr().read().busy() {}
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(5));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
+}
+
+impl<'c> CipherSized for AesCbc<'c, { 128 / 8 }> {}
+impl<'c> CipherSized for AesCbc<'c, { 192 / 8 }> {}
+impl<'c> CipherSized for AesCbc<'c, { 256 / 8 }> {}
+
+/// AES-CTR Cipher Mode
+pub struct AesCtr<'c, const KEY_SIZE: usize> {
+ iv: &'c [u8; 16],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> AesCtr<'c, KEY_SIZE> {
+ /// Constructs a new AES-CTR cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 16]) -> Self {
+ return Self { key: key, iv: iv };
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCtr<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &'c [u8] {
+ self.iv
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(6));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
+}
+
+impl<'c> CipherSized for AesCtr<'c, { 128 / 8 }> {}
+impl<'c> CipherSized for AesCtr<'c, { 192 / 8 }> {}
+impl<'c> CipherSized for AesCtr<'c, { 256 / 8 }> {}
+
+///AES-GCM Cipher Mode
+pub struct AesGcm<'c, const KEY_SIZE: usize> {
+ iv: [u8; 16],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> AesGcm<'c, KEY_SIZE> {
+ /// Constucts a new AES-GCM cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
+ let mut new_gcm = Self { key: key, iv: [0; 16] };
+ new_gcm.iv[..12].copy_from_slice(iv);
+ new_gcm.iv[15] = 2;
+ new_gcm
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &[u8] {
+ self.iv.as_slice()
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(0));
+ p.cr().modify(|w| w.set_algomode3(true));
+ }
+
+ fn init_phase(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_gcm_ccmph(0));
+ p.cr().modify(|w| w.set_crypen(true));
+ while p.cr().read().crypen() {}
+ }
+
+ fn pre_final_block(&self, p: &pac::cryp::Cryp) {
+ //Handle special GCM partial block process.
+ p.cr().modify(|w| w.set_crypen(false));
+ p.cr().modify(|w| w.set_algomode3(false));
+ p.cr().modify(|w| w.set_algomode0(6));
+ let iv1r = p.csgcmccmr(7).read() - 1;
+ p.init(1).ivrr().write_value(iv1r);
+ p.cr().modify(|w| w.set_crypen(true));
+ }
+
+ fn post_final_block(&self, p: &pac::cryp::Cryp, dir: Direction, int_data: &[u8; AES_BLOCK_SIZE]) {
+ if dir == Direction::Encrypt {
+ //Handle special GCM partial block process.
+ p.cr().modify(|w| w.set_crypen(false));
+ p.cr().write(|w| w.set_algomode3(true));
+ p.cr().write(|w| w.set_algomode0(0));
+ p.init(1).ivrr().write_value(2);
+ p.cr().modify(|w| w.set_crypen(true));
+ p.cr().modify(|w| w.set_gcm_ccmph(3));
+ let mut index = 0;
+ let end_index = Self::BLOCK_SIZE;
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&int_data[index..index + 4]);
+ p.din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ for _ in 0..4 {
+ p.dout().read();
+ }
+ }
+ }
+}
+
+impl<'c> CipherSized for AesGcm<'c, { 128 / 8 }> {}
+impl<'c> CipherSized for AesGcm<'c, { 192 / 8 }> {}
+impl<'c> CipherSized for AesGcm<'c, { 256 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> CipherAuthenticated for AesGcm<'c, KEY_SIZE> {}
+
+/// AES-GMAC Cipher Mode
+pub struct AesGmac<'c, const KEY_SIZE: usize> {
+ iv: [u8; 16],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> AesGmac<'c, KEY_SIZE> {
+ /// Constructs a new AES-GMAC cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
+ let mut new_gmac = Self { key: key, iv: [0; 16] };
+ new_gmac.iv[..12].copy_from_slice(iv);
+ new_gmac.iv[15] = 2;
+ new_gmac
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &[u8] {
+ self.iv.as_slice()
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(0));
+ p.cr().modify(|w| w.set_algomode3(true));
+ }
+
+ fn init_phase(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_gcm_ccmph(0));
+ p.cr().modify(|w| w.set_crypen(true));
+ while p.cr().read().crypen() {}
+ }
+
+ fn pre_final_block(&self, p: &pac::cryp::Cryp) {
+ //Handle special GCM partial block process.
+ p.cr().modify(|w| w.set_crypen(false));
+ p.cr().modify(|w| w.set_algomode3(false));
+ p.cr().modify(|w| w.set_algomode0(6));
+ let iv1r = p.csgcmccmr(7).read() - 1;
+ p.init(1).ivrr().write_value(iv1r);
+ p.cr().modify(|w| w.set_crypen(true));
+ }
+
+ fn post_final_block(&self, p: &pac::cryp::Cryp, dir: Direction, int_data: &[u8; AES_BLOCK_SIZE]) {
+ if dir == Direction::Encrypt {
+ //Handle special GCM partial block process.
+ p.cr().modify(|w| w.set_crypen(false));
+ p.cr().write(|w| w.set_algomode3(true));
+ p.cr().write(|w| w.set_algomode0(0));
+ p.init(1).ivrr().write_value(2);
+ p.cr().modify(|w| w.set_crypen(true));
+ p.cr().modify(|w| w.set_gcm_ccmph(3));
+ let mut index = 0;
+ let end_index = Self::BLOCK_SIZE;
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&int_data[index..index + 4]);
+ p.din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ for _ in 0..4 {
+ p.dout().read();
+ }
+ }
+ }
+}
+
+impl<'c> CipherSized for AesGmac<'c, { 128 / 8 }> {}
+impl<'c> CipherSized for AesGmac<'c, { 192 / 8 }> {}
+impl<'c> CipherSized for AesGmac<'c, { 256 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> CipherAuthenticated for AesGmac<'c, KEY_SIZE> {}
+
+// struct AesCcm<'c, const KEY_SIZE: usize> {
+// iv: &'c [u8],
+// key: &'c [u8; KEY_SIZE],
+// aad_len: usize,
+// payload_len: usize,
+// }
+
+// impl<'c, const KEY_SIZE: usize> AesCcm<'c, KEY_SIZE> {
+// pub fn new(&self, key: &[u8; KEY_SIZE], iv: &[u8], aad_len: usize, payload_len: usize) {
+// if iv.len() > 13 {
+// panic!("CCM IV length must be 13 bytes or less.");
+// }
+// self.key = key;
+// self.iv = iv;
+// self.aad_len = aad_len;
+// self.payload_len = payload_len;
+// }
+// }
+
+// impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
+// const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
+
+// fn key(&self) -> &'c [u8] {
+// self.key
+// }
+
+// fn iv(&self) -> &'c [u8] {
+// self.iv
+// }
+
+// fn set_algomode(&self, p: &pac::cryp::Cryp) {
+// p.cr().modify(|w| w.set_algomode0(1));
+// p.cr().modify(|w| w.set_algomode3(true));
+// }
+
+// fn init_phase(&self, p: &pac::cryp::Cryp) {
+// todo!();
+// }
+// }
+
+// impl<'c> CipherSized for AesCcm<'c, { 128 / 8 }> {}
+// impl<'c> CipherSized for AesCcm<'c, { 192 / 8 }> {}
+// impl<'c> CipherSized for AesCcm<'c, { 256 / 8 }> {}
+
/// Holds the state information for a cipher operation.
/// Allows suspending/resuming of cipher operations.
-pub struct Context<'c> {
- algo: Algorithm,
- mode: Mode,
+pub struct Context<'c, C: Cipher<'c> + CipherSized> {
+ phantom_data: PhantomData<&'c C>,
+ cipher: &'c C,
dir: Direction,
last_block_processed: bool,
aad_complete: bool,
cr: u32,
iv: [u32; 4],
- key: &'c [u8],
csgcmccm: [u32; 8],
csgcm: [u32; 8],
header_len: u64,
payload_len: u64,
}
-/// Selects the encryption algorithm.
-#[derive(PartialEq, Clone, Copy)]
-pub enum Algorithm {
- /// Advanced Encryption Standard
- AES,
- /// Data Encryption Standard
- DES,
- /// Triple-DES
- TDES,
-}
-
-/// Selects the cipher mode.
-#[derive(PartialEq, Clone, Copy)]
-pub enum Mode {
- /// Electronic Codebook
- ECB,
- /// Cipher Block Chaining
- CBC,
- /// Counter Mode
- CTR,
- /// Galois Counter Mode
- GCM,
- /// Galois Message Authentication Code
- GMAC,
- /// Counter with CBC-MAC
- CCM,
-}
-
/// Selects whether the crypto processor operates in encryption or decryption mode.
#[derive(PartialEq, Clone, Copy)]
pub enum Direction {
@@ -68,10 +394,6 @@ pub struct Cryp<'d, T: Instance> {
_peripheral: PeripheralRef<'d, T>,
}
-/// Initialization vector of arbitrary length.
-/// When an initialization vector is not needed, `None` may be supplied.
-pub type InitVector<'v> = Option<&'v [u8]>;
-
impl<'d, T: Instance> Cryp<'d, T> {
/// Create a new CRYP driver.
pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
@@ -85,51 +407,31 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// Key size must be 128, 192, or 256 bits.
/// Initialization vector must only be supplied if necessary.
/// Panics if there is any mismatch in parameters, such as an incorrect IV length or invalid mode.
- pub fn start<'c>(&self, key: &'c [u8], iv: InitVector, algo: Algorithm, mode: Mode, dir: Direction) -> Context<'c> {
- let mut ctx = Context {
- algo,
- mode,
+ pub fn start<'c, C: Cipher<'c> + CipherSized>(&self, cipher: &'c C, dir: Direction) -> Context<'c, C> {
+ let mut ctx: Context<'c, C> = Context {
dir,
last_block_processed: false,
cr: 0,
iv: [0; 4],
- key,
csgcmccm: [0; 8],
csgcm: [0; 8],
aad_complete: false,
header_len: 0,
payload_len: 0,
+ cipher: cipher,
+ phantom_data: PhantomData,
};
T::regs().cr().modify(|w| w.set_crypen(false));
- // Checks for correctness
- if algo == Algorithm::AES {
- let keylen = key.len() * 8;
- let ivlen;
- if let Some(iv) = iv {
- ivlen = iv.len() * 8;
- } else {
- ivlen = 0;
- }
- match keylen {
- 128 => T::regs().cr().modify(|w| w.set_keysize(0)),
- 192 => T::regs().cr().modify(|w| w.set_keysize(1)),
- 256 => T::regs().cr().modify(|w| w.set_keysize(2)),
- _ => panic!("Key length must be 128, 192, or 256 bits."),
- }
+ let key = ctx.cipher.key();
- if (mode == Mode::GCM) && (ivlen != 96) {
- panic!("IV length must be 96 bits for GCM.");
- } else if (mode == Mode::CBC) && (ivlen != 128) {
- panic!("IV length must be 128 bits for CBC.");
- } else if (mode == Mode::CCM) && (ivlen != 128) {
- panic!("IV length must be 128 bits for CCM.");
- } else if (mode == Mode::CTR) && (ivlen != 128) {
- panic!("IV length must be 128 bits for CTR.");
- } else if (mode == Mode::GMAC) && (ivlen != 96) {
- panic!("IV length must be 96 bits for GMAC.");
- }
+ if key.len() == (128 / 8) {
+ T::regs().cr().modify(|w| w.set_keysize(0));
+ } else if key.len() == (192 / 8) {
+ T::regs().cr().modify(|w| w.set_keysize(1));
+ } else if key.len() == (256 / 8) {
+ T::regs().cr().modify(|w| w.set_keysize(2));
}
self.load_key(key);
@@ -137,40 +439,9 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Set data type to 8-bit. This will match software implementations.
T::regs().cr().modify(|w| w.set_datatype(2));
- self.prepare_key(&ctx);
+ ctx.cipher.prepare_key(&T::regs());
- if algo == Algorithm::AES {
- match mode {
- Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(4)),
- Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(5)),
- Mode::CTR => T::regs().cr().modify(|w| w.set_algomode0(6)),
- Mode::GCM => T::regs().cr().modify(|w| w.set_algomode0(0)),
- Mode::GMAC => T::regs().cr().modify(|w| w.set_algomode0(0)),
- Mode::CCM => T::regs().cr().modify(|w| w.set_algomode0(1)),
- }
- match mode {
- Mode::ECB => T::regs().cr().modify(|w| w.set_algomode3(false)),
- Mode::CBC => T::regs().cr().modify(|w| w.set_algomode3(false)),
- Mode::CTR => T::regs().cr().modify(|w| w.set_algomode3(false)),
- Mode::GCM => T::regs().cr().modify(|w| w.set_algomode3(true)),
- Mode::GMAC => T::regs().cr().modify(|w| w.set_algomode3(true)),
- Mode::CCM => T::regs().cr().modify(|w| w.set_algomode3(true)),
- }
- } else if algo == Algorithm::DES {
- T::regs().cr().modify(|w| w.set_algomode3(false));
- match mode {
- Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(2)),
- Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(3)),
- _ => panic!("Only ECB and CBC modes are valid for DES."),
- }
- } else if algo == Algorithm::TDES {
- T::regs().cr().modify(|w| w.set_algomode3(false));
- match mode {
- Mode::ECB => T::regs().cr().modify(|w| w.set_algomode0(0)),
- Mode::CBC => T::regs().cr().modify(|w| w.set_algomode0(1)),
- _ => panic!("Only ECB and CBC modes are valid for TDES."),
- }
- }
+ ctx.cipher.set_algomode(&T::regs());
// Set encrypt/decrypt
if dir == Direction::Encrypt {
@@ -180,38 +451,27 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
// Load the IV into the registers.
- if let Some(iv) = iv {
- let mut full_iv: [u8; 16] = [0; 16];
- full_iv[0..iv.len()].copy_from_slice(iv);
-
- if (mode == Mode::GCM) || (mode == Mode::GMAC) {
- full_iv[15] = 2;
- }
-
- let mut iv_idx = 0;
- let mut iv_word: [u8; 4] = [0; 4];
- iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
- iv_idx += 4;
- T::regs().init(0).ivlr().write_value(u32::from_be_bytes(iv_word));
- iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
- iv_idx += 4;
- T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
- iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
- iv_idx += 4;
- T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
- iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
- T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
- }
+ let iv = ctx.cipher.iv();
+ let mut full_iv: [u8; 16] = [0; 16];
+ full_iv[0..iv.len()].copy_from_slice(iv);
+ let mut iv_idx = 0;
+ let mut iv_word: [u8; 4] = [0; 4];
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+ iv_idx += 4;
+ T::regs().init(0).ivlr().write_value(u32::from_be_bytes(iv_word));
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+ iv_idx += 4;
+ T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+ iv_idx += 4;
+ T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
+ iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+ T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
// Flush in/out FIFOs
T::regs().cr().modify(|w| w.fflush());
- if mode == Mode::GCM {
- // GCM init phase
- T::regs().cr().modify(|w| w.set_gcm_ccmph(0));
- T::regs().cr().modify(|w| w.set_crypen(true));
- while T::regs().cr().read().crypen() {}
- }
+ ctx.cipher.init_phase(&T::regs());
self.store_context(&mut ctx);
@@ -224,42 +484,38 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// All AAD must be supplied to this function prior to starting the payload phase with `payload_blocking`.
/// The AAD must be supplied in multiples of the block size (128 bits), except when supplying the last block.
/// When supplying the last block of AAD, `last_aad_block` must be `true`.
- pub fn aad_blocking(&self, ctx: &mut Context, aad: &[u8], last_aad_block: bool) {
+ pub fn aad_blocking<'c, C: Cipher<'c> + CipherSized + CipherAuthenticated>(
+ &self,
+ ctx: &mut Context<'c, C>,
+ aad: &[u8],
+ last_aad_block: bool,
+ ) {
self.load_context(ctx);
- let block_size;
- if ctx.algo == Algorithm::DES {
- block_size = DES_BLOCK_SIZE;
- } else {
- block_size = AES_BLOCK_SIZE;
- }
- let last_block_remainder = aad.len() % block_size;
+ let last_block_remainder = aad.len() % C::BLOCK_SIZE;
// Perform checks for correctness.
if ctx.aad_complete {
panic!("Cannot update AAD after calling 'update'!")
}
- if (ctx.mode != Mode::GCM) && (ctx.mode != Mode::GMAC) && (ctx.mode != Mode::CCM) {
- panic!("Associated data only valid for GCM, GMAC, and CCM modes.")
- }
if !last_aad_block {
if last_block_remainder != 0 {
- panic!("Input length must be a multiple of {} bytes.", block_size);
+ panic!("Input length must be a multiple of {} bytes.", C::BLOCK_SIZE);
}
}
ctx.header_len += aad.len() as u64;
- // GCM header phase
+ // Header phase
T::regs().cr().modify(|w| w.set_crypen(false));
T::regs().cr().modify(|w| w.set_gcm_ccmph(1));
T::regs().cr().modify(|w| w.set_crypen(true));
// Load data into core, block by block.
- let num_full_blocks = aad.len() / block_size;
+ let num_full_blocks = aad.len() / C::BLOCK_SIZE;
for block in 0..num_full_blocks {
- let mut index = block * block_size;
- let end_index = index + block_size;
+ let mut index = block * C::BLOCK_SIZE;
+ let end_index = index + C::BLOCK_SIZE;
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
@@ -276,7 +532,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
last_block[..last_block_remainder].copy_from_slice(&aad[aad.len() - last_block_remainder..aad.len()]);
let mut index = 0;
- let end_index = block_size;
+ let end_index = C::BLOCK_SIZE;
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
@@ -307,16 +563,16 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// Data must be a multiple of block size (128-bits for AES, 64-bits for DES) for CBC and ECB modes.
/// Padding or ciphertext stealing must be managed by the application for these modes.
/// Data must also be a multiple of block size unless `last_block` is `true`.
- pub fn payload_blocking(&self, ctx: &mut Context, input: &[u8], output: &mut [u8], last_block: bool) {
+ pub fn payload_blocking<'c, C: Cipher<'c> + CipherSized>(
+ &self,
+ ctx: &mut Context<'c, C>,
+ input: &[u8],
+ output: &mut [u8],
+ last_block: bool,
+ ) {
self.load_context(ctx);
- let block_size;
- if ctx.algo == Algorithm::DES {
- block_size = DES_BLOCK_SIZE;
- } else {
- block_size = AES_BLOCK_SIZE;
- }
- let last_block_remainder = input.len() % block_size;
+ let last_block_remainder = input.len() % C::BLOCK_SIZE;
// Perform checks for correctness.
if !ctx.aad_complete && ctx.header_len > 0 {
@@ -328,9 +584,6 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().cr().modify(|w| w.fflush());
T::regs().cr().modify(|w| w.set_crypen(true));
}
- if ctx.mode == Mode::GMAC {
- panic!("GMAC works on header data only. Do not call this function for GMAC.");
- }
if ctx.last_block_processed {
panic!("The last block has already been processed!");
}
@@ -339,24 +592,23 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
if !last_block {
if last_block_remainder != 0 {
- panic!("Input length must be a multiple of {} bytes.", block_size);
+ panic!("Input length must be a multiple of {} bytes.", C::BLOCK_SIZE);
}
}
- if (ctx.mode == Mode::ECB) || (ctx.mode == Mode::CBC) {
+ if C::REQUIRES_PADDING {
if last_block_remainder != 0 {
- panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", block_size);
+ panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", C::BLOCK_SIZE);
}
}
-
if last_block {
ctx.last_block_processed = true;
}
// Load data into core, block by block.
- let num_full_blocks = input.len() / block_size;
+ let num_full_blocks = input.len() / C::BLOCK_SIZE;
for block in 0..num_full_blocks {
- let mut index = block * block_size;
- let end_index = index + block_size;
+ let mut index = block * C::BLOCK_SIZE;
+ let end_index = index + C::BLOCK_SIZE;
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
@@ -364,8 +616,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().din().write_value(u32::from_ne_bytes(in_word));
index += 4;
}
- let mut index = block * block_size;
- let end_index = index + block_size;
+ let mut index = block * C::BLOCK_SIZE;
+ let end_index = index + C::BLOCK_SIZE;
// Block until there is output to read.
while !T::regs().sr().read().ofne() {}
// Read block out
@@ -378,21 +630,13 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Handle the final block, which is incomplete.
if last_block_remainder > 0 {
- if ctx.mode == Mode::GCM && ctx.dir == Direction::Encrypt {
- //Handle special GCM partial block process.
- T::regs().cr().modify(|w| w.set_crypen(false));
- T::regs().cr().modify(|w| w.set_algomode3(false));
- T::regs().cr().modify(|w| w.set_algomode0(6));
- let iv1r = T::regs().csgcmccmr(7).read() - 1;
- T::regs().init(1).ivrr().write_value(iv1r);
- T::regs().cr().modify(|w| w.set_crypen(true));
- }
+ ctx.cipher.pre_final_block(&T::regs());
let mut intermediate_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
last_block[..last_block_remainder].copy_from_slice(&input[input.len() - last_block_remainder..input.len()]);
let mut index = 0;
- let end_index = block_size;
+ let end_index = C::BLOCK_SIZE;
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
@@ -401,7 +645,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
index += 4;
}
let mut index = 0;
- let end_index = block_size;
+ let end_index = C::BLOCK_SIZE;
// Block until there is output to read.
while !T::regs().sr().read().ofne() {}
// Read block out
@@ -416,41 +660,19 @@ impl<'d, T: Instance> Cryp<'d, T> {
output[output_len - last_block_remainder..output_len]
.copy_from_slice(&intermediate_data[0..last_block_remainder]);
- if ctx.mode == Mode::GCM && ctx.dir == Direction::Encrypt {
- //Handle special GCM partial block process.
- T::regs().cr().modify(|w| w.set_crypen(false));
- T::regs().cr().write(|w| w.set_algomode3(true));
- T::regs().cr().write(|w| w.set_algomode0(0));
- T::regs().init(1).ivrr().write_value(2);
- T::regs().cr().modify(|w| w.set_crypen(true));
- T::regs().cr().modify(|w| w.set_gcm_ccmph(3));
- let mut index = 0;
- let end_index = block_size;
- while index < end_index {
- let mut in_word: [u8; 4] = [0; 4];
- in_word.copy_from_slice(&intermediate_data[index..index + 4]);
- T::regs().din().write_value(u32::from_ne_bytes(in_word));
- index += 4;
- }
- for _ in 0..4 {
- T::regs().dout().read();
- }
- }
+ ctx.cipher.post_final_block(&T::regs(), ctx.dir, &intermediate_data);
}
ctx.payload_len += input.len() as u64;
}
/// This function only needs to be called for GCM, CCM, and GMAC modes to
- /// generate an authentication tag. Calling this function on any other mode
- /// does nothing except consumes the context. A buffer for the authentication
- /// tag must be supplied.
- pub fn finish_blocking(&self, mut ctx: Context, tag: &mut [u8; 16]) {
- // Just consume the context if called for any other mode.
- if (ctx.mode != Mode::GCM) || (ctx.mode != Mode::CCM) || (ctx.mode != Mode::GMAC) {
- return;
- }
-
+ /// generate an authentication tag.
+ pub fn finish_blocking<'c, C: Cipher<'c> + CipherSized + CipherAuthenticated>(
+ &self,
+ mut ctx: Context<'c, C>,
+ tag: &mut [u8; 16],
+ ) {
self.load_context(&mut ctx);
T::regs().cr().modify(|w| w.set_crypen(false));
@@ -477,17 +699,6 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().cr().modify(|w| w.set_crypen(false));
}
- fn prepare_key(&self, ctx: &Context) {
- if ctx.algo == Algorithm::AES && ctx.dir == Direction::Decrypt {
- if (ctx.mode == Mode::ECB) || (ctx.mode == Mode::CBC) {
- T::regs().cr().modify(|w| w.set_algomode0(7));
- T::regs().cr().modify(|w| w.set_algomode3(false));
- T::regs().cr().modify(|w| w.set_crypen(true));
- while T::regs().sr().read().busy() {}
- }
- }
- }
-
fn load_key(&self, key: &[u8]) {
// Load the key into the registers.
let mut keyidx = 0;
@@ -524,7 +735,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().key(3).krr().write_value(u32::from_be_bytes(keyword));
}
- fn store_context(&self, ctx: &mut Context) {
+ fn store_context<'c, C: Cipher<'c> + CipherSized>(&self, ctx: &mut Context<'c, C>) {
// Wait for data block processing to finish.
while !T::regs().sr().read().ifem() {}
while T::regs().sr().read().ofne() {}
@@ -545,7 +756,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
}
- fn load_context(&self, ctx: &Context) {
+ fn load_context<'c, C: Cipher<'c> + CipherSized>(&self, ctx: &Context<'c, C>) {
// Reload state registers.
T::regs().cr().write(|w| w.0 = ctx.cr);
T::regs().init(0).ivlr().write_value(ctx.iv[0]);
@@ -556,10 +767,10 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().csgcmccmr(i).write_value(ctx.csgcmccm[i]);
T::regs().csgcmr(i).write_value(ctx.csgcm[i]);
}
- self.load_key(ctx.key);
+ self.load_key(ctx.cipher.key());
// Prepare key if applicable.
- self.prepare_key(ctx);
+ ctx.cipher.prepare_key(&T::regs());
T::regs().cr().write(|w| w.0 = ctx.cr);
// Enable crypto processor.
From 690b2118c6fdad88bf1e595b6a0c0afdb0583d28 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 20 Feb 2024 11:54:39 -0500
Subject: [PATCH 317/392] CCM mode functional.
---
embassy-stm32/src/cryp/mod.rs | 372 ++++++++++++++++++++++++++--------
1 file changed, 293 insertions(+), 79 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 29c1db12e..fe248def1 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1,6 +1,6 @@
//! Crypto Accelerator (CRYP)
+use core::cmp::min;
use core::marker::PhantomData;
-
use embassy_hal_internal::{into_ref, PeripheralRef};
use crate::pac;
@@ -21,7 +21,7 @@ pub trait Cipher<'c> {
const REQUIRES_PADDING: bool = false;
/// Returns the symmetric key.
- fn key(&self) -> &'c [u8];
+ fn key(&self) -> &[u8];
/// Returns the initialization vector.
fn iv(&self) -> &[u8];
@@ -36,10 +36,25 @@ pub trait Cipher<'c> {
fn init_phase(&self, _p: &pac::cryp::Cryp) {}
/// Called prior to processing the last data block for cipher-specific operations.
- fn pre_final_block(&self, _p: &pac::cryp::Cryp) {}
+ fn pre_final_block(&self, _p: &pac::cryp::Cryp, _dir: Direction) -> [u32; 4] {
+ return [0; 4];
+ }
/// Called after processing the last data block for cipher-specific operations.
- fn post_final_block(&self, _p: &pac::cryp::Cryp, _dir: Direction, _int_data: &[u8; AES_BLOCK_SIZE]) {}
+ fn post_final_block(
+ &self,
+ _p: &pac::cryp::Cryp,
+ _dir: Direction,
+ _int_data: &[u8; AES_BLOCK_SIZE],
+ _temp1: [u32; 4],
+ _padding_mask: [u8; 16],
+ ) {
+ }
+
+ /// Called prior to processing the first associated data block for cipher-specific operations.
+ fn get_header_block(&self) -> &[u8] {
+ return [0; 0].as_slice();
+ }
}
/// This trait enables restriction of ciphers to specific key sizes.
@@ -204,17 +219,27 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
while p.cr().read().crypen() {}
}
- fn pre_final_block(&self, p: &pac::cryp::Cryp) {
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction) -> [u32; 4] {
//Handle special GCM partial block process.
- p.cr().modify(|w| w.set_crypen(false));
- p.cr().modify(|w| w.set_algomode3(false));
- p.cr().modify(|w| w.set_algomode0(6));
- let iv1r = p.csgcmccmr(7).read() - 1;
- p.init(1).ivrr().write_value(iv1r);
- p.cr().modify(|w| w.set_crypen(true));
+ if dir == Direction::Encrypt {
+ p.cr().modify(|w| w.set_crypen(false));
+ p.cr().modify(|w| w.set_algomode3(false));
+ p.cr().modify(|w| w.set_algomode0(6));
+ let iv1r = p.csgcmccmr(7).read() - 1;
+ p.init(1).ivrr().write_value(iv1r);
+ p.cr().modify(|w| w.set_crypen(true));
+ }
+ [0; 4]
}
- fn post_final_block(&self, p: &pac::cryp::Cryp, dir: Direction, int_data: &[u8; AES_BLOCK_SIZE]) {
+ fn post_final_block(
+ &self,
+ p: &pac::cryp::Cryp,
+ dir: Direction,
+ int_data: &[u8; AES_BLOCK_SIZE],
+ _temp1: [u32; 4],
+ _padding_mask: [u8; 16],
+ ) {
if dir == Direction::Encrypt {
//Handle special GCM partial block process.
p.cr().modify(|w| w.set_crypen(false));
@@ -281,17 +306,27 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
while p.cr().read().crypen() {}
}
- fn pre_final_block(&self, p: &pac::cryp::Cryp) {
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction) -> [u32; 4] {
//Handle special GCM partial block process.
- p.cr().modify(|w| w.set_crypen(false));
- p.cr().modify(|w| w.set_algomode3(false));
- p.cr().modify(|w| w.set_algomode0(6));
- let iv1r = p.csgcmccmr(7).read() - 1;
- p.init(1).ivrr().write_value(iv1r);
- p.cr().modify(|w| w.set_crypen(true));
+ if dir == Direction::Encrypt {
+ p.cr().modify(|w| w.set_crypen(false));
+ p.cr().modify(|w| w.set_algomode3(false));
+ p.cr().modify(|w| w.set_algomode0(6));
+ let iv1r = p.csgcmccmr(7).read() - 1;
+ p.init(1).ivrr().write_value(iv1r);
+ p.cr().modify(|w| w.set_crypen(true));
+ }
+ [0; 4]
}
- fn post_final_block(&self, p: &pac::cryp::Cryp, dir: Direction, int_data: &[u8; AES_BLOCK_SIZE]) {
+ fn post_final_block(
+ &self,
+ p: &pac::cryp::Cryp,
+ dir: Direction,
+ int_data: &[u8; AES_BLOCK_SIZE],
+ _temp1: [u32; 4],
+ _padding_mask: [u8; 16],
+ ) {
if dir == Direction::Encrypt {
//Handle special GCM partial block process.
p.cr().modify(|w| w.set_crypen(false));
@@ -320,49 +355,180 @@ impl<'c> CipherSized for AesGmac<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesGmac<'c, { 256 / 8 }> {}
impl<'c, const KEY_SIZE: usize> CipherAuthenticated for AesGmac<'c, KEY_SIZE> {}
-// struct AesCcm<'c, const KEY_SIZE: usize> {
-// iv: &'c [u8],
-// key: &'c [u8; KEY_SIZE],
-// aad_len: usize,
-// payload_len: usize,
-// }
+pub struct AesCcm<'c, const KEY_SIZE: usize> {
+ key: &'c [u8; KEY_SIZE],
+ aad_header: [u8; 6],
+ aad_header_len: usize,
+ block0: [u8; 16],
+ ctr: [u8; 16],
+}
-// impl<'c, const KEY_SIZE: usize> AesCcm<'c, KEY_SIZE> {
-// pub fn new(&self, key: &[u8; KEY_SIZE], iv: &[u8], aad_len: usize, payload_len: usize) {
-// if iv.len() > 13 {
-// panic!("CCM IV length must be 13 bytes or less.");
-// }
-// self.key = key;
-// self.iv = iv;
-// self.aad_len = aad_len;
-// self.payload_len = payload_len;
-// }
-// }
+impl<'c, const KEY_SIZE: usize> AesCcm<'c, KEY_SIZE> {
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8], aad_len: usize, payload_len: usize, tag_len: u8) -> Self {
+ if (iv.len()) > 13 || (iv.len() < 7) {
+ panic!("CCM IV length must be 7-13 bytes.");
+ }
+ if (tag_len < 4) || (tag_len > 16) {
+ panic!("Tag length must be between 4 and 16 bytes.");
+ }
+ if tag_len % 2 > 0 {
+ panic!("Tag length must be a multiple of 2 bytes.");
+ }
-// impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
-// const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
+ let mut aad_header: [u8; 6] = [0; 6];
+ let mut aad_header_len = 0;
+ let mut block0: [u8; 16] = [0; 16];
+ if aad_len != 0 {
+ if aad_len < 65280 {
+ aad_header[0] = (aad_len >> 8) as u8 & 0xFF;
+ aad_header[1] = aad_len as u8 & 0xFF;
+ aad_header_len = 2;
+ } else {
+ aad_header[0] = 0xFF;
+ aad_header[1] = 0xFE;
+ let aad_len_bytes: [u8; 4] = aad_len.to_be_bytes();
+ aad_header[2] = aad_len_bytes[0];
+ aad_header[3] = aad_len_bytes[1];
+ aad_header[4] = aad_len_bytes[2];
+ aad_header[5] = aad_len_bytes[3];
+ aad_header_len = 6;
+ }
+ }
+ let total_aad_len = aad_header_len + aad_len;
+ let mut aad_padding_len = 16 - (total_aad_len % 16);
+ if aad_padding_len == 16 {
+ aad_padding_len = 0;
+ }
+ aad_header_len += aad_padding_len;
+ let total_aad_len_padded = aad_header_len + aad_len;
+ if total_aad_len_padded > 0 {
+ block0[0] = 0x40;
+ }
+ block0[0] |= (((tag_len - 2) >> 1) & 0x07) << 3;
+ block0[0] |= ((15 - (iv.len() as u8)) - 1) & 0x07;
+ block0[1..1 + iv.len()].copy_from_slice(iv);
+ let payload_len_bytes: [u8; 4] = payload_len.to_be_bytes();
+ if iv.len() <= 11 {
+ block0[12] = payload_len_bytes[0];
+ } else if payload_len_bytes[0] > 0 {
+ panic!("Message is too large for given IV size.");
+ }
+ if iv.len() <= 12 {
+ block0[13] = payload_len_bytes[1];
+ } else if payload_len_bytes[1] > 0 {
+ panic!("Message is too large for given IV size.");
+ }
+ block0[14] = payload_len_bytes[2];
+ block0[15] = payload_len_bytes[3];
+ let mut ctr: [u8; 16] = [0; 16];
+ ctr[0] = block0[0] & 0x07;
+ ctr[1..1 + iv.len()].copy_from_slice(&block0[1..1 + iv.len()]);
+ ctr[15] = 0x01;
-// fn key(&self) -> &'c [u8] {
-// self.key
-// }
+ return Self {
+ key: key,
+ aad_header: aad_header,
+ aad_header_len: aad_header_len,
+ block0: block0,
+ ctr: ctr,
+ };
+ }
+}
-// fn iv(&self) -> &'c [u8] {
-// self.iv
-// }
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
-// fn set_algomode(&self, p: &pac::cryp::Cryp) {
-// p.cr().modify(|w| w.set_algomode0(1));
-// p.cr().modify(|w| w.set_algomode3(true));
-// }
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
-// fn init_phase(&self, p: &pac::cryp::Cryp) {
-// todo!();
-// }
-// }
+ fn iv(&self) -> &[u8] {
+ self.ctr.as_slice()
+ }
-// impl<'c> CipherSized for AesCcm<'c, { 128 / 8 }> {}
-// impl<'c> CipherSized for AesCcm<'c, { 192 / 8 }> {}
-// impl<'c> CipherSized for AesCcm<'c, { 256 / 8 }> {}
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(1));
+ p.cr().modify(|w| w.set_algomode3(true));
+ }
+
+ fn init_phase(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_gcm_ccmph(0));
+
+ let mut index = 0;
+ let end_index = index + Self::BLOCK_SIZE;
+ // Write block in
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&self.block0[index..index + 4]);
+ p.din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ p.cr().modify(|w| w.set_crypen(true));
+ while p.cr().read().crypen() {}
+ }
+
+ fn get_header_block(&self) -> &[u8] {
+ return &self.aad_header[0..self.aad_header_len];
+ }
+
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction) -> [u32; 4] {
+ //Handle special CCM partial block process.
+ let mut temp1 = [0; 4];
+ if dir == Direction::Decrypt {
+ p.cr().modify(|w| w.set_crypen(false));
+ let iv1temp = p.init(1).ivrr().read();
+ temp1[0] = p.csgcmccmr(0).read();
+ temp1[1] = p.csgcmccmr(1).read();
+ temp1[2] = p.csgcmccmr(2).read();
+ temp1[3] = p.csgcmccmr(3).read();
+ p.init(1).ivrr().write_value(iv1temp);
+ p.cr().modify(|w| w.set_algomode3(false));
+ p.cr().modify(|w| w.set_algomode0(6));
+ p.cr().modify(|w| w.set_crypen(true));
+ }
+ return temp1;
+ }
+
+ fn post_final_block(
+ &self,
+ p: &pac::cryp::Cryp,
+ dir: Direction,
+ int_data: &[u8; AES_BLOCK_SIZE],
+ temp1: [u32; 4],
+ padding_mask: [u8; 16],
+ ) {
+ if dir == Direction::Decrypt {
+ //Handle special CCM partial block process.
+ let mut intdata_o: [u32; 4] = [0; 4];
+ for i in 0..intdata_o.len() {
+ intdata_o[i] = p.dout().read();
+ }
+ let mut temp2 = [0; 4];
+ temp2[0] = p.csgcmccmr(0).read();
+ temp2[1] = p.csgcmccmr(1).read();
+ temp2[2] = p.csgcmccmr(2).read();
+ temp2[3] = p.csgcmccmr(3).read();
+ p.cr().write(|w| w.set_algomode3(true));
+ p.cr().write(|w| w.set_algomode0(1));
+ p.cr().modify(|w| w.set_gcm_ccmph(3));
+ // Header phase
+ p.cr().modify(|w| w.set_gcm_ccmph(1));
+ let mut in_data: [u32; 4] = [0; 4];
+ for i in 0..in_data.len() {
+ let mut mask_bytes: [u8; 4] = [0; 4];
+ mask_bytes.copy_from_slice(&padding_mask[(i * 4)..(i * 4) + 4]);
+ let mask_word = u32::from_le_bytes(mask_bytes);
+ in_data[i] = intdata_o[i] & mask_word;
+ in_data[i] = in_data[i] ^ temp1[i] ^ temp2[i];
+ }
+ }
+ }
+}
+
+impl<'c> CipherSized for AesCcm<'c, { 128 / 8 }> {}
+impl<'c> CipherSized for AesCcm<'c, { 192 / 8 }> {}
+impl<'c> CipherSized for AesCcm<'c, { 256 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> CipherAuthenticated for AesCcm<'c, KEY_SIZE> {}
/// Holds the state information for a cipher operation.
/// Allows suspending/resuming of cipher operations.
@@ -371,6 +537,7 @@ pub struct Context<'c, C: Cipher<'c> + CipherSized> {
cipher: &'c C,
dir: Direction,
last_block_processed: bool,
+ header_processed: bool,
aad_complete: bool,
cr: u32,
iv: [u32; 4],
@@ -378,6 +545,8 @@ pub struct Context<'c, C: Cipher<'c> + CipherSized> {
csgcm: [u32; 8],
header_len: u64,
payload_len: u64,
+ aad_buffer: [u8; 16],
+ aad_buffer_len: usize,
}
/// Selects whether the crypto processor operates in encryption or decryption mode.
@@ -420,6 +589,9 @@ impl<'d, T: Instance> Cryp<'d, T> {
payload_len: 0,
cipher: cipher,
phantom_data: PhantomData,
+ header_processed: false,
+ aad_buffer: [0; 16],
+ aad_buffer_len: 0,
};
T::regs().cr().modify(|w| w.set_crypen(false));
@@ -492,16 +664,9 @@ impl<'d, T: Instance> Cryp<'d, T> {
) {
self.load_context(ctx);
- let last_block_remainder = aad.len() % C::BLOCK_SIZE;
-
// Perform checks for correctness.
if ctx.aad_complete {
- panic!("Cannot update AAD after calling 'update'!")
- }
- if !last_aad_block {
- if last_block_remainder != 0 {
- panic!("Input length must be a multiple of {} bytes.", C::BLOCK_SIZE);
- }
+ panic!("Cannot update AAD after starting payload!")
}
ctx.header_len += aad.len() as u64;
@@ -511,11 +676,49 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().cr().modify(|w| w.set_gcm_ccmph(1));
T::regs().cr().modify(|w| w.set_crypen(true));
- // Load data into core, block by block.
- let num_full_blocks = aad.len() / C::BLOCK_SIZE;
- for block in 0..num_full_blocks {
- let mut index = block * C::BLOCK_SIZE;
- let end_index = index + C::BLOCK_SIZE;
+ // First write the header B1 block if not yet written.
+ if !ctx.header_processed {
+ ctx.header_processed = true;
+ let header = ctx.cipher.get_header_block();
+ ctx.aad_buffer[0..header.len()].copy_from_slice(header);
+ ctx.aad_buffer_len += header.len();
+ }
+
+ // Fill the header block to make a full block.
+ let len_to_copy = min(aad.len(), C::BLOCK_SIZE - ctx.aad_buffer_len);
+ ctx.aad_buffer[ctx.aad_buffer_len..ctx.aad_buffer_len + len_to_copy].copy_from_slice(&aad[..len_to_copy]);
+ ctx.aad_buffer_len += len_to_copy;
+ ctx.aad_buffer[ctx.aad_buffer_len..].fill(0);
+ let mut aad_len_remaining = aad.len() - len_to_copy;
+
+ if ctx.aad_buffer_len < C::BLOCK_SIZE {
+ // The buffer isn't full and this is the last buffer, so process it as is (already padded).
+ if last_aad_block {
+ let mut index = 0;
+ let end_index = C::BLOCK_SIZE;
+ // Write block in
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&aad[index..index + 4]);
+ T::regs().din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ // Block until input FIFO is empty.
+ while !T::regs().sr().read().ifem() {}
+
+ // Switch to payload phase.
+ ctx.aad_complete = true;
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
+ T::regs().cr().modify(|w| w.fflush());
+ } else {
+ // Just return because we don't yet have a full block to process.
+ return;
+ }
+ } else {
+ // Load the full block from the buffer.
+ let mut index = 0;
+ let end_index = C::BLOCK_SIZE;
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
@@ -527,20 +730,26 @@ impl<'d, T: Instance> Cryp<'d, T> {
while !T::regs().sr().read().ifem() {}
}
- // Handle the final block, which is incomplete.
- if last_block_remainder > 0 {
- let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
- last_block[..last_block_remainder].copy_from_slice(&aad[aad.len() - last_block_remainder..aad.len()]);
- let mut index = 0;
- let end_index = C::BLOCK_SIZE;
+ // Handle a partial block that is passed in.
+ ctx.aad_buffer_len = 0;
+ let leftovers = aad_len_remaining % C::BLOCK_SIZE;
+ ctx.aad_buffer[..leftovers].copy_from_slice(&aad[aad.len() - leftovers..aad.len()]);
+ aad_len_remaining -= leftovers;
+ assert_eq!(aad_len_remaining % C::BLOCK_SIZE, 0);
+
+ // Load full data blocks into core.
+ let num_full_blocks = aad_len_remaining / C::BLOCK_SIZE;
+ for _ in 0..num_full_blocks {
+ let mut index = len_to_copy;
+ let end_index = len_to_copy + C::BLOCK_SIZE;
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
- in_word.copy_from_slice(&last_block[index..index + 4]);
+ in_word.copy_from_slice(&aad[index..index + 4]);
T::regs().din().write_value(u32::from_ne_bytes(in_word));
index += 4;
}
- // Block until input FIFO is empty
+ // Block until input FIFO is empty.
while !T::regs().sr().read().ifem() {}
}
@@ -630,7 +839,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Handle the final block, which is incomplete.
if last_block_remainder > 0 {
- ctx.cipher.pre_final_block(&T::regs());
+ let temp1 = ctx.cipher.pre_final_block(&T::regs(), ctx.dir);
let mut intermediate_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
@@ -660,10 +869,15 @@ impl<'d, T: Instance> Cryp<'d, T> {
output[output_len - last_block_remainder..output_len]
.copy_from_slice(&intermediate_data[0..last_block_remainder]);
- ctx.cipher.post_final_block(&T::regs(), ctx.dir, &intermediate_data);
+ let mut mask: [u8; 16] = [0; 16];
+ mask[..last_block_remainder].fill(0xFF);
+ ctx.cipher
+ .post_final_block(&T::regs(), ctx.dir, &intermediate_data, temp1, mask);
}
ctx.payload_len += input.len() as u64;
+
+ self.store_context(ctx);
}
/// This function only needs to be called for GCM, CCM, and GMAC modes to
From 1e21b758f795b5cc8a2331aacbc2a9a39bb7a7fb Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 20 Feb 2024 14:27:37 -0500
Subject: [PATCH 318/392] Corrected GCM tag generation.
---
embassy-stm32/src/cryp/mod.rs | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index fe248def1..81446e39e 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -45,7 +45,7 @@ pub trait Cipher<'c> {
&self,
_p: &pac::cryp::Cryp,
_dir: Direction,
- _int_data: &[u8; AES_BLOCK_SIZE],
+ _int_data: &mut [u8; AES_BLOCK_SIZE],
_temp1: [u32; 4],
_padding_mask: [u8; 16],
) {
@@ -236,16 +236,18 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
&self,
p: &pac::cryp::Cryp,
dir: Direction,
- int_data: &[u8; AES_BLOCK_SIZE],
+ int_data: &mut [u8; AES_BLOCK_SIZE],
_temp1: [u32; 4],
- _padding_mask: [u8; 16],
+ padding_mask: [u8; AES_BLOCK_SIZE],
) {
if dir == Direction::Encrypt {
//Handle special GCM partial block process.
p.cr().modify(|w| w.set_crypen(false));
- p.cr().write(|w| w.set_algomode3(true));
- p.cr().write(|w| w.set_algomode0(0));
- p.init(1).ivrr().write_value(2);
+ p.cr().modify(|w| w.set_algomode3(true));
+ p.cr().modify(|w| w.set_algomode0(0));
+ for i in 0..AES_BLOCK_SIZE {
+ int_data[i] = int_data[i] & padding_mask[i];
+ }
p.cr().modify(|w| w.set_crypen(true));
p.cr().modify(|w| w.set_gcm_ccmph(3));
let mut index = 0;
@@ -323,7 +325,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
&self,
p: &pac::cryp::Cryp,
dir: Direction,
- int_data: &[u8; AES_BLOCK_SIZE],
+ int_data: &mut [u8; AES_BLOCK_SIZE],
_temp1: [u32; 4],
_padding_mask: [u8; 16],
) {
@@ -493,7 +495,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
&self,
p: &pac::cryp::Cryp,
dir: Direction,
- int_data: &[u8; AES_BLOCK_SIZE],
+ int_data: &mut [u8; AES_BLOCK_SIZE],
temp1: [u32; 4],
padding_mask: [u8; 16],
) {
@@ -872,7 +874,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
let mut mask: [u8; 16] = [0; 16];
mask[..last_block_remainder].fill(0xFF);
ctx.cipher
- .post_final_block(&T::regs(), ctx.dir, &intermediate_data, temp1, mask);
+ .post_final_block(&T::regs(), ctx.dir, &mut intermediate_data, temp1, mask);
}
ctx.payload_len += input.len() as u64;
From f64a62149e423f6fdb643f7343d971eedc4a3a12 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 20 Feb 2024 15:26:31 -0500
Subject: [PATCH 319/392] Corrected CCM partial block ops.
---
embassy-stm32/src/cryp/mod.rs | 46 ++++++++++++++++++-----------------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 81446e39e..634c85883 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -327,14 +327,16 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
dir: Direction,
int_data: &mut [u8; AES_BLOCK_SIZE],
_temp1: [u32; 4],
- _padding_mask: [u8; 16],
+ padding_mask: [u8; AES_BLOCK_SIZE],
) {
if dir == Direction::Encrypt {
//Handle special GCM partial block process.
p.cr().modify(|w| w.set_crypen(false));
- p.cr().write(|w| w.set_algomode3(true));
- p.cr().write(|w| w.set_algomode0(0));
- p.init(1).ivrr().write_value(2);
+ p.cr().modify(|w| w.set_algomode3(true));
+ p.cr().modify(|w| w.set_algomode0(0));
+ for i in 0..AES_BLOCK_SIZE {
+ int_data[i] = int_data[i] & padding_mask[i];
+ }
p.cr().modify(|w| w.set_crypen(true));
p.cr().modify(|w| w.set_gcm_ccmph(3));
let mut index = 0;
@@ -479,10 +481,10 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
if dir == Direction::Decrypt {
p.cr().modify(|w| w.set_crypen(false));
let iv1temp = p.init(1).ivrr().read();
- temp1[0] = p.csgcmccmr(0).read();
- temp1[1] = p.csgcmccmr(1).read();
- temp1[2] = p.csgcmccmr(2).read();
- temp1[3] = p.csgcmccmr(3).read();
+ temp1[0] = p.csgcmccmr(0).read().swap_bytes();
+ temp1[1] = p.csgcmccmr(1).read().swap_bytes();
+ temp1[2] = p.csgcmccmr(2).read().swap_bytes();
+ temp1[3] = p.csgcmccmr(3).read().swap_bytes();
p.init(1).ivrr().write_value(iv1temp);
p.cr().modify(|w| w.set_algomode3(false));
p.cr().modify(|w| w.set_algomode0(6));
@@ -501,27 +503,27 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
) {
if dir == Direction::Decrypt {
//Handle special CCM partial block process.
- let mut intdata_o: [u32; 4] = [0; 4];
- for i in 0..intdata_o.len() {
- intdata_o[i] = p.dout().read();
- }
let mut temp2 = [0; 4];
- temp2[0] = p.csgcmccmr(0).read();
- temp2[1] = p.csgcmccmr(1).read();
- temp2[2] = p.csgcmccmr(2).read();
- temp2[3] = p.csgcmccmr(3).read();
- p.cr().write(|w| w.set_algomode3(true));
- p.cr().write(|w| w.set_algomode0(1));
+ temp2[0] = p.csgcmccmr(0).read().swap_bytes();
+ temp2[1] = p.csgcmccmr(1).read().swap_bytes();
+ temp2[2] = p.csgcmccmr(2).read().swap_bytes();
+ temp2[3] = p.csgcmccmr(3).read().swap_bytes();
+ p.cr().modify(|w| w.set_algomode3(true));
+ p.cr().modify(|w| w.set_algomode0(1));
p.cr().modify(|w| w.set_gcm_ccmph(3));
// Header phase
p.cr().modify(|w| w.set_gcm_ccmph(1));
+ for i in 0..AES_BLOCK_SIZE {
+ int_data[i] = int_data[i] & padding_mask[i];
+ }
let mut in_data: [u32; 4] = [0; 4];
for i in 0..in_data.len() {
- let mut mask_bytes: [u8; 4] = [0; 4];
- mask_bytes.copy_from_slice(&padding_mask[(i * 4)..(i * 4) + 4]);
- let mask_word = u32::from_le_bytes(mask_bytes);
- in_data[i] = intdata_o[i] & mask_word;
+ let mut int_bytes: [u8; 4] = [0; 4];
+ int_bytes.copy_from_slice(&int_data[(i * 4)..(i * 4) + 4]);
+ let int_word = u32::from_le_bytes(int_bytes);
+ in_data[i] = int_word;
in_data[i] = in_data[i] ^ temp1[i] ^ temp2[i];
+ p.din().write_value(in_data[i]);
}
}
}
From 14c2c28e068d6e506c372611800e6dded8d8f440 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Tue, 20 Feb 2024 18:05:35 -0500
Subject: [PATCH 320/392] Corrected additional associated data operation.
---
embassy-stm32/src/cryp/mod.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 634c85883..d53252a6a 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -703,7 +703,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
- in_word.copy_from_slice(&aad[index..index + 4]);
+ in_word.copy_from_slice(&ctx.aad_buffer[index..index + 4]);
T::regs().din().write_value(u32::from_ne_bytes(in_word));
index += 4;
}
From 29d8b459568b53f1e281d0914b5c897206c9bd4b Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Wed, 21 Feb 2024 12:07:53 -0500
Subject: [PATCH 321/392] Add DES and TDES support. Support variable tag sizes.
---
embassy-stm32/src/cryp/mod.rs | 237 +++++++++++++++++++++++++++++-----
1 file changed, 203 insertions(+), 34 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index d53252a6a..a4f1e42dc 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -60,8 +60,152 @@ pub trait Cipher<'c> {
/// This trait enables restriction of ciphers to specific key sizes.
pub trait CipherSized {}
+/// This trait enables restriction of initialization vectors to sizes compatibile with a cipher mode.
+pub trait IVSized {}
+
/// This trait enables restriction of a header phase to authenticated ciphers only.
-pub trait CipherAuthenticated {}
+pub trait CipherAuthenticated<const TAG_SIZE: usize> {
+ /// Defines the authentication tag size.
+ const TAG_SIZE: usize = TAG_SIZE;
+}
+
+/// TDES-ECB Cipher Mode
+pub struct TdesEcb<'c, const KEY_SIZE: usize> {
+ iv: &'c [u8; 0],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> TdesEcb<'c, KEY_SIZE> {
+ /// Constructs a new AES-ECB cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE]) -> Self {
+ return Self { key: key, iv: &[0; 0] };
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesEcb<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = DES_BLOCK_SIZE;
+ const REQUIRES_PADDING: bool = true;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &'c [u8] {
+ self.iv
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(0));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
+}
+
+impl<'c> CipherSized for TdesEcb<'c, { 112 / 8 }> {}
+impl<'c> CipherSized for TdesEcb<'c, { 168 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> IVSized for TdesEcb<'c, KEY_SIZE> {}
+
+/// TDES-CBC Cipher Mode
+pub struct TdesCbc<'c, const KEY_SIZE: usize> {
+ iv: &'c [u8; 8],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> TdesCbc<'c, KEY_SIZE> {
+ /// Constructs a new TDES-CBC cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 8]) -> Self {
+ return Self { key: key, iv: iv };
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesCbc<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = DES_BLOCK_SIZE;
+ const REQUIRES_PADDING: bool = true;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &'c [u8] {
+ self.iv
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(1));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
+}
+
+impl<'c> CipherSized for TdesCbc<'c, { 112 / 8 }> {}
+impl<'c> CipherSized for TdesCbc<'c, { 168 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> IVSized for TdesCbc<'c, KEY_SIZE> {}
+
+/// DES-ECB Cipher Mode
+pub struct DesEcb<'c, const KEY_SIZE: usize> {
+ iv: &'c [u8; 0],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> DesEcb<'c, KEY_SIZE> {
+ /// Constructs a new AES-ECB cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE]) -> Self {
+ return Self { key: key, iv: &[0; 0] };
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesEcb<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = DES_BLOCK_SIZE;
+ const REQUIRES_PADDING: bool = true;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &'c [u8] {
+ self.iv
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(2));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
+}
+
+impl<'c> CipherSized for DesEcb<'c, { 56 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> IVSized for DesEcb<'c, KEY_SIZE> {}
+
+/// DES-CBC Cipher Mode
+pub struct DesCbc<'c, const KEY_SIZE: usize> {
+ iv: &'c [u8; 8],
+ key: &'c [u8; KEY_SIZE],
+}
+
+impl<'c, const KEY_SIZE: usize> DesCbc<'c, KEY_SIZE> {
+ /// Constructs a new AES-CBC cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 8]) -> Self {
+ return Self { key: key, iv: iv };
+ }
+}
+
+impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesCbc<'c, KEY_SIZE> {
+ const BLOCK_SIZE: usize = DES_BLOCK_SIZE;
+ const REQUIRES_PADDING: bool = true;
+
+ fn key(&self) -> &'c [u8] {
+ self.key
+ }
+
+ fn iv(&self) -> &'c [u8] {
+ self.iv
+ }
+
+ fn set_algomode(&self, p: &pac::cryp::Cryp) {
+ p.cr().modify(|w| w.set_algomode0(3));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
+}
+
+impl<'c> CipherSized for DesCbc<'c, { 56 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> IVSized for DesCbc<'c, KEY_SIZE> {}
/// AES-ECB Cipher Mode
pub struct AesEcb<'c, const KEY_SIZE: usize> {
@@ -96,7 +240,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(4));
+ p.cr().modify(|w| w.set_algomode0(2));
p.cr().modify(|w| w.set_algomode3(false));
}
}
@@ -104,6 +248,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
impl<'c> CipherSized for AesEcb<'c, { 128 / 8 }> {}
impl<'c> CipherSized for AesEcb<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesEcb<'c, { 256 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> IVSized for AesEcb<'c, KEY_SIZE> {}
/// AES-CBC Cipher Mode
pub struct AesCbc<'c, const KEY_SIZE: usize> {
@@ -146,6 +291,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCbc<'c, KEY_SIZE> {
impl<'c> CipherSized for AesCbc<'c, { 128 / 8 }> {}
impl<'c> CipherSized for AesCbc<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesCbc<'c, { 256 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> IVSized for AesCbc<'c, KEY_SIZE> {}
/// AES-CTR Cipher Mode
pub struct AesCtr<'c, const KEY_SIZE: usize> {
@@ -180,6 +326,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCtr<'c, KEY_SIZE> {
impl<'c> CipherSized for AesCtr<'c, { 128 / 8 }> {}
impl<'c> CipherSized for AesCtr<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesCtr<'c, { 256 / 8 }> {}
+impl<'c, const KEY_SIZE: usize> IVSized for AesCtr<'c, KEY_SIZE> {}
///AES-GCM Cipher Mode
pub struct AesGcm<'c, const KEY_SIZE: usize> {
@@ -268,7 +415,8 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
impl<'c> CipherSized for AesGcm<'c, { 128 / 8 }> {}
impl<'c> CipherSized for AesGcm<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesGcm<'c, { 256 / 8 }> {}
-impl<'c, const KEY_SIZE: usize> CipherAuthenticated for AesGcm<'c, KEY_SIZE> {}
+impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGcm<'c, KEY_SIZE> {}
+impl<'c, const KEY_SIZE: usize> IVSized for AesGcm<'c, KEY_SIZE> {}
/// AES-GMAC Cipher Mode
pub struct AesGmac<'c, const KEY_SIZE: usize> {
@@ -357,9 +505,11 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
impl<'c> CipherSized for AesGmac<'c, { 128 / 8 }> {}
impl<'c> CipherSized for AesGmac<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesGmac<'c, { 256 / 8 }> {}
-impl<'c, const KEY_SIZE: usize> CipherAuthenticated for AesGmac<'c, KEY_SIZE> {}
+impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGmac<'c, KEY_SIZE> {}
+impl<'c, const KEY_SIZE: usize> IVSized for AesGmac<'c, KEY_SIZE> {}
-pub struct AesCcm<'c, const KEY_SIZE: usize> {
+/// AES-CCM Cipher Mode
+pub struct AesCcm<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> {
key: &'c [u8; KEY_SIZE],
aad_header: [u8; 6],
aad_header_len: usize,
@@ -367,18 +517,9 @@ pub struct AesCcm<'c, const KEY_SIZE: usize> {
ctr: [u8; 16],
}
-impl<'c, const KEY_SIZE: usize> AesCcm<'c, KEY_SIZE> {
- pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8], aad_len: usize, payload_len: usize, tag_len: u8) -> Self {
- if (iv.len()) > 13 || (iv.len() < 7) {
- panic!("CCM IV length must be 7-13 bytes.");
- }
- if (tag_len < 4) || (tag_len > 16) {
- panic!("Tag length must be between 4 and 16 bytes.");
- }
- if tag_len % 2 > 0 {
- panic!("Tag length must be a multiple of 2 bytes.");
- }
-
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE> {
+ /// Constructs a new AES-CCM cipher for a cryptographic operation.
+ pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; IV_SIZE], aad_len: usize, payload_len: usize) -> Self {
let mut aad_header: [u8; 6] = [0; 6];
let mut aad_header_len = 0;
let mut block0: [u8; 16] = [0; 16];
@@ -408,7 +549,7 @@ impl<'c, const KEY_SIZE: usize> AesCcm<'c, KEY_SIZE> {
if total_aad_len_padded > 0 {
block0[0] = 0x40;
}
- block0[0] |= (((tag_len - 2) >> 1) & 0x07) << 3;
+ block0[0] |= ((((TAG_SIZE as u8) - 2) >> 1) & 0x07) << 3;
block0[0] |= ((15 - (iv.len() as u8)) - 1) & 0x07;
block0[1..1 + iv.len()].copy_from_slice(iv);
let payload_len_bytes: [u8; 4] = payload_len.to_be_bytes();
@@ -439,7 +580,9 @@ impl<'c, const KEY_SIZE: usize> AesCcm<'c, KEY_SIZE> {
}
}
-impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cipher<'c>
+ for AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE>
+{
const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
fn key(&self) -> &'c [u8] {
@@ -529,10 +672,23 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCcm<'c, KEY_SIZE> {
}
}
-impl<'c> CipherSized for AesCcm<'c, { 128 / 8 }> {}
-impl<'c> CipherSized for AesCcm<'c, { 192 / 8 }> {}
-impl<'c> CipherSized for AesCcm<'c, { 256 / 8 }> {}
-impl<'c, const KEY_SIZE: usize> CipherAuthenticated for AesCcm<'c, KEY_SIZE> {}
+impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 128 / 8 }, TAG_SIZE, IV_SIZE> {}
+impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 192 / 8 }, TAG_SIZE, IV_SIZE> {}
+impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 256 / 8 }, TAG_SIZE, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<4> for AesCcm<'c, KEY_SIZE, 4, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<6> for AesCcm<'c, KEY_SIZE, 6, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<8> for AesCcm<'c, KEY_SIZE, 8, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<10> for AesCcm<'c, KEY_SIZE, 10, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<12> for AesCcm<'c, KEY_SIZE, 12, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<14> for AesCcm<'c, KEY_SIZE, 14, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<16> for AesCcm<'c, KEY_SIZE, 16, IV_SIZE> {}
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 7> {}
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 8> {}
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 9> {}
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 10> {}
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 11> {}
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 12> {}
+impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 13> {}
/// Holds the state information for a cipher operation.
/// Allows suspending/resuming of cipher operations.
@@ -580,7 +736,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// Key size must be 128, 192, or 256 bits.
/// Initialization vector must only be supplied if necessary.
/// Panics if there is any mismatch in parameters, such as an incorrect IV length or invalid mode.
- pub fn start<'c, C: Cipher<'c> + CipherSized>(&self, cipher: &'c C, dir: Direction) -> Context<'c, C> {
+ pub fn start<'c, C: Cipher<'c> + CipherSized + IVSized>(&self, cipher: &'c C, dir: Direction) -> Context<'c, C> {
let mut ctx: Context<'c, C> = Context {
dir,
last_block_processed: false,
@@ -660,7 +816,11 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// All AAD must be supplied to this function prior to starting the payload phase with `payload_blocking`.
/// The AAD must be supplied in multiples of the block size (128 bits), except when supplying the last block.
/// When supplying the last block of AAD, `last_aad_block` must be `true`.
- pub fn aad_blocking<'c, C: Cipher<'c> + CipherSized + CipherAuthenticated>(
+ pub fn aad_blocking<
+ 'c,
+ const TAG_SIZE: usize,
+ C: Cipher<'c> + CipherSized + IVSized + CipherAuthenticated<TAG_SIZE>,
+ >(
&self,
ctx: &mut Context<'c, C>,
aad: &[u8],
@@ -776,7 +936,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// Data must be a multiple of block size (128-bits for AES, 64-bits for DES) for CBC and ECB modes.
/// Padding or ciphertext stealing must be managed by the application for these modes.
/// Data must also be a multiple of block size unless `last_block` is `true`.
- pub fn payload_blocking<'c, C: Cipher<'c> + CipherSized>(
+ pub fn payload_blocking<'c, C: Cipher<'c> + CipherSized + IVSized>(
&self,
ctx: &mut Context<'c, C>,
input: &[u8],
@@ -886,11 +1046,14 @@ impl<'d, T: Instance> Cryp<'d, T> {
/// This function only needs to be called for GCM, CCM, and GMAC modes to
/// generate an authentication tag.
- pub fn finish_blocking<'c, C: Cipher<'c> + CipherSized + CipherAuthenticated>(
+ pub fn finish_blocking<
+ 'c,
+ const TAG_SIZE: usize,
+ C: Cipher<'c> + CipherSized + IVSized + CipherAuthenticated<TAG_SIZE>,
+ >(
&self,
mut ctx: Context<'c, C>,
- tag: &mut [u8; 16],
- ) {
+ ) -> [u8; TAG_SIZE] {
self.load_context(&mut ctx);
T::regs().cr().modify(|w| w.set_crypen(false));
@@ -909,12 +1072,17 @@ impl<'d, T: Instance> Cryp<'d, T> {
while !T::regs().sr().read().ofne() {}
- tag[0..4].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
- tag[4..8].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
- tag[8..12].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
- tag[12..16].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ let mut full_tag: [u8; 16] = [0; 16];
+ full_tag[0..4].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ full_tag[4..8].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ full_tag[8..12].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ full_tag[12..16].copy_from_slice(T::regs().dout().read().to_ne_bytes().as_slice());
+ let mut tag: [u8; TAG_SIZE] = [0; TAG_SIZE];
+ tag.copy_from_slice(&full_tag[0..TAG_SIZE]);
T::regs().cr().modify(|w| w.set_crypen(false));
+
+ tag
}
fn load_key(&self, key: &[u8]) {
@@ -949,7 +1117,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
keyidx += 4;
T::regs().key(3).klr().write_value(u32::from_be_bytes(keyword));
- keyword.copy_from_slice(&key[keyidx..keyidx + 4]);
+ keyword = [0; 4];
+ keyword[0..key.len() - keyidx].copy_from_slice(&key[keyidx..key.len()]);
T::regs().key(3).krr().write_value(u32::from_be_bytes(keyword));
}
From cbca3a5c9f8f46582287b88db173ad6876686141 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Wed, 21 Feb 2024 12:39:10 -0500
Subject: [PATCH 322/392] Support v1 and v2 cryp variants.
---
embassy-stm32/src/cryp/mod.rs | 156 +++++++++++++++++++++++++++++-----
1 file changed, 133 insertions(+), 23 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index a4f1e42dc..965e4a35d 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1,4 +1,5 @@
//! Crypto Accelerator (CRYP)
+#[cfg(cryp_v2)]
use core::cmp::min;
use core::marker::PhantomData;
use embassy_hal_internal::{into_ref, PeripheralRef};
@@ -95,8 +96,15 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesEcb<'c, KEY_SIZE> {
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(0));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(0));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(0));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
}
}
@@ -130,8 +138,15 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesCbc<'c, KEY_SIZE> {
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(1));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(1));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(1));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
}
}
@@ -165,8 +180,15 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesEcb<'c, KEY_SIZE> {
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(2));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(2));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(2));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
}
}
@@ -199,8 +221,15 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesCbc<'c, KEY_SIZE> {
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(3));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(3));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(3));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
}
}
@@ -233,15 +262,29 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
}
fn prepare_key(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(7));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(7));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(7));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
p.cr().modify(|w| w.set_crypen(true));
while p.sr().read().busy() {}
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(2));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(2));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(2));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
}
}
@@ -276,15 +319,29 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCbc<'c, KEY_SIZE> {
}
fn prepare_key(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(7));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(7));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(7));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
p.cr().modify(|w| w.set_crypen(true));
while p.sr().read().busy() {}
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(5));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(5));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(5));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
}
}
@@ -318,8 +375,15 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCtr<'c, KEY_SIZE> {
}
fn set_algomode(&self, p: &pac::cryp::Cryp) {
- p.cr().modify(|w| w.set_algomode0(6));
- p.cr().modify(|w| w.set_algomode3(false));
+ #[cfg(cryp_v1)]
+ {
+ p.cr().modify(|w| w.set_algomode(6));
+ }
+ #[cfg(cryp_v2)]
+ {
+ p.cr().modify(|w| w.set_algomode0(6));
+ p.cr().modify(|w| w.set_algomode3(false));
+ }
}
}
@@ -328,12 +392,14 @@ impl<'c> CipherSized for AesCtr<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesCtr<'c, { 256 / 8 }> {}
impl<'c, const KEY_SIZE: usize> IVSized for AesCtr<'c, KEY_SIZE> {}
+#[cfg(cryp_v2)]
///AES-GCM Cipher Mode
pub struct AesGcm<'c, const KEY_SIZE: usize> {
iv: [u8; 16],
key: &'c [u8; KEY_SIZE],
}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> AesGcm<'c, KEY_SIZE> {
/// Constucts a new AES-GCM cipher for a cryptographic operation.
pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
@@ -344,6 +410,7 @@ impl<'c, const KEY_SIZE: usize> AesGcm<'c, KEY_SIZE> {
}
}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
@@ -412,18 +479,25 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
}
}
+#[cfg(cryp_v2)]
impl<'c> CipherSized for AesGcm<'c, { 128 / 8 }> {}
+#[cfg(cryp_v2)]
impl<'c> CipherSized for AesGcm<'c, { 192 / 8 }> {}
+#[cfg(cryp_v2)]
impl<'c> CipherSized for AesGcm<'c, { 256 / 8 }> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGcm<'c, KEY_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> IVSized for AesGcm<'c, KEY_SIZE> {}
+#[cfg(cryp_v2)]
/// AES-GMAC Cipher Mode
pub struct AesGmac<'c, const KEY_SIZE: usize> {
iv: [u8; 16],
key: &'c [u8; KEY_SIZE],
}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> AesGmac<'c, KEY_SIZE> {
/// Constructs a new AES-GMAC cipher for a cryptographic operation.
pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
@@ -434,6 +508,7 @@ impl<'c, const KEY_SIZE: usize> AesGmac<'c, KEY_SIZE> {
}
}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
@@ -502,12 +577,18 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
}
}
+#[cfg(cryp_v2)]
impl<'c> CipherSized for AesGmac<'c, { 128 / 8 }> {}
+#[cfg(cryp_v2)]
impl<'c> CipherSized for AesGmac<'c, { 192 / 8 }> {}
+#[cfg(cryp_v2)]
impl<'c> CipherSized for AesGmac<'c, { 256 / 8 }> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGmac<'c, KEY_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize> IVSized for AesGmac<'c, KEY_SIZE> {}
+#[cfg(cryp_v2)]
/// AES-CCM Cipher Mode
pub struct AesCcm<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> {
key: &'c [u8; KEY_SIZE],
@@ -517,6 +598,7 @@ pub struct AesCcm<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZ
ctr: [u8; 16],
}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE> {
/// Constructs a new AES-CCM cipher for a cryptographic operation.
pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; IV_SIZE], aad_len: usize, payload_len: usize) -> Self {
@@ -580,6 +662,7 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Aes
}
}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cipher<'c>
for AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE>
{
@@ -672,24 +755,42 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
}
}
+#[cfg(cryp_v2)]
impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 128 / 8 }, TAG_SIZE, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 192 / 8 }, TAG_SIZE, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 256 / 8 }, TAG_SIZE, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<4> for AesCcm<'c, KEY_SIZE, 4, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<6> for AesCcm<'c, KEY_SIZE, 6, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<8> for AesCcm<'c, KEY_SIZE, 8, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<10> for AesCcm<'c, KEY_SIZE, 10, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<12> for AesCcm<'c, KEY_SIZE, 12, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<14> for AesCcm<'c, KEY_SIZE, 14, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<16> for AesCcm<'c, KEY_SIZE, 16, IV_SIZE> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 7> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 8> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 9> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 10> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 11> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 12> {}
+#[cfg(cryp_v2)]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 13> {}
+#[allow(dead_code)]
/// Holds the state information for a cipher operation.
/// Allows suspending/resuming of cipher operations.
pub struct Context<'c, C: Cipher<'c> + CipherSized> {
@@ -810,6 +911,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
ctx
}
+ #[cfg(cryp_v2)]
/// Controls the header phase of cipher processing.
/// This function is only valid for GCM, CCM, and GMAC modes.
/// It only needs to be called if using one of these modes and there is associated data.
@@ -951,11 +1053,14 @@ impl<'d, T: Instance> Cryp<'d, T> {
if !ctx.aad_complete && ctx.header_len > 0 {
panic!("Additional associated data must be processed first!");
} else if !ctx.aad_complete {
- ctx.aad_complete = true;
- T::regs().cr().modify(|w| w.set_crypen(false));
- T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
- T::regs().cr().modify(|w| w.fflush());
- T::regs().cr().modify(|w| w.set_crypen(true));
+ #[cfg(cryp_v2)]
+ {
+ ctx.aad_complete = true;
+ T::regs().cr().modify(|w| w.set_crypen(false));
+ T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
+ T::regs().cr().modify(|w| w.fflush());
+ T::regs().cr().modify(|w| w.set_crypen(true));
+ }
}
if ctx.last_block_processed {
panic!("The last block has already been processed!");
@@ -1044,6 +1149,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
self.store_context(ctx);
}
+ #[cfg(cryp_v2)]
/// This function only needs to be called for GCM, CCM, and GMAC modes to
/// generate an authentication tag.
pub fn finish_blocking<
@@ -1137,6 +1243,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
ctx.iv[1] = T::regs().init(0).ivrr().read();
ctx.iv[2] = T::regs().init(1).ivlr().read();
ctx.iv[3] = T::regs().init(1).ivrr().read();
+
+ #[cfg(cryp_v2)]
for i in 0..8 {
ctx.csgcmccm[i] = T::regs().csgcmccmr(i).read();
ctx.csgcm[i] = T::regs().csgcmr(i).read();
@@ -1150,6 +1258,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().init(0).ivrr().write_value(ctx.iv[1]);
T::regs().init(1).ivlr().write_value(ctx.iv[2]);
T::regs().init(1).ivrr().write_value(ctx.iv[3]);
+
+ #[cfg(cryp_v2)]
for i in 0..8 {
T::regs().csgcmccmr(i).write_value(ctx.csgcmccm[i]);
T::regs().csgcmr(i).write_value(ctx.csgcm[i]);
From bf4cbd75779b230e9e33a9d2a849f67335a68cf9 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Thu, 22 Feb 2024 15:47:36 -0500
Subject: [PATCH 323/392] Add CRYP example.
---
examples/stm32f7/Cargo.toml | 1 +
examples/stm32f7/src/bin/cryp.rs | 69 ++++++++++++++++++++++++++++++++
2 files changed, 70 insertions(+)
create mode 100644 examples/stm32f7/src/bin/cryp.rs
diff --git a/examples/stm32f7/Cargo.toml b/examples/stm32f7/Cargo.toml
index 736e81723..305816a2b 100644
--- a/examples/stm32f7/Cargo.toml
+++ b/examples/stm32f7/Cargo.toml
@@ -30,6 +30,7 @@ embedded-storage = "0.3.1"
static_cell = "2"
sha2 = { version = "0.10.8", default-features = false }
hmac = "0.12.1"
+aes-gcm = {version = "0.10.3", default-features = false, features = ["aes", "heapless"] }
[profile.release]
debug = 2
diff --git a/examples/stm32f7/src/bin/cryp.rs b/examples/stm32f7/src/bin/cryp.rs
new file mode 100644
index 000000000..c1b80ddc3
--- /dev/null
+++ b/examples/stm32f7/src/bin/cryp.rs
@@ -0,0 +1,69 @@
+#![no_std]
+#![no_main]
+
+use aes_gcm::{
+ aead::{heapless::Vec, AeadInPlace, KeyInit},
+ Aes128Gcm,
+};
+use defmt::info;
+use embassy_executor::Spawner;
+use embassy_stm32::cryp::*;
+use embassy_stm32::Config;
+use embassy_time::Instant;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) -> ! {
+ let config = Config::default();
+ let p = embassy_stm32::init(config);
+
+ let payload: &[u8] = b"hello world";
+ let aad: &[u8] = b"additional data";
+
+ let hw_cryp = Cryp::new(p.CRYP);
+ let key: [u8; 16] = [0; 16];
+ let mut ciphertext: [u8; 11] = [0; 11];
+ let mut plaintext: [u8; 11] = [0; 11];
+ let iv: [u8; 12] = [0; 12];
+
+ let hw_start_time = Instant::now();
+
+ // Encrypt in hardware using AES-GCM 128-bit
+ let aes_gcm = AesGcm::new(&key, &iv);
+ let mut gcm_encrypt = hw_cryp.start(&aes_gcm, Direction::Encrypt);
+ hw_cryp.aad_blocking(&mut gcm_encrypt, aad, true);
+ hw_cryp.payload_blocking(&mut gcm_encrypt, payload, &mut ciphertext, true);
+ let encrypt_tag = hw_cryp.finish_blocking(gcm_encrypt);
+
+ // Decrypt in hardware using AES-GCM 128-bit
+ let mut gcm_decrypt = hw_cryp.start(&aes_gcm, Direction::Decrypt);
+ hw_cryp.aad_blocking(&mut gcm_decrypt, aad, true);
+ hw_cryp.payload_blocking(&mut gcm_decrypt, &ciphertext, &mut plaintext, true);
+ let decrypt_tag = hw_cryp.finish_blocking(gcm_decrypt);
+
+ let hw_end_time = Instant::now();
+ let hw_execution_time = hw_end_time - hw_start_time;
+
+ info!("AES-GCM Ciphertext: {:?}", ciphertext);
+ info!("AES-GCM Plaintext: {:?}", plaintext);
+ assert_eq!(payload, plaintext);
+ assert_eq!(encrypt_tag, decrypt_tag);
+
+ let sw_start_time = Instant::now();
+
+ //Encrypt in software using AES-GCM 128-bit
+ let mut payload_vec: Vec<u8, 32> = Vec::from_slice(&payload).unwrap();
+ let cipher = Aes128Gcm::new(&key.into());
+ let _ = cipher.encrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
+
+ //Decrypt in software using AES-GCM 128-bit
+ let _ = cipher.encrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
+
+ let sw_end_time = Instant::now();
+ let sw_execution_time = sw_end_time - sw_start_time;
+
+ info!("Hardware Execution Time: {:?}", hw_execution_time);
+ info!("Software Execution Time: {:?}", sw_execution_time);
+
+ loop {}
+}
From 967b4927b002dbcdcfbe968bf9c15014fc1de2a0 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Fri, 23 Feb 2024 16:05:18 -0500
Subject: [PATCH 324/392] Correct tag generation.
---
embassy-stm32/src/cryp/mod.rs | 8 ++++----
examples/stm32f7/src/bin/cryp.rs | 9 ++++++---
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 965e4a35d..038923870 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1166,10 +1166,10 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().cr().modify(|w| w.set_gcm_ccmph(3));
T::regs().cr().modify(|w| w.set_crypen(true));
- let headerlen1: u32 = (ctx.header_len >> 32) as u32;
- let headerlen2: u32 = ctx.header_len as u32;
- let payloadlen1: u32 = (ctx.payload_len >> 32) as u32;
- let payloadlen2: u32 = ctx.payload_len as u32;
+ let headerlen1: u32 = ((ctx.header_len * 8) >> 32) as u32;
+ let headerlen2: u32 = (ctx.header_len * 8) as u32;
+ let payloadlen1: u32 = ((ctx.payload_len * 8) >> 32) as u32;
+ let payloadlen2: u32 = (ctx.payload_len * 8) as u32;
T::regs().din().write_value(headerlen1.swap_bytes());
T::regs().din().write_value(headerlen2.swap_bytes());
diff --git a/examples/stm32f7/src/bin/cryp.rs b/examples/stm32f7/src/bin/cryp.rs
index c1b80ddc3..be41955c5 100644
--- a/examples/stm32f7/src/bin/cryp.rs
+++ b/examples/stm32f7/src/bin/cryp.rs
@@ -51,13 +51,16 @@ async fn main(_spawner: Spawner) -> ! {
let sw_start_time = Instant::now();
- //Encrypt in software using AES-GCM 128-bit
+ // Encrypt in software using AES-GCM 128-bit
let mut payload_vec: Vec<u8, 32> = Vec::from_slice(&payload).unwrap();
let cipher = Aes128Gcm::new(&key.into());
let _ = cipher.encrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
+
+ assert_eq!(ciphertext, payload_vec[0..ciphertext.len()]);
+ assert_eq!(encrypt_tag, payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]);
- //Decrypt in software using AES-GCM 128-bit
- let _ = cipher.encrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
+ // Decrypt in software using AES-GCM 128-bit
+ let _ = cipher.decrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
let sw_end_time = Instant::now();
let sw_execution_time = sw_end_time - sw_start_time;
From 25ec838af597cc2e39c530b44f1a101c80b24260 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sat, 24 Feb 2024 15:55:20 -0500
Subject: [PATCH 325/392] Correct AAD ingest.
---
embassy-stm32/src/cryp/mod.rs | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 038923870..9d1a62905 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -988,7 +988,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
- in_word.copy_from_slice(&aad[index..index + 4]);
+ in_word.copy_from_slice(&ctx.aad_buffer[index..index + 4]);
T::regs().din().write_value(u32::from_ne_bytes(in_word));
index += 4;
}
@@ -1000,14 +1000,16 @@ impl<'d, T: Instance> Cryp<'d, T> {
ctx.aad_buffer_len = 0;
let leftovers = aad_len_remaining % C::BLOCK_SIZE;
ctx.aad_buffer[..leftovers].copy_from_slice(&aad[aad.len() - leftovers..aad.len()]);
+ ctx.aad_buffer_len += leftovers;
+ ctx.aad_buffer[ctx.aad_buffer_len..].fill(0);
aad_len_remaining -= leftovers;
assert_eq!(aad_len_remaining % C::BLOCK_SIZE, 0);
// Load full data blocks into core.
let num_full_blocks = aad_len_remaining / C::BLOCK_SIZE;
- for _ in 0..num_full_blocks {
- let mut index = len_to_copy;
- let end_index = len_to_copy + C::BLOCK_SIZE;
+ for block in 0..num_full_blocks {
+ let mut index = len_to_copy + (block * C::BLOCK_SIZE);
+ let end_index = index + C::BLOCK_SIZE;
// Write block in
while index < end_index {
let mut in_word: [u8; 4] = [0; 4];
@@ -1020,6 +1022,19 @@ impl<'d, T: Instance> Cryp<'d, T> {
}
if last_aad_block {
+ if leftovers > 0 {
+ let mut index = 0;
+ let end_index = C::BLOCK_SIZE;
+ // Write block in
+ while index < end_index {
+ let mut in_word: [u8; 4] = [0; 4];
+ in_word.copy_from_slice(&ctx.aad_buffer[index..index + 4]);
+ T::regs().din().write_value(u32::from_ne_bytes(in_word));
+ index += 4;
+ }
+ // Block until input FIFO is empty.
+ while !T::regs().sr().read().ifem() {}
+ }
// Switch to payload phase.
ctx.aad_complete = true;
T::regs().cr().modify(|w| w.set_crypen(false));
@@ -1065,7 +1080,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
if ctx.last_block_processed {
panic!("The last block has already been processed!");
}
- if input.len() != output.len() {
+ if input.len() > output.len() {
panic!("Output buffer length must match input length.");
}
if !last_block {
From f352b6d68b17fee886af58494b7e793cea3ea383 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sat, 24 Feb 2024 16:14:44 -0500
Subject: [PATCH 326/392] Address CI build issues.
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/cryp/mod.rs | 7 +++----
examples/stm32f7/src/bin/cryp.rs | 14 ++++++++------
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index d585d2cd6..4c856141b 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6097928f720646c73d6483a3245f922bd5faee2f" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ca48d946840840c5b311c96ff17cf4f8a865f9fb" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-6097928f720646c73d6483a3245f922bd5faee2f", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ca48d946840840c5b311c96ff17cf4f8a865f9fb", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 9d1a62905..fef5def6a 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -2,12 +2,11 @@
#[cfg(cryp_v2)]
use core::cmp::min;
use core::marker::PhantomData;
+
use embassy_hal_internal::{into_ref, PeripheralRef};
-use crate::pac;
-use crate::peripherals::CRYP;
use crate::rcc::sealed::RccPeripheral;
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, pac, peripherals, Peripheral};
const DES_BLOCK_SIZE: usize = 8; // 64 bits
const AES_BLOCK_SIZE: usize = 16; // 128 bits
@@ -827,7 +826,7 @@ pub struct Cryp<'d, T: Instance> {
impl<'d, T: Instance> Cryp<'d, T> {
/// Create a new CRYP driver.
pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
- CRYP::enable_and_reset();
+ T::enable_and_reset();
into_ref!(peri);
let instance = Self { _peripheral: peri };
instance
diff --git a/examples/stm32f7/src/bin/cryp.rs b/examples/stm32f7/src/bin/cryp.rs
index be41955c5..04927841a 100644
--- a/examples/stm32f7/src/bin/cryp.rs
+++ b/examples/stm32f7/src/bin/cryp.rs
@@ -1,10 +1,9 @@
#![no_std]
#![no_main]
-use aes_gcm::{
- aead::{heapless::Vec, AeadInPlace, KeyInit},
- Aes128Gcm,
-};
+use aes_gcm::aead::heapless::Vec;
+use aes_gcm::aead::{AeadInPlace, KeyInit};
+use aes_gcm::Aes128Gcm;
use defmt::info;
use embassy_executor::Spawner;
use embassy_stm32::cryp::*;
@@ -55,9 +54,12 @@ async fn main(_spawner: Spawner) -> ! {
let mut payload_vec: Vec<u8, 32> = Vec::from_slice(&payload).unwrap();
let cipher = Aes128Gcm::new(&key.into());
let _ = cipher.encrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
-
+
assert_eq!(ciphertext, payload_vec[0..ciphertext.len()]);
- assert_eq!(encrypt_tag, payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]);
+ assert_eq!(
+ encrypt_tag,
+ payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]
+ );
// Decrypt in software using AES-GCM 128-bit
let _ = cipher.decrypt_in_place(&iv.into(), aad.into(), &mut payload_vec);
From 236fc6f650af41980af05ef03a3901b2dfcfc381 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sat, 24 Feb 2024 16:31:43 -0500
Subject: [PATCH 327/392] Add CRYP test.
---
embassy-stm32/src/cryp/mod.rs | 1 -
tests/stm32/Cargo.toml | 11 +++++-
tests/stm32/src/bin/cryp.rs | 71 +++++++++++++++++++++++++++++++++++
3 files changed, 80 insertions(+), 3 deletions(-)
create mode 100644 tests/stm32/src/bin/cryp.rs
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index fef5def6a..bb64fa423 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -5,7 +5,6 @@ use core::marker::PhantomData;
use embassy_hal_internal::{into_ref, PeripheralRef};
-use crate::rcc::sealed::RccPeripheral;
use crate::{interrupt, pac, peripherals, Peripheral};
const DES_BLOCK_SIZE: usize = 8; // 64 bits
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 828a28e2c..37519ba11 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -16,8 +16,8 @@ stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng", "fdcan"]
stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "hash"]
-stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan", "hash"]
-stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan", "hash"]
+stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan", "hash", "cryp"]
+stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan", "hash", "cryp"]
stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
@@ -33,6 +33,7 @@ stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]
stm32f091rc = ["embassy-stm32/stm32f091rc", "cm0", "not-gpdma", "chrono"]
stm32h503rb = ["embassy-stm32/stm32h503rb", "rng"]
+cryp = []
hash = []
eth = ["embassy-executor/task-arena-size-16384"]
rng = []
@@ -80,6 +81,7 @@ portable-atomic = { version = "1.5", features = [] }
chrono = { version = "^0.4", default-features = false, optional = true}
sha2 = { version = "0.10.8", default-features = false }
hmac = "0.12.1"
+aes-gcm = {version = "0.10.3", default-features = false, features = ["aes", "heapless"] }
# BEGIN TESTS
# Generated by gen_test.py. DO NOT EDIT.
@@ -88,6 +90,11 @@ name = "can"
path = "src/bin/can.rs"
required-features = [ "can",]
+[[bin]]
+name = "cryp"
+path = "src/bin/cryp.rs"
+required-features = [ "hash",]
+
[[bin]]
name = "dac"
path = "src/bin/dac.rs"
diff --git a/tests/stm32/src/bin/cryp.rs b/tests/stm32/src/bin/cryp.rs
new file mode 100644
index 000000000..59c85f258
--- /dev/null
+++ b/tests/stm32/src/bin/cryp.rs
@@ -0,0 +1,71 @@
+// required-features: cryp
+#![no_std]
+#![no_main]
+
+#[path = "../common.rs"]
+mod common;
+
+use aes_gcm::aead::heapless::Vec;
+use aes_gcm::aead::{AeadInPlace, KeyInit};
+use aes_gcm::Aes128Gcm;
+use common::*;
+use embassy_executor::Spawner;
+use embassy_stm32::cryp::*;
+use {defmt_rtt as _, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
+
+ const PAYLOAD1: &[u8] = b"payload data 1 ;zdfhzdfhS;GKJASBDG;ASKDJBAL,zdfhzdfhzdfhzdfhvljhb,jhbjhb,sdhsdghsdhsfhsghzdfhzdfhzdfhzdfdhsdthsthsdhsgaadfhhgkdgfuoyguoft6783567";
+ const PAYLOAD2: &[u8] = b"payload data 2 ;SKEzdfhzdfhzbhgvljhb,jhbjhb,sdhsdghsdhsfhsghshsfhshstsdthadfhsdfjhsfgjsfgjxfgjzdhgDFghSDGHjtfjtjszftjzsdtjhstdsdhsdhsdhsdhsdthsthsdhsgfh";
+ const AAD1: &[u8] = b"additional data 1 stdargadrhaethaethjatjatjaetjartjstrjsfkk;'jopofyuisrteytweTASTUIKFUKIXTRDTEREharhaeryhaterjartjarthaethjrtjarthaetrhartjatejatrjsrtjartjyt1";
+ const AAD2: &[u8] = b"additional data 2 stdhthsthsthsrthsrthsrtjdykjdukdyuldadfhsdghsdghsdghsadghjk'hioethjrtjarthaetrhartjatecfgjhzdfhgzdfhzdfghzdfhzdfhzfhjatrjsrtjartjytjfytjfyg";
+
+ let hw_cryp = Cryp::new(p.CRYP);
+ let key: [u8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
+ let mut ciphertext: [u8; PAYLOAD1.len() + PAYLOAD2.len()] = [0; PAYLOAD1.len() + PAYLOAD2.len()];
+ let mut plaintext: [u8; PAYLOAD1.len() + PAYLOAD2.len()] = [0; PAYLOAD1.len() + PAYLOAD2.len()];
+ let iv: [u8; 12] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12];
+
+ // Encrypt in hardware using AES-GCM 128-bit
+ let aes_gcm = AesGcm::new(&key, &iv);
+ let mut gcm_encrypt = hw_cryp.start(&aes_gcm, Direction::Encrypt);
+ hw_cryp.aad_blocking(&mut gcm_encrypt, AAD1, false);
+ hw_cryp.aad_blocking(&mut gcm_encrypt, AAD2, true);
+ hw_cryp.payload_blocking(&mut gcm_encrypt, PAYLOAD1, &mut ciphertext[..PAYLOAD1.len()], false);
+ hw_cryp.payload_blocking(&mut gcm_encrypt, PAYLOAD2, &mut ciphertext[PAYLOAD1.len()..], true);
+ let encrypt_tag = hw_cryp.finish_blocking(gcm_encrypt);
+
+ // Decrypt in hardware using AES-GCM 128-bit
+ let mut gcm_decrypt = hw_cryp.start(&aes_gcm, Direction::Decrypt);
+ hw_cryp.aad_blocking(&mut gcm_decrypt, AAD1, false);
+ hw_cryp.aad_blocking(&mut gcm_decrypt, AAD2, true);
+ hw_cryp.payload_blocking(&mut gcm_decrypt, &ciphertext, &mut plaintext, true);
+ let decrypt_tag = hw_cryp.finish_blocking(gcm_decrypt);
+
+ info!("AES-GCM Ciphertext: {:?}", ciphertext);
+ info!("AES-GCM Plaintext: {:?}", plaintext);
+ defmt::assert!(PAYLOAD1 == &plaintext[..PAYLOAD1.len()]);
+ defmt::assert!(PAYLOAD2 == &plaintext[PAYLOAD1.len()..]);
+ defmt::assert!(encrypt_tag == decrypt_tag);
+
+ // Encrypt in software using AES-GCM 128-bit
+ let mut payload_vec: Vec<u8, { PAYLOAD1.len() + PAYLOAD2.len() + 16 }> = Vec::from_slice(&PAYLOAD1).unwrap();
+ payload_vec.extend_from_slice(&PAYLOAD2).unwrap();
+ let cipher = Aes128Gcm::new(&key.into());
+ let mut aad: Vec<u8, { AAD1.len() + AAD2.len() }> = Vec::from_slice(&AAD1).unwrap();
+ aad.extend_from_slice(&AAD2).unwrap();
+ let _ = cipher.encrypt_in_place(&iv.into(), &aad, &mut payload_vec);
+
+ defmt::assert!(ciphertext == payload_vec[0..ciphertext.len()]);
+ defmt::assert!(
+ encrypt_tag == payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]
+ );
+
+ // Decrypt in software using AES-GCM 128-bit
+ let _ = cipher.decrypt_in_place(&iv.into(), &aad, &mut payload_vec);
+
+ info!("Test OK");
+ cortex_m::asm::bkpt();
+}
From d9c0da8102226cebc36c92b874b8f0bf966ac959 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 25 Feb 2024 20:58:35 -0500
Subject: [PATCH 328/392] Update metapac to address CI build issue.
---
embassy-stm32/Cargo.toml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 4c856141b..e0bee6a92 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ca48d946840840c5b311c96ff17cf4f8a865f9fb" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-ca48d946840840c5b311c96ff17cf4f8a865f9fb", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4", default-features = false, features = ["metadata"]}
[features]
From 72c6f9a101141183fb2de46c2fe40aa979330d9c Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 26 Feb 2024 02:58:03 +0100
Subject: [PATCH 329/392] stm32/adc: reexport enums from PAC to avoid
boilerplate hell.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/adc/f1.rs | 18 ++--
embassy-stm32/src/adc/f3.rs | 16 +--
embassy-stm32/src/adc/f3_v1_1.rs | 51 +++++----
embassy-stm32/src/adc/mod.rs | 35 +++++--
embassy-stm32/src/adc/resolution.rs | 72 -------------
embassy-stm32/src/adc/sample_time.rs | 148 ---------------------------
embassy-stm32/src/adc/v1.rs | 2 +-
embassy-stm32/src/adc/v2.rs | 2 +-
embassy-stm32/src/adc/v3.rs | 6 +-
embassy-stm32/src/adc/v4.rs | 2 +-
examples/stm32f0/src/bin/adc.rs | 2 +-
examples/stm32f334/src/bin/adc.rs | 2 +-
examples/stm32f334/src/bin/opamp.rs | 2 +-
examples/stm32g4/src/bin/adc.rs | 2 +-
examples/stm32h7/src/bin/adc.rs | 2 +-
examples/stm32l0/src/bin/adc.rs | 2 +-
examples/stm32l4/src/bin/adc.rs | 2 +-
18 files changed, 82 insertions(+), 288 deletions(-)
delete mode 100644 embassy-stm32/src/adc/resolution.rs
delete mode 100644 embassy-stm32/src/adc/sample_time.rs
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index e0bee6a92..7d21383c3 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-88f71cbcd2f048c40bad162c7e7864cc3897eba4", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index c896d8e3a..b27b99827 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -74,7 +74,7 @@ impl<'d, T: Instance> Adc<'d, T> {
Self {
adc,
- sample_time: Default::default(),
+ sample_time: SampleTime::from_bits(0),
}
}
@@ -84,14 +84,14 @@ impl<'d, T: Instance> Adc<'d, T> {
pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
match us * Self::freq().0 / 1_000_000 {
- 0..=1 => SampleTime::Cycles1_5,
- 2..=7 => SampleTime::Cycles7_5,
- 8..=13 => SampleTime::Cycles13_5,
- 14..=28 => SampleTime::Cycles28_5,
- 29..=41 => SampleTime::Cycles41_5,
- 42..=55 => SampleTime::Cycles55_5,
- 56..=71 => SampleTime::Cycles71_5,
- _ => SampleTime::Cycles239_5,
+ 0..=1 => SampleTime::CYCLES1_5,
+ 2..=7 => SampleTime::CYCLES7_5,
+ 8..=13 => SampleTime::CYCLES13_5,
+ 14..=28 => SampleTime::CYCLES28_5,
+ 29..=41 => SampleTime::CYCLES41_5,
+ 42..=55 => SampleTime::CYCLES55_5,
+ 56..=71 => SampleTime::CYCLES71_5,
+ _ => SampleTime::CYCLES239_5,
}
}
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 6606a2b9c..efade1f64 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -97,7 +97,7 @@ impl<'d, T: Instance> Adc<'d, T> {
Self {
adc,
- sample_time: Default::default(),
+ sample_time: SampleTime::from_bits(0),
}
}
@@ -107,13 +107,13 @@ impl<'d, T: Instance> Adc<'d, T> {
pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
match us * Self::freq().0 / 1_000_000 {
- 0..=1 => SampleTime::Cycles1_5,
- 2..=4 => SampleTime::Cycles4_5,
- 5..=7 => SampleTime::Cycles7_5,
- 8..=19 => SampleTime::Cycles19_5,
- 20..=61 => SampleTime::Cycles61_5,
- 62..=181 => SampleTime::Cycles181_5,
- _ => SampleTime::Cycles601_5,
+ 0..=1 => SampleTime::CYCLES1_5,
+ 2..=4 => SampleTime::CYCLES4_5,
+ 5..=7 => SampleTime::CYCLES7_5,
+ 8..=19 => SampleTime::CYCLES19_5,
+ 20..=61 => SampleTime::CYCLES61_5,
+ 62..=181 => SampleTime::CYCLES181_5,
+ _ => SampleTime::CYCLES601_5,
}
}
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 6915a8f1c..f842893fa 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -107,12 +107,12 @@ impl Calibration {
/// Returns a calibrated voltage value as in microvolts (uV)
pub fn cal_uv(&self, raw: u16, resolution: super::Resolution) -> u32 {
- (self.vdda_uv() / resolution.to_max_count()) * raw as u32
+ (self.vdda_uv() / super::resolution_to_max_count(resolution)) * raw as u32
}
/// Returns a calibrated voltage value as an f32
pub fn cal_f32(&self, raw: u16, resolution: super::Resolution) -> f32 {
- raw as f32 * self.vdda_f32() / resolution.to_max_count() as f32
+ raw as f32 * self.vdda_f32() / super::resolution_to_max_count(resolution) as f32
}
}
@@ -175,12 +175,7 @@ impl<'d, T: Instance> Adc<'d, T> {
}
pub fn resolution(&self) -> Resolution {
- match T::regs().cr1().read().res() {
- crate::pac::adc::vals::Res::TWELVEBIT => Resolution::TwelveBit,
- crate::pac::adc::vals::Res::TENBIT => Resolution::TenBit,
- crate::pac::adc::vals::Res::EIGHTBIT => Resolution::EightBit,
- crate::pac::adc::vals::Res::SIXBIT => Resolution::SixBit,
- }
+ T::regs().cr1().read().res()
}
pub fn enable_vref(&self) -> Vref<T> {
@@ -359,23 +354,23 @@ impl<'d, T: Instance> Adc<'d, T> {
fn get_res_clks(res: Resolution) -> u32 {
match res {
- Resolution::TwelveBit => 12,
- Resolution::TenBit => 11,
- Resolution::EightBit => 9,
- Resolution::SixBit => 7,
+ Resolution::BITS12 => 12,
+ Resolution::BITS10 => 11,
+ Resolution::BITS8 => 9,
+ Resolution::BITS6 => 7,
}
}
fn get_sample_time_clks(sample_time: SampleTime) -> u32 {
match sample_time {
- SampleTime::Cycles4 => 4,
- SampleTime::Cycles9 => 9,
- SampleTime::Cycles16 => 16,
- SampleTime::Cycles24 => 24,
- SampleTime::Cycles48 => 48,
- SampleTime::Cycles96 => 96,
- SampleTime::Cycles192 => 192,
- SampleTime::Cycles384 => 384,
+ SampleTime::CYCLES4 => 4,
+ SampleTime::CYCLES9 => 9,
+ SampleTime::CYCLES16 => 16,
+ SampleTime::CYCLES24 => 24,
+ SampleTime::CYCLES48 => 48,
+ SampleTime::CYCLES96 => 96,
+ SampleTime::CYCLES192 => 192,
+ SampleTime::CYCLES384 => 384,
}
}
@@ -384,14 +379,14 @@ impl<'d, T: Instance> Adc<'d, T> {
let us_clks = us * Self::freq().0 / 1_000_000;
let clks = us_clks.saturating_sub(res_clks);
match clks {
- 0..=4 => SampleTime::Cycles4,
- 5..=9 => SampleTime::Cycles9,
- 10..=16 => SampleTime::Cycles16,
- 17..=24 => SampleTime::Cycles24,
- 25..=48 => SampleTime::Cycles48,
- 49..=96 => SampleTime::Cycles96,
- 97..=192 => SampleTime::Cycles192,
- 193.. => SampleTime::Cycles384,
+ 0..=4 => SampleTime::CYCLES4,
+ 5..=9 => SampleTime::CYCLES9,
+ 10..=16 => SampleTime::CYCLES16,
+ 17..=24 => SampleTime::CYCLES24,
+ 25..=48 => SampleTime::CYCLES48,
+ 49..=96 => SampleTime::CYCLES96,
+ 97..=192 => SampleTime::CYCLES192,
+ 193.. => SampleTime::CYCLES384,
}
}
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index b273c6394..0d0d40549 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -14,18 +14,13 @@
#[cfg_attr(adc_v4, path = "v4.rs")]
mod _version;
-#[cfg(not(any(adc_f1, adc_f3_v2)))]
-mod resolution;
-mod sample_time;
-
#[allow(unused)]
#[cfg(not(adc_f3_v2))]
pub use _version::*;
-#[cfg(not(any(adc_f1, adc_f3, adc_f3_v2)))]
-pub use resolution::Resolution;
-#[cfg(not(adc_f3_v2))]
-pub use sample_time::SampleTime;
+#[cfg(not(any(adc_f1, adc_f3_v2)))]
+pub use crate::pac::adc::vals::Res as Resolution;
+pub use crate::pac::adc::vals::SampleTime;
use crate::peripherals;
/// Analog to Digital driver.
@@ -137,3 +132,27 @@ macro_rules! impl_adc_pin {
}
};
}
+
+/// Get the maximum reading value for this resolution.
+///
+/// This is `2**n - 1`.
+#[cfg(not(any(adc_f1, adc_f3_v2)))]
+pub const fn resolution_to_max_count(res: Resolution) -> u32 {
+ match res {
+ #[cfg(adc_v4)]
+ Resolution::BITS16 => (1 << 16) - 1,
+ #[cfg(adc_v4)]
+ Resolution::BITS14 => (1 << 14) - 1,
+ #[cfg(adc_v4)]
+ Resolution::BITS14V => (1 << 14) - 1,
+ #[cfg(adc_v4)]
+ Resolution::BITS12V => (1 << 12) - 1,
+ Resolution::BITS12 => (1 << 12) - 1,
+ Resolution::BITS10 => (1 << 10) - 1,
+ Resolution::BITS8 => (1 << 8) - 1,
+ #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
+ Resolution::BITS6 => (1 << 6) - 1,
+ #[allow(unreachable_patterns)]
+ _ => core::unreachable!(),
+ }
+}
diff --git a/embassy-stm32/src/adc/resolution.rs b/embassy-stm32/src/adc/resolution.rs
deleted file mode 100644
index 37788cd77..000000000
--- a/embassy-stm32/src/adc/resolution.rs
+++ /dev/null
@@ -1,72 +0,0 @@
-/// ADC resolution
-#[allow(missing_docs)]
-#[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Resolution {
- TwelveBit,
- TenBit,
- EightBit,
- SixBit,
-}
-
-/// ADC resolution
-#[allow(missing_docs)]
-#[cfg(adc_v4)]
-#[derive(Clone, Copy, Debug, Eq, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Resolution {
- SixteenBit,
- FourteenBit,
- TwelveBit,
- TenBit,
- EightBit,
-}
-
-impl Default for Resolution {
- fn default() -> Self {
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
- {
- Self::TwelveBit
- }
- #[cfg(adc_v4)]
- {
- Self::SixteenBit
- }
- }
-}
-
-impl From<Resolution> for crate::pac::adc::vals::Res {
- fn from(res: Resolution) -> crate::pac::adc::vals::Res {
- match res {
- #[cfg(adc_v4)]
- Resolution::SixteenBit => crate::pac::adc::vals::Res::SIXTEENBIT,
- #[cfg(adc_v4)]
- Resolution::FourteenBit => crate::pac::adc::vals::Res::FOURTEENBITV,
- Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
- Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
- Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
- Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
- }
- }
-}
-
-impl Resolution {
- /// Get the maximum reading value for this resolution.
- ///
- /// This is `2**n - 1`.
- pub const fn to_max_count(&self) -> u32 {
- match self {
- #[cfg(adc_v4)]
- Resolution::SixteenBit => (1 << 16) - 1,
- #[cfg(adc_v4)]
- Resolution::FourteenBit => (1 << 14) - 1,
- Resolution::TwelveBit => (1 << 12) - 1,
- Resolution::TenBit => (1 << 10) - 1,
- Resolution::EightBit => (1 << 8) - 1,
- #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
- Resolution::SixBit => (1 << 6) - 1,
- }
- }
-}
diff --git a/embassy-stm32/src/adc/sample_time.rs b/embassy-stm32/src/adc/sample_time.rs
deleted file mode 100644
index 19bc22938..000000000
--- a/embassy-stm32/src/adc/sample_time.rs
+++ /dev/null
@@ -1,148 +0,0 @@
-#[cfg(not(adc_f3_v2))]
-macro_rules! impl_sample_time {
- ($default_doc:expr, $default:ident, ($(($doc:expr, $variant:ident, $pac_variant:ident)),*)) => {
- #[doc = concat!("ADC sample time\n\nThe default setting is ", $default_doc, " ADC clock cycles.")]
- #[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)]
- #[cfg_attr(feature = "defmt", derive(defmt::Format))]
- pub enum SampleTime {
- $(
- #[doc = concat!($doc, " ADC clock cycles.")]
- $variant,
- )*
- }
-
- impl From<SampleTime> for crate::pac::adc::vals::SampleTime {
- fn from(sample_time: SampleTime) -> crate::pac::adc::vals::SampleTime {
- match sample_time {
- $(SampleTime::$variant => crate::pac::adc::vals::SampleTime::$pac_variant),*
- }
- }
- }
-
- impl From<crate::pac::adc::vals::SampleTime> for SampleTime {
- fn from(sample_time: crate::pac::adc::vals::SampleTime) -> SampleTime {
- match sample_time {
- $(crate::pac::adc::vals::SampleTime::$pac_variant => SampleTime::$variant),*
- }
- }
- }
-
- impl Default for SampleTime {
- fn default() -> Self {
- Self::$default
- }
- }
- };
-}
-
-#[cfg(any(adc_f1, adc_v1))]
-impl_sample_time!(
- "1.5",
- Cycles1_5,
- (
- ("1.5", Cycles1_5, CYCLES1_5),
- ("7.5", Cycles7_5, CYCLES7_5),
- ("13.5", Cycles13_5, CYCLES13_5),
- ("28.5", Cycles28_5, CYCLES28_5),
- ("41.5", Cycles41_5, CYCLES41_5),
- ("55.5", Cycles55_5, CYCLES55_5),
- ("71.5", Cycles71_5, CYCLES71_5),
- ("239.5", Cycles239_5, CYCLES239_5)
- )
-);
-
-#[cfg(adc_v2)]
-impl_sample_time!(
- "3",
- Cycles3,
- (
- ("3", Cycles3, CYCLES3),
- ("15", Cycles15, CYCLES15),
- ("28", Cycles28, CYCLES28),
- ("56", Cycles56, CYCLES56),
- ("84", Cycles84, CYCLES84),
- ("112", Cycles112, CYCLES112),
- ("144", Cycles144, CYCLES144),
- ("480", Cycles480, CYCLES480)
- )
-);
-
-#[cfg(any(adc_v3, adc_h5))]
-impl_sample_time!(
- "2.5",
- Cycles2_5,
- (
- ("2.5", Cycles2_5, CYCLES2_5),
- ("6.5", Cycles6_5, CYCLES6_5),
- ("12.5", Cycles12_5, CYCLES12_5),
- ("24.5", Cycles24_5, CYCLES24_5),
- ("47.5", Cycles47_5, CYCLES47_5),
- ("92.5", Cycles92_5, CYCLES92_5),
- ("247.5", Cycles247_5, CYCLES247_5),
- ("640.5", Cycles640_5, CYCLES640_5)
- )
-);
-
-#[cfg(any(adc_l0, adc_g0))]
-impl_sample_time!(
- "1.5",
- Cycles1_5,
- (
- ("1.5", Cycles1_5, CYCLES1_5),
- ("3.5", Cycles3_5, CYCLES3_5),
- ("7.5", Cycles7_5, CYCLES7_5),
- ("12.5", Cycles12_5, CYCLES12_5),
- ("19.5", Cycles19_5, CYCLES19_5),
- ("39.5", Cycles39_5, CYCLES39_5),
- ("79.5", Cycles79_5, CYCLES79_5),
- ("160.5", Cycles160_5, CYCLES160_5)
- )
-);
-
-#[cfg(adc_v4)]
-impl_sample_time!(
- "1.5",
- Cycles1_5,
- (
- ("1.5", Cycles1_5, CYCLES1_5),
- ("2.5", Cycles2_5, CYCLES2_5),
- ("8.5", Cycles8_5, CYCLES8_5),
- ("16.5", Cycles16_5, CYCLES16_5),
- ("32.5", Cycles32_5, CYCLES32_5),
- ("64.5", Cycles64_5, CYCLES64_5),
- ("387.5", Cycles387_5, CYCLES387_5),
- ("810.5", Cycles810_5, CYCLES810_5)
- )
-);
-
-#[cfg(adc_f3)]
-impl_sample_time!(
- "1.5",
- Cycles1_5,
- (
- ("1.5", Cycles1_5, CYCLES1_5),
- ("2.5", Cycles2_5, CYCLES2_5),
- ("4.5", Cycles4_5, CYCLES4_5),
- ("7.5", Cycles7_5, CYCLES7_5),
- ("19.5", Cycles19_5, CYCLES19_5),
- ("61.5", Cycles61_5, CYCLES61_5),
- ("181.5", Cycles181_5, CYCLES181_5),
- ("601.5", Cycles601_5, CYCLES601_5)
- )
-);
-
-#[cfg(any(adc_f3_v1_1))]
-impl_sample_time!(
- "4",
- Cycles4,
- (
- ("4", Cycles4, CYCLES4),
- ("9", Cycles9, CYCLES9),
- ("16", Cycles16, CYCLES16),
- ("24", Cycles24, CYCLES24),
- ("48", Cycles48, CYCLES48),
- ("96", Cycles96, CYCLES96),
- ("192", Cycles192, CYCLES192),
- ("384", Cycles384, CYCLES384)
- )
-);
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 37115dfab..a8dc6ce98 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -109,7 +109,7 @@ impl<'d, T: Instance> Adc<'d, T> {
Self {
adc,
- sample_time: Default::default(),
+ sample_time: SampleTime::from_bits(0),
}
}
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index b37ac5a5d..f6f7dbfcc 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -111,7 +111,7 @@ where
Self {
adc,
- sample_time: Default::default(),
+ sample_time: SampleTime::from_bits(0),
}
}
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 0c44e4400..5f3512cad 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -102,7 +102,7 @@ impl<'d, T: Instance> Adc<'d, T> {
Self {
adc,
- sample_time: Default::default(),
+ sample_time: SampleTime::from_bits(0),
}
}
@@ -259,8 +259,8 @@ impl<'d, T: Instance> Adc<'d, T> {
} else {
let sample_time = sample_time.into();
T::regs()
- .smpr(ch as usize / 10)
- .modify(|reg| reg.set_smp(ch as usize % 10, sample_time));
+ .smpr(_ch as usize / 10)
+ .modify(|reg| reg.set_smp(_ch as usize % 10, sample_time));
}
}
}
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 048e73184..3fd047375 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -159,7 +159,7 @@ impl<'d, T: Instance> Adc<'d, T> {
}
let mut s = Self {
adc,
- sample_time: Default::default(),
+ sample_time: SampleTime::from_bits(0),
};
s.power_up(delay);
s.configure_differential_inputs();
diff --git a/examples/stm32f0/src/bin/adc.rs b/examples/stm32f0/src/bin/adc.rs
index 8fef062b3..c2fb143cd 100644
--- a/examples/stm32f0/src/bin/adc.rs
+++ b/examples/stm32f0/src/bin/adc.rs
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
info!("Hello World!");
let mut adc = Adc::new(p.ADC, Irqs, &mut Delay);
- adc.set_sample_time(SampleTime::Cycles71_5);
+ adc.set_sample_time(SampleTime::CYCLES71_5);
let mut pin = p.PA1;
let mut vrefint = adc.enable_vref(&mut Delay);
diff --git a/examples/stm32f334/src/bin/adc.rs b/examples/stm32f334/src/bin/adc.rs
index a9fb7f1a6..bd126ce68 100644
--- a/examples/stm32f334/src/bin/adc.rs
+++ b/examples/stm32f334/src/bin/adc.rs
@@ -40,7 +40,7 @@ async fn main(_spawner: Spawner) -> ! {
let mut adc = Adc::new(p.ADC1, Irqs, &mut Delay);
- adc.set_sample_time(SampleTime::Cycles601_5);
+ adc.set_sample_time(SampleTime::CYCLES601_5);
info!("enable vrefint...");
diff --git a/examples/stm32f334/src/bin/opamp.rs b/examples/stm32f334/src/bin/opamp.rs
index 6f25191be..a5c710aa2 100644
--- a/examples/stm32f334/src/bin/opamp.rs
+++ b/examples/stm32f334/src/bin/opamp.rs
@@ -42,7 +42,7 @@ async fn main(_spawner: Spawner) -> ! {
let mut adc = Adc::new(p.ADC2, Irqs, &mut Delay);
let mut opamp = OpAmp::new(p.OPAMP2);
- adc.set_sample_time(SampleTime::Cycles601_5);
+ adc.set_sample_time(SampleTime::CYCLES601_5);
info!("enable vrefint...");
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index 99e3ef63b..6c6de1ffe 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
info!("Hello World!");
let mut adc = Adc::new(p.ADC2, &mut Delay);
- adc.set_sample_time(SampleTime::Cycles32_5);
+ adc.set_sample_time(SampleTime::CYCLES32_5);
loop {
let measured = adc.read(&mut p.PA7);
diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs
index fe6fe69a1..f0278239f 100644
--- a/examples/stm32h7/src/bin/adc.rs
+++ b/examples/stm32h7/src/bin/adc.rs
@@ -46,7 +46,7 @@ async fn main(_spawner: Spawner) {
let mut adc = Adc::new(p.ADC3, &mut Delay);
- adc.set_sample_time(SampleTime::Cycles32_5);
+ adc.set_sample_time(SampleTime::CYCLES32_5);
let mut vrefint_channel = adc.enable_vrefint();
diff --git a/examples/stm32l0/src/bin/adc.rs b/examples/stm32l0/src/bin/adc.rs
index adeaa208a..97d41ca4b 100644
--- a/examples/stm32l0/src/bin/adc.rs
+++ b/examples/stm32l0/src/bin/adc.rs
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
info!("Hello World!");
let mut adc = Adc::new(p.ADC, Irqs, &mut Delay);
- adc.set_sample_time(SampleTime::Cycles79_5);
+ adc.set_sample_time(SampleTime::CYCLES79_5);
let mut pin = p.PA1;
let mut vrefint = adc.enable_vref(&mut Delay);
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index d01e9f1b3..910944673 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -20,7 +20,7 @@ fn main() -> ! {
let mut adc = Adc::new(p.ADC1, &mut Delay);
//adc.enable_vref();
- adc.set_resolution(Resolution::EightBit);
+ adc.set_resolution(Resolution::BITS8);
let mut channel = p.PC0;
loop {
From c83ab20526c0812d738853db015e201120ecce44 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 26 Feb 2024 03:00:04 +0100
Subject: [PATCH 330/392] stm32: update metapac.
---
embassy-stm32/src/fmc.rs | 8 +++--
embassy-stm32/src/i2s.rs | 16 +++++-----
embassy-stm32/src/lib.rs | 5 +++
embassy-stm32/src/rcc/f013.rs | 1 +
embassy-stm32/src/rcc/f247.rs | 1 +
embassy-stm32/src/rcc/g0.rs | 1 +
embassy-stm32/src/rcc/h.rs | 1 +
embassy-stm32/src/rcc/u5.rs | 2 ++
embassy-stm32/src/sai/mod.rs | 58 ++++++++++++++++++++---------------
embassy-stm32/src/spi/mod.rs | 30 +++++++++---------
10 files changed, 73 insertions(+), 50 deletions(-)
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index 873c8a70c..9d731a512 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -36,8 +36,10 @@ where
// fmc v1 and v2 does not have the fmcen bit
// fsmc v1, v2 and v3 does not have the fmcen bit
// This is a "not" because it is expected that all future versions have this bit
- #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1)))]
+ #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1, fmc_v4)))]
T::REGS.bcr1().modify(|r| r.set_fmcen(true));
+ #[cfg(any(fmc_v4))]
+ T::REGS.nor_psram().bcr1().modify(|r| r.set_fmcen(true));
}
/// Get the kernel clock currently in use for this FMC instance.
@@ -60,8 +62,10 @@ where
// fmc v1 and v2 does not have the fmcen bit
// fsmc v1, v2 and v3 does not have the fmcen bit
// This is a "not" because it is expected that all future versions have this bit
- #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1)))]
+ #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1, fmc_v4)))]
T::REGS.bcr1().modify(|r| r.set_fmcen(true));
+ #[cfg(any(fmc_v4))]
+ T::REGS.nor_psram().bcr1().modify(|r| r.set_fmcen(true));
}
fn source_clock_hz(&self) -> u32 {
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index e9065dce6..fa9ec0532 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -79,20 +79,20 @@ impl Format {
#[cfg(any(spi_v1, spi_f1))]
const fn datlen(&self) -> vals::Datlen {
match self {
- Format::Data16Channel16 => vals::Datlen::SIXTEENBIT,
- Format::Data16Channel32 => vals::Datlen::SIXTEENBIT,
- Format::Data24Channel32 => vals::Datlen::TWENTYFOURBIT,
- Format::Data32Channel32 => vals::Datlen::THIRTYTWOBIT,
+ Format::Data16Channel16 => vals::Datlen::BITS16,
+ Format::Data16Channel32 => vals::Datlen::BITS16,
+ Format::Data24Channel32 => vals::Datlen::BITS24,
+ Format::Data32Channel32 => vals::Datlen::BITS32,
}
}
#[cfg(any(spi_v1, spi_f1))]
const fn chlen(&self) -> vals::Chlen {
match self {
- Format::Data16Channel16 => vals::Chlen::SIXTEENBIT,
- Format::Data16Channel32 => vals::Chlen::THIRTYTWOBIT,
- Format::Data24Channel32 => vals::Chlen::THIRTYTWOBIT,
- Format::Data32Channel32 => vals::Chlen::THIRTYTWOBIT,
+ Format::Data16Channel16 => vals::Chlen::BITS16,
+ Format::Data16Channel32 => vals::Chlen::BITS32,
+ Format::Data24Channel32 => vals::Chlen::BITS32,
+ Format::Data32Channel32 => vals::Chlen::BITS32,
}
}
}
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index cd1ede0fa..15798e115 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -216,6 +216,11 @@ pub fn init(config: Config) -> Peripherals {
#[cfg(dbgmcu)]
crate::pac::DBGMCU.cr().modify(|cr| {
+ #[cfg(any(dbgmcu_h5))]
+ {
+ cr.set_stop(config.enable_debug_during_sleep);
+ cr.set_standby(config.enable_debug_during_sleep);
+ }
#[cfg(any(dbgmcu_f0, dbgmcu_c0, dbgmcu_g0, dbgmcu_u5, dbgmcu_wba, dbgmcu_l5))]
{
cr.set_dbg_stop(config.enable_debug_during_sleep);
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 56bb2a0d9..5046f0a3a 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -379,6 +379,7 @@ pub(crate) unsafe fn init(config: Config) {
pll1_p: pll,
#[cfg(stm32f3)]
pll1_p_mul_2: pll_mul_2,
+ hsi_div_244: hsi.map(|h| h / 244u32),
sys: Some(sys),
pclk1: Some(pclk1),
pclk2: Some(pclk2),
diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs
index e306d478d..343d075cd 100644
--- a/embassy-stm32/src/rcc/f247.rs
+++ b/embassy-stm32/src/rcc/f247.rs
@@ -288,6 +288,7 @@ pub(crate) unsafe fn init(config: Config) {
clk48: pll.q,
+ hsi_div488: hsi.map(|hsi| hsi/488u32),
hsi_hse: None,
afif: None,
);
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 0b1f34a20..ae502dd9c 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -365,5 +365,6 @@ pub(crate) unsafe fn init(config: Config) {
pll1_q: pll1_q_freq,
pll1_p: pll1_p_freq,
rtc: rtc,
+ hsi_div_488: None,
);
}
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index c2a71eaf1..c6da79afb 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -617,6 +617,7 @@ pub(crate) unsafe fn init(config: Config) {
hsi: hsi,
hsi48: hsi48,
csi: csi,
+ csi_div_122: csi.map(|c| c / 122u32),
hse: hse,
lse: None,
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 43138f05c..c8814ed69 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -290,6 +290,8 @@ pub(crate) unsafe fn init(config: Config) {
lsi: None,
msik: None,
iclk: None,
+ shsi: None,
+ shsi_div_2: None,
);
}
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index b6c3e4028..02f96f8a9 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -1,5 +1,6 @@
//! Serial Audio Interface (SAI)
#![macro_use]
+#![cfg_attr(gpdma, allow(unused))]
use core::marker::PhantomData;
@@ -7,6 +8,7 @@ use embassy_hal_internal::{into_ref, PeripheralRef};
use self::sealed::WhichSubBlock;
pub use crate::dma::word;
+#[cfg(not(gpdma))]
use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer};
use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::AnyPin;
@@ -26,6 +28,7 @@ pub enum Error {
Overrun,
}
+#[cfg(not(gpdma))]
impl From<ringbuffer::OverrunError> for Error {
fn from(_: ringbuffer::OverrunError) -> Self {
Self::Overrun
@@ -41,7 +44,7 @@ pub enum Mode {
}
impl Mode {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
match tx_rx {
TxRx::Transmitter => match self {
@@ -76,7 +79,7 @@ pub enum SlotSize {
}
impl SlotSize {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn slotsz(&self) -> vals::Slotsz {
match self {
SlotSize::DataSize => vals::Slotsz::DATASIZE,
@@ -99,7 +102,7 @@ pub enum DataSize {
}
impl DataSize {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn ds(&self) -> vals::Ds {
match self {
DataSize::Data8 => vals::Ds::BIT8,
@@ -124,7 +127,7 @@ pub enum FifoThreshold {
}
impl FifoThreshold {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn fth(&self) -> vals::Fth {
match self {
FifoThreshold::Empty => vals::Fth::EMPTY,
@@ -145,7 +148,7 @@ pub enum MuteValue {
}
impl MuteValue {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn muteval(&self) -> vals::Muteval {
match self {
MuteValue::Zero => vals::Muteval::SENDZERO,
@@ -164,7 +167,7 @@ pub enum Protocol {
}
impl Protocol {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn prtcfg(&self) -> vals::Prtcfg {
match self {
Protocol::Free => vals::Prtcfg::FREE,
@@ -183,7 +186,7 @@ pub enum SyncInput {
/// Syncs with the other A/B sub-block within the SAI unit
Internal,
/// Syncs with a sub-block in the other SAI unit
- #[cfg(sai_v4)]
+ #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
External(SyncInputInstance),
}
@@ -192,14 +195,14 @@ impl SyncInput {
match self {
SyncInput::None => vals::Syncen::ASYNCHRONOUS,
SyncInput::Internal => vals::Syncen::INTERNAL,
- #[cfg(any(sai_v4))]
+ #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
SyncInput::External(_) => vals::Syncen::EXTERNAL,
}
}
}
/// SAI instance to sync from.
-#[cfg(sai_v4)]
+#[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
#[derive(Copy, Clone, PartialEq)]
#[allow(missing_docs)]
pub enum SyncInputInstance {
@@ -222,7 +225,7 @@ pub enum StereoMono {
}
impl StereoMono {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn mono(&self) -> vals::Mono {
match self {
StereoMono::Stereo => vals::Mono::STEREO,
@@ -241,7 +244,7 @@ pub enum BitOrder {
}
impl BitOrder {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn lsbfirst(&self) -> vals::Lsbfirst {
match self {
BitOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
@@ -260,7 +263,7 @@ pub enum FrameSyncOffset {
}
impl FrameSyncOffset {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn fsoff(&self) -> vals::Fsoff {
match self {
FrameSyncOffset::OnFirstBit => vals::Fsoff::ONFIRST,
@@ -279,7 +282,7 @@ pub enum FrameSyncPolarity {
}
impl FrameSyncPolarity {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn fspol(&self) -> vals::Fspol {
match self {
FrameSyncPolarity::ActiveLow => vals::Fspol::FALLINGEDGE,
@@ -297,7 +300,7 @@ pub enum FrameSyncDefinition {
}
impl FrameSyncDefinition {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn fsdef(&self) -> bool {
match self {
FrameSyncDefinition::StartOfFrame => false,
@@ -315,7 +318,7 @@ pub enum ClockStrobe {
}
impl ClockStrobe {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn ckstr(&self) -> vals::Ckstr {
match self {
ClockStrobe::Falling => vals::Ckstr::FALLINGEDGE,
@@ -333,7 +336,7 @@ pub enum ComplementFormat {
}
impl ComplementFormat {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn cpl(&self) -> vals::Cpl {
match self {
ComplementFormat::OnesComplement => vals::Cpl::ONESCOMPLEMENT,
@@ -352,7 +355,7 @@ pub enum Companding {
}
impl Companding {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn comp(&self) -> vals::Comp {
match self {
Companding::None => vals::Comp::NOCOMPANDING,
@@ -371,7 +374,7 @@ pub enum OutputDrive {
}
impl OutputDrive {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn outdriv(&self) -> vals::Outdriv {
match self {
OutputDrive::OnStart => vals::Outdriv::ONSTART,
@@ -404,7 +407,7 @@ pub enum MasterClockDivider {
}
impl MasterClockDivider {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn mckdiv(&self) -> u8 {
match self {
MasterClockDivider::MasterClockDisabled => 0,
@@ -501,12 +504,12 @@ impl Config {
}
}
+#[cfg(not(gpdma))]
enum RingBuffer<'d, W: word::Word> {
Writable(WritableRingBuffer<'d, W>),
Readable(ReadableRingBuffer<'d, W>),
}
-#[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
fn dr<W: word::Word>(w: crate::pac::sai::Sai, sub_block: WhichSubBlock) -> *mut W {
let ch = w.ch(sub_block as usize);
ch.dr().as_ptr() as _
@@ -528,6 +531,7 @@ fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AFType, AFType) {
)
}
+#[cfg(not(gpdma))]
fn get_ring_buffer<'d, T: Instance, W: word::Word>(
dma: impl Peripheral<P = impl Channel> + 'd,
dma_buf: &'d mut [W],
@@ -554,12 +558,12 @@ fn update_synchronous_config(config: &mut Config) {
config.mode = Mode::Slave;
config.sync_output = false;
- #[cfg(any(sai_v1, sai_v2, sai_v3))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm))]
{
config.sync_input = SyncInput::Internal;
}
- #[cfg(any(sai_v4))]
+ #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
{
//this must either be Internal or External
//The asynchronous sub-block on the same SAI needs to enable sync_output
@@ -599,10 +603,14 @@ pub struct Sai<'d, T: Instance, W: word::Word> {
fs: Option<PeripheralRef<'d, AnyPin>>,
sck: Option<PeripheralRef<'d, AnyPin>>,
mclk: Option<PeripheralRef<'d, AnyPin>>,
+ #[cfg(gpdma)]
+ ring_buffer: PhantomData<W>,
+ #[cfg(not(gpdma))]
ring_buffer: RingBuffer<'d, W>,
sub_block: WhichSubBlock,
}
+#[cfg(not(gpdma))]
impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
/// Create a new SAI driver in asynchronous mode with MCLK.
///
@@ -715,13 +723,13 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
ring_buffer: RingBuffer<'d, W>,
config: Config,
) -> Self {
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
{
let ch = T::REGS.ch(sub_block as usize);
ch.cr1().modify(|w| w.set_saien(false));
}
- #[cfg(any(sai_v4))]
+ #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
{
if let SyncInput::External(i) = config.sync_input {
T::REGS.gcr().modify(|w| {
@@ -740,7 +748,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
}
}
- #[cfg(any(sai_v1, sai_v2, sai_v3, sai_v4))]
+ #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
{
let ch = T::REGS.ch(sub_block as usize);
ch.cr1().modify(|w| {
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 23f027e70..172bc8112 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -1005,8 +1005,8 @@ mod word_impl {
pub type Config = vals::Dff;
- impl_word!(u8, vals::Dff::EIGHTBIT);
- impl_word!(u16, vals::Dff::SIXTEENBIT);
+ impl_word!(u8, vals::Dff::BITS8);
+ impl_word!(u16, vals::Dff::BITS16);
}
#[cfg(spi_v2)]
@@ -1015,19 +1015,19 @@ mod word_impl {
pub type Config = (vals::Ds, vals::Frxth);
- impl_word!(word::U4, (vals::Ds::FOURBIT, vals::Frxth::QUARTER));
- impl_word!(word::U5, (vals::Ds::FIVEBIT, vals::Frxth::QUARTER));
- impl_word!(word::U6, (vals::Ds::SIXBIT, vals::Frxth::QUARTER));
- impl_word!(word::U7, (vals::Ds::SEVENBIT, vals::Frxth::QUARTER));
- impl_word!(u8, (vals::Ds::EIGHTBIT, vals::Frxth::QUARTER));
- impl_word!(word::U9, (vals::Ds::NINEBIT, vals::Frxth::HALF));
- impl_word!(word::U10, (vals::Ds::TENBIT, vals::Frxth::HALF));
- impl_word!(word::U11, (vals::Ds::ELEVENBIT, vals::Frxth::HALF));
- impl_word!(word::U12, (vals::Ds::TWELVEBIT, vals::Frxth::HALF));
- impl_word!(word::U13, (vals::Ds::THIRTEENBIT, vals::Frxth::HALF));
- impl_word!(word::U14, (vals::Ds::FOURTEENBIT, vals::Frxth::HALF));
- impl_word!(word::U15, (vals::Ds::FIFTEENBIT, vals::Frxth::HALF));
- impl_word!(u16, (vals::Ds::SIXTEENBIT, vals::Frxth::HALF));
+ impl_word!(word::U4, (vals::Ds::BITS4, vals::Frxth::QUARTER));
+ impl_word!(word::U5, (vals::Ds::BITS5, vals::Frxth::QUARTER));
+ impl_word!(word::U6, (vals::Ds::BITS6, vals::Frxth::QUARTER));
+ impl_word!(word::U7, (vals::Ds::BITS7, vals::Frxth::QUARTER));
+ impl_word!(u8, (vals::Ds::BITS8, vals::Frxth::QUARTER));
+ impl_word!(word::U9, (vals::Ds::BITS9, vals::Frxth::HALF));
+ impl_word!(word::U10, (vals::Ds::BITS10, vals::Frxth::HALF));
+ impl_word!(word::U11, (vals::Ds::BITS11, vals::Frxth::HALF));
+ impl_word!(word::U12, (vals::Ds::BITS12, vals::Frxth::HALF));
+ impl_word!(word::U13, (vals::Ds::BITS13, vals::Frxth::HALF));
+ impl_word!(word::U14, (vals::Ds::BITS14, vals::Frxth::HALF));
+ impl_word!(word::U15, (vals::Ds::BITS15, vals::Frxth::HALF));
+ impl_word!(u16, (vals::Ds::BITS16, vals::Frxth::HALF));
}
#[cfg(any(spi_v3, spi_v4, spi_v5))]
From 766372e06a413352dc07b864dd76e85e03782790 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 25 Feb 2024 21:16:43 -0500
Subject: [PATCH 331/392] rustfmt
---
tests/stm32/src/bin/cryp.rs | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/tests/stm32/src/bin/cryp.rs b/tests/stm32/src/bin/cryp.rs
index 59c85f258..f105abf26 100644
--- a/tests/stm32/src/bin/cryp.rs
+++ b/tests/stm32/src/bin/cryp.rs
@@ -59,9 +59,7 @@ async fn main(_spawner: Spawner) {
let _ = cipher.encrypt_in_place(&iv.into(), &aad, &mut payload_vec);
defmt::assert!(ciphertext == payload_vec[0..ciphertext.len()]);
- defmt::assert!(
- encrypt_tag == payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]
- );
+ defmt::assert!(encrypt_tag == payload_vec[ciphertext.len()..ciphertext.len() + encrypt_tag.len()]);
// Decrypt in software using AES-GCM 128-bit
let _ = cipher.decrypt_in_place(&iv.into(), &aad, &mut payload_vec);
From 54f502e5e6a355e0f132f33f3eecd2a0abe298bc Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Sun, 25 Feb 2024 21:31:25 -0500
Subject: [PATCH 332/392] Run gen_test.py
---
tests/stm32/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 37519ba11..bfe003a11 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -93,7 +93,7 @@ required-features = [ "can",]
[[bin]]
name = "cryp"
path = "src/bin/cryp.rs"
-required-features = [ "hash",]
+required-features = [ "cryp",]
[[bin]]
name = "dac"
From a0afd378f4f3bb0032a1f845c2883334b433dd79 Mon Sep 17 00:00:00 2001
From: Haobo Gu <haobogu@outlook.com>
Date: Mon, 26 Feb 2024 17:28:29 +0800
Subject: [PATCH 333/392] update usbd-hid to latest
Signed-off-by: Haobo Gu <haobogu@outlook.com>
---
embassy-usb/Cargo.toml | 2 +-
examples/nrf52840/Cargo.toml | 2 +-
examples/nrf5340/Cargo.toml | 2 +-
examples/rp/Cargo.toml | 2 +-
examples/stm32g4/Cargo.toml | 2 +-
examples/stm32l5/Cargo.toml | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/embassy-usb/Cargo.toml b/embassy-usb/Cargo.toml
index 1b31b6145..fe5e36b32 100644
--- a/embassy-usb/Cargo.toml
+++ b/embassy-usb/Cargo.toml
@@ -56,5 +56,5 @@ log = { version = "0.4.14", optional = true }
heapless = "0.8"
# for HID
-usbd-hid = { version = "0.6.0", optional = true }
+usbd-hid = { version = "0.7.0", optional = true }
ssmarshal = { version = "1.0", default-features = false, optional = true }
diff --git a/examples/nrf52840/Cargo.toml b/examples/nrf52840/Cargo.toml
index abb995be6..4ab5c7b7c 100644
--- a/examples/nrf52840/Cargo.toml
+++ b/examples/nrf52840/Cargo.toml
@@ -28,7 +28,7 @@ panic-probe = { version = "0.3", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
rand = { version = "0.8.4", default-features = false }
embedded-storage = "0.3.1"
-usbd-hid = "0.6.0"
+usbd-hid = "0.7.0"
serde = { version = "1.0.136", default-features = false }
embedded-hal = { version = "1.0" }
embedded-hal-async = { version = "1.0" }
diff --git a/examples/nrf5340/Cargo.toml b/examples/nrf5340/Cargo.toml
index 56b9c8018..24aa560d5 100644
--- a/examples/nrf5340/Cargo.toml
+++ b/examples/nrf5340/Cargo.toml
@@ -24,7 +24,7 @@ panic-probe = { version = "0.3", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
rand = { version = "0.8.4", default-features = false }
embedded-storage = "0.3.1"
-usbd-hid = "0.6.0"
+usbd-hid = "0.7.0"
serde = { version = "1.0.136", default-features = false }
[profile.release]
diff --git a/examples/rp/Cargo.toml b/examples/rp/Cargo.toml
index e1092dba4..585349506 100644
--- a/examples/rp/Cargo.toml
+++ b/examples/rp/Cargo.toml
@@ -36,7 +36,7 @@ display-interface = "0.4.1"
byte-slice-cast = { version = "1.2.0", default-features = false }
smart-leds = "0.3.0"
heapless = "0.8"
-usbd-hid = "0.6.1"
+usbd-hid = "0.7.0"
embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
embedded-hal-async = "1.0"
diff --git a/examples/stm32g4/Cargo.toml b/examples/stm32g4/Cargo.toml
index 74ccfa3b0..64c749b9b 100644
--- a/examples/stm32g4/Cargo.toml
+++ b/examples/stm32g4/Cargo.toml
@@ -12,7 +12,7 @@ embassy-executor = { version = "0.5.0", path = "../../embassy-executor", feature
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
-usbd-hid = "0.6.0"
+usbd-hid = "0.7.0"
defmt = "0.3"
defmt-rtt = "0.4"
diff --git a/examples/stm32l5/Cargo.toml b/examples/stm32l5/Cargo.toml
index 0c6beb72c..5bcee178f 100644
--- a/examples/stm32l5/Cargo.toml
+++ b/examples/stm32l5/Cargo.toml
@@ -13,7 +13,7 @@ embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["de
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
embassy-net = { version = "0.4.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"] }
embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
-usbd-hid = "0.6.0"
+usbd-hid = "0.7.0"
defmt = "0.3"
defmt-rtt = "0.4"
From 5c45723777dbd7d9d23188f5b5a2adc417e29292 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Fri, 23 Feb 2024 14:33:25 +0000
Subject: [PATCH 334/392] stm32: timers: use TIMx_CC interrupt source for
advanced timers
fixes (hopefully) time driver when using TIM1/8/20
---
embassy-stm32/src/time_driver.rs | 34 ++++++++++++++++++++++++++++++++
embassy-stm32/src/timer/mod.rs | 19 ++++++++++++++----
2 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 8e4e606a4..37b2e7526 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -16,6 +16,8 @@ use crate::pac::timer::vals;
use crate::rcc::sealed::RccPeripheral;
#[cfg(feature = "low-power")]
use crate::rtc::Rtc;
+#[cfg(any(time_driver_tim1, time_driver_tim8, time_driver_tim20))]
+use crate::timer::sealed::AdvancedControlInstance;
use crate::timer::sealed::{CoreInstance, GeneralPurpose16bitInstance as Instance};
use crate::{interrupt, peripherals};
@@ -76,6 +78,14 @@ foreach_interrupt! {
DRIVER.on_interrupt()
}
};
+ (TIM1, timer, $block:ident, CC, $irq:ident) => {
+ #[cfg(time_driver_tim1)]
+ #[cfg(feature = "rt")]
+ #[interrupt]
+ fn $irq() {
+ DRIVER.on_interrupt()
+ }
+ };
(TIM2, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim2)]
#[cfg(feature = "rt")]
@@ -116,6 +126,14 @@ foreach_interrupt! {
DRIVER.on_interrupt()
}
};
+ (TIM8, timer, $block:ident, CC, $irq:ident) => {
+ #[cfg(time_driver_tim8)]
+ #[cfg(feature = "rt")]
+ #[interrupt]
+ fn $irq() {
+ DRIVER.on_interrupt()
+ }
+ };
(TIM9, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim9)]
#[cfg(feature = "rt")]
@@ -148,6 +166,14 @@ foreach_interrupt! {
DRIVER.on_interrupt()
}
};
+ (TIM20, timer, $block:ident, CC, $irq:ident) => {
+ #[cfg(time_driver_tim20)]
+ #[cfg(feature = "rt")]
+ #[interrupt]
+ fn $irq() {
+ DRIVER.on_interrupt()
+ }
+ };
(TIM21, timer, $block:ident, UP, $irq:ident) => {
#[cfg(time_driver_tim21)]
#[cfg(feature = "rt")]
@@ -281,6 +307,14 @@ impl RtcDriver {
<T as CoreInstance>::Interrupt::unpend();
unsafe { <T as CoreInstance>::Interrupt::enable() };
+ #[cfg(any(time_driver_tim1, time_driver_tim8, time_driver_tim20))]
+ {
+ <T as AdvancedControlInstance>::CaptureCompareInterrupt::unpend();
+ unsafe {
+ <T as AdvancedControlInstance>::CaptureCompareInterrupt::enable();
+ }
+ }
+
r.cr1().modify(|w| w.set_cen(true));
}
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 9397da2a1..c8f580101 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -464,6 +464,9 @@ pub(crate) mod sealed {
pub trait AdvancedControlInstance:
GeneralPurpose2ChannelComplementaryInstance + GeneralPurpose16bitInstance
{
+ /// Capture compare interrupt for this timer.
+ type CaptureCompareInterrupt: interrupt::typelevel::Interrupt;
+
/// Get access to the advanced timer registers.
fn regs_advanced() -> crate::pac::timer::TimAdv;
@@ -831,8 +834,10 @@ macro_rules! impl_2ch_cmp_timer {
#[allow(unused)]
macro_rules! impl_adv_timer {
- ($inst:ident) => {
+ ($inst:ident, $irq:ident) => {
impl sealed::AdvancedControlInstance for crate::peripherals::$inst {
+ type CaptureCompareInterrupt = crate::interrupt::typelevel::$irq;
+
fn regs_advanced() -> crate::pac::timer::TimAdv {
unsafe { crate::pac::timer::TimAdv::from_ptr(crate::pac::$inst.as_ptr()) }
}
@@ -905,11 +910,13 @@ foreach_interrupt! {
impl_gp16_timer!($inst);
impl_1ch_cmp_timer!($inst);
impl_2ch_cmp_timer!($inst);
- impl_adv_timer!($inst);
impl BasicInstance for crate::peripherals::$inst {}
impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
+ ($inst:ident, timer, TIM_1CH_CMP, CC, $irq:ident) => {
+ impl_adv_timer!($inst, $irq);
+ };
($inst:ident, timer, TIM_2CH_CMP, UP, $irq:ident) => {
@@ -921,11 +928,13 @@ foreach_interrupt! {
impl_gp16_timer!($inst);
impl_1ch_cmp_timer!($inst);
impl_2ch_cmp_timer!($inst);
- impl_adv_timer!($inst);
impl BasicInstance for crate::peripherals::$inst {}
impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
+ ($inst:ident, timer, TIM_2CH_CMP, CC, $irq:ident) => {
+ impl_adv_timer!($inst, $irq);
+ };
($inst:ident, timer, TIM_ADV, UP, $irq:ident) => {
@@ -937,11 +946,13 @@ foreach_interrupt! {
impl_gp16_timer!($inst);
impl_1ch_cmp_timer!($inst);
impl_2ch_cmp_timer!($inst);
- impl_adv_timer!($inst);
impl BasicInstance for crate::peripherals::$inst {}
impl CaptureCompare16bitInstance for crate::peripherals::$inst {}
impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {}
};
+ ($inst:ident, timer, TIM_ADV, CC, $irq:ident) => {
+ impl_adv_timer!($inst, $irq);
+ };
}
// Update Event trigger DMA for every timer
From bf44adc4bcd4725f19ec99428acd70700b48e8cd Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Tue, 27 Feb 2024 14:20:58 +0800
Subject: [PATCH 335/392] allow higher psc value for iwdg_v3
---
embassy-stm32/src/wdg/mod.rs | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/embassy-stm32/src/wdg/mod.rs b/embassy-stm32/src/wdg/mod.rs
index dc701ef64..2ff0db09e 100644
--- a/embassy-stm32/src/wdg/mod.rs
+++ b/embassy-stm32/src/wdg/mod.rs
@@ -42,9 +42,13 @@ impl<'d, T: Instance> IndependentWatchdog<'d, T> {
// Prescaler value
let psc = 2u16.pow(psc_power);
+ #[cfg(not(iwdg_v3))]
+ assert!(psc <= 256, "IWDG prescaler should be no more than 256");
+ #[cfg(iwdg_v3)] // H5, U5, WBA
+ assert!(psc <= 1024, "IWDG prescaler should be no more than 1024");
+
// Convert prescaler power to PR register value
let pr = psc_power as u8 - 2;
- assert!(pr <= 0b110);
// Reload value
let rl = reload_value(psc, timeout_us);
From 0bcbca9e5bc506c846368d32db049c7cbb248997 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Tue, 27 Feb 2024 10:32:52 +0200
Subject: [PATCH 336/392] nrf: spim: Hide the "Copying SPIM tx buffer into RAM
for DMA" traces
Now that SPIM driver seems to be properly working, hide the trace logs
which occur whenever tx buffer needs to be copied into RAM.
---
embassy-nrf/src/spim.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-nrf/src/spim.rs b/embassy-nrf/src/spim.rs
index 3538afa2b..c45d45e68 100644
--- a/embassy-nrf/src/spim.rs
+++ b/embassy-nrf/src/spim.rs
@@ -312,7 +312,7 @@ impl<'d, T: Instance> Spim<'d, T> {
match self.blocking_inner_from_ram(rx, tx) {
Ok(_) => Ok(()),
Err(Error::BufferNotInRAM) => {
- trace!("Copying SPIM tx buffer into RAM for DMA");
+ // trace!("Copying SPIM tx buffer into RAM for DMA");
let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
tx_ram_buf.copy_from_slice(tx);
self.blocking_inner_from_ram(rx, tx_ram_buf)
@@ -366,7 +366,7 @@ impl<'d, T: Instance> Spim<'d, T> {
match self.async_inner_from_ram(rx, tx).await {
Ok(_) => Ok(()),
Err(Error::BufferNotInRAM) => {
- trace!("Copying SPIM tx buffer into RAM for DMA");
+ // trace!("Copying SPIM tx buffer into RAM for DMA");
let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
tx_ram_buf.copy_from_slice(tx);
self.async_inner_from_ram(rx, tx_ram_buf).await
From 137855418aa0a3596b7469d6c8ad8ffbf4e76584 Mon Sep 17 00:00:00 2001
From: Priit Laes <plaes@plaes.org>
Date: Tue, 27 Feb 2024 10:35:39 +0200
Subject: [PATCH 337/392] nrf: Bump embedded-storage-async to 0.4.1
---
embassy-nrf/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-nrf/Cargo.toml b/embassy-nrf/Cargo.toml
index 7e161df9b..0045d9f97 100644
--- a/embassy-nrf/Cargo.toml
+++ b/embassy-nrf/Cargo.toml
@@ -146,7 +146,7 @@ critical-section = "1.1"
rand_core = "0.6.3"
fixed = "1.10.0"
embedded-storage = "0.3.1"
-embedded-storage-async = "0.4.0"
+embedded-storage-async = "0.4.1"
cfg-if = "1.0.0"
document-features = "0.2.7"
From e63b0d7a2f89e3b210569ce77f45e9cb14ac6ae8 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Tue, 27 Feb 2024 10:38:07 +0000
Subject: [PATCH 338/392] stm32: can: fd: fix SID read/write from buf elems
---
embassy-stm32/src/can/fd/peripheral.rs | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 0771d6fbb..8e4ecf4a5 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -721,13 +721,15 @@ fn make_id(id: u32, extended: bool) -> embedded_can::Id {
if extended {
embedded_can::Id::from(unsafe { embedded_can::ExtendedId::new_unchecked(id & 0x1FFFFFFF) })
} else {
- embedded_can::Id::from(unsafe { embedded_can::StandardId::new_unchecked((id & 0x000007FF) as u16) })
+ // A standard identifier is stored into ID[28:18].
+ embedded_can::Id::from(unsafe { embedded_can::StandardId::new_unchecked(((id >> 18) & 0x000007FF) as u16) })
}
}
fn put_tx_header(mailbox: &mut TxBufferElement, header: &Header) {
let (id, id_type) = match header.id() {
- embedded_can::Id::Standard(id) => (id.as_raw() as u32, IdType::StandardId),
+ // A standard identifier has to be written to ID[28:18].
+ embedded_can::Id::Standard(id) => ((id.as_raw() as u32) << 18, IdType::StandardId),
embedded_can::Id::Extended(id) => (id.as_raw() as u32, IdType::ExtendedId),
};
From 9a4f58fe158551bd0c38d23a71f6b719d4ce5130 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Tue, 27 Feb 2024 10:38:40 +0000
Subject: [PATCH 339/392] stm32: can: fd: only TX with BRS if also TXing with
FDF
---
embassy-stm32/src/can/fd/peripheral.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 8e4ecf4a5..9c29e4887 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -739,7 +739,7 @@ fn put_tx_header(mailbox: &mut TxBufferElement, header: &Header) {
} else {
FrameFormat::Classic
};
- let brs = header.len() > 8 || header.bit_rate_switching();
+ let brs = (frame_format == FrameFormat::Fdcan) && header.bit_rate_switching();
mailbox.header.write(|w| {
unsafe { w.id().bits(id) }
From b7e0964a078d1760263df586953fbd1d29aabe2b Mon Sep 17 00:00:00 2001
From: Maia <mherrington@stokespace.com>
Date: Tue, 27 Feb 2024 11:07:05 -0800
Subject: [PATCH 340/392] added FDCANSEL logic for H7
---
embassy-stm32/src/rcc/h.rs | 3 +++
1 file changed, 3 insertions(+)
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index c6da79afb..7b2255cc6 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -557,6 +557,9 @@ pub(crate) unsafe fn init(config: Config) {
RCC.d3ccipr().modify(|w| {
w.set_adcsel(config.adc_clock_source);
});
+ RCC.d2ccip1r().modify(|w| {
+ w.set_fdcansel(config.fdcan_clock_source);
+ });
}
#[cfg(stm32h5)]
{
From 0ed402fd79a6dfbe4f3b2187a97d160ce7c3140b Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Tue, 27 Feb 2024 23:42:50 +0000
Subject: [PATCH 341/392] stm32: can: fd: refactor out some duplicate code
---
embassy-stm32/src/can/fd/peripheral.rs | 122 +++----------------------
embassy-stm32/src/can/fdcan.rs | 66 ++++++-------
embassy-stm32/src/can/frame.rs | 30 ++++++
3 files changed, 68 insertions(+), 150 deletions(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 9c29e4887..7d26a5fe0 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -37,7 +37,7 @@ impl Registers {
&mut self.msg_ram_mut().receive[fifonr].fxsa[bufnum]
}
- pub fn read_classic(&self, fifonr: usize) -> Option<(ClassicFrame, u16)> {
+ pub fn read<F: CanHeader>(&self, fifonr: usize) -> Option<(F, u16)> {
// Fill level - do we have a msg?
if self.regs.rxfs(fifonr).read().ffl() < 1 {
return None;
@@ -54,32 +54,8 @@ impl Registers {
match maybe_header {
Some((header, ts)) => {
- let data = ClassicData::new(&buffer[0..header.len() as usize]);
- Some((ClassicFrame::new(header, data.unwrap()), ts))
- }
- None => None,
- }
- }
-
- pub fn read_fd(&self, fifonr: usize) -> Option<(FdFrame, u16)> {
- // Fill level - do we have a msg?
- if self.regs.rxfs(fifonr).read().ffl() < 1 {
- return None;
- }
-
- let read_idx = self.regs.rxfs(fifonr).read().fgi();
- let mailbox = self.rx_fifo_element(fifonr, read_idx as usize);
-
- let mut buffer: [u8; 64] = [0; 64];
- let maybe_header = extract_frame(mailbox, &mut buffer);
-
- // Clear FIFO, reduces count and increments read buf
- self.regs.rxfa(fifonr).modify(|w| w.set_fai(read_idx));
-
- match maybe_header {
- Some((header, ts)) => {
- let data = FdData::new(&buffer[0..header.len() as usize]);
- Some((FdFrame::new(header, data.unwrap()), ts))
+ let data = &buffer[0..header.len() as usize];
+ Some((F::from_header(header, data)?, ts))
}
None => None,
}
@@ -194,10 +170,9 @@ impl Registers {
#[inline]
//fn abort_pending_mailbox<PTX, R>(&mut self, idx: Mailbox, pending: PTX) -> Option<R>
- pub fn abort_pending_mailbox(&self, bufidx: usize) -> Option<ClassicFrame>
//where
// PTX: FnOnce(Mailbox, TxFrameHeader, &[u32]) -> R,
- {
+ pub fn abort_pending_mailbox_generic<F: embedded_can::Frame>(&self, bufidx: usize) -> Option<F> {
if self.abort(bufidx) {
let mailbox = self.tx_buffer_element(bufidx);
@@ -216,50 +191,11 @@ impl Registers {
let mut data = [0u8; 64];
data_from_tx_buffer(&mut data, mailbox, len as usize);
- let cd = ClassicData::new(&data).unwrap();
- Some(ClassicFrame::new(Header::new(id, len, header_reg.rtr().bit()), cd))
- } else {
- // Abort request failed because the frame was already sent (or being sent) on
- // the bus. All mailboxes are now free. This can happen for small prescaler
- // values (e.g. 1MBit/s bit timing with a source clock of 8MHz) or when an ISR
- // has preempted the execution.
- None
- }
- }
-
- #[inline]
- //fn abort_pending_mailbox<PTX, R>(&mut self, idx: Mailbox, pending: PTX) -> Option<R>
- pub fn abort_pending_fd_mailbox(&self, bufidx: usize) -> Option<FdFrame>
-//where
- // PTX: FnOnce(Mailbox, TxFrameHeader, &[u32]) -> R,
- {
- if self.abort(bufidx) {
- let mailbox = self.tx_buffer_element(bufidx);
-
- let header_reg = mailbox.header.read();
- let id = make_id(header_reg.id().bits(), header_reg.xtd().bits());
-
- let len = match header_reg.to_data_length() {
- DataLength::Fdcan(len) => len,
- DataLength::Classic(len) => len,
- };
- if len as usize > FdFrame::MAX_DATA_LEN {
- return None;
- }
-
- //let tx_ram = self.tx_msg_ram();
- let mut data = [0u8; 64];
- data_from_tx_buffer(&mut data, mailbox, len as usize);
-
- let cd = FdData::new(&data).unwrap();
-
- let header = if header_reg.fdf().frame_format() == FrameFormat::Fdcan {
- Header::new_fd(id, len, header_reg.rtr().bit(), header_reg.brs().bit())
+ if header_reg.rtr().bit() {
+ F::new_remote(id, len as usize)
} else {
- Header::new(id, len, header_reg.rtr().bit())
- };
-
- Some(FdFrame::new(header, cd))
+ F::new(id, &data)
+ }
} else {
// Abort request failed because the frame was already sent (or being sent) on
// the bus. All mailboxes are now free. This can happen for small prescaler
@@ -272,7 +208,7 @@ impl Registers {
/// As Transmit, but if there is a pending frame, `pending` will be called so that the frame can
/// be preserved.
//pub fn transmit_preserve<PTX, P>(
- pub fn write_classic(&self, frame: &ClassicFrame) -> nb::Result<Option<ClassicFrame>, Infallible> {
+ pub fn write<F: embedded_can::Frame + CanHeader>(&self, frame: &F) -> nb::Result<Option<F>, Infallible> {
let queue_is_full = self.tx_queue_is_full();
let id = frame.header().id();
@@ -281,45 +217,11 @@ impl Registers {
// Discard the first slot with a lower priority message
let (idx, pending_frame) = if queue_is_full {
if self.is_available(0, id) {
- (0, self.abort_pending_mailbox(0))
+ (0, self.abort_pending_mailbox_generic(0))
} else if self.is_available(1, id) {
- (1, self.abort_pending_mailbox(1))
+ (1, self.abort_pending_mailbox_generic(1))
} else if self.is_available(2, id) {
- (2, self.abort_pending_mailbox(2))
- } else {
- // For now we bail when there is no lower priority slot available
- // Can this lead to priority inversion?
- return Err(nb::Error::WouldBlock);
- }
- } else {
- // Read the Write Pointer
- let idx = self.regs.txfqs().read().tfqpi();
-
- (idx, None)
- };
-
- self.put_tx_frame(idx as usize, frame.header(), frame.data());
-
- Ok(pending_frame)
- }
-
- /// As Transmit, but if there is a pending frame, `pending` will be called so that the frame can
- /// be preserved.
- //pub fn transmit_preserve<PTX, P>(
- pub fn write_fd(&self, frame: &FdFrame) -> nb::Result<Option<FdFrame>, Infallible> {
- let queue_is_full = self.tx_queue_is_full();
-
- let id = frame.header().id();
-
- // If the queue is full,
- // Discard the first slot with a lower priority message
- let (idx, pending_frame) = if queue_is_full {
- if self.is_available(0, id) {
- (0, self.abort_pending_fd_mailbox(0))
- } else if self.is_available(1, id) {
- (1, self.abort_pending_fd_mailbox(1))
- } else if self.is_available(2, id) {
- (2, self.abort_pending_fd_mailbox(2))
+ (2, self.abort_pending_mailbox_generic(2))
} else {
// For now we bail when there is no lower priority slot available
// Can this lead to priority inversion?
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 744d756f5..6a4a25cb7 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -58,7 +58,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
if !T::registers().tx_queue_is_full() {
match buf.tx_receiver.try_receive() {
Ok(frame) => {
- _ = T::registers().write_classic(&frame);
+ _ = T::registers().write(&frame);
}
Err(_) => {}
}
@@ -68,7 +68,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
if !T::registers().tx_queue_is_full() {
match buf.tx_receiver.try_receive() {
Ok(frame) => {
- _ = T::registers().write_fd(&frame);
+ _ = T::registers().write(&frame);
}
Err(_) => {}
}
@@ -359,7 +359,7 @@ impl<'d, T: Instance> Fdcan<'d, T> {
/// Returns the next received message frame
pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
- T::state().rx_mode.read::<T>().await
+ T::state().rx_mode.read_classic::<T>().await
}
/// Queues the message to be sent but exerts backpressure. If a lower-priority
@@ -633,7 +633,7 @@ impl<'c, 'd, T: Instance> FdcanTx<'d, T> {
impl<'c, 'd, T: Instance> FdcanRx<'d, T> {
/// Returns the next received message frame
pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
- T::state().rx_mode.read::<T>().await
+ T::state().rx_mode.read_classic::<T>().await
}
/// Returns the next received message frame
@@ -649,6 +649,7 @@ pub(crate) mod sealed {
use embassy_sync::channel::{DynamicReceiver, DynamicSender};
use embassy_sync::waitqueue::AtomicWaker;
+ use super::CanHeader;
use crate::can::_version::{BusError, Timestamp};
use crate::can::frame::{ClassicFrame, FdFrame};
@@ -689,13 +690,13 @@ pub(crate) mod sealed {
waker.wake();
}
RxMode::ClassicBuffered(buf) => {
- if let Some(r) = T::registers().read_classic(fifonr) {
+ if let Some(r) = T::registers().read(fifonr) {
let ts = T::calc_timestamp(T::state().ns_per_timer_tick, r.1);
let _ = buf.rx_sender.try_send((r.0, ts));
}
}
RxMode::FdBuffered(buf) => {
- if let Some(r) = T::registers().read_fd(fifonr) {
+ if let Some(r) = T::registers().read(fifonr) {
let ts = T::calc_timestamp(T::state().ns_per_timer_tick, r.1);
let _ = buf.rx_sender.try_send((r.0, ts));
}
@@ -703,15 +704,15 @@ pub(crate) mod sealed {
}
}
- pub async fn read<T: Instance>(&self) -> Result<(ClassicFrame, Timestamp), BusError> {
+ async fn read<T: Instance, F: CanHeader>(&self) -> Result<(F, Timestamp), BusError> {
poll_fn(|cx| {
T::state().err_waker.register(cx.waker());
self.register(cx.waker());
- if let Some((msg, ts)) = T::registers().read_classic(0) {
+ if let Some((msg, ts)) = T::registers().read(0) {
let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
return Poll::Ready(Ok((msg, ts)));
- } else if let Some((msg, ts)) = T::registers().read_classic(1) {
+ } else if let Some((msg, ts)) = T::registers().read(1) {
let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
return Poll::Ready(Ok((msg, ts)));
} else if let Some(err) = T::registers().curr_error() {
@@ -723,24 +724,12 @@ pub(crate) mod sealed {
.await
}
- pub async fn read_fd<T: Instance>(&self) -> Result<(FdFrame, Timestamp), BusError> {
- poll_fn(|cx| {
- T::state().err_waker.register(cx.waker());
- self.register(cx.waker());
+ pub async fn read_classic<T: Instance>(&self) -> Result<(ClassicFrame, Timestamp), BusError> {
+ self.read::<T, _>().await
+ }
- if let Some((msg, ts)) = T::registers().read_fd(0) {
- let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some((msg, ts)) = T::registers().read_fd(1) {
- let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = T::registers().curr_error() {
- // TODO: this is probably wrong
- return Poll::Ready(Err(err));
- }
- Poll::Pending
- })
- .await
+ pub async fn read_fd<T: Instance>(&self) -> Result<(FdFrame, Timestamp), BusError> {
+ self.read::<T, _>().await
}
}
@@ -766,11 +755,11 @@ pub(crate) mod sealed {
/// frame is dropped from the mailbox, it is returned. If no lower-priority frames
/// can be replaced, this call asynchronously waits for a frame to be successfully
/// transmitted, then tries again.
- pub async fn write<T: Instance>(&self, frame: &ClassicFrame) -> Option<ClassicFrame> {
+ async fn write_generic<T: Instance, F: embedded_can::Frame + CanHeader>(&self, frame: &F) -> Option<F> {
poll_fn(|cx| {
self.register(cx.waker());
- if let Ok(dropped) = T::registers().write_classic(frame) {
+ if let Ok(dropped) = T::registers().write(frame) {
return Poll::Ready(dropped);
}
@@ -781,23 +770,20 @@ pub(crate) mod sealed {
.await
}
+ /// Queues the message to be sent but exerts backpressure. If a lower-priority
+ /// frame is dropped from the mailbox, it is returned. If no lower-priority frames
+ /// can be replaced, this call asynchronously waits for a frame to be successfully
+ /// transmitted, then tries again.
+ pub async fn write<T: Instance>(&self, frame: &ClassicFrame) -> Option<ClassicFrame> {
+ self.write_generic::<T, _>(frame).await
+ }
+
/// Queues the message to be sent but exerts backpressure. If a lower-priority
/// frame is dropped from the mailbox, it is returned. If no lower-priority frames
/// can be replaced, this call asynchronously waits for a frame to be successfully
/// transmitted, then tries again.
pub async fn write_fd<T: Instance>(&self, frame: &FdFrame) -> Option<FdFrame> {
- poll_fn(|cx| {
- self.register(cx.waker());
-
- if let Ok(dropped) = T::registers().write_fd(frame) {
- return Poll::Ready(dropped);
- }
-
- // Couldn't replace any lower priority frames. Need to wait for some mailboxes
- // to clear.
- Poll::Pending
- })
- .await
+ self.write_generic::<T, _>(frame).await
}
}
diff --git a/embassy-stm32/src/can/frame.rs b/embassy-stm32/src/can/frame.rs
index 725a9b1ab..59b9fb08c 100644
--- a/embassy-stm32/src/can/frame.rs
+++ b/embassy-stm32/src/can/frame.rs
@@ -56,6 +56,16 @@ impl Header {
}
}
+/// Trait for FDCAN frame types, providing ability to construct from a Header
+/// and to retrieve the Header from a frame
+pub trait CanHeader: Sized {
+ /// Construct frame from header and payload
+ fn from_header(header: Header, data: &[u8]) -> Option<Self>;
+
+ /// Get this frame's header struct
+ fn header(&self) -> &Header;
+}
+
/// Payload of a classic CAN data frame.
///
/// Contains 0 to 8 Bytes of data.
@@ -213,6 +223,16 @@ impl embedded_can::Frame for ClassicFrame {
}
}
+impl CanHeader for ClassicFrame {
+ fn from_header(header: Header, data: &[u8]) -> Option<Self> {
+ Some(Self::new(header, ClassicData::new(data)?))
+ }
+
+ fn header(&self) -> &Header {
+ self.header()
+ }
+}
+
/// Payload of a (FD)CAN data frame.
///
/// Contains 0 to 64 Bytes of data.
@@ -368,3 +388,13 @@ impl embedded_can::Frame for FdFrame {
&self.data.raw()
}
}
+
+impl CanHeader for FdFrame {
+ fn from_header(header: Header, data: &[u8]) -> Option<Self> {
+ Some(Self::new(header, FdData::new(data)?))
+ }
+
+ fn header(&self) -> &Header {
+ self.header()
+ }
+}
From a8da42943fdd57ded612399d18846398cbd011d3 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Tue, 27 Feb 2024 23:45:53 +0000
Subject: [PATCH 342/392] stm32: can: fd: rm some irrelevant commented code and
dead code
---
embassy-stm32/src/can/fd/peripheral.rs | 42 --------------------------
embassy-stm32/src/can/frame.rs | 2 --
2 files changed, 44 deletions(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 7d26a5fe0..c5606b883 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -62,11 +62,6 @@ impl Registers {
}
pub fn put_tx_frame(&self, bufidx: usize, header: &Header, buffer: &[u8]) {
- // Fill level - do we have a msg?
- //if self.regs.rxfs(fifonr).read().ffl() < 1 { return None; }
-
- //let read_idx = self.regs.rxfs(fifonr).read().fgi();
-
let mailbox = self.tx_buffer_element(bufidx);
mailbox.reset();
@@ -169,9 +164,6 @@ impl Registers {
}
#[inline]
- //fn abort_pending_mailbox<PTX, R>(&mut self, idx: Mailbox, pending: PTX) -> Option<R>
-//where
- // PTX: FnOnce(Mailbox, TxFrameHeader, &[u32]) -> R,
pub fn abort_pending_mailbox_generic<F: embedded_can::Frame>(&self, bufidx: usize) -> Option<F> {
if self.abort(bufidx) {
let mailbox = self.tx_buffer_element(bufidx);
@@ -187,7 +179,6 @@ impl Registers {
return None;
}
- //let tx_ram = self.tx_msg_ram();
let mut data = [0u8; 64];
data_from_tx_buffer(&mut data, mailbox, len as usize);
@@ -205,9 +196,6 @@ impl Registers {
}
}
- /// As Transmit, but if there is a pending frame, `pending` will be called so that the frame can
- /// be preserved.
- //pub fn transmit_preserve<PTX, P>(
pub fn write<F: embedded_can::Frame + CanHeader>(&self, frame: &F) -> nb::Result<Option<F>, Infallible> {
let queue_is_full = self.tx_queue_is_full();
@@ -459,8 +447,6 @@ impl Registers {
/// parameter to this method.
#[inline]
pub fn set_nominal_bit_timing(&mut self, btr: NominalBitTiming) {
- //self.control.config.nbtr = btr;
-
self.regs.nbtp().write(|w| {
w.set_nbrp(btr.nbrp() - 1);
w.set_ntseg1(btr.ntseg1() - 1);
@@ -473,8 +459,6 @@ impl Registers {
/// This is not used when frame_transmit is set to anything other than AllowFdCanAndBRS.
#[inline]
pub fn set_data_bit_timing(&mut self, btr: DataBitTiming) {
- //self.control.config.dbtr = btr;
-
self.regs.dbtp().write(|w| {
w.set_dbrp(btr.dbrp() - 1);
w.set_dtseg1(btr.dtseg1() - 1);
@@ -492,7 +476,6 @@ impl Registers {
#[inline]
pub fn set_automatic_retransmit(&mut self, enabled: bool) {
self.regs.cccr().modify(|w| w.set_dar(!enabled));
- //self.control.config.automatic_retransmit = enabled;
}
/// Configures the transmit pause feature. See
@@ -500,21 +483,18 @@ impl Registers {
#[inline]
pub fn set_transmit_pause(&mut self, enabled: bool) {
self.regs.cccr().modify(|w| w.set_txp(!enabled));
- //self.control.config.transmit_pause = enabled;
}
/// Configures non-iso mode. See [`FdCanConfig::set_non_iso_mode`]
#[inline]
pub fn set_non_iso_mode(&mut self, enabled: bool) {
self.regs.cccr().modify(|w| w.set_niso(enabled));
- //self.control.config.non_iso_mode = enabled;
}
/// Configures edge filtering. See [`FdCanConfig::set_edge_filtering`]
#[inline]
pub fn set_edge_filtering(&mut self, enabled: bool) {
self.regs.cccr().modify(|w| w.set_efbi(enabled));
- //self.control.config.edge_filtering = enabled;
}
/// Configures frame transmission mode. See
@@ -534,16 +514,12 @@ impl Registers {
#[cfg(not(stm32h7))]
w.set_brse(brse);
});
-
- //self.control.config.frame_transmit = fts;
}
/// Sets the protocol exception handling on/off
#[inline]
pub fn set_protocol_exception_handling(&mut self, enabled: bool) {
self.regs.cccr().modify(|w| w.set_pxhd(!enabled));
-
- //self.control.config.protocol_exception_handling = enabled;
}
/// Configures and resets the timestamp counter
@@ -567,8 +543,6 @@ impl Registers {
w.set_tcp(tcp);
w.set_tss(tss);
});
-
- //self.control.config.timestamp_source = select;
}
#[cfg(not(stm32h7))]
@@ -696,22 +670,6 @@ fn data_from_tx_buffer(buffer: &mut [u8], mailbox: &TxBufferElement, len: usize)
}
}
-impl From<&RxFifoElement> for ClassicFrame {
- fn from(mailbox: &RxFifoElement) -> Self {
- let header_reg = mailbox.header.read();
-
- let id = make_id(header_reg.id().bits(), header_reg.xtd().bits());
- let dlc = header_reg.to_data_length().len();
- let len = dlc as usize;
-
- let mut buffer: [u8; 64] = [0; 64];
- data_from_fifo(&mut buffer, mailbox, len);
- let data = ClassicData::new(&buffer[0..len]);
- let header = Header::new(id, dlc, header_reg.rtr().bits());
- ClassicFrame::new(header, data.unwrap())
- }
-}
-
fn extract_frame(mailbox: &RxFifoElement, buffer: &mut [u8]) -> Option<(Header, u16)> {
let header_reg = mailbox.header.read();
diff --git a/embassy-stm32/src/can/frame.rs b/embassy-stm32/src/can/frame.rs
index 59b9fb08c..00a441db6 100644
--- a/embassy-stm32/src/can/frame.rs
+++ b/embassy-stm32/src/can/frame.rs
@@ -292,8 +292,6 @@ pub struct FdFrame {
}
impl FdFrame {
- pub(crate) const MAX_DATA_LEN: usize = 64;
-
/// Create a new CAN classic Frame
pub fn new(can_header: Header, data: FdData) -> FdFrame {
FdFrame { can_header, data }
From 1353a343b8e9d48b8f1f537dbf4e38e32a39c06d Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Wed, 28 Feb 2024 18:03:53 +1000
Subject: [PATCH 343/392] Buffer is not big enough for FD frames.
---
embassy-stm32/src/can/fd/peripheral.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index c5606b883..abb546895 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -46,7 +46,7 @@ impl Registers {
let read_idx = self.regs.rxfs(fifonr).read().fgi();
let mailbox = self.rx_fifo_element(fifonr, read_idx as usize);
- let mut buffer: [u8; 8] = [0; 8];
+ let mut buffer = [0u8; 64];
let maybe_header = extract_frame(mailbox, &mut buffer);
// Clear FIFO, reduces count and increments read buf
From 368b3a9aaf97a7662217b9ff2784e3648368586c Mon Sep 17 00:00:00 2001
From: "Guilherme S. Salustiano" <guissalustiano@gmail.com>
Date: Wed, 28 Feb 2024 14:54:54 +0100
Subject: [PATCH 344/392] fix: radio error
---
embassy-nrf/src/radio/ble.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index 81ef96b65..24dba582f 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -15,7 +15,7 @@ use crate::interrupt::typelevel::Interrupt;
use crate::radio::*;
use crate::util::slice_in_ram_or;
-/// UART error.
+/// RADIO error.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
From 990b44566ce1393a4a553a65d5a6c412cb656805 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Wed, 28 Feb 2024 15:11:30 +0100
Subject: [PATCH 345/392] [docs] Added some failure modes to watch out for
* Linked to probe.rs website rather than the crates.io page
* Fixed some formatting errors (>:( grrr asciidoc)
* Added cargo add probe-rs failure mode
* Added pico-w vs pico blinky failure mode
---
docs/modules/ROOT/pages/getting_started.adoc | 28 +++++++++++++++-----
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/docs/modules/ROOT/pages/getting_started.adoc b/docs/modules/ROOT/pages/getting_started.adoc
index 24bde1c1f..be2b868eb 100644
--- a/docs/modules/ROOT/pages/getting_started.adoc
+++ b/docs/modules/ROOT/pages/getting_started.adoc
@@ -3,7 +3,7 @@
So you want to try Embassy, great! To get started, there are a few tools you need to install:
* link:https://rustup.rs/[rustup] - the Rust toolchain is needed to compile Rust code.
-* link:https://crates.io/crates/probe-rs[probe-rs] - to flash the firmware on your device. If you already have other tools like `OpenOCD` setup, you can use that as well.
+* link:https://probe.rs/[probe-rs] - to flash the firmware on your device. If you already have other tools like `OpenOCD` setup, you can use that as well.
If you don't have any supported board, don't worry: you can also run embassy on your PC using the `std` examples.
@@ -82,19 +82,19 @@ If everything worked correctly, you should see a blinking LED on your board, and
└─ blinky::__embassy_main::task::{generator#0} @ src/bin/blinky.rs:27
----
-NOTE: How does the `cargo run` command know how to connect to our board and program it? In each `examples` folder, there’s a `.cargo/config.toml` file which tells cargo to use link:https://probe.rs/[probe-rs] as the runner for ARM binaries in that folder. probe-rs handles communication with the debug probe and MCU. In order for this to work, probe-rs needs to know which chip it’s programming, so you’ll have to edit this file if you want to run examples on other chips.
+NOTE: How does the `+cargo run+` command know how to connect to our board and program it? In each `examples` folder, there’s a `.cargo/config.toml` file which tells cargo to use link:https://probe.rs/[probe-rs] as the runner for ARM binaries in that folder. probe-rs handles communication with the debug probe and MCU. In order for this to work, probe-rs needs to know which chip it’s programming, so you’ll have to edit this file if you want to run examples on other chips.
=== It didn’t work!
-If you hare having issues when running `cargo run --release`, please check the following:
+If you hare having issues when running `+cargo run --release+`, please check the following:
-* You are specifying the correct `--chip` on the command line, OR
-* You have set `.cargo/config.toml`'s run line to the correct chip, AND
-* You have changed `examples/Cargo.toml`'s HAL (e.g. embassy-stm32) dependency's feature to use the correct chip (replace the existing stm32xxxx feature)
+* You are specifying the correct `+--chip+` on the command line, OR
+* You have set `+.cargo/config.toml+`’s run line to the correct chip, AND
+* You have changed `+examples/Cargo.toml+`’s HAL (e.g. embassy-stm32) dependency's feature to use the correct chip (replace the existing stm32xxxx feature)
At this point the project should run. If you do not see a blinky LED for blinky, for example, be sure to check the code is toggling your board's LED pin.
-If you are trying to run an example with `cargo run --release` and you see the following output:
+If you are trying to run an example with `+cargo run --release+` and you see the following output:
[source]
----
0.000000 INFO Hello World!
@@ -115,6 +115,20 @@ To get rid of the frame-index error add the following to your `Cargo.toml`:
debug = 2
----
+If you’re get an extremely long error message containing something like the following:
+
+[source]
+----
+error[E0463]: can't find crate for `std`
+ |
+ = note: the `thumbv6m-none-eabi` target may not support the standard library
+ = note: `std` is required by `stable_deref_trait` because it does not declare `#![no_std]`
+----
+
+Make sure that you didn’t accidentally run `+cargo add probe-rs+` (which adds it as a dependency) instead of link:https://probe.rs/docs/getting-started/installation/[correctly installing probe-rs].
+
+If you’re using a raspberry pi pico-w, make sure you’re running `+cargo run --bin wifi_blinky --release+` rather than the regular blinky. The pico-w’s on-board LED is connected to the WiFi chip, which needs to be initialized before the LED can be blinked.
+
If you’re still having problems, check the link:https://embassy.dev/book/dev/faq.html[FAQ], or ask for help in the link:https://matrix.to/#/#embassy-rs:matrix.org[Embassy Chat Room].
== What's next?
From 2787164ea9ba30f806d6c38443d2eca2984b1e62 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Wed, 28 Feb 2024 15:15:43 +0100
Subject: [PATCH 346/392] grammar fix
---
docs/modules/ROOT/pages/getting_started.adoc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/modules/ROOT/pages/getting_started.adoc b/docs/modules/ROOT/pages/getting_started.adoc
index be2b868eb..e8bc84255 100644
--- a/docs/modules/ROOT/pages/getting_started.adoc
+++ b/docs/modules/ROOT/pages/getting_started.adoc
@@ -115,7 +115,7 @@ To get rid of the frame-index error add the following to your `Cargo.toml`:
debug = 2
----
-If you’re get an extremely long error message containing something like the following:
+If you’re getting an extremely long error message containing something like the following:
[source]
----
From d07a0148d759fa09ba1ee8dc4810bb4edd8bda49 Mon Sep 17 00:00:00 2001
From: Barnaby Walters <barnaby@waterpigs.co.uk>
Date: Wed, 28 Feb 2024 15:48:37 +0100
Subject: [PATCH 347/392] Documented rp2040 probe-rs info bug, linked to
new_project page
---
docs/modules/ROOT/pages/getting_started.adoc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/docs/modules/ROOT/pages/getting_started.adoc b/docs/modules/ROOT/pages/getting_started.adoc
index e8bc84255..73cb5530d 100644
--- a/docs/modules/ROOT/pages/getting_started.adoc
+++ b/docs/modules/ROOT/pages/getting_started.adoc
@@ -129,6 +129,8 @@ Make sure that you didn’t accidentally run `+cargo add probe-rs+` (which adds
If you’re using a raspberry pi pico-w, make sure you’re running `+cargo run --bin wifi_blinky --release+` rather than the regular blinky. The pico-w’s on-board LED is connected to the WiFi chip, which needs to be initialized before the LED can be blinked.
+If you’re using an rp2040 debug probe (e.g. the pico probe) and are having issues after running `probe-rs info`, unplug and reconnect the probe, letting it power cycle. Running `probe-rs info` is link:https://github.com/probe-rs/probe-rs/issues/1849[known to put the pico probe into an unusable state].
+
If you’re still having problems, check the link:https://embassy.dev/book/dev/faq.html[FAQ], or ask for help in the link:https://matrix.to/#/#embassy-rs:matrix.org[Embassy Chat Room].
== What's next?
@@ -138,3 +140,4 @@ Congratulations, you have your first Embassy application running! Here are some
* Read more about the xref:runtime.adoc[executor].
* Read more about the xref:hal.adoc[HAL].
* Start xref:basic_application.adoc[writing your application].
+* Learn how to xref:new_project.adoc[start a new embassy project by adapting an example].
From 47c579eba2a7b4372a891bcd747f2bb0c56ce8a4 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Wed, 28 Feb 2024 18:08:41 +0800
Subject: [PATCH 348/392] update metapac
---
embassy-stm32/Cargo.toml | 4 ++--
embassy-stm32/src/can/fd/peripheral.rs | 4 +++-
embassy-stm32/src/opamp.rs | 2 ++
embassy-stm32/src/timer/mod.rs | 12 ++++++------
examples/stm32h7/src/bin/low_level_timer_api.rs | 4 ++--
5 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 81b8e2f94..08ccd35ae 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-4a0bcec33362449fb733c066936d25cbabab396a" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7c8b53413499acc3273b706318777a60f932d77a", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-4a0bcec33362449fb733c066936d25cbabab396a", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index c5606b883..9b8802ff9 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -303,7 +303,9 @@ impl Registers {
// Framework specific settings are set here
// set TxBuffer to Queue Mode
- self.regs.txbc().write(|w| w.set_tfqm(true));
+ self.regs
+ .txbc()
+ .write(|w| w.set_tfqm(crate::pac::can::vals::Tfqm::QUEUE));
// set standard filters list size to 28
// set extended filters list size to 8
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index ae8b3cacc..cf531e266 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -90,6 +90,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
in_pin.set_as_analog();
out_pin.set_as_analog();
+ // PGA_GAIN value may have different meaning in different MCU serials, use with caution.
let (vm_sel, pga_gain) = match gain {
OpAmpGain::Mul1 => (0b11, 0b00),
OpAmpGain::Mul2 => (0b10, 0b00),
@@ -127,6 +128,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
into_ref!(pin);
pin.set_as_analog();
+ // PGA_GAIN value may have different meaning in different MCU serials, use with caution.
let (vm_sel, pga_gain) = match gain {
OpAmpGain::Mul1 => (0b11, 0b00),
OpAmpGain::Mul2 => (0b10, 0b00),
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index c8f580101..8530c5229 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -379,7 +379,7 @@ pub(crate) mod sealed {
let regs = Self::regs_gp32();
regs.psc().write(|r| r.set_psc(psc));
- regs.arr().write(|r| r.set_arr(arr));
+ regs.arr().write_value(arr);
regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
regs.egr().write(|r| r.set_ug(true));
@@ -391,7 +391,7 @@ pub(crate) mod sealed {
let timer_f = Self::frequency();
let regs = Self::regs_gp32();
- let arr = regs.arr().read().arr();
+ let arr = regs.arr().read();
let psc = regs.psc().read().psc();
timer_f / arr / (psc + 1)
@@ -399,22 +399,22 @@ pub(crate) mod sealed {
/// Set comapre value for a channel.
fn set_compare_value(&self, channel: Channel, value: u32) {
- Self::regs_gp32().ccr(channel.index()).modify(|w| w.set_ccr(value));
+ Self::regs_gp32().ccr(channel.index()).write_value(value);
}
/// Get capture value for a channel.
fn get_capture_value(&self, channel: Channel) -> u32 {
- Self::regs_gp32().ccr(channel.index()).read().ccr()
+ Self::regs_gp32().ccr(channel.index()).read()
}
/// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
fn get_max_compare_value(&self) -> u32 {
- Self::regs_gp32().arr().read().arr()
+ Self::regs_gp32().arr().read()
}
/// Get compare value for a channel.
fn get_compare_value(&self, channel: Channel) -> u32 {
- Self::regs_gp32().ccr(channel.index()).read().ccr()
+ Self::regs_gp32().ccr(channel.index()).read()
}
}
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs
index cc508c3cf..049d9967d 100644
--- a/examples/stm32h7/src/bin/low_level_timer_api.rs
+++ b/examples/stm32h7/src/bin/low_level_timer_api.rs
@@ -113,11 +113,11 @@ impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> {
}
pub fn get_max_duty(&self) -> u32 {
- T::regs_gp32().arr().read().arr()
+ T::regs_gp32().arr().read()
}
pub fn set_duty(&mut self, channel: Channel, duty: u32) {
defmt::assert!(duty < self.get_max_duty());
- T::regs_gp32().ccr(channel.index()).modify(|w| w.set_ccr(duty))
+ T::regs_gp32().ccr(channel.index()).write_value(duty)
}
}
From 4294bc5e4bb191adcdd2daffd77180bb602da720 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Wed, 28 Feb 2024 22:36:31 +0100
Subject: [PATCH 349/392] Added IEEE 802.15.4 radio
---
embassy-nrf/src/chips/nrf52833.rs | 5 +
embassy-nrf/src/lib.rs | 2 +-
embassy-nrf/src/radio/ble.rs | 15 +-
embassy-nrf/src/radio/event.rs | 310 +++++++++++++++
embassy-nrf/src/radio/ieee802154.rs | 573 ++++++++++++++++++++++++++++
embassy-nrf/src/radio/mod.rs | 34 +-
6 files changed, 917 insertions(+), 22 deletions(-)
create mode 100644 embassy-nrf/src/radio/event.rs
create mode 100644 embassy-nrf/src/radio/ieee802154.rs
diff --git a/embassy-nrf/src/chips/nrf52833.rs b/embassy-nrf/src/chips/nrf52833.rs
index 7c9b66d69..20f14e2d6 100644
--- a/embassy-nrf/src/chips/nrf52833.rs
+++ b/embassy-nrf/src/chips/nrf52833.rs
@@ -170,6 +170,9 @@ embassy_hal_internal::peripherals! {
// I2S
I2S,
+
+ // Radio
+ RADIO,
}
impl_usb!(USBD, USBD, USBD);
@@ -306,6 +309,8 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 04a6293a4..132bffa8b 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -47,7 +47,7 @@ pub mod gpio;
pub mod gpiote;
// TODO: tested on other chips
-#[cfg(any(feature = "nrf52840"))]
+#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
pub mod radio;
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index 24dba582f..ecf8cc5eb 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -15,19 +15,6 @@ use crate::interrupt::typelevel::Interrupt;
use crate::radio::*;
use crate::util::slice_in_ram_or;
-/// RADIO error.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[non_exhaustive]
-pub enum Error {
- /// Buffer was too long.
- BufferTooLong,
- /// Buffer was to short.
- BufferTooShort,
- /// The buffer is not in data RAM. It is most likely in flash, and nRF's DMA cannot access flash.
- BufferNotInRAM,
-}
-
/// Radio driver.
pub struct Radio<'d, T: Instance> {
_p: PeripheralRef<'d, T>,
@@ -393,7 +380,7 @@ impl<'d, T: Instance> Radio<'d, T> {
// On poll check if interrupt happen
poll_fn(|cx| {
- s.end_waker.register(cx.waker());
+ s.event_waker.register(cx.waker());
if r.events_end.read().events_end().bit_is_set() {
// trace!("radio:end");
return core::task::Poll::Ready(());
diff --git a/embassy-nrf/src/radio/event.rs b/embassy-nrf/src/radio/event.rs
new file mode 100644
index 000000000..11056b4d8
--- /dev/null
+++ b/embassy-nrf/src/radio/event.rs
@@ -0,0 +1,310 @@
+use crate::pac;
+use bitflags;
+
+bitflags::bitflags! {
+ /// Event as bit flags
+ pub struct Event : u32 {
+ /// Radio ready
+ const READY = 1u32 << 0;
+ /// Address operation done
+ const ADDRESS = 1u32 << 1;
+ /// Payload operation done
+ const PAYLOAD = 1u32 << 2;
+ /// Packet operation done
+ const END = 1u32 << 3;
+ /// Radio has been disabled
+ const DISABLED = 1u32 << 4;
+ /// Device address match in last received packet
+ const DEV_MATCH = 1u32 << 5;
+ /// No device address match in last received packet
+ const DEV_MISS = 1u32 << 6;
+ /// RSSI sampling complete
+ const RSSI_END = 1u32 << 7;
+ /// Bit counter reached target
+ const BC_MATCH = 1u32 << 10;
+ /// CRC ok in last received packet
+ const CRC_OK = 1u32 << 12;
+ /// CRC error in last received packet
+ const CRC_ERROR = 1u32 << 13;
+ /// IEEE 802.15.4 length field received
+ const FRAME_START = 1u32 << 14;
+ /// Sampling of energy detect complete
+ const ED_END = 1u32 << 15;
+ /// Sampling of energy detect stopped
+ const ED_STOPPED = 1u32 << 16;
+ /// Wireless medium in idle, ready to sent
+ const CCA_IDLE = 1u32 << 17;
+ /// Wireless medium busy, do not send
+ const CCA_BUSY = 1u32 << 18;
+ /// Clear channel assessment stopped
+ const CCA_STOPPED = 1u32 << 19;
+ /// BLE LR rate boost received
+ const RATE_BOOST = 1u32 << 20;
+ /// Radio has ramped up transmitter
+ const TX_READY = 1u32 << 21;
+ /// Radio has ramped up receiver
+ const RX_READY = 1u32 << 22;
+ /// MAC header match found
+ const MHR_MATCH = 1u32 << 23;
+ /// Preamble received, possible false triggering
+ const SYNC = 1u32 << 26;
+ /// Last bit sent / received
+ const PHY_END = 1u32 << 27;
+ /// Continuous tone extension is present
+ const CTE_PRESENT = 1u32 << 28;
+ }
+}
+
+impl Event {
+ /// Read events from radio
+ #[cfg(not(feature = "nrf52832"))]
+ pub fn from_radio(radio: &pac::radio::RegisterBlock) -> Self {
+ let mut value = Self::empty();
+ if radio.events_ready.read().events_ready().bit_is_set() {
+ value |= Self::READY;
+ }
+ if radio.events_address.read().events_address().bit_is_set() {
+ value |= Self::ADDRESS;
+ }
+ if radio.events_payload.read().events_payload().bit_is_set() {
+ value |= Self::PAYLOAD;
+ }
+ if radio.events_end.read().events_end().bit_is_set() {
+ value |= Self::END;
+ }
+ if radio.events_disabled.read().events_disabled().bit_is_set() {
+ value |= Self::DISABLED;
+ }
+ if radio.events_devmatch.read().events_devmatch().bit_is_set() {
+ value |= Self::DEV_MATCH;
+ }
+ if radio.events_devmiss.read().events_devmiss().bit_is_set() {
+ value |= Self::DEV_MISS;
+ }
+ if radio.events_rssiend.read().events_rssiend().bit_is_set() {
+ value |= Self::RSSI_END;
+ }
+ if radio.events_bcmatch.read().events_bcmatch().bit_is_set() {
+ value |= Self::BC_MATCH;
+ }
+ if radio.events_crcok.read().events_crcok().bit_is_set() {
+ value |= Self::CRC_OK;
+ }
+ if radio.events_crcerror.read().events_crcerror().bit_is_set() {
+ value |= Self::CRC_ERROR;
+ }
+ #[cfg(any(
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_framestart.read().events_framestart().bit_is_set() {
+ value |= Self::FRAME_START;
+ }
+ #[cfg(any(
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_edend.read().events_edend().bit_is_set() {
+ value |= Self::ED_END;
+ }
+ #[cfg(any(
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_edstopped.read().events_edstopped().bit_is_set() {
+ value |= Self::ED_STOPPED;
+ }
+ #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
+ if radio.events_ccaidle.read().events_ccaidle().bit_is_set() {
+ value |= Self::CCA_IDLE;
+ }
+ #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
+ if radio.events_ccabusy.read().events_ccabusy().bit_is_set() {
+ value |= Self::CCA_BUSY;
+ }
+ #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
+ if radio.events_ccastopped.read().events_ccastopped().bit_is_set() {
+ value |= Self::CCA_STOPPED;
+ }
+ #[cfg(any(
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_rateboost.read().events_rateboost().bit_is_set() {
+ value |= Self::RATE_BOOST;
+ }
+ #[cfg(any(
+ feature = "nrf52805",
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_txready.read().events_txready().bit_is_set() {
+ value |= Self::TX_READY;
+ }
+ #[cfg(any(
+ feature = "nrf52805",
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_rxready.read().events_rxready().bit_is_set() {
+ value |= Self::RX_READY;
+ }
+ #[cfg(any(
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_mhrmatch.read().events_mhrmatch().bit_is_set() {
+ value |= Self::MHR_MATCH;
+ }
+ #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
+ if radio.events_sync.read().events_sync().bit_is_set() {
+ value |= Self::SYNC;
+ }
+ #[cfg(any(
+ feature = "nrf52805",
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_phyend.read().events_phyend().bit_is_set() {
+ value |= Self::PHY_END;
+ }
+ #[cfg(any(
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "_nrf5340-net"
+ ))]
+ if radio.events_ctepresent.read().events_ctepresent().bit_is_set() {
+ value |= Self::CTE_PRESENT;
+ }
+ value
+ }
+ // The nRF52832 SVD probably is a bit broken
+ /// Read events from radio
+ #[cfg(feature = "nrf52832")]
+ pub fn from_radio(radio: &pac::radio::RegisterBlock) -> Self {
+ let mut value = Self::empty();
+ if radio.events_ready.read().bits() == 1 {
+ value |= Self::READY;
+ }
+ if radio.events_address.read().bits() == 1 {
+ value |= Self::ADDRESS;
+ }
+ if radio.events_payload.read().bits() == 1 {
+ value |= Self::PAYLOAD;
+ }
+ if radio.events_end.read().bits() == 1 {
+ value |= Self::END;
+ }
+ if radio.events_disabled.read().bits() == 1 {
+ value |= Self::DISABLED;
+ }
+ if radio.events_devmatch.read().bits() == 1 {
+ value |= Self::DEV_MATCH;
+ }
+ if radio.events_devmiss.read().bits() == 1 {
+ value |= Self::DEV_MISS;
+ }
+ if radio.events_rssiend.read().bits() == 1 {
+ value |= Self::RSSI_END;
+ }
+ if radio.events_bcmatch.read().bits() == 1 {
+ value |= Self::BC_MATCH;
+ }
+ if radio.events_crcok.read().bits() == 1 {
+ value |= Self::CRC_OK;
+ }
+ if radio.events_crcerror.read().bits() == 1 {
+ value |= Self::CRC_ERROR;
+ }
+ value
+ }
+
+ /// Read events from radio, mask with set interrupts
+ pub fn from_radio_masked(radio: &pac::radio::RegisterBlock) -> Self {
+ Self::from_radio(radio) & Self::from_bits_truncate(radio.intenset.read().bits())
+ }
+}
+
+#[cfg(feature = "defmt")]
+impl defmt::Format for Event {
+ fn format(&self, fmt: defmt::Formatter) {
+ defmt::write!(
+ fmt,
+ "{} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {}",
+ if self.contains(Self::READY) { "RD" } else { "__" },
+ if self.contains(Self::ADDRESS) { "AD" } else { "__" },
+ if self.contains(Self::PAYLOAD) { "PL" } else { "__" },
+ if self.contains(Self::END) { " E" } else { "__" },
+ if self.contains(Self::DISABLED) { "DI" } else { "__" },
+ if self.contains(Self::DEV_MATCH) { "D+" } else { "__" },
+ if self.contains(Self::DEV_MISS) { "D-" } else { "__" },
+ if self.contains(Self::RSSI_END) { "RE" } else { "__" },
+ if self.contains(Self::BC_MATCH) { "CM" } else { "__" },
+ if self.contains(Self::CRC_OK) { "CO" } else { "__" },
+ if self.contains(Self::CRC_ERROR) { "CE" } else { "__" },
+ if self.contains(Self::FRAME_START) { "FS" } else { "__" },
+ if self.contains(Self::ED_END) { "EE" } else { "__" },
+ if self.contains(Self::ED_STOPPED) { "ES" } else { "__" },
+ if self.contains(Self::CCA_IDLE) { "CI" } else { "__" },
+ if self.contains(Self::CCA_BUSY) { "CB" } else { "__" },
+ if self.contains(Self::CCA_STOPPED) { "CS" } else { "__" },
+ if self.contains(Self::RATE_BOOST) { "RB" } else { "__" },
+ if self.contains(Self::TX_READY) { "TX" } else { "__" },
+ if self.contains(Self::RX_READY) { "RX" } else { "__" },
+ if self.contains(Self::MHR_MATCH) { "MM" } else { "__" },
+ if self.contains(Self::SYNC) { "SY" } else { "__" },
+ if self.contains(Self::PHY_END) { "PE" } else { "__" },
+ if self.contains(Self::CTE_PRESENT) { "CP" } else { "__" },
+ )
+ }
+}
+
+impl core::fmt::Display for Event {
+ fn fmt(&self, fmt: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+ write!(
+ fmt,
+ "{} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {}",
+ if self.contains(Self::READY) { "RD" } else { "__" },
+ if self.contains(Self::ADDRESS) { "AD" } else { "__" },
+ if self.contains(Self::PAYLOAD) { "PL" } else { "__" },
+ if self.contains(Self::END) { " E" } else { "__" },
+ if self.contains(Self::DISABLED) { "DI" } else { "__" },
+ if self.contains(Self::DEV_MATCH) { "D+" } else { "__" },
+ if self.contains(Self::DEV_MISS) { "D-" } else { "__" },
+ if self.contains(Self::RSSI_END) { "RE" } else { "__" },
+ if self.contains(Self::BC_MATCH) { "CM" } else { "__" },
+ if self.contains(Self::CRC_OK) { "CO" } else { "__" },
+ if self.contains(Self::CRC_ERROR) { "CE" } else { "__" },
+ if self.contains(Self::FRAME_START) { "FS" } else { "__" },
+ if self.contains(Self::ED_END) { "EE" } else { "__" },
+ if self.contains(Self::ED_STOPPED) { "ES" } else { "__" },
+ if self.contains(Self::CCA_IDLE) { "CI" } else { "__" },
+ if self.contains(Self::CCA_BUSY) { "CB" } else { "__" },
+ if self.contains(Self::CCA_STOPPED) { "CS" } else { "__" },
+ if self.contains(Self::RATE_BOOST) { "RB" } else { "__" },
+ if self.contains(Self::TX_READY) { "TX" } else { "__" },
+ if self.contains(Self::RX_READY) { "RX" } else { "__" },
+ if self.contains(Self::MHR_MATCH) { "MM" } else { "__" },
+ if self.contains(Self::SYNC) { "SY" } else { "__" },
+ if self.contains(Self::PHY_END) { "PE" } else { "__" },
+ if self.contains(Self::CTE_PRESENT) { "CP" } else { "__" },
+ )
+ }
+}
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
new file mode 100644
index 000000000..4d7949cb3
--- /dev/null
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -0,0 +1,573 @@
+//! IEEE 802.15.4 radio
+
+use core::sync::atomic::{compiler_fence, Ordering};
+use core::task::Poll;
+
+use super::{Error, Event, Instance, InterruptHandler};
+use crate::{
+ interrupt::{self, typelevel::Interrupt},
+ pac, Peripheral,
+};
+use pac::radio::{state::STATE_A as RadioState, txpower::TXPOWER_A as TxPower};
+
+use embassy_hal_internal::drop::OnDrop;
+use embassy_hal_internal::{into_ref, PeripheralRef};
+
+/// Default Start of Frame Delimiter = `0xA7` (IEEE compliant)
+pub const DEFAULT_SFD: u8 = 0xA7;
+
+// TODO expose the other variants in `pac::CCAMODE_A`
+/// Clear Channel Assessment method
+pub enum Cca {
+ /// Carrier sense
+ CarrierSense,
+ /// Energy Detection / Energy Above Threshold
+ EnergyDetection {
+ /// Energy measurements above this value mean that the channel is assumed to be busy.
+ /// Note the measurement range is 0..0xFF - where 0 means that the received power was
+ /// less than 10 dB above the selected receiver sensitivity. This value is not given in dBm,
+ /// but can be converted. See the nrf52840 Product Specification Section 6.20.12.4
+ /// for details.
+ ed_threshold: u8,
+ },
+}
+
+fn get_state(radio: &pac::radio::RegisterBlock) -> RadioState {
+ match radio.state.read().state().variant() {
+ Some(state) => state,
+ None => unreachable!(),
+ }
+}
+
+fn trace_state(state: RadioState) {
+ match state {
+ RadioState::DISABLED => trace!("radio:state:DISABLED"),
+ RadioState::RX_RU => trace!("radio:state:RX_RU"),
+ RadioState::RX_IDLE => trace!("radio:state:RX_IDLE"),
+ RadioState::RX => trace!("radio:state:RX"),
+ RadioState::RX_DISABLE => trace!("radio:state:RX_DISABLE"),
+ RadioState::TX_RU => trace!("radio:state:TX_RU"),
+ RadioState::TX_IDLE => trace!("radio:state:TX_IDLE"),
+ RadioState::TX => trace!("radio:state:TX"),
+ RadioState::TX_DISABLE => trace!("radio:state:TX_DISABLE"),
+ }
+}
+
+/// Radio driver.
+pub struct Radio<'d, T: Instance> {
+ _p: PeripheralRef<'d, T>,
+ needs_enable: bool,
+}
+
+impl<'d, T: Instance> Radio<'d, T> {
+ /// Create a new radio driver.
+ pub fn new(
+ radio: impl Peripheral<P = T> + 'd,
+ _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+ ) -> Self {
+ into_ref!(radio);
+
+ let r = T::regs();
+
+ // Disable and enable to reset peripheral
+ r.power.write(|w| w.power().disabled());
+ r.power.write(|w| w.power().enabled());
+
+ // Enable 802.15.4 mode
+ r.mode.write(|w| w.mode().ieee802154_250kbit());
+ // Configure CRC skip address
+ r.crccnf.write(|w| w.len().two().skipaddr().ieee802154());
+ unsafe {
+ // Configure CRC polynomial and init
+ r.crcpoly.write(|w| w.crcpoly().bits(0x0001_1021));
+ r.crcinit.write(|w| w.crcinit().bits(0));
+ // Configure packet layout
+ // 8-bit on air length
+ // S0 length, zero bytes
+ // S1 length, zero bytes
+ // S1 included in RAM if S1 length > 0, No.
+ // Code Indicator length, 0
+ // Preamble length 32-bit zero
+ // Exclude CRC
+ // No TERM field
+ r.pcnf0.write(|w| {
+ w.lflen()
+ .bits(8)
+ .s0len()
+ .clear_bit()
+ .s1len()
+ .bits(0)
+ .s1incl()
+ .clear_bit()
+ .cilen()
+ .bits(0)
+ .plen()
+ ._32bit_zero()
+ .crcinc()
+ .include()
+ });
+ r.pcnf1.write(|w| {
+ w.maxlen()
+ .bits(Packet::MAX_PSDU_LEN)
+ .statlen()
+ .bits(0)
+ .balen()
+ .bits(0)
+ .endian()
+ .clear_bit()
+ .whiteen()
+ .clear_bit()
+ });
+ }
+
+ // Enable NVIC interrupt
+ T::Interrupt::unpend();
+ unsafe { T::Interrupt::enable() };
+
+ let mut radio = Self {
+ _p: radio,
+ needs_enable: false,
+ };
+
+ radio.set_sfd(DEFAULT_SFD);
+ radio.set_transmission_power(0);
+ radio.set_channel(11);
+ radio.set_cca(Cca::CarrierSense);
+
+ radio
+ }
+
+ /// Changes the radio channel
+ pub fn set_channel(&mut self, channel: u8) {
+ let r = T::regs();
+ if channel < 11 || channel > 26 {
+ panic!("Bad 802.15.4 channel");
+ }
+ let frequency_offset = (channel - 10) * 5;
+ self.needs_enable = true;
+ r.frequency
+ .write(|w| unsafe { w.frequency().bits(frequency_offset).map().default() });
+ }
+
+ /// Changes the Clear Channel Assessment method
+ pub fn set_cca(&mut self, cca: Cca) {
+ let r = T::regs();
+ self.needs_enable = true;
+ match cca {
+ Cca::CarrierSense => r.ccactrl.write(|w| w.ccamode().carrier_mode()),
+ Cca::EnergyDetection { ed_threshold } => {
+ // "[ED] is enabled by first configuring the field CCAMODE=EdMode in CCACTRL
+ // and writing the CCAEDTHRES field to a chosen value."
+ r.ccactrl
+ .write(|w| unsafe { w.ccamode().ed_mode().ccaedthres().bits(ed_threshold) });
+ }
+ }
+ }
+
+ /// Changes the Start of Frame Delimiter
+ pub fn set_sfd(&mut self, sfd: u8) {
+ let r = T::regs();
+ r.sfd.write(|w| unsafe { w.sfd().bits(sfd) });
+ }
+
+ /// Clear interrupts
+ pub fn clear_all_interrupts(&mut self) {
+ let r = T::regs();
+ r.intenclr.write(|w| unsafe { w.bits(0xffff_ffff) });
+ }
+
+ /// Changes the radio transmission power
+ pub fn set_transmission_power(&mut self, power: i8) {
+ let r = T::regs();
+ self.needs_enable = true;
+
+ let tx_power: TxPower = match power {
+ 8 => TxPower::POS8D_BM,
+ 7 => TxPower::POS7D_BM,
+ 6 => TxPower::POS6D_BM,
+ 5 => TxPower::POS5D_BM,
+ 4 => TxPower::POS4D_BM,
+ 3 => TxPower::POS3D_BM,
+ 2 => TxPower::POS2D_BM,
+ 0 => TxPower::_0D_BM,
+ -4 => TxPower::NEG4D_BM,
+ -8 => TxPower::NEG8D_BM,
+ -12 => TxPower::NEG12D_BM,
+ -16 => TxPower::NEG16D_BM,
+ -20 => TxPower::NEG20D_BM,
+ -30 => TxPower::NEG30D_BM,
+ -40 => TxPower::NEG40D_BM,
+ _ => panic!("Invalid transmission power value"),
+ };
+
+ r.txpower.write(|w| w.txpower().variant(tx_power));
+ }
+
+ /// Waits until the radio state matches the given `state`
+ fn wait_for_radio_state(&self, state: RadioState) {
+ while self.state() != state {}
+ }
+
+ fn state(&self) -> RadioState {
+ let r = T::regs();
+ match r.state.read().state().variant() {
+ Some(state) => state,
+ None => unreachable!(),
+ }
+ }
+
+ fn trace_state(&self) {
+ trace_state(self.state());
+ }
+
+ /// Moves the radio from any state to the DISABLED state
+ fn disable(&mut self) {
+ let r = T::regs();
+ // See figure 110 in nRF52840-PS
+ loop {
+ match self.state() {
+ RadioState::DISABLED => return,
+
+ RadioState::RX_RU | RadioState::RX_IDLE | RadioState::TX_RU | RadioState::TX_IDLE => {
+ r.tasks_disable.write(|w| w.tasks_disable().set_bit());
+
+ self.wait_for_radio_state(RadioState::DISABLED);
+ return;
+ }
+
+ // ramping down
+ RadioState::RX_DISABLE | RadioState::TX_DISABLE => {
+ self.wait_for_radio_state(RadioState::DISABLED);
+ return;
+ }
+
+ // cancel ongoing transfer or ongoing CCA
+ RadioState::RX => {
+ r.tasks_ccastop.write(|w| w.tasks_ccastop().set_bit());
+ r.tasks_stop.write(|w| w.tasks_stop().set_bit());
+ self.wait_for_radio_state(RadioState::RX_IDLE);
+ }
+ RadioState::TX => {
+ r.tasks_stop.write(|w| w.tasks_stop().set_bit());
+ self.wait_for_radio_state(RadioState::TX_IDLE);
+ }
+ }
+ }
+ }
+
+ fn set_buffer(&mut self, buffer: &[u8]) {
+ let r = T::regs();
+ r.packetptr.write(|w| unsafe { w.bits(buffer.as_ptr() as u32) });
+ }
+
+ /// Moves the radio to the RXIDLE state
+ fn receive_prepare(&mut self) {
+ let state = self.state();
+
+ let disable = match state {
+ RadioState::DISABLED => false,
+ RadioState::RX_DISABLE => true,
+ RadioState::TX_DISABLE => true,
+ RadioState::RX_IDLE => self.needs_enable,
+ // NOTE to avoid errata 204 (see rev1 v1.4) we do TX_IDLE -> DISABLED -> RX_IDLE
+ RadioState::TX_IDLE => true,
+ _ => unreachable!(),
+ };
+ if disable {
+ trace!("Receive Setup");
+ self.trace_state();
+ self.disable();
+ }
+ self.needs_enable = false;
+ }
+
+ fn receive_start(&mut self, packet: &mut Packet) {
+ // NOTE we do NOT check the address of `packet` because the mutable reference ensures it's
+ // allocated in RAM
+ let r = T::regs();
+
+ // clear related events
+ r.events_framestart.reset();
+ r.events_ccabusy.reset();
+ r.events_phyend.reset();
+
+ self.receive_prepare();
+
+ // Configure shortcuts
+ //
+ // The radio goes through following states when receiving a 802.15.4 packet
+ //
+ // enable RX → ramp up RX → RX idle → Receive → end (PHYEND)
+ r.shorts.write(|w| w.rxready_start().enabled());
+
+ // set up RX buffer
+ self.set_buffer(packet.buffer.as_mut());
+
+ // start transfer
+ dma_start_fence();
+
+ match self.state() {
+ // Re-start receiver
+ RadioState::RX_IDLE => r.tasks_start.write(|w| w.tasks_start().set_bit()),
+ // Enable receiver
+ _ => r.tasks_rxen.write(|w| w.tasks_rxen().set_bit()),
+ }
+ }
+
+ fn receive_cancel() {
+ let r = T::regs();
+ r.shorts.reset();
+ if r.events_framestart.read().events_framestart().bit_is_set() {
+ // TODO: Is there a way to finish receiving this frame
+ trace!("EVENTS {}", Event::from_radio(r));
+ }
+ r.tasks_stop.write(|w| w.tasks_stop().set_bit());
+ loop {
+ match get_state(r) {
+ RadioState::DISABLED | RadioState::RX_IDLE => break,
+ _ => (),
+ }
+ }
+ // DMA transfer may have been in progress so synchronize with its memory operations
+ dma_end_fence();
+ }
+
+ /// Receives one radio packet and copies its contents into the given `packet` buffer
+ ///
+ /// This methods returns the `Ok` variant if the CRC included the packet was successfully
+ /// validated by the hardware; otherwise it returns the `Err` variant. In either case, `packet`
+ /// will be updated with the received packet's data
+ pub async fn receive(&mut self, packet: &mut Packet) -> Result<(), u16> {
+ let s = T::state();
+ let r = T::regs();
+
+ // Start the read
+ self.receive_start(packet);
+
+ let dropper = OnDrop::new(|| Self::receive_cancel());
+
+ self.clear_all_interrupts();
+ // wait until we have received something
+ core::future::poll_fn(|cx| {
+ s.event_waker.register(cx.waker());
+
+ if r.events_phyend.read().events_phyend().bit_is_set() {
+ r.events_phyend.reset();
+ trace!("RX done poll");
+ return Poll::Ready(());
+ } else {
+ r.intenset.write(|w| w.phyend().set());
+ };
+
+ Poll::Pending
+ })
+ .await;
+
+ dma_end_fence();
+ dropper.defuse();
+
+ let crc = r.rxcrc.read().rxcrc().bits() as u16;
+ if r.crcstatus.read().crcstatus().bit_is_set() {
+ Ok(())
+ } else {
+ Err(crc)
+ }
+ }
+
+ /// Tries to send the given `packet`
+ ///
+ /// This method performs Clear Channel Assessment (CCA) first and sends the `packet` only if the
+ /// channel is observed to be *clear* (no transmission is currently ongoing), otherwise no
+ /// packet is transmitted and the `Err` variant is returned
+ ///
+ /// NOTE this method will *not* modify the `packet` argument. The mutable reference is used to
+ /// ensure the `packet` buffer is allocated in RAM, which is required by the RADIO peripheral
+ // NOTE we do NOT check the address of `packet` because the mutable reference ensures it's
+ // allocated in RAM
+ pub async fn try_send(&mut self, packet: &mut Packet) -> Result<(), Error> {
+ let s = T::state();
+ let r = T::regs();
+
+ // clear related events
+ r.events_framestart.reset();
+ r.events_ccabusy.reset();
+ r.events_phyend.reset();
+
+ // enable radio to perform cca
+ self.receive_prepare();
+
+ /// transmit result
+ #[derive(Debug, Clone, Copy, PartialEq, Eq)]
+ #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+ pub enum TransmitResult {
+ /// Success
+ Success,
+ /// Clear channel assessment reported channel in use
+ ChannelInUse,
+ }
+
+ // Configure shortcuts
+ //
+ // The radio goes through following states when sending a 802.15.4 packet
+ //
+ // enable RX → ramp up RX → clear channel assessment (CCA) → CCA result
+ // CCA idle → enable TX → start TX → TX → end (PHYEND) → disabled
+ //
+ // CCA might end up in the event CCABUSY in which there will be no transmission
+ r.shorts.write(|w| {
+ w.rxready_ccastart()
+ .enabled()
+ .ccaidle_txen()
+ .enabled()
+ .txready_start()
+ .enabled()
+ .ccabusy_disable()
+ .enabled()
+ .phyend_disable()
+ .enabled()
+ });
+
+ // Set transmission buffer
+ self.set_buffer(packet.buffer.as_mut());
+
+ // the DMA transfer will start at some point after the following write operation so
+ // we place the compiler fence here
+ dma_start_fence();
+ // start CCA. In case the channel is clear, the data at packetptr will be sent automatically
+
+ match self.state() {
+ // Re-start receiver
+ RadioState::RX_IDLE => r.tasks_ccastart.write(|w| w.tasks_ccastart().set_bit()),
+ // Enable receiver
+ _ => r.tasks_rxen.write(|w| w.tasks_rxen().set_bit()),
+ }
+
+ self.clear_all_interrupts();
+ let result = core::future::poll_fn(|cx| {
+ s.event_waker.register(cx.waker());
+
+ if r.events_phyend.read().events_phyend().bit_is_set() {
+ r.events_phyend.reset();
+ r.events_ccabusy.reset();
+ trace!("TX done poll");
+ return Poll::Ready(TransmitResult::Success);
+ } else if r.events_ccabusy.read().events_ccabusy().bit_is_set() {
+ r.events_ccabusy.reset();
+ trace!("TX no CCA");
+ return Poll::Ready(TransmitResult::ChannelInUse);
+ }
+
+ r.intenset.write(|w| w.phyend().set().ccabusy().set());
+
+ Poll::Pending
+ })
+ .await;
+
+ match result {
+ TransmitResult::Success => Ok(()),
+ TransmitResult::ChannelInUse => Err(Error::ChannelInUse),
+ }
+ }
+}
+
+/// An IEEE 802.15.4 packet
+///
+/// This `Packet` is a PHY layer packet. It's made up of the physical header (PHR) and the PSDU
+/// (PHY service data unit). The PSDU of this `Packet` will always include the MAC level CRC, AKA
+/// the FCS (Frame Control Sequence) -- the CRC is fully computed in hardware and automatically
+/// appended on transmission and verified on reception.
+///
+/// The API lets users modify the usable part (not the CRC) of the PSDU via the `deref` and
+/// `copy_from_slice` methods. These methods will automatically update the PHR.
+///
+/// See figure 119 in the Product Specification of the nRF52840 for more details
+pub struct Packet {
+ buffer: [u8; Self::SIZE],
+}
+
+// See figure 124 in nRF52840-PS
+impl Packet {
+ // for indexing purposes
+ const PHY_HDR: usize = 0;
+ const DATA: core::ops::RangeFrom<usize> = 1..;
+
+ /// Maximum amount of usable payload (CRC excluded) a single packet can contain, in bytes
+ pub const CAPACITY: u8 = 125;
+ const CRC: u8 = 2; // size of the CRC, which is *never* copied to / from RAM
+ const MAX_PSDU_LEN: u8 = Self::CAPACITY + Self::CRC;
+ const SIZE: usize = 1 /* PHR */ + Self::MAX_PSDU_LEN as usize;
+
+ /// Returns an empty packet (length = 0)
+ pub fn new() -> Self {
+ let mut packet = Self {
+ buffer: [0; Self::SIZE],
+ };
+ packet.set_len(0);
+ packet
+ }
+
+ /// Fills the packet payload with given `src` data
+ ///
+ /// # Panics
+ ///
+ /// This function panics if `src` is larger than `Self::CAPACITY`
+ pub fn copy_from_slice(&mut self, src: &[u8]) {
+ assert!(src.len() <= Self::CAPACITY as usize);
+ let len = src.len() as u8;
+ self.buffer[Self::DATA][..len as usize].copy_from_slice(&src[..len.into()]);
+ self.set_len(len);
+ }
+
+ /// Returns the size of this packet's payload
+ pub fn len(&self) -> u8 {
+ self.buffer[Self::PHY_HDR] - Self::CRC
+ }
+
+ /// Changes the size of the packet's payload
+ ///
+ /// # Panics
+ ///
+ /// This function panics if `len` is larger than `Self::CAPACITY`
+ pub fn set_len(&mut self, len: u8) {
+ assert!(len <= Self::CAPACITY);
+ self.buffer[Self::PHY_HDR] = len + Self::CRC;
+ }
+
+ /// Returns the LQI (Link Quality Indicator) of the received packet
+ ///
+ /// Note that the LQI is stored in the `Packet`'s internal buffer by the hardware so the value
+ /// returned by this method is only valid after a `Radio.recv` operation. Operations that
+ /// modify the `Packet`, like `copy_from_slice` or `set_len`+`deref_mut`, will overwrite the
+ /// stored LQI value.
+ ///
+ /// Also note that the hardware will *not* compute a LQI for packets smaller than 3 bytes so
+ /// this method will return an invalid value for those packets.
+ pub fn lqi(&self) -> u8 {
+ self.buffer[1 /* PHY_HDR */ + self.len() as usize /* data */]
+ }
+}
+
+impl core::ops::Deref for Packet {
+ type Target = [u8];
+
+ fn deref(&self) -> &[u8] {
+ &self.buffer[Self::DATA][..self.len() as usize]
+ }
+}
+
+impl core::ops::DerefMut for Packet {
+ fn deref_mut(&mut self) -> &mut [u8] {
+ let len = self.len();
+ &mut self.buffer[Self::DATA][..len as usize]
+ }
+}
+
+/// NOTE must be followed by a volatile write operation
+fn dma_start_fence() {
+ compiler_fence(Ordering::Release);
+}
+
+/// NOTE must be preceded by a volatile read operation
+fn dma_end_fence() {
+ compiler_fence(Ordering::Acquire);
+}
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 03f967f87..430078e8a 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -7,11 +7,32 @@
/// Bluetooth Low Energy Radio driver.
pub mod ble;
+mod event;
+#[cfg(any(feature = "nrf52840", feature = "nrf52833", feature = "_nrf5340-net"))]
+/// IEEE 802.15.4
+pub mod ieee802154;
+
+pub use event::Event;
use core::marker::PhantomData;
use crate::{interrupt, pac, Peripheral};
+/// RADIO error.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[non_exhaustive]
+pub enum Error {
+ /// Buffer was too long.
+ BufferTooLong,
+ /// Buffer was too short.
+ BufferTooShort,
+ /// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
+ BufferNotInRAM,
+ /// Clear channel assessment reported channel in use
+ ChannelInUse,
+}
+
/// Interrupt handler
pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
@@ -21,11 +42,10 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
-
- if r.events_end.read().events_end().bit_is_set() {
- s.end_waker.wake();
- r.intenclr.write(|w| w.end().clear());
- }
+ let events = Event::from_radio_masked(r);
+ // clear active interrupts
+ r.intenclr.write(|w| w.bits(events.bits()));
+ s.event_waker.wake();
}
}
@@ -34,12 +54,12 @@ pub(crate) mod sealed {
pub struct State {
/// end packet transmission or reception
- pub end_waker: AtomicWaker,
+ pub event_waker: AtomicWaker,
}
impl State {
pub const fn new() -> Self {
Self {
- end_waker: AtomicWaker::new(),
+ event_waker: AtomicWaker::new(),
}
}
}
From 35febae570ef6b89eb52948ee13684754b23da4a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Thu, 29 Feb 2024 01:31:07 +0100
Subject: [PATCH 350/392] Fixed missing nrf52840 in Event
---
embassy-nrf/src/radio/event.rs | 29 ++++++++++++++++++++++++++---
embassy-nrf/src/radio/ieee802154.rs | 2 +-
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/embassy-nrf/src/radio/event.rs b/embassy-nrf/src/radio/event.rs
index 11056b4d8..8fb0958d5 100644
--- a/embassy-nrf/src/radio/event.rs
+++ b/embassy-nrf/src/radio/event.rs
@@ -97,6 +97,7 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_framestart.read().events_framestart().bit_is_set() {
@@ -106,6 +107,7 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_edend.read().events_edend().bit_is_set() {
@@ -115,20 +117,36 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_edstopped.read().events_edstopped().bit_is_set() {
value |= Self::ED_STOPPED;
}
- #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
+ #[cfg(any(
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "nrf52840",
+ feature = "_nrf5340-net"
+ ))]
if radio.events_ccaidle.read().events_ccaidle().bit_is_set() {
value |= Self::CCA_IDLE;
}
- #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
+ #[cfg(any(
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "nrf52840",
+ feature = "_nrf5340-net"
+ ))]
if radio.events_ccabusy.read().events_ccabusy().bit_is_set() {
value |= Self::CCA_BUSY;
}
- #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
+ #[cfg(any(
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "nrf52840",
+ feature = "_nrf5340-net"
+ ))]
if radio.events_ccastopped.read().events_ccastopped().bit_is_set() {
value |= Self::CCA_STOPPED;
}
@@ -136,6 +154,7 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_rateboost.read().events_rateboost().bit_is_set() {
@@ -146,6 +165,7 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_txready.read().events_txready().bit_is_set() {
@@ -156,6 +176,7 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_rxready.read().events_rxready().bit_is_set() {
@@ -165,6 +186,7 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_mhrmatch.read().events_mhrmatch().bit_is_set() {
@@ -179,6 +201,7 @@ impl Event {
feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
+ feature = "nrf52840",
feature = "_nrf5340-net"
))]
if radio.events_phyend.read().events_phyend().bit_is_set() {
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
index 4d7949cb3..adc6f8aaa 100644
--- a/embassy-nrf/src/radio/ieee802154.rs
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -164,7 +164,7 @@ impl<'d, T: Instance> Radio<'d, T> {
}
}
- /// Changes the Start of Frame Delimiter
+ /// Changes the Start of Frame Delimiter (SFD)
pub fn set_sfd(&mut self, sfd: u8) {
let r = T::regs();
r.sfd.write(|w| unsafe { w.sfd().bits(sfd) });
From f0753998bc9379bdb19ef4fcddf96ff19487a52d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Thu, 29 Feb 2024 02:02:01 +0100
Subject: [PATCH 351/392] Clear all interrupts
---
embassy-nrf/src/radio/mod.rs | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 430078e8a..914e6c438 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -42,9 +42,8 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
- let events = Event::from_radio_masked(r);
- // clear active interrupts
- r.intenclr.write(|w| w.bits(events.bits()));
+ // clear all interrupts
+ r.intenclr.write(|w| w.bits(0xffff_ffff));
s.event_waker.wake();
}
}
From 8eac5d07f65e642ca4ad763ffe90bad97803089c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Thu, 29 Feb 2024 09:50:28 +0100
Subject: [PATCH 352/392] Remove Event, which was mostly used for debugging
---
embassy-nrf/src/radio/event.rs | 333 ----------------------------
embassy-nrf/src/radio/ieee802154.rs | 3 +-
embassy-nrf/src/radio/mod.rs | 3 -
3 files changed, 1 insertion(+), 338 deletions(-)
delete mode 100644 embassy-nrf/src/radio/event.rs
diff --git a/embassy-nrf/src/radio/event.rs b/embassy-nrf/src/radio/event.rs
deleted file mode 100644
index 8fb0958d5..000000000
--- a/embassy-nrf/src/radio/event.rs
+++ /dev/null
@@ -1,333 +0,0 @@
-use crate::pac;
-use bitflags;
-
-bitflags::bitflags! {
- /// Event as bit flags
- pub struct Event : u32 {
- /// Radio ready
- const READY = 1u32 << 0;
- /// Address operation done
- const ADDRESS = 1u32 << 1;
- /// Payload operation done
- const PAYLOAD = 1u32 << 2;
- /// Packet operation done
- const END = 1u32 << 3;
- /// Radio has been disabled
- const DISABLED = 1u32 << 4;
- /// Device address match in last received packet
- const DEV_MATCH = 1u32 << 5;
- /// No device address match in last received packet
- const DEV_MISS = 1u32 << 6;
- /// RSSI sampling complete
- const RSSI_END = 1u32 << 7;
- /// Bit counter reached target
- const BC_MATCH = 1u32 << 10;
- /// CRC ok in last received packet
- const CRC_OK = 1u32 << 12;
- /// CRC error in last received packet
- const CRC_ERROR = 1u32 << 13;
- /// IEEE 802.15.4 length field received
- const FRAME_START = 1u32 << 14;
- /// Sampling of energy detect complete
- const ED_END = 1u32 << 15;
- /// Sampling of energy detect stopped
- const ED_STOPPED = 1u32 << 16;
- /// Wireless medium in idle, ready to sent
- const CCA_IDLE = 1u32 << 17;
- /// Wireless medium busy, do not send
- const CCA_BUSY = 1u32 << 18;
- /// Clear channel assessment stopped
- const CCA_STOPPED = 1u32 << 19;
- /// BLE LR rate boost received
- const RATE_BOOST = 1u32 << 20;
- /// Radio has ramped up transmitter
- const TX_READY = 1u32 << 21;
- /// Radio has ramped up receiver
- const RX_READY = 1u32 << 22;
- /// MAC header match found
- const MHR_MATCH = 1u32 << 23;
- /// Preamble received, possible false triggering
- const SYNC = 1u32 << 26;
- /// Last bit sent / received
- const PHY_END = 1u32 << 27;
- /// Continuous tone extension is present
- const CTE_PRESENT = 1u32 << 28;
- }
-}
-
-impl Event {
- /// Read events from radio
- #[cfg(not(feature = "nrf52832"))]
- pub fn from_radio(radio: &pac::radio::RegisterBlock) -> Self {
- let mut value = Self::empty();
- if radio.events_ready.read().events_ready().bit_is_set() {
- value |= Self::READY;
- }
- if radio.events_address.read().events_address().bit_is_set() {
- value |= Self::ADDRESS;
- }
- if radio.events_payload.read().events_payload().bit_is_set() {
- value |= Self::PAYLOAD;
- }
- if radio.events_end.read().events_end().bit_is_set() {
- value |= Self::END;
- }
- if radio.events_disabled.read().events_disabled().bit_is_set() {
- value |= Self::DISABLED;
- }
- if radio.events_devmatch.read().events_devmatch().bit_is_set() {
- value |= Self::DEV_MATCH;
- }
- if radio.events_devmiss.read().events_devmiss().bit_is_set() {
- value |= Self::DEV_MISS;
- }
- if radio.events_rssiend.read().events_rssiend().bit_is_set() {
- value |= Self::RSSI_END;
- }
- if radio.events_bcmatch.read().events_bcmatch().bit_is_set() {
- value |= Self::BC_MATCH;
- }
- if radio.events_crcok.read().events_crcok().bit_is_set() {
- value |= Self::CRC_OK;
- }
- if radio.events_crcerror.read().events_crcerror().bit_is_set() {
- value |= Self::CRC_ERROR;
- }
- #[cfg(any(
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_framestart.read().events_framestart().bit_is_set() {
- value |= Self::FRAME_START;
- }
- #[cfg(any(
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_edend.read().events_edend().bit_is_set() {
- value |= Self::ED_END;
- }
- #[cfg(any(
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_edstopped.read().events_edstopped().bit_is_set() {
- value |= Self::ED_STOPPED;
- }
- #[cfg(any(
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_ccaidle.read().events_ccaidle().bit_is_set() {
- value |= Self::CCA_IDLE;
- }
- #[cfg(any(
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_ccabusy.read().events_ccabusy().bit_is_set() {
- value |= Self::CCA_BUSY;
- }
- #[cfg(any(
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_ccastopped.read().events_ccastopped().bit_is_set() {
- value |= Self::CCA_STOPPED;
- }
- #[cfg(any(
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_rateboost.read().events_rateboost().bit_is_set() {
- value |= Self::RATE_BOOST;
- }
- #[cfg(any(
- feature = "nrf52805",
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_txready.read().events_txready().bit_is_set() {
- value |= Self::TX_READY;
- }
- #[cfg(any(
- feature = "nrf52805",
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_rxready.read().events_rxready().bit_is_set() {
- value |= Self::RX_READY;
- }
- #[cfg(any(
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_mhrmatch.read().events_mhrmatch().bit_is_set() {
- value |= Self::MHR_MATCH;
- }
- #[cfg(any(feature = "nrf52820", feature = "nrf52833", feature = "_nrf5340-net"))]
- if radio.events_sync.read().events_sync().bit_is_set() {
- value |= Self::SYNC;
- }
- #[cfg(any(
- feature = "nrf52805",
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "nrf52840",
- feature = "_nrf5340-net"
- ))]
- if radio.events_phyend.read().events_phyend().bit_is_set() {
- value |= Self::PHY_END;
- }
- #[cfg(any(
- feature = "nrf52811",
- feature = "nrf52820",
- feature = "nrf52833",
- feature = "_nrf5340-net"
- ))]
- if radio.events_ctepresent.read().events_ctepresent().bit_is_set() {
- value |= Self::CTE_PRESENT;
- }
- value
- }
- // The nRF52832 SVD probably is a bit broken
- /// Read events from radio
- #[cfg(feature = "nrf52832")]
- pub fn from_radio(radio: &pac::radio::RegisterBlock) -> Self {
- let mut value = Self::empty();
- if radio.events_ready.read().bits() == 1 {
- value |= Self::READY;
- }
- if radio.events_address.read().bits() == 1 {
- value |= Self::ADDRESS;
- }
- if radio.events_payload.read().bits() == 1 {
- value |= Self::PAYLOAD;
- }
- if radio.events_end.read().bits() == 1 {
- value |= Self::END;
- }
- if radio.events_disabled.read().bits() == 1 {
- value |= Self::DISABLED;
- }
- if radio.events_devmatch.read().bits() == 1 {
- value |= Self::DEV_MATCH;
- }
- if radio.events_devmiss.read().bits() == 1 {
- value |= Self::DEV_MISS;
- }
- if radio.events_rssiend.read().bits() == 1 {
- value |= Self::RSSI_END;
- }
- if radio.events_bcmatch.read().bits() == 1 {
- value |= Self::BC_MATCH;
- }
- if radio.events_crcok.read().bits() == 1 {
- value |= Self::CRC_OK;
- }
- if radio.events_crcerror.read().bits() == 1 {
- value |= Self::CRC_ERROR;
- }
- value
- }
-
- /// Read events from radio, mask with set interrupts
- pub fn from_radio_masked(radio: &pac::radio::RegisterBlock) -> Self {
- Self::from_radio(radio) & Self::from_bits_truncate(radio.intenset.read().bits())
- }
-}
-
-#[cfg(feature = "defmt")]
-impl defmt::Format for Event {
- fn format(&self, fmt: defmt::Formatter) {
- defmt::write!(
- fmt,
- "{} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {}",
- if self.contains(Self::READY) { "RD" } else { "__" },
- if self.contains(Self::ADDRESS) { "AD" } else { "__" },
- if self.contains(Self::PAYLOAD) { "PL" } else { "__" },
- if self.contains(Self::END) { " E" } else { "__" },
- if self.contains(Self::DISABLED) { "DI" } else { "__" },
- if self.contains(Self::DEV_MATCH) { "D+" } else { "__" },
- if self.contains(Self::DEV_MISS) { "D-" } else { "__" },
- if self.contains(Self::RSSI_END) { "RE" } else { "__" },
- if self.contains(Self::BC_MATCH) { "CM" } else { "__" },
- if self.contains(Self::CRC_OK) { "CO" } else { "__" },
- if self.contains(Self::CRC_ERROR) { "CE" } else { "__" },
- if self.contains(Self::FRAME_START) { "FS" } else { "__" },
- if self.contains(Self::ED_END) { "EE" } else { "__" },
- if self.contains(Self::ED_STOPPED) { "ES" } else { "__" },
- if self.contains(Self::CCA_IDLE) { "CI" } else { "__" },
- if self.contains(Self::CCA_BUSY) { "CB" } else { "__" },
- if self.contains(Self::CCA_STOPPED) { "CS" } else { "__" },
- if self.contains(Self::RATE_BOOST) { "RB" } else { "__" },
- if self.contains(Self::TX_READY) { "TX" } else { "__" },
- if self.contains(Self::RX_READY) { "RX" } else { "__" },
- if self.contains(Self::MHR_MATCH) { "MM" } else { "__" },
- if self.contains(Self::SYNC) { "SY" } else { "__" },
- if self.contains(Self::PHY_END) { "PE" } else { "__" },
- if self.contains(Self::CTE_PRESENT) { "CP" } else { "__" },
- )
- }
-}
-
-impl core::fmt::Display for Event {
- fn fmt(&self, fmt: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
- write!(
- fmt,
- "{} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {} {}",
- if self.contains(Self::READY) { "RD" } else { "__" },
- if self.contains(Self::ADDRESS) { "AD" } else { "__" },
- if self.contains(Self::PAYLOAD) { "PL" } else { "__" },
- if self.contains(Self::END) { " E" } else { "__" },
- if self.contains(Self::DISABLED) { "DI" } else { "__" },
- if self.contains(Self::DEV_MATCH) { "D+" } else { "__" },
- if self.contains(Self::DEV_MISS) { "D-" } else { "__" },
- if self.contains(Self::RSSI_END) { "RE" } else { "__" },
- if self.contains(Self::BC_MATCH) { "CM" } else { "__" },
- if self.contains(Self::CRC_OK) { "CO" } else { "__" },
- if self.contains(Self::CRC_ERROR) { "CE" } else { "__" },
- if self.contains(Self::FRAME_START) { "FS" } else { "__" },
- if self.contains(Self::ED_END) { "EE" } else { "__" },
- if self.contains(Self::ED_STOPPED) { "ES" } else { "__" },
- if self.contains(Self::CCA_IDLE) { "CI" } else { "__" },
- if self.contains(Self::CCA_BUSY) { "CB" } else { "__" },
- if self.contains(Self::CCA_STOPPED) { "CS" } else { "__" },
- if self.contains(Self::RATE_BOOST) { "RB" } else { "__" },
- if self.contains(Self::TX_READY) { "TX" } else { "__" },
- if self.contains(Self::RX_READY) { "RX" } else { "__" },
- if self.contains(Self::MHR_MATCH) { "MM" } else { "__" },
- if self.contains(Self::SYNC) { "SY" } else { "__" },
- if self.contains(Self::PHY_END) { "PE" } else { "__" },
- if self.contains(Self::CTE_PRESENT) { "CP" } else { "__" },
- )
- }
-}
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
index adc6f8aaa..32951421b 100644
--- a/embassy-nrf/src/radio/ieee802154.rs
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -3,7 +3,7 @@
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
-use super::{Error, Event, Instance, InterruptHandler};
+use super::{Error, Instance, InterruptHandler};
use crate::{
interrupt::{self, typelevel::Interrupt},
pac, Peripheral,
@@ -319,7 +319,6 @@ impl<'d, T: Instance> Radio<'d, T> {
r.shorts.reset();
if r.events_framestart.read().events_framestart().bit_is_set() {
// TODO: Is there a way to finish receiving this frame
- trace!("EVENTS {}", Event::from_radio(r));
}
r.tasks_stop.write(|w| w.tasks_stop().set_bit());
loop {
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 914e6c438..9b3a6cf49 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -7,13 +7,10 @@
/// Bluetooth Low Energy Radio driver.
pub mod ble;
-mod event;
#[cfg(any(feature = "nrf52840", feature = "nrf52833", feature = "_nrf5340-net"))]
/// IEEE 802.15.4
pub mod ieee802154;
-pub use event::Event;
-
use core::marker::PhantomData;
use crate::{interrupt, pac, Peripheral};
From e954d1716a229bae94cd4739d1349a487bdaa8ae Mon Sep 17 00:00:00 2001
From: Andreas Schmidt <ndrscodes@gmail.com>
Date: Thu, 29 Feb 2024 20:27:35 +0100
Subject: [PATCH 353/392] docs: update basic example references in
basic_application.adoc
---
docs/modules/ROOT/pages/basic_application.adoc | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/docs/modules/ROOT/pages/basic_application.adoc b/docs/modules/ROOT/pages/basic_application.adoc
index 95792d5a0..02b8981c9 100644
--- a/docs/modules/ROOT/pages/basic_application.adoc
+++ b/docs/modules/ROOT/pages/basic_application.adoc
@@ -17,15 +17,6 @@ The first thing you’ll notice are two attributes at the top of the file. These
include::example$basic/src/main.rs[lines="1..2"]
----
-=== Rust Nightly
-
-The next declaration is a Rust Unstable feature, which means that Embassy requires Rust Nightly:
-
-[source,rust]
-----
-include::example$basic/src/main.rs[lines="3"]
-----
-
=== Dealing with errors
Then, what follows are some declarations on how to deal with panics and faults. During development, a good practice is to rely on `defmt-rtt` and `panic-probe` to print diagnostics to the terminal:
@@ -41,7 +32,7 @@ After a bit of import declaration, the tasks run by the application should be de
[source,rust]
----
-include::example$basic/src/main.rs[lines="12..20"]
+include::example$basic/src/main.rs[lines="10..18"]
----
An embassy task must be declared `async`, and may NOT take generic arguments. In this case, we are handed the LED that should be blinked and the interval of the blinking.
@@ -56,7 +47,7 @@ We then initialize the HAL with a default config, which gives us a `Peripherals`
[source,rust]
----
-include::example$basic/src/main.rs[lines="22..-1"]
+include::example$basic/src/main.rs[lines="20..-1"]
----
What happens when the `blinker` task has been spawned and main returns? Well, the main entry point is actually just like any other task, except that you can only have one and it takes some specific type arguments. The magic lies within the `#[embassy_executor::main]` macro. The macro does the following:
From c9cca3c007eb4b85c559f74655c6cb018d9e28f1 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Thu, 29 Feb 2024 19:09:44 -0500
Subject: [PATCH 354/392] Fix H7 CRYP operation.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/cryp/mod.rs | 159 +++++++++++++++++++++-------------
tests/stm32/Cargo.toml | 4 +-
3 files changed, 103 insertions(+), 64 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 08ccd35ae..460184920 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-4a0bcec33362449fb733c066936d25cbabab396a" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7462d805ef05892531a83cd9ad60c9cba568d54" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-4a0bcec33362449fb733c066936d25cbabab396a", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7462d805ef05892531a83cd9ad60c9cba568d54", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index bb64fa423..8f259520a 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1,5 +1,5 @@
//! Crypto Accelerator (CRYP)
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
use core::cmp::min;
use core::marker::PhantomData;
@@ -35,7 +35,7 @@ pub trait Cipher<'c> {
fn init_phase(&self, _p: &pac::cryp::Cryp) {}
/// Called prior to processing the last data block for cipher-specific operations.
- fn pre_final_block(&self, _p: &pac::cryp::Cryp, _dir: Direction) -> [u32; 4] {
+ fn pre_final_block(&self, _p: &pac::cryp::Cryp, _dir: Direction, _padding_len: usize) -> [u32; 4] {
return [0; 4];
}
@@ -98,7 +98,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesEcb<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(0));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(0));
p.cr().modify(|w| w.set_algomode3(false));
@@ -140,7 +140,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesCbc<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(1));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(1));
p.cr().modify(|w| w.set_algomode3(false));
@@ -182,7 +182,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesEcb<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(2));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(2));
p.cr().modify(|w| w.set_algomode3(false));
@@ -223,7 +223,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesCbc<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(3));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(3));
p.cr().modify(|w| w.set_algomode3(false));
@@ -264,7 +264,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(7));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(7));
p.cr().modify(|w| w.set_algomode3(false));
@@ -278,7 +278,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(2));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(2));
p.cr().modify(|w| w.set_algomode3(false));
@@ -321,7 +321,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCbc<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(7));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(7));
p.cr().modify(|w| w.set_algomode3(false));
@@ -335,7 +335,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCbc<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(5));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(5));
p.cr().modify(|w| w.set_algomode3(false));
@@ -377,7 +377,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCtr<'c, KEY_SIZE> {
{
p.cr().modify(|w| w.set_algomode(6));
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
p.cr().modify(|w| w.set_algomode0(6));
p.cr().modify(|w| w.set_algomode3(false));
@@ -390,14 +390,14 @@ impl<'c> CipherSized for AesCtr<'c, { 192 / 8 }> {}
impl<'c> CipherSized for AesCtr<'c, { 256 / 8 }> {}
impl<'c, const KEY_SIZE: usize> IVSized for AesCtr<'c, KEY_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
///AES-GCM Cipher Mode
pub struct AesGcm<'c, const KEY_SIZE: usize> {
iv: [u8; 16],
key: &'c [u8; KEY_SIZE],
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> AesGcm<'c, KEY_SIZE> {
/// Constucts a new AES-GCM cipher for a cryptographic operation.
pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
@@ -408,7 +408,7 @@ impl<'c, const KEY_SIZE: usize> AesGcm<'c, KEY_SIZE> {
}
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
@@ -431,7 +431,8 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
while p.cr().read().crypen() {}
}
- fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction) -> [u32; 4] {
+ #[cfg(cryp_v2)]
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction, _padding_len: usize) -> [u32; 4] {
//Handle special GCM partial block process.
if dir == Direction::Encrypt {
p.cr().modify(|w| w.set_crypen(false));
@@ -444,6 +445,14 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
[0; 4]
}
+ #[cfg(cryp_v3)]
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, _dir: Direction, padding_len: usize) -> [u32; 4] {
+ //Handle special GCM partial block process.
+ p.cr().modify(|w| w.set_npblb(padding_len as u8));
+ [0; 4]
+ }
+
+ #[cfg(cryp_v2)]
fn post_final_block(
&self,
p: &pac::cryp::Cryp,
@@ -477,25 +486,25 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
}
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c> CipherSized for AesGcm<'c, { 128 / 8 }> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c> CipherSized for AesGcm<'c, { 192 / 8 }> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c> CipherSized for AesGcm<'c, { 256 / 8 }> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGcm<'c, KEY_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> IVSized for AesGcm<'c, KEY_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
/// AES-GMAC Cipher Mode
pub struct AesGmac<'c, const KEY_SIZE: usize> {
iv: [u8; 16],
key: &'c [u8; KEY_SIZE],
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> AesGmac<'c, KEY_SIZE> {
/// Constructs a new AES-GMAC cipher for a cryptographic operation.
pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
@@ -506,7 +515,7 @@ impl<'c, const KEY_SIZE: usize> AesGmac<'c, KEY_SIZE> {
}
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
@@ -529,7 +538,8 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
while p.cr().read().crypen() {}
}
- fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction) -> [u32; 4] {
+ #[cfg(cryp_v2)]
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction, _padding_len: usize) -> [u32; 4] {
//Handle special GCM partial block process.
if dir == Direction::Encrypt {
p.cr().modify(|w| w.set_crypen(false));
@@ -542,6 +552,14 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
[0; 4]
}
+ #[cfg(cryp_v3)]
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, _dir: Direction, padding_len: usize) -> [u32; 4] {
+ //Handle special GCM partial block process.
+ p.cr().modify(|w| w.set_npblb(padding_len as u8));
+ [0; 4]
+ }
+
+ #[cfg(cryp_v2)]
fn post_final_block(
&self,
p: &pac::cryp::Cryp,
@@ -575,18 +593,18 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
}
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c> CipherSized for AesGmac<'c, { 128 / 8 }> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c> CipherSized for AesGmac<'c, { 192 / 8 }> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c> CipherSized for AesGmac<'c, { 256 / 8 }> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGmac<'c, KEY_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize> IVSized for AesGmac<'c, KEY_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
/// AES-CCM Cipher Mode
pub struct AesCcm<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> {
key: &'c [u8; KEY_SIZE],
@@ -596,7 +614,7 @@ pub struct AesCcm<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZ
ctr: [u8; 16],
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE> {
/// Constructs a new AES-CCM cipher for a cryptographic operation.
pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; IV_SIZE], aad_len: usize, payload_len: usize) -> Self {
@@ -660,7 +678,7 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Aes
}
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cipher<'c>
for AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE>
{
@@ -699,7 +717,8 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
return &self.aad_header[0..self.aad_header_len];
}
- fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction) -> [u32; 4] {
+ #[cfg(cryp_v2)]
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, dir: Direction, _padding_len: usize) -> [u32; 4] {
//Handle special CCM partial block process.
let mut temp1 = [0; 4];
if dir == Direction::Decrypt {
@@ -717,6 +736,14 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
return temp1;
}
+ #[cfg(cryp_v3)]
+ fn pre_final_block(&self, p: &pac::cryp::Cryp, _dir: Direction, padding_len: usize) -> [u32; 4] {
+ //Handle special GCM partial block process.
+ p.cr().modify(|w| w.set_npblb(padding_len as u8));
+ [0; 4]
+ }
+
+ #[cfg(cryp_v2)]
fn post_final_block(
&self,
p: &pac::cryp::Cryp,
@@ -753,39 +780,39 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
}
}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 128 / 8 }, TAG_SIZE, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 192 / 8 }, TAG_SIZE, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 256 / 8 }, TAG_SIZE, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<4> for AesCcm<'c, KEY_SIZE, 4, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<6> for AesCcm<'c, KEY_SIZE, 6, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<8> for AesCcm<'c, KEY_SIZE, 8, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<10> for AesCcm<'c, KEY_SIZE, 10, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<12> for AesCcm<'c, KEY_SIZE, 12, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<14> for AesCcm<'c, KEY_SIZE, 14, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<16> for AesCcm<'c, KEY_SIZE, 16, IV_SIZE> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 7> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 8> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 9> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 10> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 11> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 12> {}
-#[cfg(cryp_v2)]
+#[cfg(any(cryp_v2, cryp_v3))]
impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 13> {}
#[allow(dead_code)]
@@ -909,7 +936,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
ctx
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
/// Controls the header phase of cipher processing.
/// This function is only valid for GCM, CCM, and GMAC modes.
/// It only needs to be called if using one of these modes and there is associated data.
@@ -1066,7 +1093,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
if !ctx.aad_complete && ctx.header_len > 0 {
panic!("Additional associated data must be processed first!");
} else if !ctx.aad_complete {
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
{
ctx.aad_complete = true;
T::regs().cr().modify(|w| w.set_crypen(false));
@@ -1121,7 +1148,8 @@ impl<'d, T: Instance> Cryp<'d, T> {
// Handle the final block, which is incomplete.
if last_block_remainder > 0 {
- let temp1 = ctx.cipher.pre_final_block(&T::regs(), ctx.dir);
+ let padding_len = C::BLOCK_SIZE - last_block_remainder;
+ let temp1 = ctx.cipher.pre_final_block(&T::regs(), ctx.dir, padding_len);
let mut intermediate_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
@@ -1162,7 +1190,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
self.store_context(ctx);
}
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
/// This function only needs to be called for GCM, CCM, and GMAC modes to
/// generate an authentication tag.
pub fn finish_blocking<
@@ -1184,10 +1212,21 @@ impl<'d, T: Instance> Cryp<'d, T> {
let payloadlen1: u32 = ((ctx.payload_len * 8) >> 32) as u32;
let payloadlen2: u32 = (ctx.payload_len * 8) as u32;
- T::regs().din().write_value(headerlen1.swap_bytes());
- T::regs().din().write_value(headerlen2.swap_bytes());
- T::regs().din().write_value(payloadlen1.swap_bytes());
- T::regs().din().write_value(payloadlen2.swap_bytes());
+ #[cfg(cryp_v2)]
+ {
+ T::regs().din().write_value(headerlen1.swap_bytes());
+ T::regs().din().write_value(headerlen2.swap_bytes());
+ T::regs().din().write_value(payloadlen1.swap_bytes());
+ T::regs().din().write_value(payloadlen2.swap_bytes());
+ }
+
+ #[cfg(cryp_v3)]
+ {
+ T::regs().din().write_value(headerlen1);
+ T::regs().din().write_value(headerlen2);
+ T::regs().din().write_value(payloadlen1);
+ T::regs().din().write_value(payloadlen2);
+ }
while !T::regs().sr().read().ofne() {}
@@ -1257,7 +1296,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
ctx.iv[2] = T::regs().init(1).ivlr().read();
ctx.iv[3] = T::regs().init(1).ivrr().read();
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
for i in 0..8 {
ctx.csgcmccm[i] = T::regs().csgcmccmr(i).read();
ctx.csgcm[i] = T::regs().csgcmr(i).read();
@@ -1272,7 +1311,7 @@ impl<'d, T: Instance> Cryp<'d, T> {
T::regs().init(1).ivlr().write_value(ctx.iv[2]);
T::regs().init(1).ivrr().write_value(ctx.iv[3]);
- #[cfg(cryp_v2)]
+ #[cfg(any(cryp_v2, cryp_v3))]
for i in 0..8 {
T::regs().csgcmccmr(i).write_value(ctx.csgcmccm[i]);
T::regs().csgcmr(i).write_value(ctx.csgcm[i]);
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index bfe003a11..3d7db2025 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -10,7 +10,7 @@ stm32c031c6 = ["embassy-stm32/stm32c031c6", "cm0", "not-gpdma"]
stm32f103c8 = ["embassy-stm32/stm32f103c8", "not-gpdma"]
stm32f207zg = ["embassy-stm32/stm32f207zg", "chrono", "not-gpdma", "eth", "rng"]
stm32f303ze = ["embassy-stm32/stm32f303ze", "chrono", "not-gpdma"]
-stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not-gpdma", "dac", "rng"]
+stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not-gpdma", "dac", "rng", "cryp"]
stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma", "dac", "sdmmc"]
stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
@@ -18,7 +18,7 @@ stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng"
stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "hash"]
stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan", "hash", "cryp"]
stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan", "hash", "cryp"]
-stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
+stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan", "cryp"]
stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
From 27fac380cfe05439adbe4f0256765f906e403733 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Thu, 29 Feb 2024 19:15:32 -0500
Subject: [PATCH 355/392] Remove CRYP from H7A3.
---
tests/stm32/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index 3d7db2025..c5f605565 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -18,7 +18,7 @@ stm32g491re = ["embassy-stm32/stm32g491re", "chrono", "stop", "not-gpdma", "rng"
stm32h563zi = ["embassy-stm32/stm32h563zi", "chrono", "eth", "rng", "hash"]
stm32h753zi = ["embassy-stm32/stm32h753zi", "chrono", "not-gpdma", "eth", "rng", "fdcan", "hash", "cryp"]
stm32h755zi = ["embassy-stm32/stm32h755zi-cm7", "chrono", "not-gpdma", "eth", "dac", "rng", "fdcan", "hash", "cryp"]
-stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan", "cryp"]
+stm32h7a3zi = ["embassy-stm32/stm32h7a3zi", "not-gpdma", "rng", "fdcan"]
stm32l073rz = ["embassy-stm32/stm32l073rz", "cm0", "not-gpdma", "rng"]
stm32l152re = ["embassy-stm32/stm32l152re", "chrono", "not-gpdma"]
stm32l496zg = ["embassy-stm32/stm32l496zg", "not-gpdma", "rng"]
From 97e125872e707e96bf81cd8e601f92f0f9f688a1 Mon Sep 17 00:00:00 2001
From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com>
Date: Thu, 29 Feb 2024 19:18:25 -0500
Subject: [PATCH 356/392] Remove CRYP from F429.
---
tests/stm32/Cargo.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/stm32/Cargo.toml b/tests/stm32/Cargo.toml
index c5f605565..bfe003a11 100644
--- a/tests/stm32/Cargo.toml
+++ b/tests/stm32/Cargo.toml
@@ -10,7 +10,7 @@ stm32c031c6 = ["embassy-stm32/stm32c031c6", "cm0", "not-gpdma"]
stm32f103c8 = ["embassy-stm32/stm32f103c8", "not-gpdma"]
stm32f207zg = ["embassy-stm32/stm32f207zg", "chrono", "not-gpdma", "eth", "rng"]
stm32f303ze = ["embassy-stm32/stm32f303ze", "chrono", "not-gpdma"]
-stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not-gpdma", "dac", "rng", "cryp"]
+stm32f429zi = ["embassy-stm32/stm32f429zi", "chrono", "eth", "stop", "can", "not-gpdma", "dac", "rng"]
stm32f446re = ["embassy-stm32/stm32f446re", "chrono", "stop", "can", "not-gpdma", "dac", "sdmmc"]
stm32f767zi = ["embassy-stm32/stm32f767zi", "chrono", "not-gpdma", "eth", "rng"]
stm32g071rb = ["embassy-stm32/stm32g071rb", "cm0", "not-gpdma", "dac"]
From 4c0d63ce6188a340bd75388c3e772ba5d89ca8d4 Mon Sep 17 00:00:00 2001
From: Andreas Schmidt <ndrscodes@gmail.com>
Date: Fri, 1 Mar 2024 10:13:59 +0100
Subject: [PATCH 357/392] docs: update broken reference in
basic_application.adoc
---
docs/modules/ROOT/pages/basic_application.adoc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/modules/ROOT/pages/basic_application.adoc b/docs/modules/ROOT/pages/basic_application.adoc
index 02b8981c9..d5aad806d 100644
--- a/docs/modules/ROOT/pages/basic_application.adoc
+++ b/docs/modules/ROOT/pages/basic_application.adoc
@@ -23,7 +23,7 @@ Then, what follows are some declarations on how to deal with panics and faults.
[source,rust]
----
-include::example$basic/src/main.rs[lines="10"]
+include::example$basic/src/main.rs[lines="8"]
----
=== Task declaration
From 96af20cf5b1af90029bd5119c2f4918b844d9fc3 Mon Sep 17 00:00:00 2001
From: Siebe Claes <siebe.claes@gmail.com>
Date: Fri, 1 Mar 2024 19:15:49 +0100
Subject: [PATCH 358/392] stm32: can: fd: Fix Frame is_extended() function
---
embassy-stm32/src/can/frame.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-stm32/src/can/frame.rs b/embassy-stm32/src/can/frame.rs
index 00a441db6..9c293035d 100644
--- a/embassy-stm32/src/can/frame.rs
+++ b/embassy-stm32/src/can/frame.rs
@@ -206,7 +206,7 @@ impl embedded_can::Frame for ClassicFrame {
fn is_extended(&self) -> bool {
match self.can_header.id {
embedded_can::Id::Extended(_) => true,
- embedded_can::Id::Standard(_) => true,
+ embedded_can::Id::Standard(_) => false,
}
}
fn is_remote_frame(&self) -> bool {
@@ -369,7 +369,7 @@ impl embedded_can::Frame for FdFrame {
fn is_extended(&self) -> bool {
match self.can_header.id {
embedded_can::Id::Extended(_) => true,
- embedded_can::Id::Standard(_) => true,
+ embedded_can::Id::Standard(_) => false,
}
}
fn is_remote_frame(&self) -> bool {
From 95234cddbac6f21fce0f5df510d49816f343b87d Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 26 Feb 2024 03:28:27 +0100
Subject: [PATCH 359/392] stm32: autogenerate mux config for all chips.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/build.rs | 315 +++++++++++++++----------
embassy-stm32/src/ipcc.rs | 19 +-
embassy-stm32/src/rcc/c0.rs | 34 +--
embassy-stm32/src/rcc/f013.rs | 6 +-
embassy-stm32/src/rcc/f247.rs | 10 +-
embassy-stm32/src/rcc/g0.rs | 63 ++---
embassy-stm32/src/rcc/g4.rs | 78 ++----
embassy-stm32/src/rcc/h.rs | 72 +-----
embassy-stm32/src/rcc/l.rs | 56 ++---
embassy-stm32/src/rcc/mod.rs | 4 +-
embassy-stm32/src/rcc/u5.rs | 7 +-
embassy-stm32/src/rcc/wba.rs | 13 +-
embassy-stm32/src/usb_otg/usb.rs | 14 --
examples/stm32f334/src/bin/pwm.rs | 2 +-
examples/stm32g0/src/bin/hf_timer.rs | 40 ++--
examples/stm32g0/src/bin/usb_serial.rs | 10 +-
examples/stm32g4/src/bin/adc.rs | 29 ++-
examples/stm32g4/src/bin/can.rs | 21 +-
examples/stm32g4/src/bin/pll.rs | 1 +
examples/stm32g4/src/bin/usb_serial.rs | 50 ++--
examples/stm32h5/src/bin/can.rs | 2 +-
examples/stm32h5/src/bin/usb_serial.rs | 7 +-
examples/stm32h7/src/bin/adc.rs | 2 +-
examples/stm32h7/src/bin/can.rs | 2 +-
examples/stm32h7/src/bin/dac.rs | 2 +-
examples/stm32h7/src/bin/dac_dma.rs | 2 +-
examples/stm32l4/src/bin/adc.rs | 14 +-
tests/stm32/src/bin/fdcan.rs | 4 +-
tests/stm32/src/common.rs | 47 ++--
30 files changed, 412 insertions(+), 518 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 460184920..4bbd43c47 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7462d805ef05892531a83cd9ad60c9cba568d54" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e853cf944b150898312984d092d63926970c340d" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-d7462d805ef05892531a83cd9ad60c9cba568d54", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e853cf944b150898312984d092d63926970c340d", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 08c051956..84e8be25d 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -5,7 +5,9 @@ use std::{env, fs};
use proc_macro2::{Ident, TokenStream};
use quote::{format_ident, quote};
-use stm32_metapac::metadata::{MemoryRegionKind, PeripheralRccKernelClock, StopMode, METADATA};
+use stm32_metapac::metadata::{
+ MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode, METADATA,
+};
fn main() {
let target = env::var("TARGET").unwrap();
@@ -374,12 +376,130 @@ fn main() {
}
}
- let force_refcount = HashSet::from(["usart"]);
- let mut refcount_statics = BTreeSet::new();
+ struct ClockGen<'a> {
+ rcc_registers: &'a PeripheralRegisters,
+ chained_muxes: HashMap<&'a str, &'a PeripheralRccRegister>,
+ force_refcount: HashSet<&'a str>,
- let mut clock_names = BTreeSet::new();
+ refcount_statics: BTreeSet<Ident>,
+ clock_names: BTreeSet<String>,
+ muxes: BTreeSet<(Ident, Ident, Ident)>,
+ }
- let mut rcc_cfgr_regs = BTreeSet::new();
+ let mut clock_gen = ClockGen {
+ rcc_registers,
+ chained_muxes: HashMap::new(),
+ force_refcount: HashSet::from(["usart"]),
+
+ refcount_statics: BTreeSet::new(),
+ clock_names: BTreeSet::new(),
+ muxes: BTreeSet::new(),
+ };
+ if chip_name.starts_with("stm32h5") {
+ clock_gen.chained_muxes.insert(
+ "PER",
+ &PeripheralRccRegister {
+ register: "CCIPR5",
+ field: "PERSEL",
+ },
+ );
+ }
+ if chip_name.starts_with("stm32h7") {
+ clock_gen.chained_muxes.insert(
+ "PER",
+ &PeripheralRccRegister {
+ register: "D1CCIPR",
+ field: "PERSEL",
+ },
+ );
+ }
+ if chip_name.starts_with("stm32u5") {
+ clock_gen.chained_muxes.insert(
+ "ICLK",
+ &PeripheralRccRegister {
+ register: "CCIPR1",
+ field: "ICLKSEL",
+ },
+ );
+ }
+ if chip_name.starts_with("stm32wb") && !chip_name.starts_with("stm32wba") {
+ clock_gen.chained_muxes.insert(
+ "CLK48",
+ &PeripheralRccRegister {
+ register: "CCIPR",
+ field: "CLK48SEL",
+ },
+ );
+ }
+ if chip_name.starts_with("stm32f7") {
+ clock_gen.chained_muxes.insert(
+ "CLK48",
+ &PeripheralRccRegister {
+ register: "DCKCFGR2",
+ field: "CLK48SEL",
+ },
+ );
+ }
+ if chip_name.starts_with("stm32f4") && !chip_name.starts_with("stm32f410") {
+ clock_gen.chained_muxes.insert(
+ "CLK48",
+ &PeripheralRccRegister {
+ register: "DCKCFGR",
+ field: "CLK48SEL",
+ },
+ );
+ }
+
+ impl<'a> ClockGen<'a> {
+ fn gen_clock(&mut self, name: &str) -> TokenStream {
+ let clock_name = format_ident!("{}", name.to_ascii_lowercase());
+ self.clock_names.insert(name.to_ascii_lowercase());
+ quote!( unsafe { crate::rcc::get_freqs().#clock_name.unwrap() } )
+ }
+
+ fn gen_mux(&mut self, mux: &PeripheralRccRegister) -> TokenStream {
+ let ir = &self.rcc_registers.ir;
+ let fieldset_name = mux.register.to_ascii_lowercase();
+ let fieldset = ir
+ .fieldsets
+ .iter()
+ .find(|i| i.name.eq_ignore_ascii_case(&fieldset_name))
+ .unwrap();
+ let field_name = mux.field.to_ascii_lowercase();
+ let field = fieldset.fields.iter().find(|i| i.name == field_name).unwrap();
+ let enum_name = field.enumm.unwrap();
+ let enumm = ir.enums.iter().find(|i| i.name == enum_name).unwrap();
+
+ let fieldset_name = format_ident!("{}", fieldset_name);
+ let field_name = format_ident!("{}", field_name);
+ let enum_name = format_ident!("{}", enum_name);
+
+ self.muxes
+ .insert((fieldset_name.clone(), field_name.clone(), enum_name.clone()));
+
+ let mut match_arms = TokenStream::new();
+
+ for v in enumm.variants.iter().filter(|v| v.name != "DISABLE") {
+ let variant_name = format_ident!("{}", v.name);
+ let expr = if let Some(mux) = self.chained_muxes.get(&v.name) {
+ self.gen_mux(mux)
+ } else {
+ self.gen_clock(&v.name)
+ };
+ match_arms.extend(quote! {
+ crate::pac::rcc::vals::#enum_name::#variant_name => #expr,
+ });
+ }
+
+ quote! {
+ match crate::pac::RCC.#fieldset_name().read().#field_name() {
+ #match_arms
+ #[allow(unreachable_patterns)]
+ _ => unreachable!(),
+ }
+ }
+ }
+ }
for p in METADATA.peripherals {
if !singletons.contains(&p.name.to_string()) {
@@ -416,12 +536,12 @@ fn main() {
let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
let refcount =
- force_refcount.contains(ptype) || *rcc_field_count.get(&(en.register, en.field)).unwrap() > 1;
+ clock_gen.force_refcount.contains(ptype) || *rcc_field_count.get(&(en.register, en.field)).unwrap() > 1;
let (before_enable, before_disable) = if refcount {
let refcount_static =
format_ident!("{}_{}", en.register.to_ascii_uppercase(), en.field.to_ascii_uppercase());
- refcount_statics.insert(refcount_static.clone());
+ clock_gen.refcount_statics.insert(refcount_static.clone());
(
quote! {
@@ -442,63 +562,12 @@ fn main() {
};
let clock_frequency = match &rcc.kernel_clock {
- PeripheralRccKernelClock::Mux(mux) => {
- let ir = &rcc_registers.ir;
- let fieldset_name = mux.register.to_ascii_lowercase();
- let fieldset = ir
- .fieldsets
- .iter()
- .find(|i| i.name.eq_ignore_ascii_case(&fieldset_name))
- .unwrap();
- let field_name = mux.field.to_ascii_lowercase();
- let field = fieldset.fields.iter().find(|i| i.name == field_name).unwrap();
- let enum_name = field.enumm.unwrap();
- let enumm = ir.enums.iter().find(|i| i.name == enum_name).unwrap();
-
- let fieldset_name = format_ident!("{}", fieldset_name);
- let field_name = format_ident!("{}", field_name);
- let enum_name = format_ident!("{}", enum_name);
-
- rcc_cfgr_regs.insert((fieldset_name.clone(), field_name.clone(), enum_name.clone()));
-
- let match_arms: TokenStream = enumm
- .variants
- .iter()
- .filter(|v| v.name != "DISABLE")
- .map(|v| {
- let variant_name = format_ident!("{}", v.name);
- let clock_name = format_ident!("{}", v.name.to_ascii_lowercase());
- clock_names.insert(v.name.to_ascii_lowercase());
- quote! {
- #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name.unwrap() },
- }
- })
- .collect();
-
- quote! {
- use crate::pac::rcc::vals::#enum_name;
-
- #[allow(unreachable_patterns)]
- match crate::pac::RCC.#fieldset_name().read().#field_name() {
- #match_arms
- _ => unreachable!(),
- }
- }
- }
- PeripheralRccKernelClock::Clock(clock) => {
- let clock = clock.to_ascii_lowercase();
- let clock_name = format_ident!("{}", clock);
- clock_names.insert(clock.to_string());
- quote! {
- unsafe { crate::rcc::get_freqs().#clock_name.unwrap() }
- }
- }
+ PeripheralRccKernelClock::Mux(mux) => clock_gen.gen_mux(mux),
+ PeripheralRccKernelClock::Clock(clock) => clock_gen.gen_clock(clock),
};
- /*
- A refcount leak can result if the same field is shared by peripherals with different stop modes
- This condition should be checked in stm32-data
- */
+ // A refcount leak can result if the same field is shared by peripherals with different stop modes
+ // This condition should be checked in stm32-data
let stop_refcount = match rcc.stop_mode {
StopMode::Standby => None,
StopMode::Stop2 => Some(quote! { REFCOUNT_STOP2 }),
@@ -543,74 +612,79 @@ fn main() {
}
}
- if !rcc_cfgr_regs.is_empty() {
- println!("cargo:rustc-cfg=clock_mux");
+ let struct_fields: Vec<_> = clock_gen
+ .muxes
+ .iter()
+ .map(|(_fieldset, fieldname, enum_name)| {
+ quote! {
+ pub #fieldname: #enum_name
+ }
+ })
+ .collect();
- let struct_fields: Vec<_> = rcc_cfgr_regs
+ let mut inits = TokenStream::new();
+ for fieldset in clock_gen
+ .muxes
+ .iter()
+ .map(|(f, _, _)| f)
+ .collect::<BTreeSet<_>>()
+ .into_iter()
+ {
+ let setters: Vec<_> = clock_gen
+ .muxes
.iter()
- .map(|(_fieldset, fieldname, enum_name)| {
- quote! {
- pub #fieldname: Option<#enum_name>
- }
- })
- .collect();
-
- let field_names: Vec<_> = rcc_cfgr_regs
- .iter()
- .map(|(_fieldset, fieldname, _enum_name)| fieldname)
- .collect();
-
- let inits: Vec<_> = rcc_cfgr_regs
- .iter()
- .map(|(fieldset, fieldname, _enum_name)| {
+ .filter(|(f, _, _)| f == fieldset)
+ .map(|(_, fieldname, _)| {
let setter = format_ident!("set_{}", fieldname);
quote! {
- match self.#fieldname {
- None => {}
- Some(val) => {
- crate::pac::RCC.#fieldset()
- .modify(|w| w.#setter(val));
- }
- };
+ w.#setter(self.#fieldname);
}
})
.collect();
- let enum_names: BTreeSet<_> = rcc_cfgr_regs
- .iter()
- .map(|(_fieldset, _fieldname, enum_name)| enum_name)
- .collect();
-
- g.extend(quote! {
- pub mod mux {
- #(pub use crate::pac::rcc::vals::#enum_names as #enum_names; )*
-
- #[derive(Clone, Copy)]
- pub struct ClockMux {
- #( #struct_fields, )*
- }
-
- impl Default for ClockMux {
- fn default() -> Self {
- Self {
- #( #field_names: None, )*
- }
- }
- }
-
- impl ClockMux {
- pub fn init(self) {
- #( #inits )*
- }
- }
- }
- });
+ inits.extend(quote! {
+ crate::pac::RCC.#fieldset().modify(|w| {
+ #(#setters)*
+ });
+ })
}
+ let enum_names: BTreeSet<_> = clock_gen.muxes.iter().map(|(_, _, enum_name)| enum_name).collect();
+
+ g.extend(quote! {
+ pub mod mux {
+ #(pub use crate::pac::rcc::vals::#enum_names as #enum_names; )*
+
+ #[derive(Clone, Copy)]
+ pub struct ClockMux {
+ #( #struct_fields, )*
+ }
+
+ impl ClockMux {
+ pub(crate) const fn default() -> Self {
+ // safety: zero value is valid for all PAC enums.
+ unsafe { ::core::mem::zeroed() }
+ }
+ }
+
+ impl Default for ClockMux {
+ fn default() -> Self {
+ Self::default()
+ }
+ }
+
+ impl ClockMux {
+ pub(crate) fn init(&self) {
+ #inits
+ }
+ }
+ }
+ });
+
// Generate RCC
- clock_names.insert("sys".to_string());
- clock_names.insert("rtc".to_string());
- let clock_idents: Vec<_> = clock_names.iter().map(|n| format_ident!("{}", n)).collect();
+ clock_gen.clock_names.insert("sys".to_string());
+ clock_gen.clock_names.insert("rtc".to_string());
+ let clock_idents: Vec<_> = clock_gen.clock_names.iter().map(|n| format_ident!("{}", n)).collect();
g.extend(quote! {
#[derive(Clone, Copy, Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -640,7 +714,8 @@ fn main() {
}
);
- let refcount_mod: TokenStream = refcount_statics
+ let refcount_mod: TokenStream = clock_gen
+ .refcount_statics
.iter()
.map(|refcount_static| {
quote! {
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 663a7f59d..523719bb9 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -7,7 +7,6 @@ use core::task::Poll;
use self::sealed::Instance;
use crate::interrupt;
use crate::interrupt::typelevel::Interrupt;
-use crate::pac::rcc::vals::{Lptim1sel, Lptim2sel};
use crate::peripherals::IPCC;
use crate::rcc::sealed::RccPeripheral;
@@ -105,7 +104,8 @@ impl Ipcc {
IPCC::enable_and_reset();
IPCC::set_cpu2(true);
- _configure_pwr();
+ // set RF wake-up clock = LSE
+ crate::pac::RCC.csr().modify(|w| w.set_rfwkpsel(0b01));
let regs = IPCC::regs();
@@ -271,18 +271,3 @@ pub(crate) mod sealed {
fn state() -> &'static State;
}
}
-
-fn _configure_pwr() {
- // TODO: move the rest of this to rcc
- let rcc = crate::pac::RCC;
-
- // TODO: required
- // set RF wake-up clock = LSE
- rcc.csr().modify(|w| w.set_rfwkpsel(0b01));
-
- // set LPTIM1 & LPTIM2 clock source
- rcc.ccipr().modify(|w| {
- w.set_lptim1sel(Lptim1sel::PCLK1);
- w.set_lptim2sel(Lptim2sel::PCLK1);
- });
-}
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index ec6ec34e8..1946c5a15 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -21,6 +21,9 @@ pub struct Config {
pub ahb_pre: AHBPrescaler,
pub apb_pre: APBPrescaler,
pub ls: super::LsConfig,
+
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
}
impl Default for Config {
@@ -31,6 +34,7 @@ impl Default for Config {
ahb_pre: AHBPrescaler::DIV1,
apb_pre: APBPrescaler::DIV1,
ls: Default::default(),
+ mux: Default::default(),
}
}
}
@@ -97,28 +101,25 @@ pub(crate) unsafe fn init(config: Config) {
if !set_flash_latency_after {
// Spin until the effective flash latency is compatible with the clock change
- while FLASH.acr().read().latency().to_bits() < target_flash_latency.to_bits() {}
+ while FLASH.acr().read().latency() < target_flash_latency {}
}
// Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
- let (sw, hpre, ppre) = (sw.into(), config.ahb_pre, config.apb_pre);
RCC.cfgr().modify(|w| {
w.set_sw(sw);
- w.set_hpre(hpre);
- w.set_ppre(ppre);
+ w.set_hpre(config.ahb_pre);
+ w.set_ppre(config.apb_pre);
});
-
- if set_flash_latency_after {
- // We can make the flash require fewer wait states
- // Spin until the SYSCLK changes have taken effect
- loop {
- let cfgr = RCC.cfgr().read();
- if cfgr.sw() == sw && cfgr.hpre() == hpre && cfgr.ppre() == ppre {
- break;
- }
+ // Spin until the SYSCLK changes have taken effect
+ loop {
+ let cfgr = RCC.cfgr().read();
+ if cfgr.sw() == sw && cfgr.hpre() == config.ahb_pre && cfgr.ppre() == config.apb_pre {
+ break;
}
+ }
- // Set the flash latency to require fewer wait states
+ // Set the flash latency to require fewer wait states
+ if set_flash_latency_after {
FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
}
@@ -132,6 +133,11 @@ pub(crate) unsafe fn init(config: Config) {
}
};
+ config.mux.init();
+
+ // without this, the ringbuffered uart test fails.
+ cortex_m::asm::dsb();
+
set_clocks!(
hsi: None,
lse: None,
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 5046f0a3a..215f8a3d2 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -98,8 +98,8 @@ pub struct Config {
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
pub adc34: AdcClockSource,
- #[cfg(clock_mux)]
- pub mux: crate::rcc::mux::ClockMux,
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
pub ls: super::LsConfig,
}
@@ -128,7 +128,6 @@ impl Default for Config {
#[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
- #[cfg(clock_mux)]
mux: Default::default(),
}
}
@@ -370,7 +369,6 @@ pub(crate) unsafe fn init(config: Config) {
};
*/
- #[cfg(clock_mux)]
config.mux.init();
set_clocks!(
diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs
index 343d075cd..7b252870c 100644
--- a/embassy-stm32/src/rcc/f247.rs
+++ b/embassy-stm32/src/rcc/f247.rs
@@ -95,6 +95,9 @@ pub struct Config {
pub ls: super::LsConfig,
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
+
#[cfg(stm32f2)]
pub voltage: VoltageScale,
}
@@ -120,6 +123,7 @@ impl Default for Config {
#[cfg(stm32f2)]
voltage: VoltageScale::Range3,
+ mux: Default::default(),
}
}
}
@@ -256,6 +260,8 @@ pub(crate) unsafe fn init(config: Config) {
});
while RCC.cfgr().read().sws() != config.sys {}
+ config.mux.init();
+
set_clocks!(
hsi: hsi,
hse: hse,
@@ -286,7 +292,9 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
pllsai1_r: pllsai.r,
- clk48: pll.q,
+ // TODO workaround until f4 rcc is fixed in stm32-data
+ #[cfg(not(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7)))]
+ pllsai1_q: None,
hsi_div488: hsi.map(|hsi| hsi/488u32),
hsi_hse: None,
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index ae502dd9c..5cfe9953b 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -71,22 +71,6 @@ pub enum PllSource {
HSE(Hertz, HseMode),
}
-/// Sets the source for the 48MHz clock to the USB peripheral.
-#[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
-pub enum UsbSrc {
- /// Use the High Speed Internal Oscillator. The CRS must be used to calibrate the
- /// oscillator to comply with the USB specification for oscillator tolerance.
- #[cfg(any(stm32g0b1, stm32g0c1))]
- Hsi48(super::Hsi48Config),
- /// Use the PLLQ output. The PLL must be configured to output a 48MHz clock. The
- /// PLL needs to be using the HSE source to comply with the USB specification for oscillator
- /// tolerance.
- PllQ,
- /// Use the HSE source directly. The HSE must be a 48MHz source. The HSE source must comply
- /// with the USB specification for oscillator tolerance.
- HSE,
-}
-
/// Clocks configutation
pub struct Config {
pub sys: Sysclk,
@@ -94,8 +78,10 @@ pub struct Config {
pub apb_pre: APBPrescaler,
pub low_power_run: bool,
pub ls: super::LsConfig,
- #[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
- pub usb_src: Option<UsbSrc>,
+ #[cfg(crs)]
+ pub hsi48: Option<super::Hsi48Config>,
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
}
impl Default for Config {
@@ -107,8 +93,9 @@ impl Default for Config {
apb_pre: APBPrescaler::DIV1,
low_power_run: false,
ls: Default::default(),
- #[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
- usb_src: None,
+ #[cfg(crs)]
+ hsi48: Some(Default::default()),
+ mux: Default::default(),
}
}
}
@@ -322,34 +309,12 @@ pub(crate) unsafe fn init(config: Config) {
let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
let hse_freq = (sw == Sw::HSE).then_some(sys_clk);
- #[cfg(any(stm32g0b1, stm32g0c1, stm32g0b0))]
- let hsi48_freq = config.usb_src.and_then(|config| {
- match config {
- UsbSrc::PllQ => {
- // Make sure the PLLQ is enabled and running at 48Mhz
- assert!(pll1_q_freq.is_some() && pll1_q_freq.unwrap().0 == 48_000_000);
- RCC.ccipr2()
- .modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::PLL1_Q));
- None
- }
- UsbSrc::HSE => {
- // Make sure the HSE is enabled and running at 48Mhz
- assert!(hse_freq.is_some() && hse_freq.unwrap().0 == 48_000_000);
- RCC.ccipr2()
- .modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::HSE));
- None
- }
- #[cfg(any(stm32g0b1, stm32g0c1))]
- UsbSrc::Hsi48(config) => {
- let freq = super::init_hsi48(config);
- RCC.ccipr2()
- .modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::HSI48));
- Some(freq)
- }
- }
- });
- #[cfg(not(any(stm32g0b1, stm32g0c1, stm32g0b0)))]
- let hsi48_freq: Option<Hertz> = None;
+ #[cfg(crs)]
+ let hsi48 = config.hsi48.map(super::init_hsi48);
+ #[cfg(not(crs))]
+ let hsi48: Option<Hertz> = None;
+
+ config.mux.init();
set_clocks!(
sys: Some(sys_clk),
@@ -357,7 +322,7 @@ pub(crate) unsafe fn init(config: Config) {
pclk1: Some(apb_freq),
pclk1_tim: Some(apb_tim_freq),
hsi: hsi_freq,
- hsi48: hsi48_freq,
+ hsi48: hsi48,
hsi_div_8: hsi_div_8_freq,
hse: hse_freq,
lse: lse_freq,
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 6ed266284..79bdbeb77 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -1,11 +1,10 @@
use stm32_metapac::flash::vals::Latency;
-use stm32_metapac::rcc::vals::{Adcsel, Sw};
+use stm32_metapac::rcc::vals::Sw;
use stm32_metapac::FLASH;
pub use crate::pac::rcc::vals::{
- Adcsel as AdcClockSource, Clk48sel as Clk48Src, Fdcansel as FdCanClockSource, Hpre as AHBPrescaler,
- Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc, Ppre as APBPrescaler,
- Sw as Sysclk,
+ Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc,
+ Ppre as APBPrescaler, Sw as Sysclk,
};
use crate::pac::{PWR, RCC};
use crate::time::Hertz;
@@ -82,24 +81,15 @@ pub struct Config {
pub low_power_run: bool,
- /// Sets the clock source for the 48MHz clock used by the USB and RNG peripherals.
- pub clk48_src: Clk48Src,
-
/// Low-Speed Clock Configuration
pub ls: super::LsConfig,
- /// Clock Source for ADCs 1 and 2
- pub adc12_clock_source: AdcClockSource,
-
- /// Clock Source for ADCs 3, 4 and 5
- pub adc345_clock_source: AdcClockSource,
-
- /// Clock Source for FDCAN
- pub fdcan_clock_source: FdCanClockSource,
-
/// Enable range1 boost mode
/// Recommended when the SYSCLK frequency is greater than 150MHz.
pub boost: bool,
+
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
}
impl Default for Config {
@@ -115,12 +105,9 @@ impl Default for Config {
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
low_power_run: false,
- clk48_src: Clk48Src::HSI48,
ls: Default::default(),
- adc12_clock_source: Adcsel::DISABLE,
- adc345_clock_source: Adcsel::DISABLE,
- fdcan_clock_source: FdCanClockSource::PCLK1,
boost: false,
+ mux: Default::default(),
}
}
}
@@ -165,9 +152,7 @@ pub(crate) unsafe fn init(config: Config) {
};
// Configure HSI48 if required
- if let Some(hsi48_config) = config.hsi48 {
- super::init_hsi48(hsi48_config);
- }
+ let hsi48 = config.hsi48.map(super::init_hsi48);
let pll_freq = config.pll.map(|pll_config| {
let src_freq = match pll_config.source {
@@ -176,13 +161,13 @@ pub(crate) unsafe fn init(config: Config) {
_ => unreachable!(),
};
- assert!(max::PLL_IN.contains(&src_freq));
-
// Disable PLL before configuration
RCC.cr().modify(|w| w.set_pllon(false));
while RCC.cr().read().pllrdy() {}
- let internal_freq = src_freq / pll_config.prediv * pll_config.mul;
+ let in_freq = src_freq / pll_config.prediv;
+ assert!(max::PLL_IN.contains(&in_freq));
+ let internal_freq = in_freq * pll_config.mul;
assert!(max::PLL_VCO.contains(&internal_freq));
@@ -301,42 +286,6 @@ pub(crate) unsafe fn init(config: Config) {
let (apb1_freq, apb1_tim_freq) = super::util::calc_pclk(hclk, config.apb1_pre);
let (apb2_freq, apb2_tim_freq) = super::util::calc_pclk(hclk, config.apb2_pre);
- // Configure the 48MHz clock source for USB and RNG peripherals.
- RCC.ccipr().modify(|w| {
- w.set_clk48sel(match config.clk48_src {
- Clk48Src::PLL1_Q => {
- // Not checking that PLL1_Q is 48MHz here so as not to require the user to have a 48MHz clock.
- // Peripherals which require one (USB, RNG) should check that they‘re driven by a valid 48MHz
- // clock at init.
- crate::pac::rcc::vals::Clk48sel::PLL1_Q
- }
- Clk48Src::HSI48 => {
- // Make sure HSI48 is enabled
- assert!(config.hsi48.is_some());
- crate::pac::rcc::vals::Clk48sel::HSI48
- }
- _ => unreachable!(),
- })
- });
-
- RCC.ccipr().modify(|w| w.set_adc12sel(config.adc12_clock_source));
- RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
- RCC.ccipr().modify(|w| w.set_fdcansel(config.fdcan_clock_source));
-
- let adc12_ck = match config.adc12_clock_source {
- AdcClockSource::DISABLE => None,
- AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
- AdcClockSource::SYS => Some(sys_clk),
- _ => unreachable!(),
- };
-
- let adc345_ck = match config.adc345_clock_source {
- AdcClockSource::DISABLE => None,
- AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
- AdcClockSource::SYS => Some(sys_clk),
- _ => unreachable!(),
- };
-
if config.low_power_run {
assert!(sys_clk <= Hertz(2_000_000));
PWR.cr1().modify(|w| w.set_lpr(true));
@@ -344,6 +293,8 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
+ config.mux.init();
+
set_clocks!(
sys: Some(sys_clk),
hclk1: Some(hclk),
@@ -353,12 +304,11 @@ pub(crate) unsafe fn init(config: Config) {
pclk1_tim: Some(apb1_tim_freq),
pclk2: Some(apb2_freq),
pclk2_tim: Some(apb2_tim_freq),
- adc: adc12_ck,
- adc34: adc345_ck,
pll1_p: pll_freq.as_ref().and_then(|pll| pll.pll_p),
pll1_q: pll_freq.as_ref().and_then(|pll| pll.pll_q),
pll1_r: pll_freq.as_ref().and_then(|pll| pll.pll_r),
hse: hse,
+ hsi48: hsi48,
rtc: rtc,
);
}
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 7b2255cc6..bab8bb19e 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -2,15 +2,10 @@ use core::ops::RangeInclusive;
use crate::pac;
use crate::pac::pwr::vals::Vos;
-#[cfg(stm32h5)]
-pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
-#[cfg(stm32h7)]
-pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
pub use crate::pac::rcc::vals::{
- Ckpersel as PerClockSource, Fdcansel as FdCanClockSource, Hsidiv as HSIPrescaler, Plldiv as PllDiv,
- Pllm as PllPreDiv, Plln as PllMul, Pllsrc as PllSource, Sw as Sysclk,
+ Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul, Pllsrc as PllSource, Sw as Sysclk,
};
-use crate::pac::rcc::vals::{Ckpersel, Pllrge, Pllvcosel, Timpre};
+use crate::pac::rcc::vals::{Pllrge, Pllvcosel, Timpre};
use crate::pac::{FLASH, PWR, RCC};
use crate::time::Hertz;
@@ -194,16 +189,15 @@ pub struct Config {
#[cfg(stm32h7)]
pub apb4_pre: APBPrescaler,
- pub per_clock_source: PerClockSource,
- pub adc_clock_source: AdcClockSource,
- pub fdcan_clock_source: FdCanClockSource,
-
pub timer_prescaler: TimerPrescaler,
pub voltage_scale: VoltageScale,
pub ls: super::LsConfig,
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
pub supply_config: SupplyConfig,
+
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
}
impl Default for Config {
@@ -227,21 +221,14 @@ impl Default for Config {
#[cfg(stm32h7)]
apb4_pre: APBPrescaler::DIV1,
- per_clock_source: PerClockSource::HSI,
-
- #[cfg(stm32h5)]
- adc_clock_source: AdcClockSource::HCLK1,
- #[cfg(stm32h7)]
- adc_clock_source: AdcClockSource::PER,
-
- fdcan_clock_source: FdCanClockSource::from_bits(0), // HSE
-
timer_prescaler: TimerPrescaler::DefaultX2,
voltage_scale: VoltageScale::Scale0,
ls: Default::default(),
#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
supply_config: SupplyConfig::Default,
+
+ mux: Default::default(),
}
}
}
@@ -504,31 +491,6 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h7)]
assert!(apb4 <= pclk_max);
- let _per_ck = match config.per_clock_source {
- Ckpersel::HSI => hsi,
- Ckpersel::CSI => csi,
- Ckpersel::HSE => hse,
- _ => unreachable!(),
- };
-
- #[cfg(stm32h7)]
- let adc = match config.adc_clock_source {
- AdcClockSource::PLL2_P => pll2.p,
- AdcClockSource::PLL3_R => pll3.r,
- AdcClockSource::PER => _per_ck,
- _ => unreachable!(),
- };
- #[cfg(stm32h5)]
- let adc = match config.adc_clock_source {
- AdcClockSource::HCLK1 => Some(hclk),
- AdcClockSource::SYS => Some(sys),
- AdcClockSource::PLL2_R => pll2.r,
- AdcClockSource::HSE => hse,
- AdcClockSource::HSI => hsi,
- AdcClockSource::CSI => csi,
- _ => unreachable!(),
- };
-
flash_setup(hclk, config.voltage_scale);
let rtc = config.ls.init();
@@ -550,16 +512,6 @@ pub(crate) unsafe fn init(config: Config) {
RCC.d3cfgr().modify(|w| {
w.set_d3ppre(config.apb4_pre);
});
-
- RCC.d1ccipr().modify(|w| {
- w.set_ckpersel(config.per_clock_source);
- });
- RCC.d3ccipr().modify(|w| {
- w.set_adcsel(config.adc_clock_source);
- });
- RCC.d2ccip1r().modify(|w| {
- w.set_fdcansel(config.fdcan_clock_source);
- });
}
#[cfg(stm32h5)]
{
@@ -573,12 +525,6 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre2(config.apb2_pre);
w.set_ppre3(config.apb3_pre);
});
-
- RCC.ccipr5().modify(|w| {
- w.set_ckpersel(config.per_clock_source);
- w.set_adcdacsel(config.adc_clock_source);
- w.set_fdcan12sel(config.fdcan_clock_source)
- });
}
RCC.cfgr().modify(|w| w.set_timpre(config.timer_prescaler.into()));
@@ -601,6 +547,8 @@ pub(crate) unsafe fn init(config: Config) {
while !pac::SYSCFG.cccsr().read().ready() {}
}
+ config.mux.init();
+
set_clocks!(
sys: Some(sys),
hclk1: Some(hclk),
@@ -614,7 +562,6 @@ pub(crate) unsafe fn init(config: Config) {
pclk4: Some(apb4),
pclk1_tim: Some(apb1_tim),
pclk2_tim: Some(apb2_tim),
- adc: adc,
rtc: rtc,
hsi: hsi,
@@ -646,7 +593,6 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h5)]
audioclk: None,
- per: None,
i2s_ckin: None,
);
}
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index aa4245d4e..9079ddd41 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -1,10 +1,6 @@
#[cfg(any(stm32l0, stm32l1))]
pub use crate::pac::pwr::vals::Vos as VoltageScale;
use crate::pac::rcc::regs::Cfgr;
-#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
-pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
-#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
-pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
#[cfg(any(stm32wb, stm32wl))]
pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as Sysclk};
@@ -59,18 +55,14 @@ pub struct Config {
#[cfg(any(stm32wl, stm32wb))]
pub shared_ahb_pre: AHBPrescaler,
- // muxes
- #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
- pub clk48_src: Clk48Src,
-
// low speed LSI/LSE/RTC
pub ls: super::LsConfig,
- #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
- pub adc_clock_source: AdcClockSource,
-
#[cfg(any(stm32l0, stm32l1))]
pub voltage_scale: VoltageScale,
+
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
}
impl Default for Config {
@@ -95,13 +87,10 @@ impl Default for Config {
pllsai2: None,
#[cfg(crs)]
hsi48: Some(Default::default()),
- #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
- clk48_src: Clk48Src::HSI48,
ls: Default::default(),
- #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
- adc_clock_source: AdcClockSource::SYS,
#[cfg(any(stm32l0, stm32l1))]
voltage_scale: VoltageScale::RANGE1,
+ mux: Default::default(),
}
}
}
@@ -118,7 +107,6 @@ pub const WPAN_DEFAULT: Config = Config {
hsi48: Some(super::Hsi48Config { sync_from_usb: false }),
msi: None,
hsi: false,
- clk48_src: Clk48Src::PLL1_Q,
ls: super::LsConfig::default_lse(),
@@ -137,7 +125,8 @@ pub const WPAN_DEFAULT: Config = Config {
shared_ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
- adc_clock_source: AdcClockSource::SYS,
+
+ mux: super::mux::ClockMux::default(),
};
fn msi_enable(range: MSIRange) {
@@ -267,21 +256,6 @@ pub(crate) unsafe fn init(config: Config) {
Sysclk::PLL1_R => pll.r.unwrap(),
};
- #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
- RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
- #[cfg(any(rcc_l0_v2))]
- let clk48 = match config.clk48_src {
- Clk48Src::HSI48 => hsi48,
- Clk48Src::PLL1_VCO_DIV_2 => pll.clk48,
- };
- #[cfg(any(stm32l4, stm32l5, stm32wb))]
- let clk48 = match config.clk48_src {
- Clk48Src::HSI48 => hsi48,
- Clk48Src::MSI => msi,
- Clk48Src::PLLSAI1_Q => pllsai1.q,
- Clk48Src::PLL1_Q => pll.q,
- };
-
#[cfg(rcc_l4plus)]
assert!(sys_clk.0 <= 120_000_000);
#[cfg(all(stm32l4, not(rcc_l4plus)))]
@@ -357,9 +331,6 @@ pub(crate) unsafe fn init(config: Config) {
});
while RCC.cfgr().read().sws() != config.sys {}
- #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
- RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
-
#[cfg(any(stm32wl, stm32wb))]
{
RCC.extcfgr().modify(|w| {
@@ -372,6 +343,8 @@ pub(crate) unsafe fn init(config: Config) {
while !RCC.extcfgr().read().c2hpref() {}
}
+ config.mux.init();
+
set_clocks!(
sys: Some(sys_clk),
hclk1: Some(hclk1),
@@ -388,10 +361,11 @@ pub(crate) unsafe fn init(config: Config) {
hsi: hsi,
hse: hse,
msi: msi,
- #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
- clk48: clk48,
hsi48: hsi48,
+ #[cfg(any(stm32l0, stm32l1))]
+ pll1_vco_div_2: pll.vco.map(|c| c/2u32),
+
#[cfg(not(any(stm32l0, stm32l1)))]
pll1_p: pll.p,
#[cfg(not(any(stm32l0, stm32l1)))]
@@ -511,7 +485,7 @@ mod pll {
#[derive(Default)]
pub(super) struct PllOutput {
pub r: Option<Hertz>,
- pub clk48: Option<Hertz>,
+ pub vco: Option<Hertz>,
}
pub(super) fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
@@ -528,7 +502,6 @@ mod pll {
let vco_freq = pll_src * pll.mul;
let r = vco_freq / pll.div;
- let clk48 = (vco_freq == Hertz(96_000_000)).then_some(Hertz(48_000_000));
assert!(r <= Hertz(32_000_000));
@@ -541,7 +514,10 @@ mod pll {
// Enable PLL
pll_enable(instance, true);
- PllOutput { r: Some(r), clk48 }
+ PllOutput {
+ r: Some(r),
+ vco: Some(vco_freq),
+ }
}
}
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index c8ca713de..910ebe205 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -31,9 +31,7 @@ mod _version;
pub use _version::*;
-#[cfg(clock_mux)]
-pub use crate::_generated::mux;
-pub use crate::_generated::Clocks;
+pub use crate::_generated::{mux, Clocks};
#[cfg(feature = "low-power")]
/// Must be written within a critical section
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index c8814ed69..9533e16c4 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -85,6 +85,9 @@ pub struct Config {
/// See RM0456 § 10.5.4 for a general overview and § 11.4.10 for clock source frequency limits.
pub voltage_range: VoltageScale,
pub ls: super::LsConfig,
+
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
}
impl Default for Config {
@@ -104,6 +107,7 @@ impl Default for Config {
apb3_pre: APBPrescaler::DIV1,
voltage_range: VoltageScale::RANGE1,
ls: Default::default(),
+ mux: Default::default(),
}
}
}
@@ -259,6 +263,8 @@ pub(crate) unsafe fn init(config: Config) {
let rtc = config.ls.init();
+ config.mux.init();
+
set_clocks!(
sys: Some(sys_clk),
hclk1: Some(hclk),
@@ -289,7 +295,6 @@ pub(crate) unsafe fn init(config: Config) {
lse: None,
lsi: None,
msik: None,
- iclk: None,
shsi: None,
shsi_div_2: None,
);
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 9d5dcfc4b..8e1779d7c 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -1,8 +1,6 @@
pub use crate::pac::pwr::vals::Vos as VoltageScale;
use crate::pac::rcc::regs::Cfgr1;
-pub use crate::pac::rcc::vals::{
- Adcsel as AdcClockSource, Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk,
-};
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsepre as HsePrescaler, Ppre as APBPrescaler, Sw as Sysclk};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
@@ -32,9 +30,10 @@ pub struct Config {
// low speed LSI/LSE/RTC
pub ls: super::LsConfig,
- pub adc_clock_source: AdcClockSource,
-
pub voltage_scale: VoltageScale,
+
+ /// Per-peripheral kernel clock selection muxes
+ pub mux: super::mux::ClockMux,
}
impl Default for Config {
@@ -49,8 +48,8 @@ impl Default for Config {
apb2_pre: APBPrescaler::DIV1,
apb7_pre: APBPrescaler::DIV1,
ls: Default::default(),
- adc_clock_source: AdcClockSource::HCLK4,
voltage_scale: VoltageScale::RANGE2,
+ mux: Default::default(),
}
}
}
@@ -152,7 +151,7 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre2(config.apb2_pre);
});
- RCC.ccipr3().modify(|w| w.set_adcsel(config.adc_clock_source));
+ config.mux.init();
set_clocks!(
sys: Some(sys_clk),
diff --git a/embassy-stm32/src/usb_otg/usb.rs b/embassy-stm32/src/usb_otg/usb.rs
index 190fb274f..373697ec8 100644
--- a/embassy-stm32/src/usb_otg/usb.rs
+++ b/embassy-stm32/src/usb_otg/usb.rs
@@ -606,13 +606,6 @@ impl<'d, T: Instance> Bus<'d, T> {
// Wait for USB power to stabilize
while !crate::pac::PWR.cr3().read().usb33rdy() {}
- // Use internal 48MHz HSI clock. Should be enabled in RCC by default.
- critical_section::with(|_| {
- crate::pac::RCC
- .d2ccip2r()
- .modify(|w| w.set_usbsel(crate::pac::rcc::vals::Usbsel::HSI48))
- });
-
// Enable ULPI clock if external PHY is used
let ulpien = !self.phy_type.internal();
critical_section::with(|_| {
@@ -645,13 +638,6 @@ impl<'d, T: Instance> Bus<'d, T> {
// Wait for USB power to stabilize
while !crate::pac::PWR.svmsr().read().vddusbrdy() {}
-
- // Select HSI48 as USB clock source.
- critical_section::with(|_| {
- crate::pac::RCC.ccipr1().modify(|w| {
- w.set_iclksel(crate::pac::rcc::vals::Iclksel::HSI48);
- })
- });
}
<T as RccPeripheral>::enable_and_reset();
diff --git a/examples/stm32f334/src/bin/pwm.rs b/examples/stm32f334/src/bin/pwm.rs
index 7c6d6cd71..e6d1a6c02 100644
--- a/examples/stm32f334/src/bin/pwm.rs
+++ b/examples/stm32f334/src/bin/pwm.rs
@@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) {
config.rcc.apb1_pre = APBPrescaler::DIV2;
config.rcc.apb2_pre = APBPrescaler::DIV1;
- config.rcc.mux.hrtim1sw = Some(embassy_stm32::rcc::mux::Timsw::PLL1_P);
+ config.rcc.mux.hrtim1sw = embassy_stm32::rcc::mux::Timsw::PLL1_P;
}
let p = embassy_stm32::init(config);
diff --git a/examples/stm32g0/src/bin/hf_timer.rs b/examples/stm32g0/src/bin/hf_timer.rs
index 3f63d0dfd..647ff0419 100644
--- a/examples/stm32g0/src/bin/hf_timer.rs
+++ b/examples/stm32g0/src/bin/hf_timer.rs
@@ -4,37 +4,35 @@
use defmt::info;
use embassy_executor::Spawner;
use embassy_stm32::gpio::OutputType;
-use embassy_stm32::pac::rcc::vals::Tim1sel;
-use embassy_stm32::rcc::{Config as RccConfig, PllConfig, PllSource, Pllm, Plln, Pllq, Pllr, Sysclk};
use embassy_stm32::time::khz;
use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, ComplementaryPwmPin};
use embassy_stm32::timer::simple_pwm::PwmPin;
use embassy_stm32::timer::Channel;
-use embassy_stm32::{pac, Config as PeripheralConfig};
+use embassy_stm32::Config as PeripheralConfig;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
- let mut rcc_config = RccConfig::default();
- rcc_config.sys = Sysclk::PLL(PllConfig {
- source: PllSource::HSI,
- m: Pllm::DIV1,
- n: Plln::MUL16,
- r: Pllr::DIV4, // CPU clock comes from PLLR (HSI (16MHz) / 1 * 16 / 4 = 64MHz)
- q: Some(Pllq::DIV2), // TIM1 or TIM15 can be sourced from PLLQ (HSI (16MHz) / 1 * 16 / 2 = 128MHz)
- p: None,
- });
+ let mut config = PeripheralConfig::default();
+ {
+ use embassy_stm32::rcc::*;
- let mut peripheral_config = PeripheralConfig::default();
- peripheral_config.rcc = rcc_config;
+ config.rcc.sys = Sysclk::PLL(PllConfig {
+ source: PllSource::HSI,
+ m: Pllm::DIV1,
+ n: Plln::MUL16,
+ r: Pllr::DIV4, // CPU clock comes from PLLR (HSI (16MHz) / 1 * 16 / 4 = 64MHz)
+ q: Some(Pllq::DIV2), // TIM1 or TIM15 can be sourced from PLLQ (HSI (16MHz) / 1 * 16 / 2 = 128MHz)
+ p: None,
+ });
- let p = embassy_stm32::init(peripheral_config);
-
- // configure TIM1 mux to select PLLQ as clock source
- // https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
- // RM0444 page 210
- // RCC - Peripherals Independent Clock Control Register - bit 22 -> 1
- pac::RCC.ccipr().modify(|w| w.set_tim1sel(Tim1sel::PLL1_Q));
+ // configure TIM1 mux to select PLLQ as clock source
+ // https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+ // RM0444 page 210
+ // RCC - Peripherals Independent Clock Control Register - bit 22 -> 1
+ config.rcc.mux.tim1sel = embassy_stm32::rcc::mux::Tim1sel::PLL1_Q;
+ }
+ let p = embassy_stm32::init(config);
let ch1 = PwmPin::new_ch1(p.PA8, OutputType::PushPull);
let ch1n = ComplementaryPwmPin::new_ch1(p.PA7, OutputType::PushPull);
diff --git a/examples/stm32g0/src/bin/usb_serial.rs b/examples/stm32g0/src/bin/usb_serial.rs
index f5aaa5624..8b9915626 100644
--- a/examples/stm32g0/src/bin/usb_serial.rs
+++ b/examples/stm32g0/src/bin/usb_serial.rs
@@ -4,7 +4,6 @@
use defmt::{panic, *};
use embassy_executor::Spawner;
use embassy_futures::join::join;
-use embassy_stm32::rcc::{Hsi48Config, UsbSrc};
use embassy_stm32::usb::{Driver, Instance};
use embassy_stm32::{bind_interrupts, peripherals, usb, Config};
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
@@ -19,10 +18,11 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
- config.rcc.usb_src = Some(UsbSrc::Hsi48(Hsi48Config {
- sync_from_usb: true,
- ..Default::default()
- }));
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true });
+ config.rcc.mux.usbsel = mux::Usbsel::HSI48;
+ }
let p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index 6c6de1ffe..f81335f93 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -4,7 +4,6 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
-use embassy_stm32::rcc::{AdcClockSource, Pll, PllMul, PllPreDiv, PllRDiv, Pllsrc, Sysclk};
use embassy_stm32::Config;
use embassy_time::{Delay, Timer};
use {defmt_rtt as _, panic_probe as _};
@@ -12,20 +11,20 @@ use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
-
- config.rcc.pll = Some(Pll {
- source: Pllsrc::HSI,
- prediv: PllPreDiv::DIV4,
- mul: PllMul::MUL85,
- divp: None,
- divq: None,
- // Main system clock at 170 MHz
- divr: Some(PllRDiv::DIV2),
- });
-
- config.rcc.adc12_clock_source = AdcClockSource::SYS;
- config.rcc.sys = Sysclk::PLL1_R;
-
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.pll = Some(Pll {
+ source: Pllsrc::HSI,
+ prediv: PllPreDiv::DIV4,
+ mul: PllMul::MUL85,
+ divp: None,
+ divq: None,
+ // Main system clock at 170 MHz
+ divr: Some(PllRDiv::DIV2),
+ });
+ config.rcc.mux.adc12sel = mux::Adcsel::SYS;
+ config.rcc.sys = Sysclk::PLL1_R;
+ }
let mut p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
index a41f765c1..7551b2a55 100644
--- a/examples/stm32g4/src/bin/can.rs
+++ b/examples/stm32g4/src/bin/can.rs
@@ -3,6 +3,7 @@
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::peripherals::*;
+use embassy_stm32::time::Hertz;
use embassy_stm32::{bind_interrupts, can, Config};
use embassy_time::Timer;
use static_cell::StaticCell;
@@ -15,8 +16,24 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
- let config = Config::default();
-
+ let mut config = Config::default();
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(24_000_000),
+ mode: HseMode::Oscillator,
+ });
+ config.rcc.pll = Some(Pll {
+ source: Pllsrc::HSE,
+ prediv: PllPreDiv::DIV6,
+ mul: PllMul::MUL85,
+ divp: None,
+ divq: Some(PllQDiv::DIV8), // 42.5 Mhz for fdcan.
+ divr: Some(PllRDiv::DIV2), // Main system clock at 170 MHz
+ });
+ config.rcc.mux.fdcansel = mux::Fdcansel::PLL1_Q;
+ config.rcc.sys = Sysclk::PLL1_R;
+ }
let peripherals = embassy_stm32::init(config);
let mut can = can::FdcanConfigurator::new(peripherals.FDCAN1, peripherals.PA11, peripherals.PA12, Irqs);
diff --git a/examples/stm32g4/src/bin/pll.rs b/examples/stm32g4/src/bin/pll.rs
index 5274de79d..2609abfa2 100644
--- a/examples/stm32g4/src/bin/pll.rs
+++ b/examples/stm32g4/src/bin/pll.rs
@@ -12,6 +12,7 @@ use {defmt_rtt as _, panic_probe as _};
async fn main(_spawner: Spawner) {
let mut config = Config::default();
+ config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: Pllsrc::HSI,
prediv: PllPreDiv::DIV4,
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index 989fef5b0..90caaae14 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -3,9 +3,6 @@
use defmt::{panic, *};
use embassy_executor::Spawner;
-use embassy_stm32::rcc::{
- Clk48Src, Hse, HseMode, Hsi48Config, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, Pllsrc, Sysclk,
-};
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{self, Driver, Instance};
use embassy_stm32::{bind_interrupts, peripherals, Config};
@@ -22,38 +19,27 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
-
- // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
- const USE_HSI48: bool = true;
-
- let plldivq = if USE_HSI48 { None } else { Some(PllQDiv::DIV6) };
-
- config.rcc.hse = Some(Hse {
- freq: Hertz(8_000_000),
- mode: HseMode::Oscillator,
- });
-
- config.rcc.pll = Some(Pll {
- source: Pllsrc::HSE,
- prediv: PllPreDiv::DIV2,
- mul: PllMul::MUL72,
- divp: None,
- divq: plldivq,
- // Main system clock at 144 MHz
- divr: Some(PllRDiv::DIV2),
- });
-
- config.rcc.sys = Sysclk::PLL1_R;
- config.rcc.boost = true; // BOOST!
-
- if USE_HSI48 {
+ {
+ use embassy_stm32::rcc::*;
// Sets up the Clock Recovery System (CRS) to use the USB SOF to trim the HSI48 oscillator.
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true });
- config.rcc.clk48_src = Clk48Src::HSI48;
- } else {
- config.rcc.clk48_src = Clk48Src::PLL1_Q;
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(8_000_000),
+ mode: HseMode::Oscillator,
+ });
+ config.rcc.pll = Some(Pll {
+ source: Pllsrc::HSE,
+ prediv: PllPreDiv::DIV2,
+ mul: PllMul::MUL72,
+ divp: None,
+ divq: Some(PllQDiv::DIV6), // 48mhz
+ divr: Some(PllRDiv::DIV2), // Main system clock at 144 MHz
+ });
+ config.rcc.sys = Sysclk::PLL1_R;
+ config.rcc.boost = true; // BOOST!
+ config.rcc.mux.clk48sel = mux::Clk48sel::HSI48;
+ //config.rcc.mux.clk48sel = mux::Clk48sel::PLL1_Q; // uncomment to use PLL1_Q instead.
}
-
let p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/examples/stm32h5/src/bin/can.rs b/examples/stm32h5/src/bin/can.rs
index e5ccfe4f7..643df27f9 100644
--- a/examples/stm32h5/src/bin/can.rs
+++ b/examples/stm32h5/src/bin/can.rs
@@ -20,7 +20,7 @@ async fn main(_spawner: Spawner) {
freq: embassy_stm32::time::Hertz(25_000_000),
mode: rcc::HseMode::Oscillator,
});
- config.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
+ config.rcc.mux.fdcan12sel = rcc::mux::Fdcansel::HSE;
let peripherals = embassy_stm32::init(config);
diff --git a/examples/stm32h5/src/bin/usb_serial.rs b/examples/stm32h5/src/bin/usb_serial.rs
index 208493d8c..83477c8fa 100644
--- a/examples/stm32h5/src/bin/usb_serial.rs
+++ b/examples/stm32h5/src/bin/usb_serial.rs
@@ -5,7 +5,7 @@ use defmt::{panic, *};
use embassy_executor::Spawner;
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{Driver, Instance};
-use embassy_stm32::{bind_interrupts, pac, peripherals, usb, Config};
+use embassy_stm32::{bind_interrupts, peripherals, usb, Config};
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
use embassy_usb::driver::EndpointError;
use embassy_usb::Builder;
@@ -41,15 +41,12 @@ async fn main(_spawner: Spawner) {
config.rcc.apb3_pre = APBPrescaler::DIV4;
config.rcc.sys = Sysclk::PLL1_P;
config.rcc.voltage_scale = VoltageScale::Scale0;
+ config.rcc.mux.usbsel = mux::Usbsel::HSI48;
}
let p = embassy_stm32::init(config);
info!("Hello World!");
- pac::RCC.ccipr4().write(|w| {
- w.set_usbsel(pac::rcc::vals::Usbsel::HSI48);
- });
-
// Create the driver, from the HAL.
let driver = Driver::new(p.USB, Irqs, p.PA12, p.PA11);
diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs
index f0278239f..a5594d10c 100644
--- a/examples/stm32h7/src/bin/adc.rs
+++ b/examples/stm32h7/src/bin/adc.rs
@@ -38,7 +38,7 @@ async fn main(_spawner: Spawner) {
config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.voltage_scale = VoltageScale::Scale1;
- config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+ config.rcc.mux.adcsel = mux::Adcsel::PLL2_P;
}
let mut p = embassy_stm32::init(config);
diff --git a/examples/stm32h7/src/bin/can.rs b/examples/stm32h7/src/bin/can.rs
index e5ccfe4f7..13a6a5051 100644
--- a/examples/stm32h7/src/bin/can.rs
+++ b/examples/stm32h7/src/bin/can.rs
@@ -20,7 +20,7 @@ async fn main(_spawner: Spawner) {
freq: embassy_stm32::time::Hertz(25_000_000),
mode: rcc::HseMode::Oscillator,
});
- config.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
+ config.rcc.mux.fdcansel = rcc::mux::Fdcansel::HSE;
let peripherals = embassy_stm32::init(config);
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
index a9bf46de0..a6f969aba 100644
--- a/examples/stm32h7/src/bin/dac.rs
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -40,7 +40,7 @@ fn main() -> ! {
config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.voltage_scale = VoltageScale::Scale1;
- config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+ config.rcc.mux.adcsel = mux::Adcsel::PLL2_P;
}
let p = embassy_stm32::init(config);
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs
index d88bd838f..feec28993 100644
--- a/examples/stm32h7/src/bin/dac_dma.rs
+++ b/examples/stm32h7/src/bin/dac_dma.rs
@@ -42,7 +42,7 @@ async fn main(spawner: Spawner) {
config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.voltage_scale = VoltageScale::Scale1;
- config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+ config.rcc.mux.adcsel = mux::Adcsel::PLL2_P;
}
// Initialize the board and obtain a Peripherals instance
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index 910944673..a9f4604aa 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -3,7 +3,7 @@
use defmt::*;
use embassy_stm32::adc::{Adc, Resolution};
-use embassy_stm32::pac;
+use embassy_stm32::Config;
use embassy_time::Delay;
use {defmt_rtt as _, panic_probe as _};
@@ -11,12 +11,12 @@ use {defmt_rtt as _, panic_probe as _};
fn main() -> ! {
info!("Hello World!");
- pac::RCC.ccipr().modify(|w| {
- w.set_adcsel(pac::rcc::vals::Adcsel::SYS);
- });
- pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
-
- let p = embassy_stm32::init(Default::default());
+ let mut config = Config::default();
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.mux.adcsel = mux::Adcsel::SYS;
+ }
+ let p = embassy_stm32::init(config);
let mut adc = Adc::new(p.ADC1, &mut Delay);
//adc.enable_vref();
diff --git a/tests/stm32/src/bin/fdcan.rs b/tests/stm32/src/bin/fdcan.rs
index f21aa797c..dd78d7fb3 100644
--- a/tests/stm32/src/bin/fdcan.rs
+++ b/tests/stm32/src/bin/fdcan.rs
@@ -33,7 +33,7 @@ fn options() -> TestOptions {
freq: embassy_stm32::time::Hertz(25_000_000),
mode: rcc::HseMode::Oscillator,
});
- c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
+ c.rcc.mux.fdcansel = rcc::mux::Fdcansel::HSE;
TestOptions {
config: c,
max_latency: Duration::from_micros(1200),
@@ -50,7 +50,7 @@ fn options() -> TestOptions {
freq: embassy_stm32::time::Hertz(25_000_000),
mode: rcc::HseMode::Oscillator,
});
- c.rcc.fdcan_clock_source = rcc::FdCanClockSource::HSE;
+ c.rcc.mux.fdcansel = rcc::mux::Fdcansel::HSE;
TestOptions {
config: c,
max_latency: Duration::from_micros(1200),
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 7b9585afd..cf3e04a4b 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -2,6 +2,8 @@
pub use defmt::*;
#[allow(unused)]
+use embassy_stm32::rcc::*;
+#[allow(unused)]
use embassy_stm32::time::Hertz;
use embassy_stm32::Config;
use {defmt_rtt as _, panic_probe as _};
@@ -265,7 +267,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32f091rc")]
{
- use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Bypass,
@@ -281,7 +282,6 @@ pub fn config() -> Config {
}
#[cfg(feature = "stm32f103c8")]
{
- use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Oscillator,
@@ -298,7 +298,6 @@ pub fn config() -> Config {
}
#[cfg(feature = "stm32f207zg")]
{
- use embassy_stm32::rcc::*;
// By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
@@ -327,7 +326,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32f303ze")]
{
- use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Bypass,
@@ -345,7 +343,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32f429zi")]
{
- use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Bypass,
@@ -366,7 +363,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32f446re")]
{
- use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Oscillator,
@@ -387,7 +383,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32f767zi")]
{
- use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Bypass,
@@ -408,7 +403,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32h563zi")]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = None;
config.rcc.hsi48 = Some(Default::default()); // needed for RNG
config.rcc.hse = Some(Hse {
@@ -433,7 +427,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32h503rb")]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = None;
config.rcc.hsi48 = Some(Default::default()); // needed for RNG
config.rcc.hse = Some(Hse {
@@ -456,9 +449,26 @@ pub fn config() -> Config {
config.rcc.voltage_scale = VoltageScale::Scale0;
}
+ #[cfg(feature = "stm32g491re")]
+ {
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(24_000_000),
+ mode: HseMode::Oscillator,
+ });
+ config.rcc.pll = Some(Pll {
+ source: Pllsrc::HSE,
+ prediv: PllPreDiv::DIV6,
+ mul: PllMul::MUL85,
+ divp: None,
+ divq: Some(PllQDiv::DIV8), // 42.5 Mhz for fdcan.
+ divr: Some(PllRDiv::DIV2), // Main system clock at 170 MHz
+ });
+ config.rcc.mux.fdcansel = mux::Fdcansel::PLL1_Q;
+ config.rcc.sys = Sysclk::PLL1_R;
+ }
+
#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = Some(HSIPrescaler::DIV1);
config.rcc.csi = true;
config.rcc.hsi48 = Some(Default::default()); // needed for RNG
@@ -485,7 +495,7 @@ pub fn config() -> Config {
config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
config.rcc.voltage_scale = VoltageScale::Scale1;
- config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+ config.rcc.mux.adcsel = mux::Adcsel::PLL2_P;
#[cfg(any(feature = "stm32h755zi"))]
{
config.rcc.supply_config = SupplyConfig::DirectSMPS;
@@ -494,7 +504,6 @@ pub fn config() -> Config {
#[cfg(any(feature = "stm32h7a3zi"))]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = Some(HSIPrescaler::DIV1);
config.rcc.csi = true;
config.rcc.hsi48 = Some(Default::default()); // needed for RNG
@@ -521,12 +530,11 @@ pub fn config() -> Config {
config.rcc.apb3_pre = APBPrescaler::DIV2; // 140 Mhz
config.rcc.apb4_pre = APBPrescaler::DIV2; // 140 Mhz
config.rcc.voltage_scale = VoltageScale::Scale0;
- config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
+ config.rcc.mux.adcsel = mux::Adcsel::PLL2_P;
}
#[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
{
- use embassy_stm32::rcc::*;
config.rcc.sys = Sysclk::PLL1_R;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
@@ -541,7 +549,6 @@ pub fn config() -> Config {
#[cfg(feature = "stm32wl55jc")]
{
- use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(32_000_000),
mode: HseMode::Bypass,
@@ -560,7 +567,6 @@ pub fn config() -> Config {
#[cfg(any(feature = "stm32l552ze"))]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = true;
config.rcc.sys = Sysclk::PLL1_R;
config.rcc.pll = Some(Pll {
@@ -576,7 +582,6 @@ pub fn config() -> Config {
#[cfg(any(feature = "stm32u585ai", feature = "stm32u5a5zj"))]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = true;
config.rcc.pll1 = Some(Pll {
source: PllSource::HSI, // 16 MHz
@@ -593,17 +598,12 @@ pub fn config() -> Config {
#[cfg(feature = "stm32wba52cg")]
{
- use embassy_stm32::rcc::*;
config.rcc.sys = Sysclk::HSI;
-
- embassy_stm32::pac::RCC.ccipr2().write(|w| {
- w.set_rngsel(embassy_stm32::pac::rcc::vals::Rngsel::HSI);
- });
+ config.rcc.mux.rngsel = mux::Rngsel::HSI;
}
#[cfg(feature = "stm32l073rz")]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PllSource::HSI,
@@ -615,7 +615,6 @@ pub fn config() -> Config {
#[cfg(any(feature = "stm32l152re"))]
{
- use embassy_stm32::rcc::*;
config.rcc.hsi = true;
config.rcc.pll = Some(Pll {
source: PllSource::HSI,
From df8f508ffa2bec79f6e3fba4ac3cfe0e5545b5b2 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 2 Mar 2024 09:00:54 +1000
Subject: [PATCH 360/392] Writing to TX buffer also needs to fire an interrupt
to kick off transmission if it is idle.
Formatting
---
embassy-stm32/src/can/fdcan.rs | 62 ++++++++++++++++++++++++++++++---
examples/stm32g4/src/bin/can.rs | 6 +++-
2 files changed, 63 insertions(+), 5 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 6a4a25cb7..77db774fc 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -436,7 +436,31 @@ pub struct BufferedCan<'d, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_S
}
/// Sender that can be used for sending CAN frames.
-pub type BufferedCanSender = embassy_sync::channel::DynamicSender<'static, ClassicFrame>;
+#[derive(Copy, Clone)]
+pub struct BufferedCanSender {
+ tx_buf: embassy_sync::channel::DynamicSender<'static, ClassicFrame>,
+ waker: fn(),
+}
+
+impl BufferedCanSender {
+ /// Async write frame to TX buffer.
+ pub fn try_write(&mut self, frame: ClassicFrame) -> Result<(), embassy_sync::channel::TrySendError<ClassicFrame>> {
+ self.tx_buf.try_send(frame)?;
+ (self.waker)();
+ Ok(())
+ }
+
+ /// Async write frame to TX buffer.
+ pub async fn write(&mut self, frame: ClassicFrame) {
+ self.tx_buf.send(frame).await;
+ (self.waker)();
+ }
+
+ /// Allows a poll_fn to poll until the channel is ready to write
+ pub fn poll_ready_to_send(&self, cx: &mut core::task::Context<'_>) -> core::task::Poll<()> {
+ self.tx_buf.poll_ready_to_send(cx)
+ }
+}
/// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
pub type BufferedCanReceiver = embassy_sync::channel::DynamicReceiver<'static, (ClassicFrame, Timestamp)>;
@@ -489,7 +513,10 @@ impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
/// Returns a sender that can be used for sending CAN frames.
pub fn writer(&self) -> BufferedCanSender {
- self.tx_buf.sender().into()
+ BufferedCanSender {
+ tx_buf: self.tx_buf.sender().into(),
+ waker: T::IT0Interrupt::pend,
+ }
}
/// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
@@ -525,7 +552,31 @@ pub struct BufferedCanFd<'d, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF
}
/// Sender that can be used for sending CAN frames.
-pub type BufferedFdCanSender = embassy_sync::channel::DynamicSender<'static, FdFrame>;
+#[derive(Copy, Clone)]
+pub struct BufferedFdCanSender {
+ tx_buf: embassy_sync::channel::DynamicSender<'static, FdFrame>,
+ waker: fn(),
+}
+
+impl BufferedFdCanSender {
+ /// Async write frame to TX buffer.
+ pub fn try_write(&mut self, frame: FdFrame) -> Result<(), embassy_sync::channel::TrySendError<FdFrame>> {
+ self.tx_buf.try_send(frame)?;
+ (self.waker)();
+ Ok(())
+ }
+
+ /// Async write frame to TX buffer.
+ pub async fn write(&mut self, frame: FdFrame) {
+ self.tx_buf.send(frame).await;
+ (self.waker)();
+ }
+
+ /// Allows a poll_fn to poll until the channel is ready to write
+ pub fn poll_ready_to_send(&self, cx: &mut core::task::Context<'_>) -> core::task::Poll<()> {
+ self.tx_buf.poll_ready_to_send(cx)
+ }
+}
/// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
pub type BufferedFdCanReceiver = embassy_sync::channel::DynamicReceiver<'static, (FdFrame, Timestamp)>;
@@ -578,7 +629,10 @@ impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
/// Returns a sender that can be used for sending CAN frames.
pub fn writer(&self) -> BufferedFdCanSender {
- self.tx_buf.sender().into()
+ BufferedFdCanSender {
+ tx_buf: self.tx_buf.sender().into(),
+ waker: T::IT0Interrupt::pend,
+ }
}
/// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
index a41f765c1..11e96361e 100644
--- a/examples/stm32g4/src/bin/can.rs
+++ b/examples/stm32g4/src/bin/can.rs
@@ -184,7 +184,11 @@ async fn main(_spawner: Spawner) {
let frame = can::frame::ClassicFrame::new_extended(0x123456F, &[i; 8]).unwrap();
info!("Writing frame");
- _ = can.write(frame).await;
+ // You can use any of these approaches to send. The writer makes it
+ // easy to share sending from multiple tasks.
+ //_ = can.write(frame).await;
+ //can.writer().try_write(frame).unwrap();
+ can.writer().write(frame).await;
match can.read().await {
Ok((rx_frame, ts)) => {
From 2c42463205dae7e38535fb18f58e872df99e125a Mon Sep 17 00:00:00 2001
From: Zheng Li <875543533@qq.com>
Date: Sat, 2 Mar 2024 00:21:56 +0100
Subject: [PATCH 361/392] executor: remove portable-atomic for riscv.
---
embassy-executor/Cargo.toml | 5 ++---
embassy-executor/src/arch/riscv32.rs | 2 +-
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/embassy-executor/Cargo.toml b/embassy-executor/Cargo.toml
index 409df0d75..431165cee 100644
--- a/embassy-executor/Cargo.toml
+++ b/embassy-executor/Cargo.toml
@@ -40,8 +40,7 @@ critical-section = "1.1"
document-features = "0.2.7"
-# needed for riscv and avr
-# remove when https://github.com/rust-lang/rust/pull/114499 lands on stable (on 1.76)
+# needed for AVR
portable-atomic = { version = "1.5", optional = true }
# arch-cortex-m dependencies
@@ -78,7 +77,7 @@ arch-std = ["_arch", "critical-section/std"]
## Cortex-M
arch-cortex-m = ["_arch", "dep:cortex-m"]
## RISC-V 32
-arch-riscv32 = ["_arch", "dep:portable-atomic"]
+arch-riscv32 = ["_arch"]
## WASM
arch-wasm = ["_arch", "dep:wasm-bindgen", "dep:js-sys"]
## AVR
diff --git a/embassy-executor/src/arch/riscv32.rs b/embassy-executor/src/arch/riscv32.rs
index c56f502d3..01e63a9fd 100644
--- a/embassy-executor/src/arch/riscv32.rs
+++ b/embassy-executor/src/arch/riscv32.rs
@@ -6,9 +6,9 @@ pub use thread::*;
#[cfg(feature = "executor-thread")]
mod thread {
use core::marker::PhantomData;
+ use core::sync::atomic::{AtomicBool, Ordering};
pub use embassy_executor_macros::main_riscv as main;
- use portable_atomic::{AtomicBool, Ordering};
use crate::{raw, Spawner};
From 30606f9782247b7f0e485b39042100ec3286aaa2 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Tue, 27 Feb 2024 14:59:02 +0000
Subject: [PATCH 362/392] stm32: can: fd: allow TX buffers in FIFO mode
---
embassy-stm32/src/can/fd/config.rs | 21 +++++++++++++++++++++
embassy-stm32/src/can/fd/peripheral.rs | 6 ++----
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index f2401d92f..e959913e4 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -287,6 +287,24 @@ impl Default for GlobalFilter {
}
}
+/// TX buffer operation mode
+#[derive(Clone, Copy, Debug)]
+pub enum TxBufferMode {
+ /// TX FIFO operation
+ Fifo,
+ /// TX queue operation
+ Queue,
+}
+
+impl From<TxBufferMode> for crate::pac::can::vals::Tfqm {
+ fn from(value: TxBufferMode) -> Self {
+ match value {
+ TxBufferMode::Queue => Self::QUEUE,
+ TxBufferMode::Fifo => Self::FIFO,
+ }
+ }
+}
+
/// FdCan Config Struct
#[derive(Clone, Copy, Debug)]
pub struct FdCanConfig {
@@ -327,6 +345,8 @@ pub struct FdCanConfig {
pub timestamp_source: TimestampSource,
/// Configures the Global Filter
pub global_filter: GlobalFilter,
+ /// TX buffer mode (FIFO or queue)
+ pub tx_buffer_mode: TxBufferMode,
}
impl FdCanConfig {
@@ -433,6 +453,7 @@ impl Default for FdCanConfig {
clock_divider: ClockDivider::_1,
timestamp_source: TimestampSource::None,
global_filter: GlobalFilter::default(),
+ tx_buffer_mode: TxBufferMode::Queue,
}
}
}
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index e87a3c213..0ebbdb3b7 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -302,10 +302,8 @@ impl Registers {
// Framework specific settings are set here
- // set TxBuffer to Queue Mode
- self.regs
- .txbc()
- .write(|w| w.set_tfqm(crate::pac::can::vals::Tfqm::QUEUE));
+ // set TxBuffer Mode
+ self.regs.txbc().write(|w| w.set_tfqm(_config.tx_buffer_mode.into()));
// set standard filters list size to 28
// set extended filters list size to 8
From befbb2845aebde5aa879bbe6dd0bdb08c277e492 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Wed, 28 Feb 2024 10:10:15 +0000
Subject: [PATCH 363/392] stm32: can: fd: write: if in TX FIFO mode & bufs
full, then abort
---
embassy-stm32/src/can/fd/config.rs | 11 ++++++++++-
embassy-stm32/src/can/fd/peripheral.rs | 21 ++++++++++++++-------
2 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index e959913e4..338e4979d 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -288,7 +288,7 @@ impl Default for GlobalFilter {
}
/// TX buffer operation mode
-#[derive(Clone, Copy, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub enum TxBufferMode {
/// TX FIFO operation
Fifo,
@@ -305,6 +305,15 @@ impl From<TxBufferMode> for crate::pac::can::vals::Tfqm {
}
}
+impl From<crate::pac::can::vals::Tfqm> for TxBufferMode {
+ fn from(value: crate::pac::can::vals::Tfqm) -> Self {
+ match value {
+ crate::pac::can::vals::Tfqm::QUEUE => Self::Queue,
+ crate::pac::can::vals::Tfqm::FIFO => Self::Fifo,
+ }
+ }
+}
+
/// FdCan Config Struct
#[derive(Clone, Copy, Debug)]
pub struct FdCanConfig {
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 0ebbdb3b7..2a183d2e8 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -114,6 +114,12 @@ impl Registers {
self.regs.txfqs().read().tfqf()
}
+ /// Returns the current TX buffer operation mode (queue or FIFO)
+ #[inline]
+ pub fn tx_queue_mode(&self) -> TxBufferMode {
+ self.regs.txbc().read().tfqm().into()
+ }
+
#[inline]
pub fn has_pending_frame(&self, idx: usize) -> bool {
self.regs.txbrp().read().trp(idx)
@@ -197,13 +203,14 @@ impl Registers {
}
pub fn write<F: embedded_can::Frame + CanHeader>(&self, frame: &F) -> nb::Result<Option<F>, Infallible> {
- let queue_is_full = self.tx_queue_is_full();
-
- let id = frame.header().id();
-
- // If the queue is full,
- // Discard the first slot with a lower priority message
- let (idx, pending_frame) = if queue_is_full {
+ let (idx, pending_frame) = if self.tx_queue_is_full() {
+ if self.tx_queue_mode() == TxBufferMode::Fifo {
+ // Does not make sense to cancel a pending frame when using FIFO
+ return Err(nb::Error::WouldBlock);
+ }
+ // If the queue is full,
+ // Discard the first slot with a lower priority message
+ let id = frame.header().id();
if self.is_available(0, id) {
(0, self.abort_pending_mailbox_generic(0))
} else if self.is_available(1, id) {
From 9e403fa89aae1d13948fcc15d1cc1f3c709dca88 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Wed, 28 Feb 2024 10:12:22 +0000
Subject: [PATCH 364/392] stm32: can: fd: rename abort_pending_mailbox, rm pub
qualifier
---
embassy-stm32/src/can/fd/peripheral.rs | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 2a183d2e8..3a95b2659 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -170,7 +170,7 @@ impl Registers {
}
#[inline]
- pub fn abort_pending_mailbox_generic<F: embedded_can::Frame>(&self, bufidx: usize) -> Option<F> {
+ fn abort_pending_mailbox<F: embedded_can::Frame>(&self, bufidx: usize) -> Option<F> {
if self.abort(bufidx) {
let mailbox = self.tx_buffer_element(bufidx);
@@ -212,11 +212,11 @@ impl Registers {
// Discard the first slot with a lower priority message
let id = frame.header().id();
if self.is_available(0, id) {
- (0, self.abort_pending_mailbox_generic(0))
+ (0, self.abort_pending_mailbox(0))
} else if self.is_available(1, id) {
- (1, self.abort_pending_mailbox_generic(1))
+ (1, self.abort_pending_mailbox(1))
} else if self.is_available(2, id) {
- (2, self.abort_pending_mailbox_generic(2))
+ (2, self.abort_pending_mailbox(2))
} else {
// For now we bail when there is no lower priority slot available
// Can this lead to priority inversion?
From bf06d10534fcf6e6f2fd34c1517500a59ed4b626 Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 2 Mar 2024 09:45:30 +1000
Subject: [PATCH 365/392] Delay setting TX buffer mode until user had a chance
to configure it.
---
embassy-stm32/src/can/fd/config.rs | 4 ++--
embassy-stm32/src/can/fd/peripheral.rs | 12 +++++++-----
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index 338e4979d..adaffe9cc 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -290,9 +290,9 @@ impl Default for GlobalFilter {
/// TX buffer operation mode
#[derive(Clone, Copy, PartialEq, Eq, Debug)]
pub enum TxBufferMode {
- /// TX FIFO operation
+ /// TX FIFO operation - In this mode CAN frames are trasmitted strictly in write order.
Fifo,
- /// TX queue operation
+ /// TX queue operation - In this mode CAN frames are transmitted according to CAN priority.
Queue,
}
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 3a95b2659..f0aab132b 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -307,11 +307,6 @@ impl Registers {
"Error reading endianness test value from FDCAN core"
);
- // Framework specific settings are set here
-
- // set TxBuffer Mode
- self.regs.txbc().write(|w| w.set_tfqm(_config.tx_buffer_mode.into()));
-
// set standard filters list size to 28
// set extended filters list size to 8
// REQUIRED: we use the memory map as if these settings are set
@@ -357,6 +352,7 @@ impl Registers {
/// Applies the settings of a new FdCanConfig See [`FdCanConfig`]
#[inline]
pub fn apply_config(&mut self, config: FdCanConfig) {
+ self.set_tx_buffer_mode(config.tx_buffer_mode);
self.set_data_bit_timing(config.dbtr);
self.set_nominal_bit_timing(config.nbtr);
self.set_automatic_retransmit(config.automatic_retransmit);
@@ -504,6 +500,12 @@ impl Registers {
self.regs.cccr().modify(|w| w.set_efbi(enabled));
}
+ /// Configures TX Buffer Mode
+ #[inline]
+ pub fn set_tx_buffer_mode(&mut self, tbm: TxBufferMode) {
+ self.regs.txbc().write(|w| w.set_tfqm(tbm.into()));
+ }
+
/// Configures frame transmission mode. See
/// [`FdCanConfig::set_frame_transmit`]
#[inline]
From b693ab9b34fad5844401bc80b9968940e750680e Mon Sep 17 00:00:00 2001
From: Corey Schuhen <cschuhen@gmail.com>
Date: Sat, 2 Mar 2024 12:57:03 +1000
Subject: [PATCH 366/392] Restore init order to restore H7.
Previous commit broke H7 support in HIL farm. Restore previous order by moving a bunch of config from new and into_config_mode to apply_config.
This is a cleanup that I had considered to move more register access into peripheral.rs.
---
embassy-stm32/src/can/fd/peripheral.rs | 133 +++++++++++++++++++++----
embassy-stm32/src/can/fdcan.rs | 92 +----------------
2 files changed, 113 insertions(+), 112 deletions(-)
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index f0aab132b..8ec09ac12 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -22,6 +22,7 @@ enum LoopbackMode {
pub struct Registers {
pub regs: &'static crate::pac::can::Fdcan,
pub msgram: &'static crate::pac::fdcanram::Fdcanram,
+ pub msg_ram_offset: usize,
}
impl Registers {
@@ -294,7 +295,6 @@ impl Registers {
pub fn into_config_mode(mut self, _config: FdCanConfig) {
self.set_power_down_mode(false);
self.enter_init_mode();
-
self.reset_msg_ram();
// check the FDCAN core matches our expections
@@ -307,27 +307,6 @@ impl Registers {
"Error reading endianness test value from FDCAN core"
);
- // set standard filters list size to 28
- // set extended filters list size to 8
- // REQUIRED: we use the memory map as if these settings are set
- // instead of re-calculating them.
- #[cfg(not(stm32h7))]
- {
- self.regs.rxgfc().modify(|w| {
- w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX);
- w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX);
- });
- }
- #[cfg(stm32h7)]
- {
- self.regs
- .sidfc()
- .modify(|w| w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX));
- self.regs
- .xidfc()
- .modify(|w| w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX));
- }
-
/*
for fid in 0..crate::can::message_ram::STANDARD_FILTER_MAX {
self.set_standard_filter((fid as u8).into(), StandardFilter::disable());
@@ -353,6 +332,51 @@ impl Registers {
#[inline]
pub fn apply_config(&mut self, config: FdCanConfig) {
self.set_tx_buffer_mode(config.tx_buffer_mode);
+
+ // set standard filters list size to 28
+ // set extended filters list size to 8
+ // REQUIRED: we use the memory map as if these settings are set
+ // instead of re-calculating them.
+ #[cfg(not(stm32h7))]
+ {
+ self.regs.rxgfc().modify(|w| {
+ w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX);
+ w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX);
+ });
+ }
+ #[cfg(stm32h7)]
+ {
+ self.regs
+ .sidfc()
+ .modify(|w| w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX));
+ self.regs
+ .xidfc()
+ .modify(|w| w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX));
+ }
+
+ self.configure_msg_ram();
+
+ // Enable timestamping
+ #[cfg(not(stm32h7))]
+ self.regs
+ .tscc()
+ .write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
+ #[cfg(stm32h7)]
+ self.regs.tscc().write(|w| w.set_tss(0x01));
+
+ // this isn't really documented in the reference manual
+ // but corresponding txbtie bit has to be set for the TC (TxComplete) interrupt to fire
+ self.regs.txbtie().write(|w| w.0 = 0xffff_ffff);
+ self.regs.ie().modify(|w| {
+ w.set_rfne(0, true); // Rx Fifo 0 New Msg
+ w.set_rfne(1, true); // Rx Fifo 1 New Msg
+ w.set_tce(true); // Tx Complete
+ });
+ self.regs.ile().modify(|w| {
+ w.set_eint0(true); // Interrupt Line 0
+ w.set_eint1(true); // Interrupt Line 1
+ });
+
self.set_data_bit_timing(config.dbtr);
self.set_nominal_bit_timing(config.nbtr);
self.set_automatic_retransmit(config.automatic_retransmit);
@@ -600,6 +624,71 @@ impl Registers {
w.set_rrfe(filter.reject_remote_extended_frames);
});
}
+
+ #[cfg(not(stm32h7))]
+ fn configure_msg_ram(&mut self) {}
+
+ #[cfg(stm32h7)]
+ fn configure_msg_ram(&mut self) {
+ let r = self.regs;
+
+ use crate::can::fd::message_ram::*;
+ //use fdcan::message_ram::*;
+ let mut offset_words = self.msg_ram_offset as u16;
+
+ // 11-bit filter
+ r.sidfc().modify(|w| w.set_flssa(offset_words));
+ offset_words += STANDARD_FILTER_MAX as u16;
+
+ // 29-bit filter
+ r.xidfc().modify(|w| w.set_flesa(offset_words));
+ offset_words += 2 * EXTENDED_FILTER_MAX as u16;
+
+ // Rx FIFO 0 and 1
+ for i in 0..=1 {
+ r.rxfc(i).modify(|w| {
+ w.set_fsa(offset_words);
+ w.set_fs(RX_FIFO_MAX);
+ w.set_fwm(RX_FIFO_MAX);
+ });
+ offset_words += 18 * RX_FIFO_MAX as u16;
+ }
+
+ // Rx buffer - see below
+ // Tx event FIFO
+ r.txefc().modify(|w| {
+ w.set_efsa(offset_words);
+ w.set_efs(TX_EVENT_MAX);
+ w.set_efwm(TX_EVENT_MAX);
+ });
+ offset_words += 2 * TX_EVENT_MAX as u16;
+
+ // Tx buffers
+ r.txbc().modify(|w| {
+ w.set_tbsa(offset_words);
+ w.set_tfqs(TX_FIFO_MAX);
+ });
+ offset_words += 18 * TX_FIFO_MAX as u16;
+
+ // Rx Buffer - not used
+ r.rxbc().modify(|w| {
+ w.set_rbsa(offset_words);
+ });
+
+ // TX event FIFO?
+ // Trigger memory?
+
+ // Set the element sizes to 16 bytes
+ r.rxesc().modify(|w| {
+ w.set_rbds(0b111);
+ for i in 0..=1 {
+ w.set_fds(i, 0b111);
+ }
+ });
+ r.txesc().modify(|w| {
+ w.set_tbds(0b111);
+ })
+ }
}
fn make_id(id: u32, extended: bool) -> embedded_can::Id {
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 77db774fc..20d00ccb5 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -184,43 +184,20 @@ impl<'d, T: Instance> FdcanConfigurator<'d, T> {
T::enable_and_reset();
let mut config = crate::can::fd::config::FdCanConfig::default();
+ config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
T::registers().into_config_mode(config);
rx.set_as_af(rx.af_num(), AFType::Input);
tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
- T::configure_msg_ram();
unsafe {
- // Enable timestamping
- #[cfg(not(stm32h7))]
- T::regs()
- .tscc()
- .write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
- #[cfg(stm32h7)]
- T::regs().tscc().write(|w| w.set_tss(0x01));
- config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
-
T::IT0Interrupt::unpend(); // Not unsafe
T::IT0Interrupt::enable();
T::IT1Interrupt::unpend(); // Not unsafe
T::IT1Interrupt::enable();
-
- // this isn't really documented in the reference manual
- // but corresponding txbtie bit has to be set for the TC (TxComplete) interrupt to fire
- T::regs().txbtie().write(|w| w.0 = 0xffff_ffff);
}
- T::regs().ie().modify(|w| {
- w.set_rfne(0, true); // Rx Fifo 0 New Msg
- w.set_rfne(1, true); // Rx Fifo 1 New Msg
- w.set_tce(true); // Tx Complete
- });
- T::regs().ile().modify(|w| {
- w.set_eint0(true); // Interrupt Line 0
- w.set_eint1(true); // Interrupt Line 1
- });
-
Self {
config,
instance: FdcanInstance(peri),
@@ -869,71 +846,6 @@ pub(crate) mod sealed {
fn state() -> &'static State;
unsafe fn mut_state() -> &'static mut State;
fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp;
-
- #[cfg(not(stm32h7))]
- fn configure_msg_ram() {}
-
- #[cfg(stm32h7)]
- fn configure_msg_ram() {
- let r = Self::regs();
-
- use crate::can::fd::message_ram::*;
- //use fdcan::message_ram::*;
- let mut offset_words = Self::MSG_RAM_OFFSET as u16;
-
- // 11-bit filter
- r.sidfc().modify(|w| w.set_flssa(offset_words));
- offset_words += STANDARD_FILTER_MAX as u16;
-
- // 29-bit filter
- r.xidfc().modify(|w| w.set_flesa(offset_words));
- offset_words += 2 * EXTENDED_FILTER_MAX as u16;
-
- // Rx FIFO 0 and 1
- for i in 0..=1 {
- r.rxfc(i).modify(|w| {
- w.set_fsa(offset_words);
- w.set_fs(RX_FIFO_MAX);
- w.set_fwm(RX_FIFO_MAX);
- });
- offset_words += 18 * RX_FIFO_MAX as u16;
- }
-
- // Rx buffer - see below
- // Tx event FIFO
- r.txefc().modify(|w| {
- w.set_efsa(offset_words);
- w.set_efs(TX_EVENT_MAX);
- w.set_efwm(TX_EVENT_MAX);
- });
- offset_words += 2 * TX_EVENT_MAX as u16;
-
- // Tx buffers
- r.txbc().modify(|w| {
- w.set_tbsa(offset_words);
- w.set_tfqs(TX_FIFO_MAX);
- });
- offset_words += 18 * TX_FIFO_MAX as u16;
-
- // Rx Buffer - not used
- r.rxbc().modify(|w| {
- w.set_rbsa(offset_words);
- });
-
- // TX event FIFO?
- // Trigger memory?
-
- // Set the element sizes to 16 bytes
- r.rxesc().modify(|w| {
- w.set_rbds(0b111);
- for i in 0..=1 {
- w.set_fds(i, 0b111);
- }
- });
- r.txesc().modify(|w| {
- w.set_tbds(0b111);
- })
- }
}
}
@@ -957,7 +869,7 @@ macro_rules! impl_fdcan {
&crate::pac::$inst
}
fn registers() -> Registers {
- Registers{regs: &crate::pac::$inst, msgram: &crate::pac::$msg_ram_inst}
+ Registers{regs: &crate::pac::$inst, msgram: &crate::pac::$msg_ram_inst, msg_ram_offset: Self::MSG_RAM_OFFSET}
}
fn ram() -> &'static crate::pac::fdcanram::Fdcanram {
&crate::pac::$msg_ram_inst
From 69d37503c22be73c3d8283f39155cfa1559a37eb Mon Sep 17 00:00:00 2001
From: Peter Krull <peterkrullpeter@gmail.com>
Date: Sat, 2 Mar 2024 13:13:26 +0100
Subject: [PATCH 367/392] Add constructor for dynamic channel
---
embassy-sync/src/channel.rs | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/embassy-sync/src/channel.rs b/embassy-sync/src/channel.rs
index ff7129303..01db0d09a 100644
--- a/embassy-sync/src/channel.rs
+++ b/embassy-sync/src/channel.rs
@@ -507,6 +507,16 @@ where
Receiver { channel: self }
}
+ /// Get a sender for this channel using dynamic dispatch.
+ pub fn dyn_sender(&self) -> DynamicSender<'_, T> {
+ DynamicSender { channel: self }
+ }
+
+ /// Get a receiver for this channel using dynamic dispatch.
+ pub fn dyn_receiver(&self) -> DynamicReceiver<'_, T> {
+ DynamicReceiver { channel: self }
+ }
+
/// Send a value, waiting until there is capacity.
///
/// Sending completes when the value has been pushed to the channel's queue.
@@ -648,7 +658,7 @@ mod tests {
}
#[test]
- fn dynamic_dispatch() {
+ fn dynamic_dispatch_into() {
let c = Channel::<NoopRawMutex, u32, 3>::new();
let s: DynamicSender<'_, u32> = c.sender().into();
let r: DynamicReceiver<'_, u32> = c.receiver().into();
@@ -657,6 +667,16 @@ mod tests {
assert_eq!(r.try_receive().unwrap(), 1);
}
+ #[test]
+ fn dynamic_dispatch_constructor() {
+ let c = Channel::<NoopRawMutex, u32, 3>::new();
+ let s = c.dyn_sender();
+ let r = c.dyn_receiver();
+
+ assert!(s.try_send(1).is_ok());
+ assert_eq!(r.try_receive().unwrap(), 1);
+ }
+
#[futures_test::test]
async fn receiver_receives_given_try_send_async() {
let executor = ThreadPool::new().unwrap();
From 047b20cee42e4438bcf054c4f94812c4895508e7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Sun, 3 Mar 2024 01:12:08 +0100
Subject: [PATCH 368/392] Export Error in BLE module
---
embassy-nrf/src/radio/ble.rs | 1 +
1 file changed, 1 insertion(+)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index ecf8cc5eb..93c701de0 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -12,6 +12,7 @@ use pac::radio::state::STATE_A as RadioState;
pub use pac::radio::txpower::TXPOWER_A as TxPower;
use crate::interrupt::typelevel::Interrupt;
+pub use crate::radio::Error;
use crate::radio::*;
use crate::util::slice_in_ram_or;
From 0c4c996339ea7e70f40b0ad77a8850728ef9dcf8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Sun, 3 Mar 2024 02:15:16 +0100
Subject: [PATCH 369/392] Fixed formatting
---
embassy-nrf/src/radio/ieee802154.rs | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
index 32951421b..91c6dbd3b 100644
--- a/embassy-nrf/src/radio/ieee802154.rs
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -3,15 +3,15 @@
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
-use super::{Error, Instance, InterruptHandler};
-use crate::{
- interrupt::{self, typelevel::Interrupt},
- pac, Peripheral,
-};
-use pac::radio::{state::STATE_A as RadioState, txpower::TXPOWER_A as TxPower};
-
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
+use pac::radio::state::STATE_A as RadioState;
+use pac::radio::txpower::TXPOWER_A as TxPower;
+
+use super::{Error, Instance, InterruptHandler};
+use crate::interrupt::typelevel::Interrupt;
+use crate::interrupt::{self};
+use crate::{pac, Peripheral};
/// Default Start of Frame Delimiter = `0xA7` (IEEE compliant)
pub const DEFAULT_SFD: u8 = 0xA7;
From b4567bb8c56dced1c64177d727ebb32ee4680ea3 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sun, 3 Mar 2024 23:18:29 +0100
Subject: [PATCH 370/392] stm32/rcc: g4: consistent PllSource, add pll pqr
limits, simplify a bit.
---
embassy-stm32/src/rcc/g4.rs | 206 +++++++++++++------------
examples/stm32g4/src/bin/adc.rs | 2 +-
examples/stm32g4/src/bin/can.rs | 2 +-
examples/stm32g4/src/bin/pll.rs | 29 ++--
examples/stm32g4/src/bin/usb_serial.rs | 2 +-
tests/stm32/src/common.rs | 2 +-
6 files changed, 123 insertions(+), 120 deletions(-)
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index 79bdbeb77..cd2d2a8a2 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -1,12 +1,9 @@
-use stm32_metapac::flash::vals::Latency;
-use stm32_metapac::rcc::vals::Sw;
-use stm32_metapac::FLASH;
-
+use crate::pac::flash::vals::Latency;
pub use crate::pac::rcc::vals::{
- Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc,
- Ppre as APBPrescaler, Sw as Sysclk,
+ Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
+ Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
};
-use crate::pac::{PWR, RCC};
+use crate::pac::{FLASH, PWR, RCC};
use crate::time::Hertz;
/// HSI speed
@@ -37,7 +34,7 @@ pub struct Hse {
/// frequency ranges for each of these settings.
pub struct Pll {
/// PLL Source clock selection.
- pub source: Pllsrc,
+ pub source: PllSource,
/// PLL pre-divider
pub prediv: PllPreDiv,
@@ -73,7 +70,7 @@ pub struct Config {
/// PLL Configuration
pub pll: Option<Pll>,
- /// Iff PLL is requested as the main clock source in the `mux` field then the PLL configuration
+ /// If PLL is requested as the main clock source in the `sys` field then the PLL configuration
/// MUST turn on the PLLR output.
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
@@ -112,6 +109,7 @@ impl Default for Config {
}
}
+#[derive(Default)]
pub struct PllFreq {
pub pll_p: Option<Hertz>,
pub pll_q: Option<Hertz>,
@@ -154,91 +152,91 @@ pub(crate) unsafe fn init(config: Config) {
// Configure HSI48 if required
let hsi48 = config.hsi48.map(super::init_hsi48);
- let pll_freq = config.pll.map(|pll_config| {
- let src_freq = match pll_config.source {
- Pllsrc::HSI => unwrap!(hsi),
- Pllsrc::HSE => unwrap!(hse),
- _ => unreachable!(),
- };
+ let pll = config
+ .pll
+ .map(|pll_config| {
+ let src_freq = match pll_config.source {
+ PllSource::HSI => unwrap!(hsi),
+ PllSource::HSE => unwrap!(hse),
+ _ => unreachable!(),
+ };
- // Disable PLL before configuration
- RCC.cr().modify(|w| w.set_pllon(false));
- while RCC.cr().read().pllrdy() {}
+ // Disable PLL before configuration
+ RCC.cr().modify(|w| w.set_pllon(false));
+ while RCC.cr().read().pllrdy() {}
- let in_freq = src_freq / pll_config.prediv;
- assert!(max::PLL_IN.contains(&in_freq));
- let internal_freq = in_freq * pll_config.mul;
+ let in_freq = src_freq / pll_config.prediv;
+ assert!(max::PLL_IN.contains(&in_freq));
+ let internal_freq = in_freq * pll_config.mul;
- assert!(max::PLL_VCO.contains(&internal_freq));
+ assert!(max::PLL_VCO.contains(&internal_freq));
- RCC.pllcfgr().write(|w| {
- w.set_plln(pll_config.mul);
- w.set_pllm(pll_config.prediv);
- w.set_pllsrc(pll_config.source.into());
- });
-
- let pll_p_freq = pll_config.divp.map(|div_p| {
- RCC.pllcfgr().modify(|w| {
- w.set_pllp(div_p);
- w.set_pllpen(true);
+ RCC.pllcfgr().write(|w| {
+ w.set_plln(pll_config.mul);
+ w.set_pllm(pll_config.prediv);
+ w.set_pllsrc(pll_config.source.into());
});
- let freq = internal_freq / div_p;
- assert!(max::PCLK.contains(&freq));
- freq
- });
- let pll_q_freq = pll_config.divq.map(|div_q| {
- RCC.pllcfgr().modify(|w| {
- w.set_pllq(div_q);
- w.set_pllqen(true);
+ let pll_p_freq = pll_config.divp.map(|div_p| {
+ RCC.pllcfgr().modify(|w| {
+ w.set_pllp(div_p);
+ w.set_pllpen(true);
+ });
+ let freq = internal_freq / div_p;
+ assert!(max::PLL_P.contains(&freq));
+ freq
});
- let freq = internal_freq / div_q;
- assert!(max::PCLK.contains(&freq));
- freq
- });
- let pll_r_freq = pll_config.divr.map(|div_r| {
- RCC.pllcfgr().modify(|w| {
- w.set_pllr(div_r);
- w.set_pllren(true);
+ let pll_q_freq = pll_config.divq.map(|div_q| {
+ RCC.pllcfgr().modify(|w| {
+ w.set_pllq(div_q);
+ w.set_pllqen(true);
+ });
+ let freq = internal_freq / div_q;
+ assert!(max::PLL_Q.contains(&freq));
+ freq
});
- let freq = internal_freq / div_r;
- assert!(max::PCLK.contains(&freq));
- freq
- });
- // Enable the PLL
- RCC.cr().modify(|w| w.set_pllon(true));
- while !RCC.cr().read().pllrdy() {}
+ let pll_r_freq = pll_config.divr.map(|div_r| {
+ RCC.pllcfgr().modify(|w| {
+ w.set_pllr(div_r);
+ w.set_pllren(true);
+ });
+ let freq = internal_freq / div_r;
+ assert!(max::PLL_R.contains(&freq));
+ freq
+ });
- PllFreq {
- pll_p: pll_p_freq,
- pll_q: pll_q_freq,
- pll_r: pll_r_freq,
- }
- });
+ // Enable the PLL
+ RCC.cr().modify(|w| w.set_pllon(true));
+ while !RCC.cr().read().pllrdy() {}
- let (sys_clk, sw) = match config.sys {
- Sysclk::HSI => (HSI_FREQ, Sw::HSI),
- Sysclk::HSE => (unwrap!(hse), Sw::HSE),
- Sysclk::PLL1_R => {
- assert!(pll_freq.is_some());
- assert!(pll_freq.as_ref().unwrap().pll_r.is_some());
+ PllFreq {
+ pll_p: pll_p_freq,
+ pll_q: pll_q_freq,
+ pll_r: pll_r_freq,
+ }
+ })
+ .unwrap_or_default();
- let freq = pll_freq.as_ref().unwrap().pll_r.unwrap().0;
-
- assert!(max::SYSCLK.contains(&Hertz(freq)));
-
- (Hertz(freq), Sw::PLL1_R)
- }
+ let sys = match config.sys {
+ Sysclk::HSI => unwrap!(hsi),
+ Sysclk::HSE => unwrap!(hse),
+ Sysclk::PLL1_R => unwrap!(pll.pll_r),
_ => unreachable!(),
};
- // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
- let hclk = sys_clk / config.ahb_pre;
+ assert!(max::SYSCLK.contains(&sys));
+ // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
+ let hclk = sys / config.ahb_pre;
assert!(max::HCLK.contains(&hclk));
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+ let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
+ assert!(max::PCLK.contains(&pclk2));
+ assert!(max::PCLK.contains(&pclk2));
+
// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
if config.boost {
// RM0440 p235
@@ -253,23 +251,28 @@ pub(crate) unsafe fn init(config: Config) {
// 4. Configure and switch to new frequency
}
+ let latency = match (config.boost, hclk.0) {
+ (true, ..=34_000_000) => Latency::WS0,
+ (true, ..=68_000_000) => Latency::WS1,
+ (true, ..=102_000_000) => Latency::WS2,
+ (true, ..=136_000_000) => Latency::WS3,
+ (true, _) => Latency::WS4,
+
+ (false, ..=36_000_000) => Latency::WS0,
+ (false, ..=60_000_000) => Latency::WS1,
+ (false, ..=90_000_000) => Latency::WS2,
+ (false, ..=120_000_000) => Latency::WS3,
+ (false, _) => Latency::WS4,
+ };
+
// Configure flash read access latency based on boost mode and frequency (RM0440 p98)
FLASH.acr().modify(|w| {
- w.set_latency(match (config.boost, hclk.0) {
- (true, ..=34_000_000) => Latency::WS0,
- (true, ..=68_000_000) => Latency::WS1,
- (true, ..=102_000_000) => Latency::WS2,
- (true, ..=136_000_000) => Latency::WS3,
- (true, _) => Latency::WS4,
-
- (false, ..=36_000_000) => Latency::WS0,
- (false, ..=60_000_000) => Latency::WS1,
- (false, ..=90_000_000) => Latency::WS2,
- (false, ..=120_000_000) => Latency::WS3,
- (false, _) => Latency::WS4,
- })
+ w.set_latency(latency);
});
+ // Spin until the effective flash latency is set.
+ while FLASH.acr().read().latency() != latency {}
+
if config.boost {
// 5. Wait for at least 1us and then reconfigure the AHB prescaler to get the needed HCLK clock frequency.
cortex_m::asm::delay(16);
@@ -277,17 +280,14 @@ pub(crate) unsafe fn init(config: Config) {
// Now that boost mode and flash read access latency are configured, set up SYSCLK
RCC.cfgr().modify(|w| {
- w.set_sw(sw);
+ w.set_sw(config.sys);
w.set_hpre(config.ahb_pre);
w.set_ppre1(config.apb1_pre);
w.set_ppre2(config.apb2_pre);
});
- let (apb1_freq, apb1_tim_freq) = super::util::calc_pclk(hclk, config.apb1_pre);
- let (apb2_freq, apb2_tim_freq) = super::util::calc_pclk(hclk, config.apb2_pre);
-
if config.low_power_run {
- assert!(sys_clk <= Hertz(2_000_000));
+ assert!(sys <= Hertz(2_000_000));
PWR.cr1().modify(|w| w.set_lpr(true));
}
@@ -296,17 +296,18 @@ pub(crate) unsafe fn init(config: Config) {
config.mux.init();
set_clocks!(
- sys: Some(sys_clk),
+ sys: Some(sys),
hclk1: Some(hclk),
hclk2: Some(hclk),
hclk3: Some(hclk),
- pclk1: Some(apb1_freq),
- pclk1_tim: Some(apb1_tim_freq),
- pclk2: Some(apb2_freq),
- pclk2_tim: Some(apb2_tim_freq),
- pll1_p: pll_freq.as_ref().and_then(|pll| pll.pll_p),
- pll1_q: pll_freq.as_ref().and_then(|pll| pll.pll_q),
- pll1_r: pll_freq.as_ref().and_then(|pll| pll.pll_r),
+ pclk1: Some(pclk1),
+ pclk1_tim: Some(pclk1_tim),
+ pclk2: Some(pclk2),
+ pclk2_tim: Some(pclk2_tim),
+ pll1_p: pll.pll_p,
+ pll1_q: pll.pll_q,
+ pll1_r: pll.pll_r,
+ hsi: hsi,
hse: hse,
hsi48: hsi48,
rtc: rtc,
@@ -342,4 +343,7 @@ mod max {
/// PLL VCO (internal) Frequency Range (STM32G474 Datasheet p123, Table 46)
pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(96_000_000)..=Hertz(344_000_000);
+ pub(crate) const PLL_P: RangeInclusive<Hertz> = Hertz(2_064_500)..=Hertz(170_000_000);
+ pub(crate) const PLL_Q: RangeInclusive<Hertz> = Hertz(8_000_000)..=Hertz(170_000_000);
+ pub(crate) const PLL_R: RangeInclusive<Hertz> = Hertz(8_000_000)..=Hertz(170_000_000);
}
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index f81335f93..ae64bc8e4 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
{
use embassy_stm32::rcc::*;
config.rcc.pll = Some(Pll {
- source: Pllsrc::HSI,
+ source: PllSource::HSI,
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL85,
divp: None,
diff --git a/examples/stm32g4/src/bin/can.rs b/examples/stm32g4/src/bin/can.rs
index 93b206de8..4373a89a8 100644
--- a/examples/stm32g4/src/bin/can.rs
+++ b/examples/stm32g4/src/bin/can.rs
@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
mode: HseMode::Oscillator,
});
config.rcc.pll = Some(Pll {
- source: Pllsrc::HSE,
+ source: PllSource::HSE,
prediv: PllPreDiv::DIV6,
mul: PllMul::MUL85,
divp: None,
diff --git a/examples/stm32g4/src/bin/pll.rs b/examples/stm32g4/src/bin/pll.rs
index 2609abfa2..08ed95b34 100644
--- a/examples/stm32g4/src/bin/pll.rs
+++ b/examples/stm32g4/src/bin/pll.rs
@@ -3,7 +3,6 @@
use defmt::*;
use embassy_executor::Spawner;
-use embassy_stm32::rcc::{Pll, PllMul, PllPreDiv, PllRDiv, Pllsrc, Sysclk};
use embassy_stm32::Config;
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};
@@ -11,20 +10,20 @@ use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
-
- config.rcc.hsi = true;
- config.rcc.pll = Some(Pll {
- source: Pllsrc::HSI,
- prediv: PllPreDiv::DIV4,
- mul: PllMul::MUL85,
- divp: None,
- divq: None,
- // Main system clock at 170 MHz
- divr: Some(PllRDiv::DIV2),
- });
-
- config.rcc.sys = Sysclk::PLL1_R;
-
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hsi = true;
+ config.rcc.pll = Some(Pll {
+ source: PllSource::HSI,
+ prediv: PllPreDiv::DIV4,
+ mul: PllMul::MUL85,
+ divp: None,
+ divq: None,
+ // Main system clock at 170 MHz
+ divr: Some(PllRDiv::DIV2),
+ });
+ config.rcc.sys = Sysclk::PLL1_R;
+ }
let _p = embassy_stm32::init(config);
info!("Hello World!");
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index 90caaae14..dc95aa6e5 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) {
mode: HseMode::Oscillator,
});
config.rcc.pll = Some(Pll {
- source: Pllsrc::HSE,
+ source: PllSource::HSE,
prediv: PllPreDiv::DIV2,
mul: PllMul::MUL72,
divp: None,
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index cf3e04a4b..c3f39c04f 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -456,7 +456,7 @@ pub fn config() -> Config {
mode: HseMode::Oscillator,
});
config.rcc.pll = Some(Pll {
- source: Pllsrc::HSE,
+ source: PllSource::HSE,
prediv: PllPreDiv::DIV6,
mul: PllMul::MUL85,
divp: None,
From c8c4b0b701ecfbb146c6f651bebd43f053f55ac2 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Sun, 3 Mar 2024 23:19:54 +0100
Subject: [PATCH 371/392] stm32/rcc: port g0 to new api.
---
embassy-stm32/src/rcc/g0.rs | 512 +++++++++++++--------------
examples/stm32g0/src/bin/hf_timer.rs | 15 +-
tests/stm32/src/common.rs | 13 +
3 files changed, 264 insertions(+), 276 deletions(-)
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 5cfe9953b..ea4422ccc 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -1,7 +1,8 @@
use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::{self, Sw};
+pub use crate::pac::pwr::vals::Vos as VoltageRange;
pub use crate::pac::rcc::vals::{
- Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Pllm, Plln, Pllp, Pllq, Pllr, Ppre as APBPrescaler,
+ Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
+ Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
};
use crate::pac::{FLASH, PWR, RCC};
use crate::time::Hertz;
@@ -9,6 +10,7 @@ use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
+/// HSE Mode
#[derive(Clone, Copy, Eq, PartialEq)]
pub enum HseMode {
/// crystal/ceramic oscillator (HSEBYP=0)
@@ -17,69 +19,71 @@ pub enum HseMode {
Bypass,
}
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum Sysclk {
- HSE(Hertz, HseMode),
- HSI(HSIPrescaler),
- PLL(PllConfig),
- LSI,
-}
-
-/// The PLL configuration.
-///
-/// * `VCOCLK = source / m * n`
-/// * `PLLRCLK = VCOCLK / r`
-/// * `PLLQCLK = VCOCLK / q`
-/// * `PLLPCLK = VCOCLK / p`
-#[derive(Clone, Copy)]
-pub struct PllConfig {
- /// The source from which the PLL receives a clock signal
- pub source: PllSource,
- /// The initial divisor of that clock signal
- pub m: Pllm,
- /// The PLL VCO multiplier, which must be in the range `8..=86`.
- pub n: Plln,
- /// The final divisor for `PLLRCLK` output which drives the system clock
- pub r: Pllr,
-
- /// The divisor for the `PLLQCLK` output, if desired
- pub q: Option<Pllq>,
-
- /// The divisor for the `PLLPCLK` output, if desired
- pub p: Option<Pllp>,
-}
-
-impl Default for PllConfig {
- #[inline]
- fn default() -> PllConfig {
- // HSI / 1 * 8 / 2 = 64 MHz
- PllConfig {
- source: PllSource::HSI,
- m: Pllm::DIV1,
- n: Plln::MUL8,
- r: Pllr::DIV2,
- q: None,
- p: None,
- }
- }
-}
-
+/// HSE Configuration
#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum PllSource {
- HSI,
- HSE(Hertz, HseMode),
+pub struct Hse {
+ /// HSE frequency.
+ pub freq: Hertz,
+ /// HSE mode.
+ pub mode: HseMode,
+}
+
+/// PLL Configuration
+///
+/// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
+/// dividers. Be sure to keep check the datasheet for your specific part for the appropriate
+/// frequency ranges for each of these settings.
+pub struct Pll {
+ /// PLL Source clock selection.
+ pub source: PllSource,
+
+ /// PLL pre-divider
+ pub prediv: PllPreDiv,
+
+ /// PLL multiplication factor for VCO
+ pub mul: PllMul,
+
+ /// PLL division factor for P clock (ADC Clock)
+ pub divp: Option<PllPDiv>,
+
+ /// PLL division factor for Q clock (USB, I2S23, SAI1, FDCAN, QSPI)
+ pub divq: Option<PllQDiv>,
+
+ /// PLL division factor for R clock (SYSCLK)
+ pub divr: Option<PllRDiv>,
}
/// Clocks configutation
+#[non_exhaustive]
pub struct Config {
+ /// HSI Enable
+ pub hsi: bool,
+
+ /// HSE Configuration
+ pub hse: Option<Hse>,
+
+ /// System Clock Configuration
pub sys: Sysclk,
- pub ahb_pre: AHBPrescaler,
- pub apb_pre: APBPrescaler,
- pub low_power_run: bool,
- pub ls: super::LsConfig,
+
+ /// HSI48 Configuration
#[cfg(crs)]
pub hsi48: Option<super::Hsi48Config>,
+
+ /// PLL Configuration
+ pub pll: Option<Pll>,
+
+ /// If PLL is requested as the main clock source in the `sys` field then the PLL configuration
+ /// MUST turn on the PLLR output.
+ pub ahb_pre: AHBPrescaler,
+ pub apb1_pre: APBPrescaler,
+
+ /// Low-Speed Clock Configuration
+ pub ls: super::LsConfig,
+
+ pub low_power_run: bool,
+
+ pub voltage_range: VoltageRange,
+
/// Per-peripheral kernel clock selection muxes
pub mux: super::mux::ClockMux,
}
@@ -88,248 +92,218 @@ impl Default for Config {
#[inline]
fn default() -> Config {
Config {
- sys: Sysclk::HSI(HSIPrescaler::DIV1),
- ahb_pre: AHBPrescaler::DIV1,
- apb_pre: APBPrescaler::DIV1,
- low_power_run: false,
- ls: Default::default(),
+ hsi: true,
+ hse: None,
+ sys: Sysclk::HSI,
#[cfg(crs)]
hsi48: Some(Default::default()),
+ pll: None,
+ ahb_pre: AHBPrescaler::DIV1,
+ apb1_pre: APBPrescaler::DIV1,
+ low_power_run: false,
+ ls: Default::default(),
+ voltage_range: VoltageRange::RANGE1,
mux: Default::default(),
}
}
}
-impl PllConfig {
- pub(crate) fn init(self) -> (Hertz, Option<Hertz>, Option<Hertz>) {
- let (src, input_freq) = match self.source {
- PllSource::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
- PllSource::HSE(freq, _) => (vals::Pllsrc::HSE, freq),
- };
-
- let m_freq = input_freq / self.m;
- // RM0454 § 5.4.4:
- // > Caution: The software must set these bits so that the PLL input frequency after the
- // > /M divider is between 2.66 and 16 MHz.
- debug_assert!(m_freq.0 >= 2_660_000 && m_freq.0 <= 16_000_000);
-
- let n_freq = m_freq * self.n as u32;
- // RM0454 § 5.4.4:
- // > Caution: The software must set these bits so that the VCO output frequency is between
- // > 64 and 344 MHz.
- debug_assert!(n_freq.0 >= 64_000_000 && n_freq.0 <= 344_000_000);
-
- let r_freq = n_freq / self.r;
- // RM0454 § 5.4.4:
- // > Caution: The software must set this bitfield so as not to exceed 64 MHz on this clock.
- debug_assert!(r_freq.0 <= 64_000_000);
-
- let q_freq = self.q.map(|q| n_freq / q);
- let p_freq = self.p.map(|p| n_freq / p);
-
- // RM0454 § 5.2.3:
- // > To modify the PLL configuration, proceed as follows:
- // > 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR).
- RCC.cr().modify(|w| w.set_pllon(false));
-
- // > 2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
- while RCC.cr().read().pllrdy() {}
-
- // > 3. Change the desired parameter.
- // Enable whichever clock source we're using, and wait for it to become ready
- match self.source {
- PllSource::HSI => {
- RCC.cr().write(|w| w.set_hsion(true));
- while !RCC.cr().read().hsirdy() {}
- }
- PllSource::HSE(_, mode) => {
- RCC.cr().write(|w| {
- w.set_hsebyp(mode != HseMode::Oscillator);
- w.set_hseon(true);
- });
- while !RCC.cr().read().hserdy() {}
- }
- }
-
- // Configure PLLCFGR
- RCC.pllcfgr().modify(|w| {
- w.set_pllr(self.r);
- w.set_pllren(false);
- w.set_pllq(self.q.unwrap_or(Pllq::DIV2));
- w.set_pllqen(false);
- w.set_pllp(self.p.unwrap_or(Pllp::DIV2));
- w.set_pllpen(false);
- w.set_plln(self.n);
- w.set_pllm(self.m);
- w.set_pllsrc(src)
- });
-
- // > 4. Enable the PLL again by setting PLLON to 1.
- RCC.cr().modify(|w| w.set_pllon(true));
-
- // Wait for the PLL to become ready
- while !RCC.cr().read().pllrdy() {}
-
- // > 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL
- // > configuration register (RCC_PLLCFGR).
- RCC.pllcfgr().modify(|w| {
- // We'll use R for system clock, so enable that unconditionally
- w.set_pllren(true);
-
- // We may also use Q or P
- w.set_pllqen(self.q.is_some());
- w.set_pllpen(self.p.is_some());
- });
-
- (r_freq, q_freq, p_freq)
- }
+#[derive(Default)]
+pub struct PllFreq {
+ pub pll_p: Option<Hertz>,
+ pub pll_q: Option<Hertz>,
+ pub pll_r: Option<Hertz>,
}
pub(crate) unsafe fn init(config: Config) {
- let mut pll1_q_freq = None;
- let mut pll1_p_freq = None;
-
- let (sys_clk, sw) = match config.sys {
- Sysclk::HSI(div) => {
- // Enable HSI
- RCC.cr().write(|w| {
- w.set_hsidiv(div);
- w.set_hsion(true)
- });
+ // Configure HSI
+ let hsi = match config.hsi {
+ false => {
+ RCC.cr().modify(|w| w.set_hsion(false));
+ None
+ }
+ true => {
+ RCC.cr().modify(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
-
- (HSI_FREQ / div, Sw::HSI)
- }
- Sysclk::HSE(freq, mode) => {
- // Enable HSE
- RCC.cr().write(|w| {
- w.set_hseon(true);
- w.set_hsebyp(mode != HseMode::Oscillator);
- });
- while !RCC.cr().read().hserdy() {}
-
- (freq, Sw::HSE)
- }
- Sysclk::PLL(pll) => {
- let (r_freq, q_freq, p_freq) = pll.init();
-
- pll1_q_freq = q_freq;
- pll1_p_freq = p_freq;
-
- (r_freq, Sw::PLL1_R)
- }
- Sysclk::LSI => {
- // Enable LSI
- RCC.csr().write(|w| w.set_lsion(true));
- while !RCC.csr().read().lsirdy() {}
- (super::LSI_FREQ, Sw::LSI)
+ Some(HSI_FREQ)
}
};
- // Determine the flash latency implied by the target clock speed
- // RM0454 § 3.3.4:
- let target_flash_latency = if sys_clk.0 <= 24_000_000 {
- Latency::WS0
- } else if sys_clk.0 <= 48_000_000 {
- Latency::WS1
- } else {
- Latency::WS2
- };
-
- // Increase the number of cycles we wait for flash if the new value is higher
- // There's no harm in waiting a little too much before the clock change, but we'll
- // crash immediately if we don't wait enough after the clock change
- let mut set_flash_latency_after = false;
- FLASH.acr().modify(|w| {
- // Is the current flash latency less than what we need at the new SYSCLK?
- if w.latency().to_bits() <= target_flash_latency.to_bits() {
- // We must increase the number of wait states now
- w.set_latency(target_flash_latency)
- } else {
- // We may decrease the number of wait states later
- set_flash_latency_after = true;
+ // Configure HSE
+ let hse = match config.hse {
+ None => {
+ RCC.cr().modify(|w| w.set_hseon(false));
+ None
}
-
- // RM0454 § 3.3.5:
- // > Prefetch is enabled by setting the PRFTEN bit of the FLASH access control register
- // > (FLASH_ACR). This feature is useful if at least one wait state is needed to access the
- // > Flash memory.
- //
- // Enable flash prefetching if we have at least one wait state, and disable it otherwise.
- w.set_prften(target_flash_latency.to_bits() > 0);
- });
-
- if !set_flash_latency_after {
- // Spin until the effective flash latency is compatible with the clock change
- while FLASH.acr().read().latency().to_bits() < target_flash_latency.to_bits() {}
- }
-
- // Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
- let (sw, hpre, ppre) = (sw.into(), config.ahb_pre, config.apb_pre);
- RCC.cfgr().modify(|w| {
- w.set_sw(sw);
- w.set_hpre(hpre);
- w.set_ppre(ppre);
- });
-
- if set_flash_latency_after {
- // We can make the flash require fewer wait states
- // Spin until the SYSCLK changes have taken effect
- loop {
- let cfgr = RCC.cfgr().read();
- if cfgr.sw() == sw && cfgr.hpre() == hpre && cfgr.ppre() == ppre {
- break;
+ Some(hse) => {
+ match hse.mode {
+ HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+ HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
}
- }
- // Set the flash latency to require fewer wait states
- FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
- }
-
- let ahb_freq = sys_clk / config.ahb_pre;
-
- let (apb_freq, apb_tim_freq) = match config.apb_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
+ RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+ RCC.cr().modify(|w| w.set_hseon(true));
+ while !RCC.cr().read().hserdy() {}
+ Some(hse.freq)
}
};
+ // Configure HSI48 if required
+ #[cfg(crs)]
+ let hsi48 = config.hsi48.map(super::init_hsi48);
+
+ let pll = config
+ .pll
+ .map(|pll_config| {
+ let src_freq = match pll_config.source {
+ PllSource::HSI => unwrap!(hsi),
+ PllSource::HSE => unwrap!(hse),
+ _ => unreachable!(),
+ };
+
+ // Disable PLL before configuration
+ RCC.cr().modify(|w| w.set_pllon(false));
+ while RCC.cr().read().pllrdy() {}
+
+ let in_freq = src_freq / pll_config.prediv;
+ assert!(max::PLL_IN.contains(&in_freq));
+ let internal_freq = in_freq * pll_config.mul;
+
+ assert!(max::PLL_VCO.contains(&internal_freq));
+
+ RCC.pllcfgr().write(|w| {
+ w.set_plln(pll_config.mul);
+ w.set_pllm(pll_config.prediv);
+ w.set_pllsrc(pll_config.source.into());
+ });
+
+ let pll_p_freq = pll_config.divp.map(|div_p| {
+ RCC.pllcfgr().modify(|w| {
+ w.set_pllp(div_p);
+ w.set_pllpen(true);
+ });
+ let freq = internal_freq / div_p;
+ assert!(max::PLL_P.contains(&freq));
+ freq
+ });
+
+ let pll_q_freq = pll_config.divq.map(|div_q| {
+ RCC.pllcfgr().modify(|w| {
+ w.set_pllq(div_q);
+ w.set_pllqen(true);
+ });
+ let freq = internal_freq / div_q;
+ assert!(max::PLL_Q.contains(&freq));
+ freq
+ });
+
+ let pll_r_freq = pll_config.divr.map(|div_r| {
+ RCC.pllcfgr().modify(|w| {
+ w.set_pllr(div_r);
+ w.set_pllren(true);
+ });
+ let freq = internal_freq / div_r;
+ assert!(max::PLL_R.contains(&freq));
+ freq
+ });
+
+ // Enable the PLL
+ RCC.cr().modify(|w| w.set_pllon(true));
+ while !RCC.cr().read().pllrdy() {}
+
+ PllFreq {
+ pll_p: pll_p_freq,
+ pll_q: pll_q_freq,
+ pll_r: pll_r_freq,
+ }
+ })
+ .unwrap_or_default();
+
+ let sys = match config.sys {
+ Sysclk::HSI => unwrap!(hsi),
+ Sysclk::HSE => unwrap!(hse),
+ Sysclk::PLL1_R => unwrap!(pll.pll_r),
+ _ => unreachable!(),
+ };
+
+ assert!(max::SYSCLK.contains(&sys));
+
+ // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
+ let hclk = sys / config.ahb_pre;
+ assert!(max::HCLK.contains(&hclk));
+
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+ assert!(max::PCLK.contains(&pclk1));
+
+ let latency = match (config.voltage_range, hclk.0) {
+ (VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0,
+ (VoltageRange::RANGE1, ..=48_000_000) => Latency::WS1,
+ (VoltageRange::RANGE1, _) => Latency::WS2,
+ (VoltageRange::RANGE2, ..=8_000_000) => Latency::WS0,
+ (VoltageRange::RANGE2, ..=16_000_000) => Latency::WS1,
+ (VoltageRange::RANGE2, _) => Latency::WS2,
+ _ => unreachable!(),
+ };
+
+ // Configure flash read access latency based on voltage scale and frequency (RM0444 3.3.4)
+ FLASH.acr().modify(|w| {
+ w.set_latency(latency);
+ });
+
+ // Spin until the effective flash latency is set.
+ while FLASH.acr().read().latency() != latency {}
+
+ // Now that boost mode and flash read access latency are configured, set up SYSCLK
+ RCC.cfgr().modify(|w| {
+ w.set_sw(config.sys);
+ w.set_hpre(config.ahb_pre);
+ w.set_ppre(config.apb1_pre);
+ });
+
if config.low_power_run {
- assert!(sys_clk.0 <= 2_000_000);
+ assert!(sys <= Hertz(2_000_000));
PWR.cr1().modify(|w| w.set_lpr(true));
}
let rtc = config.ls.init();
- let lse_freq = config.ls.lse.map(|lse| lse.frequency);
-
- let hsi_freq = (sw == Sw::HSI).then_some(HSI_FREQ);
- let hsi_div_8_freq = hsi_freq.map(|f| f / 8u32);
- let lsi_freq = (sw == Sw::LSI).then_some(super::LSI_FREQ);
- let hse_freq = (sw == Sw::HSE).then_some(sys_clk);
-
- #[cfg(crs)]
- let hsi48 = config.hsi48.map(super::init_hsi48);
- #[cfg(not(crs))]
- let hsi48: Option<Hertz> = None;
config.mux.init();
set_clocks!(
- sys: Some(sys_clk),
- hclk1: Some(ahb_freq),
- pclk1: Some(apb_freq),
- pclk1_tim: Some(apb_tim_freq),
- hsi: hsi_freq,
+ sys: Some(sys),
+ hclk1: Some(hclk),
+ pclk1: Some(pclk1),
+ pclk1_tim: Some(pclk1_tim),
+ pll1_p: pll.pll_p,
+ pll1_q: pll.pll_q,
+ pll1_r: pll.pll_r,
+ hsi: hsi,
+ hse: hse,
+ #[cfg(crs)]
hsi48: hsi48,
- hsi_div_8: hsi_div_8_freq,
- hse: hse_freq,
- lse: lse_freq,
- lsi: lsi_freq,
- pll1_q: pll1_q_freq,
- pll1_p: pll1_p_freq,
rtc: rtc,
- hsi_div_488: None,
+ hsi_div_8: hsi.map(|h| h / 8u32),
+ hsi_div_488: hsi.map(|h| h / 488u32),
+
+ // TODO
+ lsi: None,
+ lse: None,
);
}
+
+mod max {
+ use core::ops::RangeInclusive;
+
+ use crate::time::Hertz;
+
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(48_000_000);
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+ pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(64_000_000);
+ pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(8)..=Hertz(64_000_000);
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(64_000_000);
+ pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(2_660_000)..=Hertz(16_000_000);
+ pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(96_000_000)..=Hertz(344_000_000);
+ pub(crate) const PLL_P: RangeInclusive<Hertz> = Hertz(3_090_000)..=Hertz(122_000_000);
+ pub(crate) const PLL_Q: RangeInclusive<Hertz> = Hertz(12_000_000)..=Hertz(128_000_000);
+ pub(crate) const PLL_R: RangeInclusive<Hertz> = Hertz(12_000_000)..=Hertz(64_000_000);
+}
diff --git a/examples/stm32g0/src/bin/hf_timer.rs b/examples/stm32g0/src/bin/hf_timer.rs
index 647ff0419..3ea06cdee 100644
--- a/examples/stm32g0/src/bin/hf_timer.rs
+++ b/examples/stm32g0/src/bin/hf_timer.rs
@@ -16,15 +16,16 @@ async fn main(_spawner: Spawner) {
let mut config = PeripheralConfig::default();
{
use embassy_stm32::rcc::*;
-
- config.rcc.sys = Sysclk::PLL(PllConfig {
+ config.rcc.hsi = true;
+ config.rcc.pll = Some(Pll {
source: PllSource::HSI,
- m: Pllm::DIV1,
- n: Plln::MUL16,
- r: Pllr::DIV4, // CPU clock comes from PLLR (HSI (16MHz) / 1 * 16 / 4 = 64MHz)
- q: Some(Pllq::DIV2), // TIM1 or TIM15 can be sourced from PLLQ (HSI (16MHz) / 1 * 16 / 2 = 128MHz)
- p: None,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL16,
+ divp: None,
+ divq: Some(PllQDiv::DIV2), // 16 / 1 * 16 / 2 = 128 Mhz
+ divr: Some(PllRDiv::DIV4), // 16 / 1 * 16 / 4 = 64 Mhz
});
+ config.rcc.sys = Sysclk::PLL1_R;
// configure TIM1 mux to select PLLQ as clock source
// https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index c3f39c04f..1587a6fb4 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -260,6 +260,19 @@ pub fn config() -> Config {
#[allow(unused_mut)]
let mut config = Config::default();
+ #[cfg(feature = "stm32g071rb")]
+ {
+ config.rcc.hsi = true;
+ config.rcc.pll = Some(Pll {
+ source: PllSource::HSI,
+ prediv: PllPreDiv::DIV1,
+ mul: PllMul::MUL16,
+ divp: None,
+ divq: None,
+ divr: Some(PllRDiv::DIV4), // 16 / 1 * 16 / 4 = 64 Mhz
+ });
+ config.rcc.sys = Sysclk::PLL1_R;
+ }
#[cfg(feature = "stm32wb55rg")]
{
config.rcc = embassy_stm32::rcc::WPAN_DEFAULT;
From ae266f3bf528c334c4712cd37305d2bcb71c0936 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Mon, 4 Mar 2024 00:03:07 +0100
Subject: [PATCH 372/392] stm32/rcc: port c0 to new api. Add c0 HSIKER/HSISYS
support.
---
embassy-stm32/Cargo.toml | 4 +-
embassy-stm32/src/rcc/c0.rs | 248 ++++++++++++++++++++----------------
tests/stm32/src/common.rs | 11 ++
3 files changed, 154 insertions(+), 109 deletions(-)
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 4bbd43c47..b326c26fd 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -70,7 +70,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
critical-section = "1.1"
#stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e853cf944b150898312984d092d63926970c340d" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e7f91751fbbf856e0cb30e50ae6db79f0409b085" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@@ -94,7 +94,7 @@ critical-section = { version = "1.1", features = ["std"] }
proc-macro2 = "1.0.36"
quote = "1.0.15"
#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e853cf944b150898312984d092d63926970c340d", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e7f91751fbbf856e0cb30e50ae6db79f0409b085", default-features = false, features = ["metadata"]}
[features]
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index 1946c5a15..7ca737bf0 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -1,25 +1,56 @@
use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::Sw;
-pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Hsidiv as HSIPrescaler, Ppre as APBPrescaler};
+pub use crate::pac::rcc::vals::{
+ Hpre as AHBPrescaler, Hsidiv as HsiSysDiv, Hsikerdiv as HsiKerDiv, Ppre as APBPrescaler, Sw as Sysclk,
+};
use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(48_000_000);
+pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum Sysclk {
- HSE(Hertz),
- HSI(HSIPrescaler),
- LSI,
+/// HSE Mode
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+ /// crystal/ceramic oscillator (HSEBYP=0)
+ Oscillator,
+ /// external analog clock (low swing) (HSEBYP=1)
+ Bypass,
+}
+
+/// HSE Configuration
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+ /// HSE frequency.
+ pub freq: Hertz,
+ /// HSE mode.
+ pub mode: HseMode,
+}
+
+/// HSI Configuration
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hsi {
+ /// Division factor for HSISYS clock. Default is 4.
+ pub sys_div: HsiSysDiv,
+ /// Division factor for HSIKER clock. Default is 3.
+ pub ker_div: HsiKerDiv,
}
/// Clocks configutation
+#[non_exhaustive]
pub struct Config {
+ /// HSI Configuration
+ pub hsi: Option<Hsi>,
+
+ /// HSE Configuration
+ pub hse: Option<Hse>,
+
+ /// System Clock Configuration
pub sys: Sysclk,
+
pub ahb_pre: AHBPrescaler,
- pub apb_pre: APBPrescaler,
+ pub apb1_pre: APBPrescaler,
+
+ /// Low-Speed Clock Configuration
pub ls: super::LsConfig,
/// Per-peripheral kernel clock selection muxes
@@ -30,9 +61,14 @@ impl Default for Config {
#[inline]
fn default() -> Config {
Config {
- sys: Sysclk::HSI(HSIPrescaler::DIV1),
+ hsi: Some(Hsi {
+ sys_div: HsiSysDiv::DIV4,
+ ker_div: HsiKerDiv::DIV3,
+ }),
+ hse: None,
+ sys: Sysclk::HSISYS,
ahb_pre: AHBPrescaler::DIV1,
- apb_pre: APBPrescaler::DIV1,
+ apb1_pre: APBPrescaler::DIV1,
ls: Default::default(),
mux: Default::default(),
}
@@ -40,111 +76,109 @@ impl Default for Config {
}
pub(crate) unsafe fn init(config: Config) {
- let (sys_clk, sw) = match config.sys {
- Sysclk::HSI(div) => {
- // Enable HSI
- RCC.cr().write(|w| {
- w.set_hsidiv(div);
- w.set_hsion(true)
+ // Configure HSI
+ let (hsi, hsisys, hsiker) = match config.hsi {
+ None => {
+ RCC.cr().modify(|w| w.set_hsion(false));
+ (None, None, None)
+ }
+ Some(hsi) => {
+ RCC.cr().modify(|w| {
+ w.set_hsidiv(hsi.sys_div);
+ w.set_hsikerdiv(hsi.ker_div);
+ w.set_hsion(true);
});
while !RCC.cr().read().hsirdy() {}
-
- (HSI_FREQ / div, Sw::HSI)
- }
- Sysclk::HSE(freq) => {
- // Enable HSE
- RCC.cr().write(|w| w.set_hseon(true));
- while !RCC.cr().read().hserdy() {}
-
- (freq, Sw::HSE)
- }
- Sysclk::LSI => {
- // Enable LSI
- RCC.csr2().write(|w| w.set_lsion(true));
- while !RCC.csr2().read().lsirdy() {}
- (super::LSI_FREQ, Sw::LSI)
+ (
+ Some(HSI_FREQ),
+ Some(HSI_FREQ / hsi.sys_div),
+ Some(HSI_FREQ / hsi.ker_div),
+ )
}
};
+ // Configure HSE
+ let hse = match config.hse {
+ None => {
+ RCC.cr().modify(|w| w.set_hseon(false));
+ None
+ }
+ Some(hse) => {
+ match hse.mode {
+ HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+ HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+ }
+
+ RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
+ RCC.cr().modify(|w| w.set_hseon(true));
+ while !RCC.cr().read().hserdy() {}
+ Some(hse.freq)
+ }
+ };
+
+ let sys = match config.sys {
+ Sysclk::HSISYS => unwrap!(hsisys),
+ Sysclk::HSE => unwrap!(hse),
+ _ => unreachable!(),
+ };
+
+ assert!(max::SYSCLK.contains(&sys));
+
+ // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
+ let hclk = sys / config.ahb_pre;
+ assert!(max::HCLK.contains(&hclk));
+
+ let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
+ assert!(max::PCLK.contains(&pclk1));
+
+ let latency = match hclk.0 {
+ ..=24_000_000 => Latency::WS0,
+ _ => Latency::WS1,
+ };
+
+ // Configure flash read access latency based on voltage scale and frequency
+ FLASH.acr().modify(|w| {
+ w.set_latency(latency);
+ });
+
+ // Spin until the effective flash latency is set.
+ while FLASH.acr().read().latency() != latency {}
+
+ // Now that boost mode and flash read access latency are configured, set up SYSCLK
+ RCC.cfgr().modify(|w| {
+ w.set_sw(config.sys);
+ w.set_hpre(config.ahb_pre);
+ w.set_ppre(config.apb1_pre);
+ });
+
let rtc = config.ls.init();
- // Determine the flash latency implied by the target clock speed
- // RM0454 § 3.3.4:
- let target_flash_latency = if sys_clk <= Hertz(24_000_000) {
- Latency::WS0
- } else {
- Latency::WS1
- };
-
- // Increase the number of cycles we wait for flash if the new value is higher
- // There's no harm in waiting a little too much before the clock change, but we'll
- // crash immediately if we don't wait enough after the clock change
- let mut set_flash_latency_after = false;
- FLASH.acr().modify(|w| {
- // Is the current flash latency less than what we need at the new SYSCLK?
- if w.latency().to_bits() <= target_flash_latency.to_bits() {
- // We must increase the number of wait states now
- w.set_latency(target_flash_latency)
- } else {
- // We may decrease the number of wait states later
- set_flash_latency_after = true;
- }
-
- // RM0490 § 3.3.4:
- // > Prefetch is enabled by setting the PRFTEN bit of the FLASH access control register
- // > (FLASH_ACR). This feature is useful if at least one wait state is needed to access the
- // > Flash memory.
- //
- // Enable flash prefetching if we have at least one wait state, and disable it otherwise.
- w.set_prften(target_flash_latency.to_bits() > 0);
- });
-
- if !set_flash_latency_after {
- // Spin until the effective flash latency is compatible with the clock change
- while FLASH.acr().read().latency() < target_flash_latency {}
- }
-
- // Configure SYSCLK source, HCLK divisor, and PCLK divisor all at once
- RCC.cfgr().modify(|w| {
- w.set_sw(sw);
- w.set_hpre(config.ahb_pre);
- w.set_ppre(config.apb_pre);
- });
- // Spin until the SYSCLK changes have taken effect
- loop {
- let cfgr = RCC.cfgr().read();
- if cfgr.sw() == sw && cfgr.hpre() == config.ahb_pre && cfgr.ppre() == config.apb_pre {
- break;
- }
- }
-
- // Set the flash latency to require fewer wait states
- if set_flash_latency_after {
- FLASH.acr().modify(|w| w.set_latency(target_flash_latency));
- }
-
- let ahb_freq = sys_clk / config.ahb_pre;
-
- let (apb_freq, apb_tim_freq) = match config.apb_pre {
- APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
- pre => {
- let freq = ahb_freq / pre;
- (freq, freq * 2u32)
- }
- };
-
config.mux.init();
- // without this, the ringbuffered uart test fails.
- cortex_m::asm::dsb();
-
set_clocks!(
- hsi: None,
- lse: None,
- sys: Some(sys_clk),
- hclk1: Some(ahb_freq),
- pclk1: Some(apb_freq),
- pclk1_tim: Some(apb_tim_freq),
+ sys: Some(sys),
+ hclk1: Some(hclk),
+ pclk1: Some(pclk1),
+ pclk1_tim: Some(pclk1_tim),
+ hsi: hsi,
+ hsiker: hsiker,
+ hse: hse,
rtc: rtc,
+
+ // TODO
+ lsi: None,
+ lse: None,
);
}
+
+mod max {
+ use core::ops::RangeInclusive;
+
+ use crate::time::Hertz;
+
+ pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(48_000_000);
+ pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+ pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+ pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(8)..=Hertz(48_000_000);
+ pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
+}
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 1587a6fb4..3297ea7e2 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -260,6 +260,17 @@ pub fn config() -> Config {
#[allow(unused_mut)]
let mut config = Config::default();
+ #[cfg(feature = "stm32c031c6")]
+ {
+ config.rcc.hsi = Some(Hsi {
+ sys_div: HsiSysDiv::DIV1, // 48Mhz
+ ker_div: HsiKerDiv::DIV3, // 16Mhz
+ });
+ config.rcc.sys = Sysclk::HSISYS;
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV1;
+ }
+
#[cfg(feature = "stm32g071rb")]
{
config.rcc.hsi = true;
From 873934aae5dd320133c383891b7b334d34d6454d Mon Sep 17 00:00:00 2001
From: William Yager <will@yager.io>
Date: Sun, 3 Mar 2024 18:43:44 -0500
Subject: [PATCH 373/392] ok
---
embassy-boot-stm32/src/lib.rs | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/embassy-boot-stm32/src/lib.rs b/embassy-boot-stm32/src/lib.rs
index 4b4091ac9..708441835 100644
--- a/embassy-boot-stm32/src/lib.rs
+++ b/embassy-boot-stm32/src/lib.rs
@@ -4,8 +4,8 @@
mod fmt;
pub use embassy_boot::{
- AlignedBuffer, BlockingFirmwareState, BlockingFirmwareUpdater, BootLoaderConfig, FirmwareState, FirmwareUpdater,
- FirmwareUpdaterConfig, State,
+ AlignedBuffer, BlockingFirmwareState, BlockingFirmwareUpdater, BootError, BootLoaderConfig, FirmwareState,
+ FirmwareUpdater, FirmwareUpdaterConfig, State,
};
use embedded_storage::nor_flash::NorFlash;
@@ -20,10 +20,17 @@ impl BootLoader {
pub fn prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>(
config: BootLoaderConfig<ACTIVE, DFU, STATE>,
) -> Self {
+ Self::try_prepare::<ACTIVE, DFU, STATE, BUFFER_SIZE>(config).expect("Boot prepare error")
+ }
+
+ /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware
+ pub fn try_prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash, const BUFFER_SIZE: usize>(
+ config: BootLoaderConfig<ACTIVE, DFU, STATE>,
+ ) -> Result<Self, BootError> {
let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
let mut boot = embassy_boot::BootLoader::new(config);
- let state = boot.prepare_boot(aligned_buf.as_mut()).expect("Boot prepare error");
- Self { state }
+ let state = boot.prepare_boot(aligned_buf.as_mut())?;
+ Ok(Self { state })
}
/// Boots the application.
From cde6e2b58be4910c73b3738bb3b0e264c8ac6049 Mon Sep 17 00:00:00 2001
From: William Yager <will@yager.io>
Date: Sun, 3 Mar 2024 18:50:27 -0500
Subject: [PATCH 374/392] ok
---
embassy-boot-nrf/src/lib.rs | 17 ++++++++++++-----
embassy-boot-rp/src/lib.rs | 15 +++++++++++----
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/embassy-boot-nrf/src/lib.rs b/embassy-boot-nrf/src/lib.rs
index 5b20a93c6..6996a92f8 100644
--- a/embassy-boot-nrf/src/lib.rs
+++ b/embassy-boot-nrf/src/lib.rs
@@ -4,8 +4,8 @@
mod fmt;
pub use embassy_boot::{
- AlignedBuffer, BlockingFirmwareState, BlockingFirmwareUpdater, BootLoaderConfig, FirmwareState, FirmwareUpdater,
- FirmwareUpdaterConfig,
+ AlignedBuffer, BlockingFirmwareState, BlockingFirmwareUpdater, BootError, BootLoaderConfig, FirmwareState,
+ FirmwareUpdater, FirmwareUpdaterConfig,
};
use embassy_nrf::nvmc::PAGE_SIZE;
use embassy_nrf::peripherals::WDT;
@@ -16,14 +16,21 @@ use embedded_storage::nor_flash::{ErrorType, NorFlash, ReadNorFlash};
pub struct BootLoader<const BUFFER_SIZE: usize = PAGE_SIZE>;
impl<const BUFFER_SIZE: usize> BootLoader<BUFFER_SIZE> {
- /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware.
+ /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware
pub fn prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>(
config: BootLoaderConfig<ACTIVE, DFU, STATE>,
) -> Self {
+ Self::try_prepare::<ACTIVE, DFU, STATE>(config).expect("Boot prepare error")
+ }
+
+ /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware
+ pub fn try_prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>(
+ config: BootLoaderConfig<ACTIVE, DFU, STATE>,
+ ) -> Result<Self, BootError> {
let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
let mut boot = embassy_boot::BootLoader::new(config);
- boot.prepare_boot(&mut aligned_buf.0).expect("Boot prepare error");
- Self
+ let state = boot.prepare_boot(aligned_buf.as_mut())?;
+ Ok(Self)
}
/// Boots the application without softdevice mechanisms.
diff --git a/embassy-boot-rp/src/lib.rs b/embassy-boot-rp/src/lib.rs
index 07a5b3f4d..d88e6dfc6 100644
--- a/embassy-boot-rp/src/lib.rs
+++ b/embassy-boot-rp/src/lib.rs
@@ -4,8 +4,8 @@
mod fmt;
pub use embassy_boot::{
- AlignedBuffer, BlockingFirmwareState, BlockingFirmwareUpdater, BootLoaderConfig, FirmwareState, FirmwareUpdater,
- FirmwareUpdaterConfig, State,
+ AlignedBuffer, BlockingFirmwareState, BlockingFirmwareUpdater, BootError, BootLoaderConfig, FirmwareState,
+ FirmwareUpdater, FirmwareUpdaterConfig, State,
};
use embassy_rp::flash::{Blocking, Flash, ERASE_SIZE};
use embassy_rp::peripherals::{FLASH, WATCHDOG};
@@ -21,10 +21,17 @@ impl<const BUFFER_SIZE: usize> BootLoader<BUFFER_SIZE> {
pub fn prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>(
config: BootLoaderConfig<ACTIVE, DFU, STATE>,
) -> Self {
+ Self::try_prepare::<ACTIVE, DFU, STATE>(config).expect("Boot prepare error")
+ }
+
+ /// Inspect the bootloader state and perform actions required before booting, such as swapping firmware
+ pub fn try_prepare<ACTIVE: NorFlash, DFU: NorFlash, STATE: NorFlash>(
+ config: BootLoaderConfig<ACTIVE, DFU, STATE>,
+ ) -> Result<Self, BootError> {
let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
let mut boot = embassy_boot::BootLoader::new(config);
- boot.prepare_boot(aligned_buf.as_mut()).expect("Boot prepare error");
- Self
+ let state = boot.prepare_boot(aligned_buf.as_mut())?;
+ Ok(Self { state })
}
/// Boots the application.
From 0813f42d082c6dd8ec1714c1a1ed18c4f64d9590 Mon Sep 17 00:00:00 2001
From: William Yager <will@yager.io>
Date: Sun, 3 Mar 2024 21:07:08 -0500
Subject: [PATCH 375/392] ci
---
embassy-boot-nrf/src/lib.rs | 2 +-
embassy-boot-rp/src/lib.rs | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/embassy-boot-nrf/src/lib.rs b/embassy-boot-nrf/src/lib.rs
index 6996a92f8..d53e78895 100644
--- a/embassy-boot-nrf/src/lib.rs
+++ b/embassy-boot-nrf/src/lib.rs
@@ -29,7 +29,7 @@ impl<const BUFFER_SIZE: usize> BootLoader<BUFFER_SIZE> {
) -> Result<Self, BootError> {
let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
let mut boot = embassy_boot::BootLoader::new(config);
- let state = boot.prepare_boot(aligned_buf.as_mut())?;
+ let _state = boot.prepare_boot(aligned_buf.as_mut())?;
Ok(Self)
}
diff --git a/embassy-boot-rp/src/lib.rs b/embassy-boot-rp/src/lib.rs
index d88e6dfc6..d0a393bed 100644
--- a/embassy-boot-rp/src/lib.rs
+++ b/embassy-boot-rp/src/lib.rs
@@ -30,8 +30,8 @@ impl<const BUFFER_SIZE: usize> BootLoader<BUFFER_SIZE> {
) -> Result<Self, BootError> {
let mut aligned_buf = AlignedBuffer([0; BUFFER_SIZE]);
let mut boot = embassy_boot::BootLoader::new(config);
- let state = boot.prepare_boot(aligned_buf.as_mut())?;
- Ok(Self { state })
+ let _state = boot.prepare_boot(aligned_buf.as_mut())?;
+ Ok(Self)
}
/// Boots the application.
From 72c6cdc5d5bd851855975061b1c6713cf482e6fb Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Mon, 4 Mar 2024 12:22:18 +0000
Subject: [PATCH 376/392] stm32: can: fd: rename TxBufferMode::Queue ->
::Priority for clarity
---
embassy-stm32/src/can/fd/config.rs | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index adaffe9cc..68161ca50 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -292,14 +292,14 @@ impl Default for GlobalFilter {
pub enum TxBufferMode {
/// TX FIFO operation - In this mode CAN frames are trasmitted strictly in write order.
Fifo,
- /// TX queue operation - In this mode CAN frames are transmitted according to CAN priority.
- Queue,
+ /// TX priority queue operation - In this mode CAN frames are transmitted according to CAN priority.
+ Priority,
}
impl From<TxBufferMode> for crate::pac::can::vals::Tfqm {
fn from(value: TxBufferMode) -> Self {
match value {
- TxBufferMode::Queue => Self::QUEUE,
+ TxBufferMode::Priority => Self::QUEUE,
TxBufferMode::Fifo => Self::FIFO,
}
}
@@ -308,7 +308,7 @@ impl From<TxBufferMode> for crate::pac::can::vals::Tfqm {
impl From<crate::pac::can::vals::Tfqm> for TxBufferMode {
fn from(value: crate::pac::can::vals::Tfqm) -> Self {
match value {
- crate::pac::can::vals::Tfqm::QUEUE => Self::Queue,
+ crate::pac::can::vals::Tfqm::QUEUE => Self::Priority,
crate::pac::can::vals::Tfqm::FIFO => Self::Fifo,
}
}
@@ -354,7 +354,7 @@ pub struct FdCanConfig {
pub timestamp_source: TimestampSource,
/// Configures the Global Filter
pub global_filter: GlobalFilter,
- /// TX buffer mode (FIFO or queue)
+ /// TX buffer mode (FIFO or priority queue)
pub tx_buffer_mode: TxBufferMode,
}
@@ -445,6 +445,13 @@ impl FdCanConfig {
self.global_filter = filter;
self
}
+
+ /// Sets the TX buffer mode (FIFO or priority queue)
+ #[inline]
+ pub const fn set_tx_buffer_mode(mut self, txbm: TxBufferMode) -> Self {
+ self.tx_buffer_mode = txbm;
+ self
+ }
}
impl Default for FdCanConfig {
@@ -462,7 +469,7 @@ impl Default for FdCanConfig {
clock_divider: ClockDivider::_1,
timestamp_source: TimestampSource::None,
global_filter: GlobalFilter::default(),
- tx_buffer_mode: TxBufferMode::Queue,
+ tx_buffer_mode: TxBufferMode::Priority,
}
}
}
From e0018c6f4f56cdef286934fb368cd4053c209461 Mon Sep 17 00:00:00 2001
From: Torin Cooper-Bennun <tcbennun@maxiluxsystems.com>
Date: Mon, 4 Mar 2024 12:22:59 +0000
Subject: [PATCH 377/392] stm32: can:fd: merge read impls; buffered RX returns
Result<_, BusError>
---
embassy-stm32/src/can/fdcan.rs | 65 +++++++++++++++++++---------------
1 file changed, 37 insertions(+), 28 deletions(-)
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 20d00ccb5..fe8969a5a 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -398,7 +398,8 @@ impl<'d, T: Instance> Fdcan<'d, T> {
}
/// User supplied buffer for RX Buffering
-pub type RxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, (ClassicFrame, Timestamp), BUF_SIZE>;
+pub type RxBuf<const BUF_SIZE: usize> =
+ Channel<CriticalSectionRawMutex, Result<(ClassicFrame, Timestamp), BusError>, BUF_SIZE>;
/// User supplied buffer for TX buffering
pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, ClassicFrame, BUF_SIZE>;
@@ -440,7 +441,8 @@ impl BufferedCanSender {
}
/// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
-pub type BufferedCanReceiver = embassy_sync::channel::DynamicReceiver<'static, (ClassicFrame, Timestamp)>;
+pub type BufferedCanReceiver =
+ embassy_sync::channel::DynamicReceiver<'static, Result<(ClassicFrame, Timestamp), BusError>>;
impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
BufferedCan<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
@@ -485,7 +487,7 @@ impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
/// Async read frame from RX buffer.
pub async fn read(&mut self) -> Result<(ClassicFrame, Timestamp), BusError> {
- Ok(self.rx_buf.receive().await)
+ self.rx_buf.receive().await
}
/// Returns a sender that can be used for sending CAN frames.
@@ -514,7 +516,8 @@ impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Dr
}
/// User supplied buffer for RX Buffering
-pub type RxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, (FdFrame, Timestamp), BUF_SIZE>;
+pub type RxFdBuf<const BUF_SIZE: usize> =
+ Channel<CriticalSectionRawMutex, Result<(FdFrame, Timestamp), BusError>, BUF_SIZE>;
/// User supplied buffer for TX buffering
pub type TxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, FdFrame, BUF_SIZE>;
@@ -556,7 +559,8 @@ impl BufferedFdCanSender {
}
/// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
-pub type BufferedFdCanReceiver = embassy_sync::channel::DynamicReceiver<'static, (FdFrame, Timestamp)>;
+pub type BufferedFdCanReceiver =
+ embassy_sync::channel::DynamicReceiver<'static, Result<(FdFrame, Timestamp), BusError>>;
impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
BufferedCanFd<'d, T, TX_BUF_SIZE, RX_BUF_SIZE>
@@ -601,7 +605,7 @@ impl<'c, 'd, T: Instance, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
/// Async read frame from RX buffer.
pub async fn read(&mut self) -> Result<(FdFrame, Timestamp), BusError> {
- Ok(self.rx_buf.receive().await)
+ self.rx_buf.receive().await
}
/// Returns a sender that can be used for sending CAN frames.
@@ -685,14 +689,14 @@ pub(crate) mod sealed {
use crate::can::frame::{ClassicFrame, FdFrame};
pub struct ClassicBufferedRxInner {
- pub rx_sender: DynamicSender<'static, (ClassicFrame, Timestamp)>,
+ pub rx_sender: DynamicSender<'static, Result<(ClassicFrame, Timestamp), BusError>>,
}
pub struct ClassicBufferedTxInner {
pub tx_receiver: DynamicReceiver<'static, ClassicFrame>,
}
pub struct FdBufferedRxInner {
- pub rx_sender: DynamicSender<'static, (FdFrame, Timestamp)>,
+ pub rx_sender: DynamicSender<'static, Result<(FdFrame, Timestamp), BusError>>,
}
pub struct FdBufferedTxInner {
pub tx_receiver: DynamicReceiver<'static, FdFrame>,
@@ -721,46 +725,51 @@ pub(crate) mod sealed {
waker.wake();
}
RxMode::ClassicBuffered(buf) => {
- if let Some(r) = T::registers().read(fifonr) {
- let ts = T::calc_timestamp(T::state().ns_per_timer_tick, r.1);
- let _ = buf.rx_sender.try_send((r.0, ts));
+ if let Some(result) = self.read::<T, _>() {
+ let _ = buf.rx_sender.try_send(result);
}
}
RxMode::FdBuffered(buf) => {
- if let Some(r) = T::registers().read(fifonr) {
- let ts = T::calc_timestamp(T::state().ns_per_timer_tick, r.1);
- let _ = buf.rx_sender.try_send((r.0, ts));
+ if let Some(result) = self.read::<T, _>() {
+ let _ = buf.rx_sender.try_send(result);
}
}
}
}
- async fn read<T: Instance, F: CanHeader>(&self) -> Result<(F, Timestamp), BusError> {
+ fn read<T: Instance, F: CanHeader>(&self) -> Option<Result<(F, Timestamp), BusError>> {
+ if let Some((msg, ts)) = T::registers().read(0) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+ Some(Ok((msg, ts)))
+ } else if let Some((msg, ts)) = T::registers().read(1) {
+ let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+ Some(Ok((msg, ts)))
+ } else if let Some(err) = T::registers().curr_error() {
+ // TODO: this is probably wrong
+ Some(Err(err))
+ } else {
+ None
+ }
+ }
+
+ async fn read_async<T: Instance, F: CanHeader>(&self) -> Result<(F, Timestamp), BusError> {
poll_fn(|cx| {
T::state().err_waker.register(cx.waker());
self.register(cx.waker());
-
- if let Some((msg, ts)) = T::registers().read(0) {
- let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some((msg, ts)) = T::registers().read(1) {
- let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
- return Poll::Ready(Ok((msg, ts)));
- } else if let Some(err) = T::registers().curr_error() {
- // TODO: this is probably wrong
- return Poll::Ready(Err(err));
+ match self.read::<T, _>() {
+ Some(result) => Poll::Ready(result),
+ None => Poll::Pending,
}
- Poll::Pending
})
.await
}
pub async fn read_classic<T: Instance>(&self) -> Result<(ClassicFrame, Timestamp), BusError> {
- self.read::<T, _>().await
+ self.read_async::<T, _>().await
}
pub async fn read_fd<T: Instance>(&self) -> Result<(FdFrame, Timestamp), BusError> {
- self.read::<T, _>().await
+ self.read_async::<T, _>().await
}
}
From 2a257573773f3dabdf16ea6a44ba0dadef786f37 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <ulf.lilleengen@gmail.com>
Date: Mon, 4 Mar 2024 18:36:34 +0100
Subject: [PATCH 378/392] docs: clarify capabilities of zerocopy channel
---
embassy-sync/src/zerocopy_channel.rs | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/embassy-sync/src/zerocopy_channel.rs b/embassy-sync/src/zerocopy_channel.rs
index f704cbd5d..cfce9a571 100644
--- a/embassy-sync/src/zerocopy_channel.rs
+++ b/embassy-sync/src/zerocopy_channel.rs
@@ -1,10 +1,7 @@
//! A zero-copy queue for sending values between asynchronous tasks.
//!
-//! It can be used concurrently by multiple producers (senders) and multiple
-//! consumers (receivers), i.e. it is an "MPMC channel".
-//!
-//! Receivers are competing for messages. So a message that is received by
-//! one receiver is not received by any other.
+//! It can be used concurrently by a producer (sender) and a
+//! consumer (receiver), i.e. it is an "SPSC channel".
//!
//! This queue takes a Mutex type so that various
//! targets can be attained. For example, a ThreadModeMutex can be used
From c00f014f18e7ade176ed29cc06070466079d8268 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Tue, 5 Mar 2024 01:03:10 +0100
Subject: [PATCH 379/392] Some more unifying, documentation
---
embassy-nrf/src/radio/ble.rs | 14 +---
embassy-nrf/src/radio/ieee802154.rs | 109 ++++++++--------------------
embassy-nrf/src/radio/mod.rs | 28 +++++++
3 files changed, 61 insertions(+), 90 deletions(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index 93c701de0..846ac98af 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -8,8 +8,6 @@ use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
pub use pac::radio::mode::MODE_A as Mode;
use pac::radio::pcnf0::PLEN_A as PreambleLength;
-use pac::radio::state::STATE_A as RadioState;
-pub use pac::radio::txpower::TXPOWER_A as TxPower;
use crate::interrupt::typelevel::Interrupt;
pub use crate::radio::Error;
@@ -111,17 +109,7 @@ impl<'d, T: Instance> Radio<'d, T> {
#[allow(dead_code)]
fn trace_state(&self) {
- match self.state() {
- RadioState::DISABLED => trace!("radio:state:DISABLED"),
- RadioState::RX_RU => trace!("radio:state:RX_RU"),
- RadioState::RX_IDLE => trace!("radio:state:RX_IDLE"),
- RadioState::RX => trace!("radio:state:RX"),
- RadioState::RX_DISABLE => trace!("radio:state:RX_DISABLE"),
- RadioState::TX_RU => trace!("radio:state:TX_RU"),
- RadioState::TX_IDLE => trace!("radio:state:TX_IDLE"),
- RadioState::TX => trace!("radio:state:TX"),
- RadioState::TX_DISABLE => trace!("radio:state:TX_DISABLE"),
- }
+ super::trace_state(T::regs())
}
/// Set the radio mode
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
index 91c6dbd3b..2de53b392 100644
--- a/embassy-nrf/src/radio/ieee802154.rs
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -1,19 +1,17 @@
-//! IEEE 802.15.4 radio
+//! IEEE 802.15.4 radio driver
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
-use pac::radio::state::STATE_A as RadioState;
-use pac::radio::txpower::TXPOWER_A as TxPower;
-use super::{Error, Instance, InterruptHandler};
+use super::{state, Error, Instance, InterruptHandler, RadioState, TxPower};
use crate::interrupt::typelevel::Interrupt;
use crate::interrupt::{self};
-use crate::{pac, Peripheral};
+use crate::Peripheral;
-/// Default Start of Frame Delimiter = `0xA7` (IEEE compliant)
+/// Default (IEEE compliant) Start of Frame Delimiter
pub const DEFAULT_SFD: u8 = 0xA7;
// TODO expose the other variants in `pac::CCAMODE_A`
@@ -32,35 +30,14 @@ pub enum Cca {
},
}
-fn get_state(radio: &pac::radio::RegisterBlock) -> RadioState {
- match radio.state.read().state().variant() {
- Some(state) => state,
- None => unreachable!(),
- }
-}
-
-fn trace_state(state: RadioState) {
- match state {
- RadioState::DISABLED => trace!("radio:state:DISABLED"),
- RadioState::RX_RU => trace!("radio:state:RX_RU"),
- RadioState::RX_IDLE => trace!("radio:state:RX_IDLE"),
- RadioState::RX => trace!("radio:state:RX"),
- RadioState::RX_DISABLE => trace!("radio:state:RX_DISABLE"),
- RadioState::TX_RU => trace!("radio:state:TX_RU"),
- RadioState::TX_IDLE => trace!("radio:state:TX_IDLE"),
- RadioState::TX => trace!("radio:state:TX"),
- RadioState::TX_DISABLE => trace!("radio:state:TX_DISABLE"),
- }
-}
-
-/// Radio driver.
+/// IEEE 802.15.4 radio driver.
pub struct Radio<'d, T: Instance> {
_p: PeripheralRef<'d, T>,
needs_enable: bool,
}
impl<'d, T: Instance> Radio<'d, T> {
- /// Create a new radio driver.
+ /// Create a new IEEE 802.15.4 radio driver.
pub fn new(
radio: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
@@ -81,40 +58,43 @@ impl<'d, T: Instance> Radio<'d, T> {
// Configure CRC polynomial and init
r.crcpoly.write(|w| w.crcpoly().bits(0x0001_1021));
r.crcinit.write(|w| w.crcinit().bits(0));
- // Configure packet layout
- // 8-bit on air length
- // S0 length, zero bytes
- // S1 length, zero bytes
- // S1 included in RAM if S1 length > 0, No.
- // Code Indicator length, 0
- // Preamble length 32-bit zero
- // Exclude CRC
- // No TERM field
r.pcnf0.write(|w| {
+ // 8-bit on air length
w.lflen()
.bits(8)
+ // Zero bytes S0 field length
.s0len()
.clear_bit()
+ // Zero bytes S1 field length
.s1len()
.bits(0)
+ // Do not include S1 field in RAM if S1 length > 0
.s1incl()
.clear_bit()
+ // Zero code Indicator length
.cilen()
.bits(0)
+ // 32-bit zero preamble
.plen()
._32bit_zero()
+ // Include CRC in length
.crcinc()
.include()
});
r.pcnf1.write(|w| {
+ // Maximum packet length
w.maxlen()
.bits(Packet::MAX_PSDU_LEN)
+ // Zero static length
.statlen()
.bits(0)
+ // Zero base address length
.balen()
.bits(0)
+ // Little-endian
.endian()
.clear_bit()
+ // Disable packet whitening
.whiteen()
.clear_bit()
});
@@ -208,16 +188,9 @@ impl<'d, T: Instance> Radio<'d, T> {
while self.state() != state {}
}
+ /// Get the current radio state
fn state(&self) -> RadioState {
- let r = T::regs();
- match r.state.read().state().variant() {
- Some(state) => state,
- None => unreachable!(),
- }
- }
-
- fn trace_state(&self) {
- trace_state(self.state());
+ state(T::regs())
}
/// Moves the radio from any state to the DISABLED state
@@ -227,20 +200,17 @@ impl<'d, T: Instance> Radio<'d, T> {
loop {
match self.state() {
RadioState::DISABLED => return,
-
+ // idle or ramping up
RadioState::RX_RU | RadioState::RX_IDLE | RadioState::TX_RU | RadioState::TX_IDLE => {
r.tasks_disable.write(|w| w.tasks_disable().set_bit());
-
self.wait_for_radio_state(RadioState::DISABLED);
return;
}
-
// ramping down
RadioState::RX_DISABLE | RadioState::TX_DISABLE => {
self.wait_for_radio_state(RadioState::DISABLED);
return;
}
-
// cancel ongoing transfer or ongoing CCA
RadioState::RX => {
r.tasks_ccastop.write(|w| w.tasks_ccastop().set_bit());
@@ -262,35 +232,27 @@ impl<'d, T: Instance> Radio<'d, T> {
/// Moves the radio to the RXIDLE state
fn receive_prepare(&mut self) {
- let state = self.state();
-
- let disable = match state {
+ // clear related events
+ T::regs().events_ccabusy.reset();
+ T::regs().events_phyend.reset();
+ // NOTE to avoid errata 204 (see rev1 v1.4) we do TX_IDLE -> DISABLED -> RX_IDLE
+ let disable = match self.state() {
RadioState::DISABLED => false,
- RadioState::RX_DISABLE => true,
- RadioState::TX_DISABLE => true,
RadioState::RX_IDLE => self.needs_enable,
- // NOTE to avoid errata 204 (see rev1 v1.4) we do TX_IDLE -> DISABLED -> RX_IDLE
- RadioState::TX_IDLE => true,
- _ => unreachable!(),
+ _ => true,
};
if disable {
- trace!("Receive Setup");
- self.trace_state();
self.disable();
}
self.needs_enable = false;
}
+ /// Prepare radio for receiving a packet
fn receive_start(&mut self, packet: &mut Packet) {
// NOTE we do NOT check the address of `packet` because the mutable reference ensures it's
// allocated in RAM
let r = T::regs();
- // clear related events
- r.events_framestart.reset();
- r.events_ccabusy.reset();
- r.events_phyend.reset();
-
self.receive_prepare();
// Configure shortcuts
@@ -314,15 +276,13 @@ impl<'d, T: Instance> Radio<'d, T> {
}
}
+ /// Cancel receiving packet
fn receive_cancel() {
let r = T::regs();
r.shorts.reset();
- if r.events_framestart.read().events_framestart().bit_is_set() {
- // TODO: Is there a way to finish receiving this frame
- }
r.tasks_stop.write(|w| w.tasks_stop().set_bit());
loop {
- match get_state(r) {
+ match state(r) {
RadioState::DISABLED | RadioState::RX_IDLE => break,
_ => (),
}
@@ -336,7 +296,7 @@ impl<'d, T: Instance> Radio<'d, T> {
/// This methods returns the `Ok` variant if the CRC included the packet was successfully
/// validated by the hardware; otherwise it returns the `Err` variant. In either case, `packet`
/// will be updated with the received packet's data
- pub async fn receive(&mut self, packet: &mut Packet) -> Result<(), u16> {
+ pub async fn receive(&mut self, packet: &mut Packet) -> Result<(), Error> {
let s = T::state();
let r = T::regs();
@@ -369,7 +329,7 @@ impl<'d, T: Instance> Radio<'d, T> {
if r.crcstatus.read().crcstatus().bit_is_set() {
Ok(())
} else {
- Err(crc)
+ Err(Error::CrcFailed(crc))
}
}
@@ -387,11 +347,6 @@ impl<'d, T: Instance> Radio<'d, T> {
let s = T::state();
let r = T::regs();
- // clear related events
- r.events_framestart.reset();
- r.events_ccabusy.reset();
- r.events_phyend.reset();
-
// enable radio to perform cca
self.receive_prepare();
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 9b3a6cf49..333dfb33d 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -15,6 +15,9 @@ use core::marker::PhantomData;
use crate::{interrupt, pac, Peripheral};
+use pac::radio::state::STATE_A as RadioState;
+use pac::radio::txpower::TXPOWER_A as TxPower;
+
/// RADIO error.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -28,6 +31,8 @@ pub enum Error {
BufferNotInRAM,
/// Clear channel assessment reported channel in use
ChannelInUse,
+ /// CRC check failed
+ CrcFailed(u16),
}
/// Interrupt handler
@@ -89,3 +94,26 @@ pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: interrupt::typelevel::Interrupt;
}
+
+/// Get the state of the radio
+pub(crate) fn state(radio: &pac::radio::RegisterBlock) -> RadioState {
+ match radio.state.read().state().variant() {
+ Some(state) => state,
+ None => unreachable!(),
+ }
+}
+
+#[allow(dead_code)]
+pub(crate) fn trace_state(radio: &pac::radio::RegisterBlock) {
+ match state(radio) {
+ RadioState::DISABLED => trace!("radio:state:DISABLED"),
+ RadioState::RX_RU => trace!("radio:state:RX_RU"),
+ RadioState::RX_IDLE => trace!("radio:state:RX_IDLE"),
+ RadioState::RX => trace!("radio:state:RX"),
+ RadioState::RX_DISABLE => trace!("radio:state:RX_DISABLE"),
+ RadioState::TX_RU => trace!("radio:state:TX_RU"),
+ RadioState::TX_IDLE => trace!("radio:state:TX_IDLE"),
+ RadioState::TX => trace!("radio:state:TX"),
+ RadioState::TX_DISABLE => trace!("radio:state:TX_DISABLE"),
+ }
+}
From 84935fbfab6a053113c135110ec4a1f4373ccfb3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Tue, 5 Mar 2024 01:06:04 +0100
Subject: [PATCH 380/392] More formatting
---
embassy-nrf/src/radio/mod.rs | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 333dfb33d..487e52d79 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -13,11 +13,11 @@ pub mod ieee802154;
use core::marker::PhantomData;
-use crate::{interrupt, pac, Peripheral};
-
use pac::radio::state::STATE_A as RadioState;
use pac::radio::txpower::TXPOWER_A as TxPower;
+use crate::{interrupt, pac, Peripheral};
+
/// RADIO error.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
From bc258b322b3828b5e52cba3e51c7de4ec014268e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Tue, 5 Mar 2024 11:39:15 +0100
Subject: [PATCH 381/392] Support nearly all nRF5 RADIOs
---
embassy-nrf/src/chips/nrf51.rs | 5 ++++
embassy-nrf/src/chips/nrf52805.rs | 5 ++++
embassy-nrf/src/chips/nrf52810.rs | 5 ++++
embassy-nrf/src/chips/nrf52811.rs | 5 ++++
embassy-nrf/src/chips/nrf52820.rs | 5 ++++
embassy-nrf/src/chips/nrf52832.rs | 5 ++++
embassy-nrf/src/chips/nrf5340_net.rs | 5 ++++
embassy-nrf/src/lib.rs | 2 +-
embassy-nrf/src/radio/ble.rs | 35 +++++++++++++++++++++++++++-
embassy-nrf/src/radio/ieee802154.rs | 19 +++++++++++++++
embassy-nrf/src/radio/mod.rs | 7 +++++-
11 files changed, 95 insertions(+), 3 deletions(-)
diff --git a/embassy-nrf/src/chips/nrf51.rs b/embassy-nrf/src/chips/nrf51.rs
index 016352fb8..cc1cbc8a0 100644
--- a/embassy-nrf/src/chips/nrf51.rs
+++ b/embassy-nrf/src/chips/nrf51.rs
@@ -99,6 +99,9 @@ embassy_hal_internal::peripherals! {
// TEMP
TEMP,
+
+ // Radio
+ RADIO,
}
impl_timer!(TIMER0, TIMER0, TIMER0);
@@ -140,6 +143,8 @@ impl_pin!(P0_29, 0, 29);
impl_pin!(P0_30, 0, 30);
impl_pin!(P0_31, 0, 31);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52805.rs b/embassy-nrf/src/chips/nrf52805.rs
index 624d6613d..14c3f9b1a 100644
--- a/embassy-nrf/src/chips/nrf52805.rs
+++ b/embassy-nrf/src/chips/nrf52805.rs
@@ -129,6 +129,9 @@ embassy_hal_internal::peripherals! {
// QDEC
QDEC,
+
+ // Radio
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -209,6 +212,8 @@ impl_ppi_channel!(PPI_CH31, 31 => static);
impl_saadc_input!(P0_04, ANALOG_INPUT2);
impl_saadc_input!(P0_05, ANALOG_INPUT3);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52810.rs b/embassy-nrf/src/chips/nrf52810.rs
index 002feab3b..c607586db 100644
--- a/embassy-nrf/src/chips/nrf52810.rs
+++ b/embassy-nrf/src/chips/nrf52810.rs
@@ -135,6 +135,9 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
+
+ // Radio
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -235,6 +238,8 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52811.rs b/embassy-nrf/src/chips/nrf52811.rs
index 5952907f8..5f70365b4 100644
--- a/embassy-nrf/src/chips/nrf52811.rs
+++ b/embassy-nrf/src/chips/nrf52811.rs
@@ -135,6 +135,9 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
+
+ // Radio
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -237,6 +240,8 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52820.rs b/embassy-nrf/src/chips/nrf52820.rs
index c2f792cb9..82d097407 100644
--- a/embassy-nrf/src/chips/nrf52820.rs
+++ b/embassy-nrf/src/chips/nrf52820.rs
@@ -130,6 +130,9 @@ embassy_hal_internal::peripherals! {
// QDEC
QDEC,
+
+ // Radio
+ RADIO,
}
impl_usb!(USBD, USBD, USBD);
@@ -224,6 +227,8 @@ impl_ppi_channel!(PPI_CH29, 29 => static);
impl_ppi_channel!(PPI_CH30, 30 => static);
impl_ppi_channel!(PPI_CH31, 31 => static);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf52832.rs b/embassy-nrf/src/chips/nrf52832.rs
index 65d52364d..67b32fe5f 100644
--- a/embassy-nrf/src/chips/nrf52832.rs
+++ b/embassy-nrf/src/chips/nrf52832.rs
@@ -150,6 +150,9 @@ embassy_hal_internal::peripherals! {
// PDM
PDM,
+
+ // Radio
+ RADIO,
}
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
@@ -264,6 +267,8 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
POWER_CLOCK,
RADIO,
diff --git a/embassy-nrf/src/chips/nrf5340_net.rs b/embassy-nrf/src/chips/nrf5340_net.rs
index a7cf82872..65e8f9653 100644
--- a/embassy-nrf/src/chips/nrf5340_net.rs
+++ b/embassy-nrf/src/chips/nrf5340_net.rs
@@ -248,6 +248,9 @@ embassy_hal_internal::peripherals! {
P1_13,
P1_14,
P1_15,
+
+ // Radio
+ RADIO,
}
impl_uarte!(SERIAL0, UARTE0, SERIAL0);
@@ -345,6 +348,8 @@ impl_ppi_channel!(PPI_CH29, 29 => configurable);
impl_ppi_channel!(PPI_CH30, 30 => configurable);
impl_ppi_channel!(PPI_CH31, 31 => configurable);
+impl_radio!(RADIO, RADIO, RADIO);
+
embassy_hal_internal::interrupt_mod!(
CLOCK_POWER,
RADIO,
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 132bffa8b..06a25a36d 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -47,7 +47,7 @@ pub mod gpio;
pub mod gpiote;
// TODO: tested on other chips
-#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
+#[cfg(not(any(feature = "nrf51", feature = "_nrf9160")))]
pub mod radio;
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index 846ac98af..a306971b0 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -7,6 +7,7 @@ use core::task::Poll;
use embassy_hal_internal::drop::OnDrop;
use embassy_hal_internal::{into_ref, PeripheralRef};
pub use pac::radio::mode::MODE_A as Mode;
+#[cfg(not(feature = "nrf51"))]
use pac::radio::pcnf0::PLEN_A as PreambleLength;
use crate::interrupt::typelevel::Interrupt;
@@ -84,6 +85,7 @@ impl<'d, T: Instance> Radio<'d, T> {
// Ch map between 2400 MHZ .. 2500 MHz
// All modes use this range
+ #[cfg(not(feature = "nrf51"))]
r.frequency.write(|w| w.map().default());
// Configure shortcuts to simplify and speed up sending and receiving packets.
@@ -121,10 +123,18 @@ impl<'d, T: Instance> Radio<'d, T> {
let r = T::regs();
r.mode.write(|w| w.mode().variant(mode));
+ #[cfg(not(feature = "nrf51"))]
r.pcnf0.write(|w| {
w.plen().variant(match mode {
Mode::BLE_1MBIT => PreambleLength::_8BIT,
Mode::BLE_2MBIT => PreambleLength::_16BIT,
+ #[cfg(any(
+ feature = "nrf52811",
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "nrf52840",
+ feature = "_nrf5340-net"
+ ))]
Mode::BLE_LR125KBIT | Mode::BLE_LR500KBIT => PreambleLength::LONG_RANGE,
_ => unimplemented!(),
})
@@ -307,7 +317,11 @@ impl<'d, T: Instance> Radio<'d, T> {
self.trigger_and_wait_end(move || {
// Initialize the transmission
// trace!("txen");
+
+ #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
r.tasks_txen.write(|w| w.tasks_txen().set_bit());
+ #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
+ r.tasks_txen.write(|w| unsafe { w.bits(1) });
})
.await;
@@ -324,7 +338,10 @@ impl<'d, T: Instance> Radio<'d, T> {
self.trigger_and_wait_end(move || {
// Initialize the transmission
// trace!("rxen");
+ #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
r.tasks_rxen.write(|w| w.tasks_rxen().set_bit());
+ #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
+ r.tasks_rxen.write(|w| unsafe { w.bits(1) });
})
.await;
@@ -346,10 +363,16 @@ impl<'d, T: Instance> Radio<'d, T> {
r.intenclr.write(|w| w.end().clear());
r.events_end.reset();
+ #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
r.tasks_stop.write(|w| w.tasks_stop().set_bit());
+ #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
+ r.tasks_stop.write(|w| unsafe { w.bits(1) });
// The docs don't explicitly mention any event to acknowledge the stop task
+ #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
while r.events_end.read().events_end().bit_is_clear() {}
+ #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
+ while r.events_end.read().bits() == 0 {}
trace!("radio drop: stopped");
});
@@ -370,7 +393,11 @@ impl<'d, T: Instance> Radio<'d, T> {
// On poll check if interrupt happen
poll_fn(|cx| {
s.event_waker.register(cx.waker());
- if r.events_end.read().events_end().bit_is_set() {
+ #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
+ let end_event = r.events_end.read().events_end().bit_is_set();
+ #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
+ let end_event = r.events_end.read().bits() == 1;
+ if end_event {
// trace!("radio:end");
return core::task::Poll::Ready(());
}
@@ -394,10 +421,16 @@ impl<'d, T: Instance> Radio<'d, T> {
if self.state() != RadioState::DISABLED {
trace!("radio:disable");
// Trigger the disable task
+ #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
r.tasks_disable.write(|w| w.tasks_disable().set_bit());
+ #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
+ r.tasks_disable.write(|w| unsafe { w.bits(1) });
// Wait until the radio is disabled
+ #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
while r.events_disabled.read().events_disabled().bit_is_clear() {}
+ #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
+ while r.events_disabled.read().bits() == 0 {}
compiler_fence(Ordering::SeqCst);
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
index 2de53b392..7bec4cb8c 100644
--- a/embassy-nrf/src/radio/ieee802154.rs
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -162,15 +162,34 @@ impl<'d, T: Instance> Radio<'d, T> {
self.needs_enable = true;
let tx_power: TxPower = match power {
+ #[cfg(not(feature = "_nrf5340-net"))]
8 => TxPower::POS8D_BM,
+ #[cfg(not(feature = "_nrf5340-net"))]
7 => TxPower::POS7D_BM,
+ #[cfg(not(feature = "_nrf5340-net"))]
6 => TxPower::POS6D_BM,
+ #[cfg(not(feature = "_nrf5340-net"))]
5 => TxPower::POS5D_BM,
+ #[cfg(not(feature = "_nrf5340-net"))]
4 => TxPower::POS4D_BM,
+ #[cfg(not(feature = "_nrf5340-net"))]
3 => TxPower::POS3D_BM,
+ #[cfg(not(feature = "_nrf5340-net"))]
2 => TxPower::POS2D_BM,
0 => TxPower::_0D_BM,
+ #[cfg(feature = "_nrf5340-net")]
+ -1 => TxPower::NEG1D_BM,
+ #[cfg(feature = "_nrf5340-net")]
+ -2 => TxPower::NEG2D_BM,
+ #[cfg(feature = "_nrf5340-net")]
+ -3 => TxPower::NEG3D_BM,
-4 => TxPower::NEG4D_BM,
+ #[cfg(feature = "_nrf5340-net")]
+ -5 => TxPower::NEG5D_BM,
+ #[cfg(feature = "_nrf5340-net")]
+ -6 => TxPower::NEG6D_BM,
+ #[cfg(feature = "_nrf5340-net")]
+ -7 => TxPower::NEG7D_BM,
-8 => TxPower::NEG8D_BM,
-12 => TxPower::NEG12D_BM,
-16 => TxPower::NEG16D_BM,
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 487e52d79..adb8e1206 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -7,7 +7,12 @@
/// Bluetooth Low Energy Radio driver.
pub mod ble;
-#[cfg(any(feature = "nrf52840", feature = "nrf52833", feature = "_nrf5340-net"))]
+#[cfg(any(
+ feature = "nrf52820",
+ feature = "nrf52833",
+ feature = "nrf52840",
+ feature = "_nrf5340-net"
+))]
/// IEEE 802.15.4
pub mod ieee802154;
From 5408f21e993c0f94f04ed0c891b050d9a762289a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Tue, 5 Mar 2024 11:47:06 +0100
Subject: [PATCH 382/392] Fixed nrf51 radio build
---
embassy-nrf/src/lib.rs | 2 +-
embassy-nrf/src/radio/mod.rs | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index 06a25a36d..e59a7bd5d 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -47,7 +47,7 @@ pub mod gpio;
pub mod gpiote;
// TODO: tested on other chips
-#[cfg(not(any(feature = "nrf51", feature = "_nrf9160")))]
+#[cfg(not(any(feature = "_nrf9160")))]
pub mod radio;
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index adb8e1206..5a2982d89 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -6,6 +6,7 @@
#![macro_use]
/// Bluetooth Low Energy Radio driver.
+#[cfg(not(feature = "nrf51"))]
pub mod ble;
#[cfg(any(
feature = "nrf52820",
@@ -19,6 +20,7 @@ pub mod ieee802154;
use core::marker::PhantomData;
use pac::radio::state::STATE_A as RadioState;
+#[cfg(not(feature = "nrf51"))]
use pac::radio::txpower::TXPOWER_A as TxPower;
use crate::{interrupt, pac, Peripheral};
From 5b5d54c0c75e8a7fbe5370af4932c9845f4ce123 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Tue, 5 Mar 2024 11:58:32 +0100
Subject: [PATCH 383/392] Do not build radio for nrf5340-app
---
embassy-nrf/src/lib.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-nrf/src/lib.rs b/embassy-nrf/src/lib.rs
index e59a7bd5d..718f229a3 100644
--- a/embassy-nrf/src/lib.rs
+++ b/embassy-nrf/src/lib.rs
@@ -47,7 +47,7 @@ pub mod gpio;
pub mod gpiote;
// TODO: tested on other chips
-#[cfg(not(any(feature = "_nrf9160")))]
+#[cfg(not(any(feature = "_nrf9160", feature = "_nrf5340-app")))]
pub mod radio;
#[cfg(any(feature = "nrf52832", feature = "nrf52833", feature = "nrf52840"))]
From 869d590301c840cbb378a576f7c8268eec990b92 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Tue, 5 Mar 2024 21:38:05 +0800
Subject: [PATCH 384/392] ci stm32: update U5 H5 WBA target to Armv8-M
---
ci.sh | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/ci.sh b/ci.sh
index b2170a225..b5850aa9d 100755
--- a/ci.sh
+++ b/ci.sh
@@ -144,8 +144,8 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f107vc,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103re,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f100c4,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32h503rb,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32h562ag,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h503rb,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h562ag,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32wb35ce,defmt,exti,time-driver-any,time \
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features ''\
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'log' \
@@ -178,7 +178,7 @@ cargo batch \
--- build --release --manifest-path examples/stm32c0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32c0 \
--- build --release --manifest-path examples/stm32g0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32g0 \
--- build --release --manifest-path examples/stm32g4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32g4 \
- --- build --release --manifest-path examples/stm32h5/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h5 \
+ --- build --release --manifest-path examples/stm32h5/Cargo.toml --target thumbv8m.main-none-eabihf --out-dir out/examples/stm32h5 \
--- build --release --manifest-path examples/stm32h7/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h7 \
--- build --release --manifest-path examples/stm32l0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32l0 \
--- build --release --manifest-path examples/stm32l1/Cargo.toml --target thumbv7m-none-eabi --out-dir out/examples/stm32l1 \
@@ -216,10 +216,10 @@ cargo batch \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h753zi --out-dir out/tests/stm32h753zi \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h7a3zi --out-dir out/tests/stm32h7a3zi \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55rg --out-dir out/tests/stm32wb55rg \
- --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h563zi --out-dir out/tests/stm32h563zi \
- --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai --out-dir out/tests/stm32u585ai \
- --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u5a5zj --out-dir out/tests/stm32u5a5zj \
- --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wba52cg --out-dir out/tests/stm32wba52cg \
+ --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h563zi --out-dir out/tests/stm32h563zi \
+ --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u585ai --out-dir out/tests/stm32u585ai \
+ --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32u5a5zj --out-dir out/tests/stm32u5a5zj \
+ --- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32wba52cg --out-dir out/tests/stm32wba52cg \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l073rz --out-dir out/tests/stm32l073rz \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32l152re --out-dir out/tests/stm32l152re \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l4a6zg --out-dir out/tests/stm32l4a6zg \
From bb73d6b3fe81f26cb527d45bd700d2aef9b07090 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Erik=20B=C3=A5nvik?= <erik.public@gmail.com>
Date: Tue, 5 Mar 2024 15:01:05 +0100
Subject: [PATCH 385/392] Fixed suggestions, added nRF51 to BLE
---
embassy-nrf/src/radio/ble.rs | 36 +++--------------------------
embassy-nrf/src/radio/ieee802154.rs | 10 ++++----
embassy-nrf/src/radio/mod.rs | 20 ++--------------
embassy-nrf/src/util.rs | 1 -
4 files changed, 10 insertions(+), 57 deletions(-)
diff --git a/embassy-nrf/src/radio/ble.rs b/embassy-nrf/src/radio/ble.rs
index a306971b0..93003fb19 100644
--- a/embassy-nrf/src/radio/ble.rs
+++ b/embassy-nrf/src/radio/ble.rs
@@ -11,8 +11,8 @@ pub use pac::radio::mode::MODE_A as Mode;
use pac::radio::pcnf0::PLEN_A as PreambleLength;
use crate::interrupt::typelevel::Interrupt;
-pub use crate::radio::Error;
use crate::radio::*;
+pub use crate::radio::{Error, TxPower};
use crate::util::slice_in_ram_or;
/// Radio driver.
@@ -103,15 +103,7 @@ impl<'d, T: Instance> Radio<'d, T> {
}
fn state(&self) -> RadioState {
- match T::regs().state.read().state().variant() {
- Some(s) => s,
- None => unreachable!(),
- }
- }
-
- #[allow(dead_code)]
- fn trace_state(&self) {
- super::trace_state(T::regs())
+ super::state(T::regs())
}
/// Set the radio mode
@@ -318,9 +310,6 @@ impl<'d, T: Instance> Radio<'d, T> {
// Initialize the transmission
// trace!("txen");
- #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
- r.tasks_txen.write(|w| w.tasks_txen().set_bit());
- #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
r.tasks_txen.write(|w| unsafe { w.bits(1) });
})
.await;
@@ -338,9 +327,6 @@ impl<'d, T: Instance> Radio<'d, T> {
self.trigger_and_wait_end(move || {
// Initialize the transmission
// trace!("rxen");
- #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
- r.tasks_rxen.write(|w| w.tasks_rxen().set_bit());
- #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
r.tasks_rxen.write(|w| unsafe { w.bits(1) });
})
.await;
@@ -363,15 +349,9 @@ impl<'d, T: Instance> Radio<'d, T> {
r.intenclr.write(|w| w.end().clear());
r.events_end.reset();
- #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
- r.tasks_stop.write(|w| w.tasks_stop().set_bit());
- #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
r.tasks_stop.write(|w| unsafe { w.bits(1) });
// The docs don't explicitly mention any event to acknowledge the stop task
- #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
- while r.events_end.read().events_end().bit_is_clear() {}
- #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
while r.events_end.read().bits() == 0 {}
trace!("radio drop: stopped");
@@ -393,11 +373,7 @@ impl<'d, T: Instance> Radio<'d, T> {
// On poll check if interrupt happen
poll_fn(|cx| {
s.event_waker.register(cx.waker());
- #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
- let end_event = r.events_end.read().events_end().bit_is_set();
- #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
- let end_event = r.events_end.read().bits() == 1;
- if end_event {
+ if r.events_end.read().bits() == 1 {
// trace!("radio:end");
return core::task::Poll::Ready(());
}
@@ -421,15 +397,9 @@ impl<'d, T: Instance> Radio<'d, T> {
if self.state() != RadioState::DISABLED {
trace!("radio:disable");
// Trigger the disable task
- #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
- r.tasks_disable.write(|w| w.tasks_disable().set_bit());
- #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
r.tasks_disable.write(|w| unsafe { w.bits(1) });
// Wait until the radio is disabled
- #[cfg(not(any(feature = "nrf51", feature = "nrf52832")))]
- while r.events_disabled.read().events_disabled().bit_is_clear() {}
- #[cfg(any(feature = "nrf51", feature = "nrf52832"))]
while r.events_disabled.read().bits() == 0 {}
compiler_fence(Ordering::SeqCst);
diff --git a/embassy-nrf/src/radio/ieee802154.rs b/embassy-nrf/src/radio/ieee802154.rs
index 7bec4cb8c..298f8a574 100644
--- a/embassy-nrf/src/radio/ieee802154.rs
+++ b/embassy-nrf/src/radio/ieee802154.rs
@@ -162,19 +162,19 @@ impl<'d, T: Instance> Radio<'d, T> {
self.needs_enable = true;
let tx_power: TxPower = match power {
- #[cfg(not(feature = "_nrf5340-net"))]
+ #[cfg(not(any(feature = "nrf52811", feature = "_nrf5340-net")))]
8 => TxPower::POS8D_BM,
- #[cfg(not(feature = "_nrf5340-net"))]
+ #[cfg(not(any(feature = "nrf52811", feature = "_nrf5340-net")))]
7 => TxPower::POS7D_BM,
- #[cfg(not(feature = "_nrf5340-net"))]
+ #[cfg(not(any(feature = "nrf52811", feature = "_nrf5340-net")))]
6 => TxPower::POS6D_BM,
- #[cfg(not(feature = "_nrf5340-net"))]
+ #[cfg(not(any(feature = "nrf52811", feature = "_nrf5340-net")))]
5 => TxPower::POS5D_BM,
#[cfg(not(feature = "_nrf5340-net"))]
4 => TxPower::POS4D_BM,
#[cfg(not(feature = "_nrf5340-net"))]
3 => TxPower::POS3D_BM,
- #[cfg(not(feature = "_nrf5340-net"))]
+ #[cfg(not(any(feature = "nrf52811", feature = "_nrf5340-net")))]
2 => TxPower::POS2D_BM,
0 => TxPower::_0D_BM,
#[cfg(feature = "_nrf5340-net")]
diff --git a/embassy-nrf/src/radio/mod.rs b/embassy-nrf/src/radio/mod.rs
index 5a2982d89..4c0cc3280 100644
--- a/embassy-nrf/src/radio/mod.rs
+++ b/embassy-nrf/src/radio/mod.rs
@@ -6,9 +6,9 @@
#![macro_use]
/// Bluetooth Low Energy Radio driver.
-#[cfg(not(feature = "nrf51"))]
pub mod ble;
#[cfg(any(
+ feature = "nrf52811",
feature = "nrf52820",
feature = "nrf52833",
feature = "nrf52840",
@@ -20,8 +20,7 @@ pub mod ieee802154;
use core::marker::PhantomData;
use pac::radio::state::STATE_A as RadioState;
-#[cfg(not(feature = "nrf51"))]
-use pac::radio::txpower::TXPOWER_A as TxPower;
+pub use pac::radio::txpower::TXPOWER_A as TxPower;
use crate::{interrupt, pac, Peripheral};
@@ -109,18 +108,3 @@ pub(crate) fn state(radio: &pac::radio::RegisterBlock) -> RadioState {
None => unreachable!(),
}
}
-
-#[allow(dead_code)]
-pub(crate) fn trace_state(radio: &pac::radio::RegisterBlock) {
- match state(radio) {
- RadioState::DISABLED => trace!("radio:state:DISABLED"),
- RadioState::RX_RU => trace!("radio:state:RX_RU"),
- RadioState::RX_IDLE => trace!("radio:state:RX_IDLE"),
- RadioState::RX => trace!("radio:state:RX"),
- RadioState::RX_DISABLE => trace!("radio:state:RX_DISABLE"),
- RadioState::TX_RU => trace!("radio:state:TX_RU"),
- RadioState::TX_IDLE => trace!("radio:state:TX_IDLE"),
- RadioState::TX => trace!("radio:state:TX"),
- RadioState::TX_DISABLE => trace!("radio:state:TX_DISABLE"),
- }
-}
diff --git a/embassy-nrf/src/util.rs b/embassy-nrf/src/util.rs
index 6cdb97f08..13aba7dec 100644
--- a/embassy-nrf/src/util.rs
+++ b/embassy-nrf/src/util.rs
@@ -34,7 +34,6 @@ pub(crate) fn slice_in_ram<T>(slice: *const [T]) -> bool {
}
/// Return an error if slice is not in RAM. Skips check if slice is zero-length.
-#[cfg(not(feature = "nrf51"))]
pub(crate) fn slice_in_ram_or<T, E>(slice: *const [T], err: E) -> Result<(), E> {
let (_, len) = slice_ptr_parts(slice);
if len == 0 || slice_in_ram(slice) {
From 6d35e3f63ca04e648a2ee33a1737f10704b388b3 Mon Sep 17 00:00:00 2001
From: eZio Pan <eziopan@qq.com>
Date: Wed, 6 Mar 2024 00:58:04 +0800
Subject: [PATCH 386/392] ci stm32: build target fix
---
ci.sh | 51 ++++++++++++++++++++++++++-------------------------
1 file changed, 26 insertions(+), 25 deletions(-)
diff --git a/ci.sh b/ci.sh
index b5850aa9d..cd82af2f1 100755
--- a/ci.sh
+++ b/ci.sh
@@ -15,7 +15,8 @@ if [ $TARGET = "x86_64-unknown-linux-gnu" ]; then
BUILD_EXTRA="--- build --release --manifest-path examples/std/Cargo.toml --target $TARGET --out-dir out/examples/std"
fi
-cargo batch \
+# CI intentionally does not use -eabihf on thumbv7em to minimize dep compile time.
+cargo batch \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features log \
--- build --release --manifest-path embassy-executor/Cargo.toml --target thumbv7em-none-eabi --features defmt \
@@ -87,16 +88,16 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030r8,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f031k6,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f030rc,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f070f6,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f078vb,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f038f6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f030c6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f058t8,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f030r8,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f031k6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f030rc,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f070f6,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f078vb,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f042g4,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32f072c8,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f401ve,defmt,exti,time-driver-any \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f405zg,defmt,exti,time-driver-any \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f407zg,defmt,exti,time-driver-any \
@@ -132,9 +133,9 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l051k8,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l073cz,defmt,exti,time-driver-any,low-power,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32l151cb-a,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f303c8,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f398ve,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f378cc,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f303c8,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f398ve,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f378cc,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g0c1ve,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f217zg,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32l552ze,defmt,exti,time-driver-any,low-power,time \
@@ -146,7 +147,7 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f100c4,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h503rb,defmt,exti,time-driver-any,time \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv8m.main-none-eabihf --features stm32h562ag,defmt,exti,time-driver-any,time \
- --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32wb35ce,defmt,exti,time-driver-any,time \
+ --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb35ce,defmt,exti,time-driver-any,time \
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features ''\
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'log' \
--- build --release --manifest-path cyw43/Cargo.toml --target thumbv6m-none-eabi --features 'defmt' \
@@ -171,10 +172,10 @@ cargo batch \
--- build --release --manifest-path examples/stm32f0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32f0 \
--- build --release --manifest-path examples/stm32f1/Cargo.toml --target thumbv7m-none-eabi --out-dir out/examples/stm32f1 \
--- build --release --manifest-path examples/stm32f2/Cargo.toml --target thumbv7m-none-eabi --out-dir out/examples/stm32f2 \
- --- build --release --manifest-path examples/stm32f3/Cargo.toml --target thumbv7em-none-eabihf --out-dir out/examples/stm32f3 \
- --- build --release --manifest-path examples/stm32f334/Cargo.toml --target thumbv7em-none-eabihf --out-dir out/examples/stm32f334 \
+ --- build --release --manifest-path examples/stm32f3/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32f3 \
+ --- build --release --manifest-path examples/stm32f334/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32f334 \
--- build --release --manifest-path examples/stm32f4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32f4 \
- --- build --release --manifest-path examples/stm32f7/Cargo.toml --target thumbv7em-none-eabihf --out-dir out/examples/stm32f7 \
+ --- build --release --manifest-path examples/stm32f7/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32f7 \
--- build --release --manifest-path examples/stm32c0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32c0 \
--- build --release --manifest-path examples/stm32g0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32g0 \
--- build --release --manifest-path examples/stm32g4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32g4 \
@@ -185,10 +186,10 @@ cargo batch \
--- build --release --manifest-path examples/stm32l4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32l4 \
--- build --release --manifest-path examples/stm32l5/Cargo.toml --target thumbv8m.main-none-eabihf --out-dir out/examples/stm32l5 \
--- build --release --manifest-path examples/stm32u5/Cargo.toml --target thumbv8m.main-none-eabihf --out-dir out/examples/stm32u5 \
- --- build --release --manifest-path examples/stm32wb/Cargo.toml --target thumbv7em-none-eabihf --out-dir out/examples/stm32wb \
+ --- build --release --manifest-path examples/stm32wb/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32wb \
--- build --release --manifest-path examples/stm32wba/Cargo.toml --target thumbv8m.main-none-eabihf --out-dir out/examples/stm32wba \
- --- build --release --manifest-path examples/stm32wl/Cargo.toml --target thumbv7em-none-eabihf --out-dir out/examples/stm32wl \
- --- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840,skip-include --out-dir out/examples/boot/nrf52840 \
+ --- build --release --manifest-path examples/stm32wl/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32wl \
+ --- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840,skip-include --out-dir out/examples/boot/nrf52840 \
--- build --release --manifest-path examples/boot/application/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns,skip-include --out-dir out/examples/boot/nrf9160 \
--- build --release --manifest-path examples/boot/application/rp/Cargo.toml --target thumbv6m-none-eabi --features skip-include --out-dir out/examples/boot/rp \
--- build --release --manifest-path examples/boot/application/stm32f3/Cargo.toml --target thumbv7em-none-eabi --features skip-include --out-dir out/examples/boot/stm32f3 \
@@ -197,14 +198,14 @@ cargo batch \
--- build --release --manifest-path examples/boot/application/stm32l0/Cargo.toml --target thumbv6m-none-eabi --features skip-include --out-dir out/examples/boot/stm32l0 \
--- build --release --manifest-path examples/boot/application/stm32l1/Cargo.toml --target thumbv7m-none-eabi --features skip-include --out-dir out/examples/boot/stm32l1 \
--- build --release --manifest-path examples/boot/application/stm32l4/Cargo.toml --target thumbv7em-none-eabi --features skip-include --out-dir out/examples/boot/stm32l4 \
- --- build --release --manifest-path examples/boot/application/stm32wl/Cargo.toml --target thumbv7em-none-eabihf --features skip-include --out-dir out/examples/boot/stm32wl \
- --- build --release --manifest-path examples/boot/application/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabihf --out-dir out/examples/boot/stm32wb-dfu \
+ --- build --release --manifest-path examples/boot/application/stm32wl/Cargo.toml --target thumbv7em-none-eabi --features skip-include --out-dir out/examples/boot/stm32wl \
+ --- build --release --manifest-path examples/boot/application/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/boot/stm32wb-dfu \
--- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840 \
--- build --release --manifest-path examples/boot/bootloader/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns \
--- build --release --manifest-path examples/boot/bootloader/rp/Cargo.toml --target thumbv6m-none-eabi \
--- build --release --manifest-path examples/boot/bootloader/stm32/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32wl55jc-cm4 \
- --- build --release --manifest-path examples/boot/bootloader/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabihf --features embassy-stm32/stm32wb55rg \
- --- build --release --manifest-path examples/boot/bootloader/stm32-dual-bank/Cargo.toml --target thumbv7em-none-eabihf --features embassy-stm32/stm32h747xi-cm7 \
+ --- build --release --manifest-path examples/boot/bootloader/stm32wb-dfu/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32wb55rg \
+ --- build --release --manifest-path examples/boot/bootloader/stm32-dual-bank/Cargo.toml --target thumbv7em-none-eabi --features embassy-stm32/stm32h747xi-cm7 \
--- build --release --manifest-path examples/wasm/Cargo.toml --target wasm32-unknown-unknown --out-dir out/examples/wasm \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32f103c8 --out-dir out/tests/stm32f103c8 \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi --out-dir out/tests/stm32f429zi \
From 315fb040ee15306158d1c7c24249ee08cd22e36a Mon Sep 17 00:00:00 2001
From: Vo Trung Chi <chi.votrung@vn.bosch.com>
Date: Thu, 7 Mar 2024 00:45:01 +0700
Subject: [PATCH 387/392] stm32: add usb_hid_mouse example
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
---
examples/stm32f4/Cargo.toml | 1 +
examples/stm32f4/src/bin/usb_hid_mouse.rs | 148 ++++++++++++++++++++++
2 files changed, 149 insertions(+)
create mode 100644 examples/stm32f4/src/bin/usb_hid_mouse.rs
diff --git a/examples/stm32f4/Cargo.toml b/examples/stm32f4/Cargo.toml
index cd46fc85b..512158bef 100644
--- a/examples/stm32f4/Cargo.toml
+++ b/examples/stm32f4/Cargo.toml
@@ -27,6 +27,7 @@ heapless = { version = "0.8", default-features = false }
nb = "1.0.0"
embedded-storage = "0.3.1"
micromath = "2.0.0"
+usbd-hid = "0.7.0"
static_cell = "2"
chrono = { version = "^0.4", default-features = false}
diff --git a/examples/stm32f4/src/bin/usb_hid_mouse.rs b/examples/stm32f4/src/bin/usb_hid_mouse.rs
new file mode 100644
index 000000000..add1ef306
--- /dev/null
+++ b/examples/stm32f4/src/bin/usb_hid_mouse.rs
@@ -0,0 +1,148 @@
+#![no_std]
+#![no_main]
+
+use defmt::*;
+use embassy_executor::Spawner;
+use embassy_stm32::time::Hertz;
+use embassy_stm32::usb_otg::Driver;
+use embassy_stm32::{bind_interrupts, peripherals, usb_otg, Config};
+use embassy_time::Timer;
+use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
+use embassy_usb::control::OutResponse;
+use embassy_usb::Builder;
+use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
+use futures::future::join;
+use {defmt_rtt as _, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+ OTG_FS => usb_otg::InterruptHandler<peripherals::USB_OTG_FS>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+ let mut config = Config::default();
+ {
+ use embassy_stm32::rcc::*;
+ config.rcc.hse = Some(Hse {
+ freq: Hertz(8_000_000),
+ mode: HseMode::Bypass,
+ });
+ config.rcc.pll_src = PllSource::HSE;
+ config.rcc.pll = Some(Pll {
+ prediv: PllPreDiv::DIV4,
+ mul: PllMul::MUL168,
+ divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+ divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+ divr: None,
+ });
+ config.rcc.ahb_pre = AHBPrescaler::DIV1;
+ config.rcc.apb1_pre = APBPrescaler::DIV4;
+ config.rcc.apb2_pre = APBPrescaler::DIV2;
+ config.rcc.sys = Sysclk::PLL1_P;
+ }
+ let p = embassy_stm32::init(config);
+
+ // Create the driver, from the HAL.
+ let mut ep_out_buffer = [0u8; 256];
+ let mut config = embassy_stm32::usb_otg::Config::default();
+ config.vbus_detection = true;
+ let driver = Driver::new_fs(p.USB_OTG_FS, Irqs, p.PA12, p.PA11, &mut ep_out_buffer, config);
+
+ // Create embassy-usb Config
+ let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
+ config.manufacturer = Some("Embassy");
+ config.product = Some("HID mouse example");
+ config.serial_number = Some("12345678");
+
+ // Required for windows compatibility.
+ // https://developer.nordicsemi.com/nRF_Connect_SDK/doc/1.9.1/kconfig/CONFIG_CDC_ACM_IAD.html#help
+ config.device_class = 0xEF;
+ config.device_sub_class = 0x02;
+ config.device_protocol = 0x01;
+ config.composite_with_iads = true;
+
+ // Create embassy-usb DeviceBuilder using the driver and config.
+ // It needs some buffers for building the descriptors.
+ let mut device_descriptor = [0; 256];
+ let mut config_descriptor = [0; 256];
+ let mut bos_descriptor = [0; 256];
+ let mut control_buf = [0; 64];
+
+ let request_handler = MyRequestHandler {};
+
+ let mut state = State::new();
+
+ let mut builder = Builder::new(
+ driver,
+ config,
+ &mut device_descriptor,
+ &mut config_descriptor,
+ &mut bos_descriptor,
+ &mut [], // no msos descriptors
+ &mut control_buf,
+ );
+
+ // Create classes on the builder.
+ let config = embassy_usb::class::hid::Config {
+ report_descriptor: MouseReport::desc(),
+ request_handler: Some(&request_handler),
+ poll_ms: 60,
+ max_packet_size: 8,
+ };
+
+ let mut writer = HidWriter::<_, 5>::new(&mut builder, &mut state, config);
+
+ // Build the builder.
+ let mut usb = builder.build();
+
+ // Run the USB device.
+ let usb_fut = usb.run();
+
+ // Do stuff with the class!
+ let hid_fut = async {
+ let mut y: i8 = 5;
+ loop {
+ Timer::after_millis(500).await;
+
+ y = -y;
+ let report = MouseReport {
+ buttons: 0,
+ x: 0,
+ y,
+ wheel: 0,
+ pan: 0,
+ };
+ match writer.write_serialize(&report).await {
+ Ok(()) => {}
+ Err(e) => warn!("Failed to send report: {:?}", e),
+ }
+ }
+ };
+
+// Run everything concurrently.
+// If we had made everything `'static` above instead, we could do this using separate tasks instead.
+join(usb_fut, hid_fut).await;
+}
+
+struct MyRequestHandler {}
+
+impl RequestHandler for MyRequestHandler {
+fn get_report(&self, id: ReportId, _buf: &mut [u8]) -> Option<usize> {
+ info!("Get report for {:?}", id);
+ None
+}
+
+fn set_report(&self, id: ReportId, data: &[u8]) -> OutResponse {
+ info!("Set report for {:?}: {=[u8]}", id, data);
+ OutResponse::Accepted
+}
+
+fn set_idle_ms(&self, id: Option<ReportId>, dur: u32) {
+ info!("Set idle rate for {:?} to {:?}", id, dur);
+}
+
+fn get_idle_ms(&self, id: Option<ReportId>) -> Option<u32> {
+ info!("Get idle rate for {:?}", id);
+ None
+}
+}
From 61653229b6c0c77235704dc3b4283f57deabc02b Mon Sep 17 00:00:00 2001
From: Vo Trung Chi <chi.votrung@vn.bosch.com>
Date: Thu, 7 Mar 2024 00:57:18 +0700
Subject: [PATCH 388/392] stm32: add usb_hid_mouse example
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
---
examples/stm32f4/src/bin/usb_hid_mouse.rs | 32 +++++++++++------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/examples/stm32f4/src/bin/usb_hid_mouse.rs b/examples/stm32f4/src/bin/usb_hid_mouse.rs
index add1ef306..0dc5f5804 100644
--- a/examples/stm32f4/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32f4/src/bin/usb_hid_mouse.rs
@@ -10,8 +10,8 @@ use embassy_time::Timer;
use embassy_usb::class::hid::{HidWriter, ReportId, RequestHandler, State};
use embassy_usb::control::OutResponse;
use embassy_usb::Builder;
-use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
use futures::future::join;
+use usbd_hid::descriptor::{MouseReport, SerializedDescriptor};
use {defmt_rtt as _, panic_probe as _};
bind_interrupts!(struct Irqs {
@@ -127,22 +127,22 @@ join(usb_fut, hid_fut).await;
struct MyRequestHandler {}
impl RequestHandler for MyRequestHandler {
-fn get_report(&self, id: ReportId, _buf: &mut [u8]) -> Option<usize> {
- info!("Get report for {:?}", id);
- None
-}
+ fn get_report(&self, id: ReportId, _buf: &mut [u8]) -> Option<usize> {
+ info!("Get report for {:?}", id);
+ None
+ }
-fn set_report(&self, id: ReportId, data: &[u8]) -> OutResponse {
- info!("Set report for {:?}: {=[u8]}", id, data);
- OutResponse::Accepted
-}
+ fn set_report(&self, id: ReportId, data: &[u8]) -> OutResponse {
+ info!("Set report for {:?}: {=[u8]}", id, data);
+ OutResponse::Accepted
+ }
-fn set_idle_ms(&self, id: Option<ReportId>, dur: u32) {
- info!("Set idle rate for {:?} to {:?}", id, dur);
-}
+ fn set_idle_ms(&self, id: Option<ReportId>, dur: u32) {
+ info!("Set idle rate for {:?} to {:?}", id, dur);
+ }
-fn get_idle_ms(&self, id: Option<ReportId>) -> Option<u32> {
- info!("Get idle rate for {:?}", id);
- None
-}
+ fn get_idle_ms(&self, id: Option<ReportId>) -> Option<u32> {
+ info!("Get idle rate for {:?}", id);
+ None
+ }
}
From 5d53348c76242a83cdd42a69ec2ae418d43f6238 Mon Sep 17 00:00:00 2001
From: Vo Trung Chi <chi.votrung@vn.bosch.com>
Date: Thu, 7 Mar 2024 00:59:49 +0700
Subject: [PATCH 389/392] stm32: add usb_hid_mouse example
Signed-off-by: Vo Trung Chi <chi.votrung@vn.bosch.com>
---
examples/stm32f4/src/bin/usb_hid_mouse.rs | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/examples/stm32f4/src/bin/usb_hid_mouse.rs b/examples/stm32f4/src/bin/usb_hid_mouse.rs
index 0dc5f5804..c98792880 100644
--- a/examples/stm32f4/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32f4/src/bin/usb_hid_mouse.rs
@@ -119,9 +119,9 @@ async fn main(_spawner: Spawner) {
}
};
-// Run everything concurrently.
-// If we had made everything `'static` above instead, we could do this using separate tasks instead.
-join(usb_fut, hid_fut).await;
+ // Run everything concurrently.
+ // If we had made everything `'static` above instead, we could do this using separate tasks instead.
+ join(usb_fut, hid_fut).await;
}
struct MyRequestHandler {}
From f3efa4ee3ba562fd51cd49b70a6c5305a1aaac6a Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 6 Mar 2024 19:45:57 +0100
Subject: [PATCH 390/392] stm32/rtc: remove use of deprecated .timestamp()
---
examples/stm32f4/src/bin/rtc.rs | 2 +-
examples/stm32h7/src/bin/rtc.rs | 4 ++--
examples/stm32l4/src/bin/rtc.rs | 4 ++--
examples/stm32wl/src/bin/rtc.rs | 4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/examples/stm32f4/src/bin/rtc.rs b/examples/stm32f4/src/bin/rtc.rs
index abab07b6b..82d8a37ba 100644
--- a/examples/stm32f4/src/bin/rtc.rs
+++ b/examples/stm32f4/src/bin/rtc.rs
@@ -28,7 +28,7 @@ async fn main(_spawner: Spawner) {
loop {
let now: NaiveDateTime = rtc.now().unwrap().into();
- info!("{}", now.timestamp());
+ info!("{}", now.and_utc().timestamp());
Timer::after_millis(1000).await;
}
diff --git a/examples/stm32h7/src/bin/rtc.rs b/examples/stm32h7/src/bin/rtc.rs
index c6b9cf57e..0adb48877 100644
--- a/examples/stm32h7/src/bin/rtc.rs
+++ b/examples/stm32h7/src/bin/rtc.rs
@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
.unwrap();
let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
- info!("Got RTC! {:?}", now.timestamp());
+ info!("Got RTC! {:?}", now.and_utc().timestamp());
rtc.set_datetime(now.into()).expect("datetime not set");
@@ -32,5 +32,5 @@ async fn main(_spawner: Spawner) {
Timer::after_millis(20000).await;
let then: NaiveDateTime = rtc.now().unwrap().into();
- info!("Got RTC! {:?}", then.timestamp());
+ info!("Got RTC! {:?}", then.and_utc().timestamp());
}
diff --git a/examples/stm32l4/src/bin/rtc.rs b/examples/stm32l4/src/bin/rtc.rs
index a8a375ab4..f554f0f78 100644
--- a/examples/stm32l4/src/bin/rtc.rs
+++ b/examples/stm32l4/src/bin/rtc.rs
@@ -40,7 +40,7 @@ async fn main(_spawner: Spawner) {
.unwrap();
let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
- info!("Got RTC! {:?}", now.timestamp());
+ info!("Got RTC! {:?}", now.and_utc().timestamp());
rtc.set_datetime(now.into()).expect("datetime not set");
@@ -48,5 +48,5 @@ async fn main(_spawner: Spawner) {
Timer::after_millis(20000).await;
let then: NaiveDateTime = rtc.now().unwrap().into();
- info!("Got RTC! {:?}", then.timestamp());
+ info!("Got RTC! {:?}", then.and_utc().timestamp());
}
diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs
index 0c26426ef..cf7d6d220 100644
--- a/examples/stm32wl/src/bin/rtc.rs
+++ b/examples/stm32wl/src/bin/rtc.rs
@@ -40,7 +40,7 @@ async fn main(_spawner: Spawner) {
.unwrap();
let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
- info!("Got RTC! {:?}", now.timestamp());
+ info!("Got RTC! {:?}", now.and_utc().timestamp());
rtc.set_datetime(now.into()).expect("datetime not set");
@@ -48,5 +48,5 @@ async fn main(_spawner: Spawner) {
Timer::after_millis(20000).await;
let then: NaiveDateTime = rtc.now().unwrap().into();
- info!("Got RTC! {:?}", then.timestamp());
+ info!("Got RTC! {:?}", then.and_utc().timestamp());
}
From bbc06458a31946a2faf96d418d51d09d880fb1c9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Timo=20Kro=CC=88ger?= <timokroeger93@gmail.com>
Date: Thu, 7 Mar 2024 15:03:40 +0100
Subject: [PATCH 391/392] stm32: Implement `Channel` trait for `AnyChannel`
---
embassy-stm32/src/dma/mod.rs | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 6b1ac6207..960483f34 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -96,6 +96,13 @@ impl AnyChannel {
}
}
+impl sealed::Channel for AnyChannel {
+ fn id(&self) -> u8 {
+ self.id
+ }
+}
+impl Channel for AnyChannel {}
+
const CHANNEL_COUNT: usize = crate::_generated::DMA_CHANNELS.len();
static STATE: [ChannelState; CHANNEL_COUNT] = [ChannelState::NEW; CHANNEL_COUNT];
From bb3711bbf9fc1c63148c41587b5d0d0e0890c7cc Mon Sep 17 00:00:00 2001
From: Tomas Barton <87450069+tomasbarton-stemcell@users.noreply.github.com>
Date: Thu, 7 Mar 2024 06:51:32 -0800
Subject: [PATCH 392/392] update stm32c0 HSI frequency
---
embassy-stm32/src/rcc/c0.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index 7ca737bf0..349f978c5 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -6,7 +6,7 @@ use crate::pac::{FLASH, RCC};
use crate::time::Hertz;
/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
+pub const HSI_FREQ: Hertz = Hertz(48_000_000);
/// HSE Mode
#[derive(Clone, Copy, Eq, PartialEq)]