From 051c6350ea5340d860dde0cea1b4c21e4f4884b6 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Thu, 17 Mar 2022 18:23:47 +0200 Subject: [PATCH 1/2] Make UART futures Send --- embassy-stm32/src/usart/mod.rs | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 80d928786..83cdd66b9 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -106,8 +106,8 @@ impl<'d, T: Instance, TxDma> UartTx<'d, T, TxDma> { reg.set_dmat(true); }); } - let dst = tdr(T::regs()); - crate::dma::write(ch, request, buffer, dst).await; + let transfer = crate::dma::write(ch, request, buffer, tdr(T::regs())); + transfer.await; Ok(()) } @@ -150,9 +150,8 @@ impl<'d, T: Instance, RxDma> UartRx<'d, T, RxDma> { reg.set_dmar(true); }); } - let r = T::regs(); - let src = rdr(r); - crate::dma::read(ch, request, src, buffer).await; + let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer); + transfer.await; Ok(()) } From d26b751edc9aa9d5e5d74da298fcd35ade1d5620 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Thu, 17 Mar 2022 19:41:44 +0200 Subject: [PATCH 2/2] Add comments --- embassy-stm32/src/usart/mod.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs index 83cdd66b9..0466065f1 100644 --- a/embassy-stm32/src/usart/mod.rs +++ b/embassy-stm32/src/usart/mod.rs @@ -106,6 +106,8 @@ impl<'d, T: Instance, TxDma> UartTx<'d, T, TxDma> { reg.set_dmat(true); }); } + // If we don't assign future to a variable, the data register pointer + // is held across an await and makes the future non-Send. let transfer = crate::dma::write(ch, request, buffer, tdr(T::regs())); transfer.await; Ok(()) @@ -150,6 +152,8 @@ impl<'d, T: Instance, RxDma> UartRx<'d, T, RxDma> { reg.set_dmar(true); }); } + // If we don't assign future to a variable, the data register pointer + // is held across an await and makes the future non-Send. let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer); transfer.await; Ok(())