stm32: add H5 support.
This commit is contained in:
Dario Nieuwenhuis
parent
9f28d80977
commit
611d023829
22 changed files with 1390 additions and 21 deletions
3
ci.sh
3
ci.sh
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@ -66,6 +66,8 @@ cargo batch \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f107vc,defmt,exti,time-driver-any,unstable-traits \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f103re,defmt,exti,time-driver-any,unstable-traits \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f100c4,defmt,exti,time-driver-any,unstable-traits \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32h503rb,defmt,exti,time-driver-any,unstable-traits \
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--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32h562ag,defmt,exti,time-driver-any,unstable-traits \
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--- build --release --manifest-path embassy-boot/nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840 \
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--- build --release --manifest-path embassy-boot/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns \
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--- build --release --manifest-path embassy-boot/rp/Cargo.toml --target thumbv6m-none-eabi \
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@ -87,6 +89,7 @@ cargo batch \
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--- build --release --manifest-path examples/stm32c0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32c0 \
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--- build --release --manifest-path examples/stm32g0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32g0 \
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--- build --release --manifest-path examples/stm32g4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32g4 \
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--- build --release --manifest-path examples/stm32h5/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h5 \
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--- build --release --manifest-path examples/stm32h7/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h7 \
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--- build --release --manifest-path examples/stm32l0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32l0 \
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--- build --release --manifest-path examples/stm32l1/Cargo.toml --target thumbv7m-none-eabi --out-dir out/examples/stm32l1 \
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@ -834,6 +834,37 @@ stm32g4a1ke = [ "stm32-metapac/stm32g4a1ke" ]
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stm32g4a1me = [ "stm32-metapac/stm32g4a1me" ]
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stm32g4a1re = [ "stm32-metapac/stm32g4a1re" ]
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stm32g4a1ve = [ "stm32-metapac/stm32g4a1ve" ]
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stm32h503cb = [ "stm32-metapac/stm32h503cb" ]
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stm32h503eb = [ "stm32-metapac/stm32h503eb" ]
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stm32h503kb = [ "stm32-metapac/stm32h503kb" ]
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stm32h503rb = [ "stm32-metapac/stm32h503rb" ]
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stm32h562ag = [ "stm32-metapac/stm32h562ag" ]
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stm32h562ai = [ "stm32-metapac/stm32h562ai" ]
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stm32h562ig = [ "stm32-metapac/stm32h562ig" ]
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stm32h562ii = [ "stm32-metapac/stm32h562ii" ]
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stm32h562rg = [ "stm32-metapac/stm32h562rg" ]
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stm32h562ri = [ "stm32-metapac/stm32h562ri" ]
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stm32h562vg = [ "stm32-metapac/stm32h562vg" ]
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stm32h562vi = [ "stm32-metapac/stm32h562vi" ]
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stm32h562zg = [ "stm32-metapac/stm32h562zg" ]
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stm32h562zi = [ "stm32-metapac/stm32h562zi" ]
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stm32h563ag = [ "stm32-metapac/stm32h563ag" ]
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stm32h563ai = [ "stm32-metapac/stm32h563ai" ]
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stm32h563ig = [ "stm32-metapac/stm32h563ig" ]
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stm32h563ii = [ "stm32-metapac/stm32h563ii" ]
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stm32h563mi = [ "stm32-metapac/stm32h563mi" ]
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stm32h563rg = [ "stm32-metapac/stm32h563rg" ]
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stm32h563ri = [ "stm32-metapac/stm32h563ri" ]
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stm32h563vg = [ "stm32-metapac/stm32h563vg" ]
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stm32h563vi = [ "stm32-metapac/stm32h563vi" ]
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stm32h563zg = [ "stm32-metapac/stm32h563zg" ]
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stm32h563zi = [ "stm32-metapac/stm32h563zi" ]
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stm32h573ai = [ "stm32-metapac/stm32h573ai" ]
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stm32h573ii = [ "stm32-metapac/stm32h573ii" ]
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stm32h573mi = [ "stm32-metapac/stm32h573mi" ]
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stm32h573ri = [ "stm32-metapac/stm32h573ri" ]
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stm32h573vi = [ "stm32-metapac/stm32h573vi" ]
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stm32h573zi = [ "stm32-metapac/stm32h573zi" ]
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stm32h723ve = [ "stm32-metapac/stm32h723ve" ]
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stm32h723vg = [ "stm32-metapac/stm32h723vg" ]
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stm32h723ze = [ "stm32-metapac/stm32h723ze" ]
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@ -1316,6 +1347,22 @@ stm32l562qe = [ "stm32-metapac/stm32l562qe" ]
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stm32l562re = [ "stm32-metapac/stm32l562re" ]
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stm32l562ve = [ "stm32-metapac/stm32l562ve" ]
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stm32l562ze = [ "stm32-metapac/stm32l562ze" ]
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stm32u535cb = [ "stm32-metapac/stm32u535cb" ]
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stm32u535cc = [ "stm32-metapac/stm32u535cc" ]
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stm32u535ce = [ "stm32-metapac/stm32u535ce" ]
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stm32u535je = [ "stm32-metapac/stm32u535je" ]
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stm32u535nc = [ "stm32-metapac/stm32u535nc" ]
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stm32u535ne = [ "stm32-metapac/stm32u535ne" ]
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stm32u535rb = [ "stm32-metapac/stm32u535rb" ]
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stm32u535rc = [ "stm32-metapac/stm32u535rc" ]
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stm32u535re = [ "stm32-metapac/stm32u535re" ]
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stm32u535vc = [ "stm32-metapac/stm32u535vc" ]
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stm32u535ve = [ "stm32-metapac/stm32u535ve" ]
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stm32u545ce = [ "stm32-metapac/stm32u545ce" ]
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stm32u545je = [ "stm32-metapac/stm32u545je" ]
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stm32u545ne = [ "stm32-metapac/stm32u545ne" ]
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stm32u545re = [ "stm32-metapac/stm32u545re" ]
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stm32u545ve = [ "stm32-metapac/stm32u545ve" ]
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stm32u575ag = [ "stm32-metapac/stm32u575ag" ]
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stm32u575ai = [ "stm32-metapac/stm32u575ai" ]
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stm32u575cg = [ "stm32-metapac/stm32u575cg" ]
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@ -1337,6 +1384,32 @@ stm32u585qi = [ "stm32-metapac/stm32u585qi" ]
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stm32u585ri = [ "stm32-metapac/stm32u585ri" ]
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stm32u585vi = [ "stm32-metapac/stm32u585vi" ]
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stm32u585zi = [ "stm32-metapac/stm32u585zi" ]
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stm32u595ai = [ "stm32-metapac/stm32u595ai" ]
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stm32u595aj = [ "stm32-metapac/stm32u595aj" ]
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stm32u595qi = [ "stm32-metapac/stm32u595qi" ]
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stm32u595qj = [ "stm32-metapac/stm32u595qj" ]
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stm32u595ri = [ "stm32-metapac/stm32u595ri" ]
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stm32u595rj = [ "stm32-metapac/stm32u595rj" ]
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stm32u595vi = [ "stm32-metapac/stm32u595vi" ]
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stm32u595vj = [ "stm32-metapac/stm32u595vj" ]
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stm32u595zi = [ "stm32-metapac/stm32u595zi" ]
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stm32u595zj = [ "stm32-metapac/stm32u595zj" ]
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stm32u599bj = [ "stm32-metapac/stm32u599bj" ]
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stm32u599ni = [ "stm32-metapac/stm32u599ni" ]
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stm32u599nj = [ "stm32-metapac/stm32u599nj" ]
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stm32u599vi = [ "stm32-metapac/stm32u599vi" ]
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stm32u599vj = [ "stm32-metapac/stm32u599vj" ]
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stm32u599zi = [ "stm32-metapac/stm32u599zi" ]
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stm32u599zj = [ "stm32-metapac/stm32u599zj" ]
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stm32u5a5aj = [ "stm32-metapac/stm32u5a5aj" ]
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stm32u5a5qj = [ "stm32-metapac/stm32u5a5qj" ]
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stm32u5a5rj = [ "stm32-metapac/stm32u5a5rj" ]
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stm32u5a5vj = [ "stm32-metapac/stm32u5a5vj" ]
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stm32u5a5zj = [ "stm32-metapac/stm32u5a5zj" ]
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stm32u5a9bj = [ "stm32-metapac/stm32u5a9bj" ]
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stm32u5a9nj = [ "stm32-metapac/stm32u5a9nj" ]
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stm32u5a9vj = [ "stm32-metapac/stm32u5a9vj" ]
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stm32u5a9zj = [ "stm32-metapac/stm32u5a9zj" ]
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stm32wb10cc = [ "stm32-metapac/stm32wb10cc" ]
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stm32wb15cc = [ "stm32-metapac/stm32wb15cc" ]
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stm32wb30ce = [ "stm32-metapac/stm32wb30ce" ]
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@ -50,7 +50,7 @@ fn main() {
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// We *shouldn't* have singletons for these, but the HAL currently requires
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// singletons, for using with RccPeripheral to enable/disable clocks to them.
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"rcc" => {
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if r.version.starts_with("h7") || r.version.starts_with("f4") {
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if r.version.starts_with("h5") || r.version.starts_with("h7") || r.version.starts_with("f4") {
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singletons.push("MCO1".to_string());
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singletons.push("MCO2".to_string());
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}
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@ -539,7 +539,10 @@ fn main() {
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// MCO is special
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if pin.signal.starts_with("MCO_") {
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// Supported in H7 only for now
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if regs.version.starts_with("h7") || regs.version.starts_with("f4") {
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if regs.version.starts_with("h5")
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|| regs.version.starts_with("h7")
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|| regs.version.starts_with("f4")
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{
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peri = format_ident!("{}", pin.signal.replace("_", ""));
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} else {
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continue;
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@ -9,7 +9,7 @@ pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
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use super::*;
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::{AnyPin, Speed};
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use crate::pac::{ETH, RCC, SYSCFG};
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use crate::pac::ETH;
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use crate::Peripheral;
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const MTU: usize = 1514; // 14 Ethernet header + 1500 IP packet
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@ -60,16 +60,33 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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unsafe {
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// Enable the necessary Clocks
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// NOTE(unsafe) We have exclusive access to the registers
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#[cfg(not(rcc_h5))]
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critical_section::with(|_| {
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RCC.apb4enr().modify(|w| w.set_syscfgen(true));
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RCC.ahb1enr().modify(|w| {
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crate::pac::RCC.apb4enr().modify(|w| w.set_syscfgen(true));
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crate::pac::RCC.ahb1enr().modify(|w| {
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w.set_eth1macen(true);
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w.set_eth1txen(true);
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w.set_eth1rxen(true);
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});
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// RMII
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SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
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crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
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});
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#[cfg(rcc_h5)]
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critical_section::with(|_| {
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crate::pac::RCC.apb3enr().modify(|w| w.set_sbsen(true));
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crate::pac::RCC.ahb1enr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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// RMII
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crate::pac::SBS
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.pmcr()
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.modify(|w| w.set_eth_sel_phy(crate::pac::sbs::vals::EthSelPhy::B_0X4));
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});
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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@ -25,11 +25,11 @@ fn cpu_regs() -> pac::exti::Exti {
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EXTI
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}
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, gpio_v1, exti_u5)))]
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50)))]
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fn exticr_regs() -> pac::syscfg::Syscfg {
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pac::SYSCFG
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}
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
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fn exticr_regs() -> pac::exti::Exti {
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EXTI
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}
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@ -39,9 +39,9 @@ fn exticr_regs() -> pac::afio::Afio {
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}
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pub unsafe fn on_irq() {
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
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let bits = EXTI.pr(0).read().0;
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
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let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
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// Mask all the channels that fired.
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@ -53,9 +53,9 @@ pub unsafe fn on_irq() {
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}
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// Clear pending
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
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EXTI.pr(0).write_value(Lines(bits));
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
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{
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EXTI.rpr(0).write_value(Lines(bits));
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EXTI.fpr(0).write_value(Lines(bits));
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@ -213,9 +213,9 @@ impl<'a> ExtiInputFuture<'a> {
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EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
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// clear pending bit
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
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#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
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EXTI.pr(0).write(|w| w.set_line(pin, true));
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
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#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
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{
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EXTI.rpr(0).write(|w| w.set_line(pin, true));
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EXTI.fpr(0).write(|w| w.set_line(pin, true));
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@ -364,7 +364,7 @@ pub(crate) unsafe fn init() {
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foreach_exti_irq!(enable_irq);
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#[cfg(not(any(rcc_wb, rcc_wl5, rcc_wle, stm32f1)))]
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#[cfg(not(any(rcc_wb, rcc_wl5, rcc_wle, stm32f1, exti_h5, exti_h50)))]
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<crate::peripherals::SYSCFG as crate::rcc::sealed::RccPeripheral>::enable();
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#[cfg(stm32f1)]
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<crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable();
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606
embassy-stm32/src/rcc/h5.rs
Normal file
606
embassy-stm32/src/rcc/h5.rs
Normal file
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@ -0,0 +1,606 @@
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use core::marker::PhantomData;
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use stm32_metapac::rcc::vals::{Hpre, Ppre, Timpre};
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use crate::pac::pwr::vals::Vos;
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use crate::pac::rcc::vals::{Hseext, Hsidiv, Mco1, Mco2, Pllrge, Pllsrc, Pllvcosel, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::{peripherals, Peripheral};
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(64_000_000);
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/// CSI speed
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pub const CSI_FREQ: Hertz = Hertz(4_000_000);
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/// HSI48 speed
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pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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const VCO_MIN: u32 = 150_000_000;
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const VCO_MAX: u32 = 420_000_000;
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const VCO_WIDE_MIN: u32 = 128_000_000;
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const VCO_WIDE_MAX: u32 = 560_000_000;
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/// Voltage Scale
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///
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||||
/// Represents the voltage range feeding the CPU core. The maximum core
|
||||
/// clock frequency depends on this value.
|
||||
#[derive(Copy, Clone, PartialEq)]
|
||||
pub enum VoltageScale {
|
||||
/// VOS 0 range VCORE 1.30V - 1.40V
|
||||
Scale0,
|
||||
/// VOS 1 range VCORE 1.15V - 1.26V
|
||||
Scale1,
|
||||
/// VOS 2 range VCORE 1.05V - 1.15V
|
||||
Scale2,
|
||||
/// VOS 3 range VCORE 0.95V - 1.05V
|
||||
Scale3,
|
||||
}
|
||||
|
||||
pub enum HseMode {
|
||||
/// crystal/ceramic oscillator (HSEBYP=0)
|
||||
Oscillator,
|
||||
/// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
|
||||
BypassAnalog,
|
||||
/// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
|
||||
BypassDigital,
|
||||
}
|
||||
|
||||
pub struct Hse {
|
||||
/// HSE frequency.
|
||||
pub freq: Hertz,
|
||||
/// HSE mode.
|
||||
pub mode: HseMode,
|
||||
}
|
||||
|
||||
pub enum Hsi {
|
||||
/// 64Mhz
|
||||
Mhz64,
|
||||
/// 32Mhz (divided by 2)
|
||||
Mhz32,
|
||||
/// 16Mhz (divided by 4)
|
||||
Mhz16,
|
||||
/// 8Mhz (divided by 8)
|
||||
Mhz8,
|
||||
}
|
||||
|
||||
pub enum Sysclk {
|
||||
/// HSI selected as sysclk
|
||||
HSI,
|
||||
/// HSE selected as sysclk
|
||||
HSE,
|
||||
/// CSI selected as sysclk
|
||||
CSI,
|
||||
/// PLL1_P selected as sysclk
|
||||
Pll1P,
|
||||
}
|
||||
|
||||
pub enum PllSource {
|
||||
Hsi,
|
||||
Csi,
|
||||
Hse,
|
||||
}
|
||||
|
||||
pub struct Pll {
|
||||
/// Source clock selection.
|
||||
pub source: PllSource,
|
||||
|
||||
/// PLL pre-divider (DIVM). Must be between 1 and 63.
|
||||
pub prediv: u8,
|
||||
|
||||
/// PLL multiplication factor. Must be between 4 and 512.
|
||||
pub mul: u16,
|
||||
|
||||
/// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
|
||||
/// On PLL1, it must be even (in particular, it cannot be 1.)
|
||||
pub divp: Option<u16>,
|
||||
/// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
|
||||
pub divq: Option<u16>,
|
||||
/// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
|
||||
pub divr: Option<u16>,
|
||||
}
|
||||
|
||||
/// AHB prescaler
|
||||
#[derive(Clone, Copy, PartialEq)]
|
||||
pub enum AHBPrescaler {
|
||||
NotDivided,
|
||||
Div2,
|
||||
Div4,
|
||||
Div8,
|
||||
Div16,
|
||||
Div64,
|
||||
Div128,
|
||||
Div256,
|
||||
Div512,
|
||||
}
|
||||
|
||||
impl AHBPrescaler {
|
||||
fn div(&self, clk: Hertz) -> Hertz {
|
||||
match self {
|
||||
Self::NotDivided => clk,
|
||||
Self::Div2 => clk / 2u32,
|
||||
Self::Div4 => clk / 4u32,
|
||||
Self::Div8 => clk / 8u32,
|
||||
Self::Div16 => clk / 16u32,
|
||||
Self::Div64 => clk / 64u32,
|
||||
Self::Div128 => clk / 128u32,
|
||||
Self::Div256 => clk / 256u32,
|
||||
Self::Div512 => clk / 512u32,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// APB prescaler
|
||||
#[derive(Clone, Copy)]
|
||||
pub enum APBPrescaler {
|
||||
NotDivided,
|
||||
Div2,
|
||||
Div4,
|
||||
Div8,
|
||||
Div16,
|
||||
}
|
||||
|
||||
impl APBPrescaler {
|
||||
fn div(&self, clk: Hertz) -> Hertz {
|
||||
match self {
|
||||
Self::NotDivided => clk,
|
||||
Self::Div2 => clk / 2u32,
|
||||
Self::Div4 => clk / 4u32,
|
||||
Self::Div8 => clk / 8u32,
|
||||
Self::Div16 => clk / 16u32,
|
||||
}
|
||||
}
|
||||
|
||||
fn div_tim(&self, clk: Hertz, tim: TimerPrescaler) -> Hertz {
|
||||
match (tim, self) {
|
||||
// The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a
|
||||
// division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2
|
||||
(TimerPrescaler::DefaultX2, Self::NotDivided) => clk,
|
||||
(TimerPrescaler::DefaultX2, Self::Div2) => clk,
|
||||
(TimerPrescaler::DefaultX2, Self::Div4) => clk / 2u32,
|
||||
(TimerPrescaler::DefaultX2, Self::Div8) => clk / 4u32,
|
||||
(TimerPrescaler::DefaultX2, Self::Div16) => clk / 8u32,
|
||||
// The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2
|
||||
// corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2
|
||||
// this makes NO SENSE and is different than in the H7. Mistake in the RM??
|
||||
(TimerPrescaler::DefaultX4, Self::NotDivided) => clk * 2u32,
|
||||
(TimerPrescaler::DefaultX4, Self::Div2) => clk,
|
||||
(TimerPrescaler::DefaultX4, Self::Div4) => clk / 2u32,
|
||||
(TimerPrescaler::DefaultX4, Self::Div8) => clk / 2u32,
|
||||
(TimerPrescaler::DefaultX4, Self::Div16) => clk / 4u32,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// APB prescaler
|
||||
#[derive(Clone, Copy)]
|
||||
pub enum TimerPrescaler {
|
||||
DefaultX2,
|
||||
DefaultX4,
|
||||
}
|
||||
|
||||
impl From<TimerPrescaler> for Timpre {
|
||||
fn from(value: TimerPrescaler) -> Self {
|
||||
match value {
|
||||
TimerPrescaler::DefaultX2 => Timpre::DEFAULTX2,
|
||||
TimerPrescaler::DefaultX4 => Timpre::DEFAULTX4,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl From<APBPrescaler> for Ppre {
|
||||
fn from(val: APBPrescaler) -> Ppre {
|
||||
match val {
|
||||
APBPrescaler::NotDivided => Ppre::DIV1,
|
||||
APBPrescaler::Div2 => Ppre::DIV2,
|
||||
APBPrescaler::Div4 => Ppre::DIV4,
|
||||
APBPrescaler::Div8 => Ppre::DIV8,
|
||||
APBPrescaler::Div16 => Ppre::DIV16,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl From<AHBPrescaler> for Hpre {
|
||||
fn from(val: AHBPrescaler) -> Hpre {
|
||||
match val {
|
||||
AHBPrescaler::NotDivided => Hpre::DIV1,
|
||||
AHBPrescaler::Div2 => Hpre::DIV2,
|
||||
AHBPrescaler::Div4 => Hpre::DIV4,
|
||||
AHBPrescaler::Div8 => Hpre::DIV8,
|
||||
AHBPrescaler::Div16 => Hpre::DIV16,
|
||||
AHBPrescaler::Div64 => Hpre::DIV64,
|
||||
AHBPrescaler::Div128 => Hpre::DIV128,
|
||||
AHBPrescaler::Div256 => Hpre::DIV256,
|
||||
AHBPrescaler::Div512 => Hpre::DIV512,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Configuration of the core clocks
|
||||
#[non_exhaustive]
|
||||
pub struct Config {
|
||||
pub hsi: Option<Hsi>,
|
||||
pub hse: Option<Hse>,
|
||||
pub csi: bool,
|
||||
pub hsi48: bool,
|
||||
pub sys: Sysclk,
|
||||
|
||||
pub pll1: Option<Pll>,
|
||||
pub pll2: Option<Pll>,
|
||||
#[cfg(rcc_h5)]
|
||||
pub pll3: Option<Pll>,
|
||||
|
||||
pub ahb_pre: AHBPrescaler,
|
||||
pub apb1_pre: APBPrescaler,
|
||||
pub apb2_pre: APBPrescaler,
|
||||
pub apb3_pre: APBPrescaler,
|
||||
pub timer_prescaler: TimerPrescaler,
|
||||
|
||||
pub voltage_scale: VoltageScale,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
hsi: Some(Hsi::Mhz64),
|
||||
hse: None,
|
||||
csi: false,
|
||||
hsi48: false,
|
||||
sys: Sysclk::HSI,
|
||||
pll1: None,
|
||||
pll2: None,
|
||||
#[cfg(rcc_h5)]
|
||||
pll3: None,
|
||||
|
||||
ahb_pre: AHBPrescaler::NotDivided,
|
||||
apb1_pre: APBPrescaler::NotDivided,
|
||||
apb2_pre: APBPrescaler::NotDivided,
|
||||
apb3_pre: APBPrescaler::NotDivided,
|
||||
timer_prescaler: TimerPrescaler::DefaultX2,
|
||||
|
||||
voltage_scale: VoltageScale::Scale3,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
pub trait McoInstance {
|
||||
type Source;
|
||||
unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8);
|
||||
}
|
||||
}
|
||||
|
||||
pub trait McoInstance: sealed::McoInstance + 'static {}
|
||||
|
||||
pin_trait!(McoPin, McoInstance);
|
||||
|
||||
macro_rules! impl_peri {
|
||||
($peri:ident, $source:ident, $set_source:ident, $set_prescaler:ident) => {
|
||||
impl sealed::McoInstance for peripherals::$peri {
|
||||
type Source = $source;
|
||||
|
||||
unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8) {
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.$set_source(source);
|
||||
w.$set_prescaler(prescaler);
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
impl McoInstance for peripherals::$peri {}
|
||||
};
|
||||
}
|
||||
|
||||
impl_peri!(MCO1, Mco1, set_mco1, set_mco1pre);
|
||||
impl_peri!(MCO2, Mco2, set_mco2, set_mco2pre);
|
||||
|
||||
pub struct Mco<'d, T: McoInstance> {
|
||||
phantom: PhantomData<&'d mut T>,
|
||||
}
|
||||
|
||||
impl<'d, T: McoInstance> Mco<'d, T> {
|
||||
pub fn new(
|
||||
_peri: impl Peripheral<P = T> + 'd,
|
||||
_pin: impl Peripheral<P = impl McoPin<T>> + 'd,
|
||||
_source: T::Source,
|
||||
) -> Self {
|
||||
todo!();
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) unsafe fn init(config: Config) {
|
||||
let (vos, max_clk) = match config.voltage_scale {
|
||||
VoltageScale::Scale0 => (Vos::SCALE0, Hertz(250_000_000)),
|
||||
VoltageScale::Scale1 => (Vos::SCALE1, Hertz(200_000_000)),
|
||||
VoltageScale::Scale2 => (Vos::SCALE2, Hertz(150_000_000)),
|
||||
VoltageScale::Scale3 => (Vos::SCALE3, Hertz(100_000_000)),
|
||||
};
|
||||
|
||||
// Configure voltage scale.
|
||||
PWR.voscr().modify(|w| w.set_vos(vos));
|
||||
while !PWR.vossr().read().vosrdy() {}
|
||||
|
||||
// Configure HSI
|
||||
let hsi = match config.hsi {
|
||||
None => {
|
||||
RCC.cr().modify(|w| w.set_hsion(false));
|
||||
None
|
||||
}
|
||||
Some(hsi) => {
|
||||
let (freq, hsidiv) = match hsi {
|
||||
Hsi::Mhz64 => (HSI_FREQ / 1u32, Hsidiv::DIV1),
|
||||
Hsi::Mhz32 => (HSI_FREQ / 2u32, Hsidiv::DIV2),
|
||||
Hsi::Mhz16 => (HSI_FREQ / 4u32, Hsidiv::DIV4),
|
||||
Hsi::Mhz8 => (HSI_FREQ / 8u32, Hsidiv::DIV8),
|
||||
};
|
||||
RCC.cr().modify(|w| {
|
||||
w.set_hsidiv(hsidiv);
|
||||
w.set_hsion(true);
|
||||
});
|
||||
while !RCC.cr().read().hsirdy() {}
|
||||
Some(freq)
|
||||
}
|
||||
};
|
||||
|
||||
// Configure HSE
|
||||
let hse = match config.hse {
|
||||
None => {
|
||||
RCC.cr().modify(|w| w.set_hseon(false));
|
||||
None
|
||||
}
|
||||
Some(hse) => {
|
||||
let (byp, ext) = match hse.mode {
|
||||
HseMode::Oscillator => (false, Hseext::ANALOG),
|
||||
HseMode::BypassAnalog => (true, Hseext::ANALOG),
|
||||
HseMode::BypassDigital => (true, Hseext::DIGITAL),
|
||||
};
|
||||
|
||||
RCC.cr().modify(|w| {
|
||||
w.set_hsebyp(byp);
|
||||
w.set_hseext(ext);
|
||||
});
|
||||
RCC.cr().modify(|w| w.set_hseon(true));
|
||||
while !RCC.cr().read().hserdy() {}
|
||||
Some(hse.freq)
|
||||
}
|
||||
};
|
||||
|
||||
// Configure HSI48.
|
||||
RCC.cr().modify(|w| w.set_hsi48on(config.hsi48));
|
||||
let _hsi48 = match config.hsi48 {
|
||||
false => None,
|
||||
true => {
|
||||
while !RCC.cr().read().hsi48rdy() {}
|
||||
Some(CSI_FREQ)
|
||||
}
|
||||
};
|
||||
|
||||
// Configure CSI.
|
||||
RCC.cr().modify(|w| w.set_csion(config.csi));
|
||||
let csi = match config.csi {
|
||||
false => None,
|
||||
true => {
|
||||
while !RCC.cr().read().csirdy() {}
|
||||
Some(CSI_FREQ)
|
||||
}
|
||||
};
|
||||
|
||||
// Configure PLLs.
|
||||
let pll_input = PllInput { csi, hse, hsi };
|
||||
let pll1 = init_pll(0, config.pll1, &pll_input);
|
||||
let _pll2 = init_pll(1, config.pll2, &pll_input);
|
||||
#[cfg(rcc_h5)]
|
||||
let _pll3 = init_pll(2, config.pll3, &pll_input);
|
||||
|
||||
// Configure sysclk
|
||||
let (sys, sw) = match config.sys {
|
||||
Sysclk::HSI => (unwrap!(hsi), Sw::HSI),
|
||||
Sysclk::HSE => (unwrap!(hse), Sw::HSE),
|
||||
Sysclk::CSI => (unwrap!(csi), Sw::CSI),
|
||||
Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1),
|
||||
};
|
||||
assert!(sys <= max_clk);
|
||||
|
||||
let hclk = config.ahb_pre.div(sys);
|
||||
|
||||
let apb1 = config.apb1_pre.div(hclk);
|
||||
let apb1_tim = config.apb1_pre.div_tim(hclk, config.timer_prescaler);
|
||||
let apb2 = config.apb2_pre.div(hclk);
|
||||
let apb2_tim = config.apb2_pre.div_tim(hclk, config.timer_prescaler);
|
||||
let apb3 = config.apb3_pre.div(hclk);
|
||||
|
||||
flash_setup(hclk, config.voltage_scale);
|
||||
|
||||
// Set hpre
|
||||
let hpre = config.ahb_pre.into();
|
||||
RCC.cfgr2().modify(|w| w.set_hpre(hpre));
|
||||
while RCC.cfgr2().read().hpre() != hpre {}
|
||||
|
||||
// set ppre
|
||||
RCC.cfgr2().modify(|w| {
|
||||
w.set_ppre1(config.apb1_pre.into());
|
||||
w.set_ppre2(config.apb2_pre.into());
|
||||
w.set_ppre3(config.apb3_pre.into());
|
||||
});
|
||||
|
||||
RCC.cfgr().modify(|w| w.set_timpre(config.timer_prescaler.into()));
|
||||
|
||||
RCC.cfgr().modify(|w| w.set_sw(sw));
|
||||
while RCC.cfgr().read().sws() != sw {}
|
||||
|
||||
set_freqs(Clocks {
|
||||
sys,
|
||||
ahb1: hclk,
|
||||
ahb2: hclk,
|
||||
ahb3: hclk,
|
||||
ahb4: hclk,
|
||||
apb1,
|
||||
apb2,
|
||||
apb3,
|
||||
apb1_tim,
|
||||
apb2_tim,
|
||||
adc: None,
|
||||
});
|
||||
}
|
||||
|
||||
struct PllInput {
|
||||
hsi: Option<Hertz>,
|
||||
hse: Option<Hertz>,
|
||||
csi: Option<Hertz>,
|
||||
}
|
||||
|
||||
struct PllOutput {
|
||||
p: Option<Hertz>,
|
||||
#[allow(dead_code)]
|
||||
q: Option<Hertz>,
|
||||
#[allow(dead_code)]
|
||||
r: Option<Hertz>,
|
||||
}
|
||||
|
||||
unsafe fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
|
||||
let Some(config) = config else {
|
||||
// Stop PLL
|
||||
RCC.cr().modify(|w| w.set_pllon(num, false));
|
||||
while RCC.cr().read().pllrdy(num) {}
|
||||
|
||||
// "To save power when PLL1 is not used, the value of PLL1M must be set to 0.""
|
||||
RCC.pllcfgr(num).write(|w| {
|
||||
w.set_divm(0);
|
||||
});
|
||||
|
||||
return PllOutput{
|
||||
p: None,
|
||||
q: None,
|
||||
r: None,
|
||||
}
|
||||
};
|
||||
|
||||
assert!(1 <= config.prediv && config.prediv <= 63);
|
||||
assert!(4 <= config.mul && config.mul <= 512);
|
||||
|
||||
let (in_clk, src) = match config.source {
|
||||
PllSource::Hsi => (unwrap!(input.hsi), Pllsrc::HSI),
|
||||
PllSource::Hse => (unwrap!(input.hse), Pllsrc::HSE),
|
||||
PllSource::Csi => (unwrap!(input.csi), Pllsrc::CSI),
|
||||
};
|
||||
|
||||
let ref_clk = in_clk / config.prediv as u32;
|
||||
|
||||
let ref_range = match ref_clk.0 {
|
||||
..=1_999_999 => Pllrge::RANGE1,
|
||||
..=3_999_999 => Pllrge::RANGE2,
|
||||
..=7_999_999 => Pllrge::RANGE4,
|
||||
..=16_000_000 => Pllrge::RANGE8,
|
||||
x => panic!("pll ref_clk out of range: {} mhz", x),
|
||||
};
|
||||
|
||||
// The smaller range (150 to 420 MHz) must
|
||||
// be chosen when the reference clock frequency is lower than 2 MHz.
|
||||
let wide_allowed = ref_range != Pllrge::RANGE1;
|
||||
|
||||
let vco_clk = ref_clk * config.mul;
|
||||
let vco_range = match vco_clk.0 {
|
||||
VCO_MIN..=VCO_MAX => Pllvcosel::MEDIUMVCO,
|
||||
VCO_WIDE_MIN..=VCO_WIDE_MAX if wide_allowed => Pllvcosel::WIDEVCO,
|
||||
x => panic!("pll vco_clk out of range: {} mhz", x),
|
||||
};
|
||||
|
||||
let p = config.divp.map(|div| {
|
||||
assert!(1 <= div && div <= 128);
|
||||
if num == 0 {
|
||||
// on PLL1, DIVP must be even.
|
||||
assert!(div % 2 == 0);
|
||||
}
|
||||
|
||||
vco_clk / div
|
||||
});
|
||||
let q = config.divq.map(|div| {
|
||||
assert!(1 <= div && div <= 128);
|
||||
vco_clk / div
|
||||
});
|
||||
let r = config.divr.map(|div| {
|
||||
assert!(1 <= div && div <= 128);
|
||||
vco_clk / div
|
||||
});
|
||||
|
||||
RCC.pllcfgr(num).write(|w| {
|
||||
w.set_pllsrc(src);
|
||||
w.set_divm(config.prediv);
|
||||
w.set_pllvcosel(vco_range);
|
||||
w.set_pllrge(ref_range);
|
||||
w.set_pllfracen(false);
|
||||
w.set_pllpen(p.is_some());
|
||||
w.set_pllqen(q.is_some());
|
||||
w.set_pllren(r.is_some());
|
||||
});
|
||||
RCC.plldivr(num).write(|w| {
|
||||
w.set_plln(config.mul - 1);
|
||||
w.set_pllp((config.divp.unwrap_or(1) - 1) as u8);
|
||||
w.set_pllq((config.divq.unwrap_or(1) - 1) as u8);
|
||||
w.set_pllr((config.divr.unwrap_or(1) - 1) as u8);
|
||||
});
|
||||
|
||||
RCC.cr().modify(|w| w.set_pllon(num, true));
|
||||
while !RCC.cr().read().pllrdy(num) {}
|
||||
|
||||
PllOutput { p, q, r }
|
||||
}
|
||||
|
||||
fn flash_setup(clk: Hertz, vos: VoltageScale) {
|
||||
// RM0481 Rev 1, table 37
|
||||
// LATENCY WRHIGHFREQ VOS3 VOS2 VOS1 VOS0
|
||||
// 0 0 0 to 20 MHz 0 to 30 MHz 0 to 34 MHz 0 to 42 MHz
|
||||
// 1 0 20 to 40 MHz 30 to 60 MHz 34 to 68 MHz 42 to 84 MHz
|
||||
// 2 1 40 to 60 MHz 60 to 90 MHz 68 to 102 MHz 84 to 126 MHz
|
||||
// 3 1 60 to 80 MHz 90 to 120 MHz 102 to 136 MHz 126 to 168 MHz
|
||||
// 4 2 80 to 100 MHz 120 to 150 MHz 136 to 170 MHz 168 to 210 MHz
|
||||
// 5 2 170 to 200 MHz 210 to 250 MHz
|
||||
|
||||
// See RM0433 Rev 7 Table 17. FLASH recommended number of wait
|
||||
// states and programming delay
|
||||
let (latency, wrhighfreq) = match (vos, clk.0) {
|
||||
(VoltageScale::Scale0, ..=42_000_000) => (0, 0),
|
||||
(VoltageScale::Scale0, ..=84_000_000) => (1, 0),
|
||||
(VoltageScale::Scale0, ..=126_000_000) => (2, 1),
|
||||
(VoltageScale::Scale0, ..=168_000_000) => (3, 1),
|
||||
(VoltageScale::Scale0, ..=210_000_000) => (4, 2),
|
||||
(VoltageScale::Scale0, ..=250_000_000) => (5, 2),
|
||||
|
||||
(VoltageScale::Scale1, ..=34_000_000) => (0, 0),
|
||||
(VoltageScale::Scale1, ..=68_000_000) => (1, 0),
|
||||
(VoltageScale::Scale1, ..=102_000_000) => (2, 1),
|
||||
(VoltageScale::Scale1, ..=136_000_000) => (3, 1),
|
||||
(VoltageScale::Scale1, ..=170_000_000) => (4, 2),
|
||||
(VoltageScale::Scale1, ..=200_000_000) => (5, 2),
|
||||
|
||||
(VoltageScale::Scale2, ..=30_000_000) => (0, 0),
|
||||
(VoltageScale::Scale2, ..=60_000_000) => (1, 0),
|
||||
(VoltageScale::Scale2, ..=90_000_000) => (2, 1),
|
||||
(VoltageScale::Scale2, ..=120_000_000) => (3, 1),
|
||||
(VoltageScale::Scale2, ..=150_000_000) => (4, 2),
|
||||
|
||||
(VoltageScale::Scale3, ..=20_000_000) => (0, 0),
|
||||
(VoltageScale::Scale3, ..=40_000_000) => (1, 0),
|
||||
(VoltageScale::Scale3, ..=60_000_000) => (2, 1),
|
||||
(VoltageScale::Scale3, ..=80_000_000) => (3, 1),
|
||||
(VoltageScale::Scale3, ..=100_000_000) => (4, 2),
|
||||
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
defmt::debug!("flash: latency={} wrhighfreq={}", latency, wrhighfreq);
|
||||
|
||||
// NOTE(unsafe) Atomic write
|
||||
unsafe {
|
||||
FLASH.acr().write(|w| {
|
||||
w.set_wrhighfreq(wrhighfreq);
|
||||
w.set_latency(latency);
|
||||
});
|
||||
while FLASH.acr().read().latency() != latency {}
|
||||
}
|
||||
}
|
||||
|
|
@ -21,6 +21,7 @@ use crate::time::Hertz;
|
|||
#[cfg_attr(rcc_u5, path = "u5.rs")]
|
||||
#[cfg_attr(rcc_wb, path = "wb.rs")]
|
||||
#[cfg_attr(any(rcc_wl5, rcc_wle), path = "wl.rs")]
|
||||
#[cfg_attr(any(rcc_h5, rcc_h50), path = "h5.rs")]
|
||||
mod _version;
|
||||
pub use _version::*;
|
||||
|
||||
|
|
@ -36,7 +37,7 @@ pub struct Clocks {
|
|||
pub apb2: Hertz,
|
||||
#[cfg(not(any(rcc_c0, rcc_g0)))]
|
||||
pub apb2_tim: Hertz,
|
||||
#[cfg(any(rcc_wl5, rcc_wle, rcc_u5))]
|
||||
#[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_u5))]
|
||||
pub apb3: Hertz,
|
||||
#[cfg(any(rcc_h7, rcc_h7ab))]
|
||||
pub apb4: Hertz,
|
||||
|
|
@ -44,14 +45,16 @@ pub struct Clocks {
|
|||
// AHB
|
||||
pub ahb1: Hertz,
|
||||
#[cfg(any(
|
||||
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb, rcc_wl5, rcc_wle
|
||||
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb,
|
||||
rcc_wl5, rcc_wle
|
||||
))]
|
||||
pub ahb2: Hertz,
|
||||
#[cfg(any(
|
||||
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5, rcc_wle
|
||||
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5,
|
||||
rcc_wle
|
||||
))]
|
||||
pub ahb3: Hertz,
|
||||
#[cfg(any(rcc_h7, rcc_h7ab))]
|
||||
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab))]
|
||||
pub ahb4: Hertz,
|
||||
|
||||
#[cfg(any(rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
|
||||
|
|
@ -60,7 +63,7 @@ pub struct Clocks {
|
|||
#[cfg(stm32f1)]
|
||||
pub adc: Hertz,
|
||||
|
||||
#[cfg(any(rcc_h7, rcc_h7ab))]
|
||||
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab))]
|
||||
pub adc: Option<Hertz>,
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
//! Time units
|
||||
|
||||
use core::ops::{Div, Mul};
|
||||
|
||||
/// Hertz
|
||||
#[derive(PartialEq, PartialOrd, Clone, Copy, Debug, Eq)]
|
||||
#[derive(Eq, PartialEq, Ord, PartialOrd, Clone, Copy, Debug)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub struct Hertz(pub u32);
|
||||
|
||||
|
|
@ -33,3 +35,45 @@ pub fn khz(kilohertz: u32) -> Hertz {
|
|||
pub fn mhz(megahertz: u32) -> Hertz {
|
||||
Hertz::mhz(megahertz)
|
||||
}
|
||||
|
||||
impl Mul<u32> for Hertz {
|
||||
type Output = Hertz;
|
||||
fn mul(self, rhs: u32) -> Self::Output {
|
||||
Hertz(self.0 * rhs)
|
||||
}
|
||||
}
|
||||
|
||||
impl Div<u32> for Hertz {
|
||||
type Output = Hertz;
|
||||
fn div(self, rhs: u32) -> Self::Output {
|
||||
Hertz(self.0 / rhs)
|
||||
}
|
||||
}
|
||||
|
||||
impl Mul<u16> for Hertz {
|
||||
type Output = Hertz;
|
||||
fn mul(self, rhs: u16) -> Self::Output {
|
||||
self * (rhs as u32)
|
||||
}
|
||||
}
|
||||
|
||||
impl Div<u16> for Hertz {
|
||||
type Output = Hertz;
|
||||
fn div(self, rhs: u16) -> Self::Output {
|
||||
self / (rhs as u32)
|
||||
}
|
||||
}
|
||||
|
||||
impl Mul<u8> for Hertz {
|
||||
type Output = Hertz;
|
||||
fn mul(self, rhs: u8) -> Self::Output {
|
||||
self * (rhs as u32)
|
||||
}
|
||||
}
|
||||
|
||||
impl Div<u8> for Hertz {
|
||||
type Output = Hertz;
|
||||
fn div(self, rhs: u8) -> Self::Output {
|
||||
self / (rhs as u32)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -186,6 +186,11 @@ impl<'d, T: Instance> Driver<'d, T> {
|
|||
crate::pac::PWR.cr2().modify(|w| w.set_usv(true));
|
||||
}
|
||||
|
||||
#[cfg(pwr_h5)]
|
||||
unsafe {
|
||||
crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true))
|
||||
}
|
||||
|
||||
unsafe {
|
||||
<T as RccPeripheral>::enable();
|
||||
<T as RccPeripheral>::reset();
|
||||
|
|
|
|||
8
examples/stm32h5/.cargo/config.toml
Normal file
8
examples/stm32h5/.cargo/config.toml
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
[target.thumbv8m.main-none-eabihf]
|
||||
runner = 'probe-rs-cli run --chip STM32H563ZITx'
|
||||
|
||||
[build]
|
||||
target = "thumbv8m.main-none-eabihf"
|
||||
|
||||
[env]
|
||||
DEFMT_LOG = "trace"
|
||||
71
examples/stm32h5/Cargo.toml
Normal file
71
examples/stm32h5/Cargo.toml
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
[package]
|
||||
edition = "2021"
|
||||
name = "embassy-stm32h7-examples"
|
||||
version = "0.1.0"
|
||||
license = "MIT OR Apache-2.0"
|
||||
|
||||
[dependencies]
|
||||
embassy-sync = { version = "0.1.0", path = "../../embassy-sync", features = ["defmt"] }
|
||||
embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
|
||||
embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
|
||||
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h563zi", "time-driver-any", "exti", "unstable-pac", "unstable-traits"] }
|
||||
embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "unstable-traits", "proto-ipv6"] }
|
||||
embedded-io = { version = "0.4.0", features = ["async"] }
|
||||
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
|
||||
|
||||
defmt = "0.3"
|
||||
defmt-rtt = "0.4"
|
||||
|
||||
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
|
||||
cortex-m-rt = "0.7.0"
|
||||
embedded-hal = "0.2.6"
|
||||
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
|
||||
embedded-hal-async = { version = "=0.2.0-alpha.0" }
|
||||
embedded-nal-async = "0.4.0"
|
||||
panic-probe = { version = "0.3", features = ["print-defmt"] }
|
||||
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
|
||||
heapless = { version = "0.7.5", default-features = false }
|
||||
rand_core = "0.6.3"
|
||||
critical-section = "1.1"
|
||||
micromath = "2.0.0"
|
||||
stm32-fmc = "0.2.4"
|
||||
embedded-storage = "0.3.0"
|
||||
static_cell = "1.0"
|
||||
|
||||
# cargo build/run
|
||||
[profile.dev]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = true # <-
|
||||
incremental = false
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = true # <-
|
||||
|
||||
# cargo test
|
||||
[profile.test]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = true # <-
|
||||
incremental = false
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = true # <-
|
||||
|
||||
# cargo build/run --release
|
||||
[profile.release]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = false # <-
|
||||
incremental = false
|
||||
lto = 'fat'
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = false # <-
|
||||
|
||||
# cargo test --release
|
||||
[profile.bench]
|
||||
codegen-units = 1
|
||||
debug = 2
|
||||
debug-assertions = false # <-
|
||||
incremental = false
|
||||
lto = 'fat'
|
||||
opt-level = 3 # <-
|
||||
overflow-checks = false # <-
|
||||
5
examples/stm32h5/build.rs
Normal file
5
examples/stm32h5/build.rs
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
fn main() {
|
||||
println!("cargo:rustc-link-arg-bins=--nmagic");
|
||||
println!("cargo:rustc-link-arg-bins=-Tlink.x");
|
||||
println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
|
||||
}
|
||||
5
examples/stm32h5/memory.x
Normal file
5
examples/stm32h5/memory.x
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
MEMORY
|
||||
{
|
||||
FLASH : ORIGIN = 0x08000000, LENGTH = 0x200000
|
||||
RAM : ORIGIN = 0x20000000, LENGTH = 0x50000
|
||||
}
|
||||
27
examples/stm32h5/src/bin/blinky.rs
Normal file
27
examples/stm32h5/src/bin/blinky.rs
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::gpio::{Level, Output, Speed};
|
||||
use embassy_time::{Duration, Timer};
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let mut led = Output::new(p.PB0, Level::High, Speed::Low);
|
||||
|
||||
loop {
|
||||
info!("high");
|
||||
led.set_high();
|
||||
Timer::after(Duration::from_millis(500)).await;
|
||||
|
||||
info!("low");
|
||||
led.set_low();
|
||||
Timer::after(Duration::from_millis(500)).await;
|
||||
}
|
||||
}
|
||||
27
examples/stm32h5/src/bin/button_exti.rs
Normal file
27
examples/stm32h5/src/bin/button_exti.rs
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::exti::ExtiInput;
|
||||
use embassy_stm32::gpio::{Input, Pull};
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let button = Input::new(p.PC13, Pull::Down);
|
||||
let mut button = ExtiInput::new(button, p.EXTI13);
|
||||
|
||||
info!("Press the USER button...");
|
||||
|
||||
loop {
|
||||
button.wait_for_rising_edge().await;
|
||||
info!("Pressed!");
|
||||
button.wait_for_falling_edge().await;
|
||||
info!("Released!");
|
||||
}
|
||||
}
|
||||
133
examples/stm32h5/src/bin/eth.rs
Normal file
133
examples/stm32h5/src/bin/eth.rs
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_net::tcp::TcpSocket;
|
||||
use embassy_net::{Ipv4Address, Stack, StackResources};
|
||||
use embassy_stm32::eth::generic_smi::GenericSMI;
|
||||
use embassy_stm32::eth::{Ethernet, PacketQueue};
|
||||
use embassy_stm32::peripherals::ETH;
|
||||
use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale};
|
||||
use embassy_stm32::rng::Rng;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::{interrupt, Config};
|
||||
use embassy_time::{Duration, Timer};
|
||||
use embedded_io::asynch::Write;
|
||||
use rand_core::RngCore;
|
||||
use static_cell::StaticCell;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
macro_rules! singleton {
|
||||
($val:expr) => {{
|
||||
type T = impl Sized;
|
||||
static STATIC_CELL: StaticCell<T> = StaticCell::new();
|
||||
let (x,) = STATIC_CELL.init(($val,));
|
||||
x
|
||||
}};
|
||||
}
|
||||
|
||||
type Device = Ethernet<'static, ETH, GenericSMI>;
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn net_task(stack: &'static Stack<Device>) -> ! {
|
||||
stack.run().await
|
||||
}
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(spawner: Spawner) -> ! {
|
||||
let mut config = Config::default();
|
||||
config.rcc.hsi = None;
|
||||
config.rcc.hsi48 = true; // needed for rng
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
mode: HseMode::BypassDigital,
|
||||
});
|
||||
config.rcc.pll1 = Some(Pll {
|
||||
source: PllSource::Hse,
|
||||
prediv: 2,
|
||||
mul: 125,
|
||||
divp: Some(2),
|
||||
divq: Some(2),
|
||||
divr: None,
|
||||
});
|
||||
config.rcc.ahb_pre = AHBPrescaler::NotDivided;
|
||||
config.rcc.apb1_pre = APBPrescaler::NotDivided;
|
||||
config.rcc.apb2_pre = APBPrescaler::NotDivided;
|
||||
config.rcc.apb3_pre = APBPrescaler::NotDivided;
|
||||
config.rcc.sys = Sysclk::Pll1P;
|
||||
config.rcc.voltage_scale = VoltageScale::Scale0;
|
||||
let p = embassy_stm32::init(config);
|
||||
info!("Hello World!");
|
||||
|
||||
// Generate random seed.
|
||||
let mut rng = Rng::new(p.RNG);
|
||||
let mut seed = [0; 8];
|
||||
rng.fill_bytes(&mut seed);
|
||||
let seed = u64::from_le_bytes(seed);
|
||||
|
||||
let eth_int = interrupt::take!(ETH);
|
||||
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
|
||||
|
||||
let device = Ethernet::new(
|
||||
singleton!(PacketQueue::<4, 4>::new()),
|
||||
p.ETH,
|
||||
eth_int,
|
||||
p.PA1,
|
||||
p.PA2,
|
||||
p.PC1,
|
||||
p.PA7,
|
||||
p.PC4,
|
||||
p.PC5,
|
||||
p.PG13,
|
||||
p.PB15,
|
||||
p.PG11,
|
||||
GenericSMI,
|
||||
mac_addr,
|
||||
0,
|
||||
);
|
||||
|
||||
let config = embassy_net::Config::Dhcp(Default::default());
|
||||
//let config = embassy_net::Config::Static(embassy_net::StaticConfig {
|
||||
// address: Ipv4Cidr::new(Ipv4Address::new(10, 42, 0, 61), 24),
|
||||
// dns_servers: Vec::new(),
|
||||
// gateway: Some(Ipv4Address::new(10, 42, 0, 1)),
|
||||
//});
|
||||
|
||||
// Init network stack
|
||||
let stack = &*singleton!(Stack::new(device, config, singleton!(StackResources::<2>::new()), seed));
|
||||
|
||||
// Launch network task
|
||||
unwrap!(spawner.spawn(net_task(&stack)));
|
||||
|
||||
info!("Network task initialized");
|
||||
|
||||
// Then we can use it!
|
||||
let mut rx_buffer = [0; 1024];
|
||||
let mut tx_buffer = [0; 1024];
|
||||
|
||||
loop {
|
||||
let mut socket = TcpSocket::new(&stack, &mut rx_buffer, &mut tx_buffer);
|
||||
|
||||
socket.set_timeout(Some(embassy_net::SmolDuration::from_secs(10)));
|
||||
|
||||
let remote_endpoint = (Ipv4Address::new(10, 42, 0, 1), 8000);
|
||||
info!("connecting...");
|
||||
let r = socket.connect(remote_endpoint).await;
|
||||
if let Err(e) = r {
|
||||
info!("connect error: {:?}", e);
|
||||
Timer::after(Duration::from_secs(3)).await;
|
||||
continue;
|
||||
}
|
||||
info!("connected!");
|
||||
loop {
|
||||
let r = socket.write_all(b"Hello\n").await;
|
||||
if let Err(e) = r {
|
||||
info!("write error: {:?}", e);
|
||||
continue;
|
||||
}
|
||||
Timer::after(Duration::from_secs(1)).await;
|
||||
}
|
||||
}
|
||||
}
|
||||
44
examples/stm32h5/src/bin/i2c.rs
Normal file
44
examples/stm32h5/src/bin/i2c.rs
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::i2c::{Error, I2c, TimeoutI2c};
|
||||
use embassy_stm32::interrupt;
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_time::Duration;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
const ADDRESS: u8 = 0x5F;
|
||||
const WHOAMI: u8 = 0x0F;
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
info!("Hello world!");
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
|
||||
let irq = interrupt::take!(I2C2_EV);
|
||||
let mut i2c = I2c::new(
|
||||
p.I2C2,
|
||||
p.PB10,
|
||||
p.PB11,
|
||||
irq,
|
||||
p.GPDMA1_CH4,
|
||||
p.GPDMA1_CH5,
|
||||
Hertz(100_000),
|
||||
Default::default(),
|
||||
);
|
||||
|
||||
// I2C bus can freeze if SCL line is shorted or due to a broken device that clock stretches for too long.
|
||||
// TimeoutI2c allows recovering from such errors by throwing `Error::Timeout` after a given delay.
|
||||
let mut timeout_i2c = TimeoutI2c::new(&mut i2c, Duration::from_millis(1000));
|
||||
|
||||
let mut data = [0u8; 1];
|
||||
|
||||
match timeout_i2c.blocking_write_read(ADDRESS, &[WHOAMI], &mut data) {
|
||||
Ok(()) => info!("Whoami: {}", data[0]),
|
||||
Err(Error::Timeout) => error!("Operation timed out"),
|
||||
Err(e) => error!("I2c Error: {:?}", e),
|
||||
}
|
||||
}
|
||||
20
examples/stm32h5/src/bin/rng.rs
Normal file
20
examples/stm32h5/src/bin/rng.rs
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::rng::Rng;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let mut rng = Rng::new(p.RNG);
|
||||
|
||||
let mut buf = [0u8; 16];
|
||||
unwrap!(rng.async_fill_bytes(&mut buf).await);
|
||||
info!("random bytes: {:02x}", buf);
|
||||
}
|
||||
43
examples/stm32h5/src/bin/usart.rs
Normal file
43
examples/stm32h5/src/bin/usart.rs
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use defmt::*;
|
||||
use embassy_executor::Executor;
|
||||
use embassy_stm32::dma::NoDma;
|
||||
use embassy_stm32::interrupt;
|
||||
use embassy_stm32::usart::{Config, Uart};
|
||||
use static_cell::StaticCell;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn main_task() {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
|
||||
let config = Config::default();
|
||||
let irq = interrupt::take!(UART7);
|
||||
let mut usart = Uart::new(p.UART7, p.PF6, p.PF7, irq, NoDma, NoDma, config);
|
||||
|
||||
unwrap!(usart.blocking_write(b"Hello Embassy World!\r\n"));
|
||||
info!("wrote Hello, starting echo");
|
||||
|
||||
let mut buf = [0u8; 1];
|
||||
loop {
|
||||
unwrap!(usart.blocking_read(&mut buf));
|
||||
unwrap!(usart.blocking_write(&buf));
|
||||
}
|
||||
}
|
||||
|
||||
static EXECUTOR: StaticCell<Executor> = StaticCell::new();
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
info!("Hello World!");
|
||||
|
||||
let executor = EXECUTOR.init(Executor::new());
|
||||
|
||||
executor.run(|spawner| {
|
||||
unwrap!(spawner.spawn(main_task()));
|
||||
})
|
||||
}
|
||||
46
examples/stm32h5/src/bin/usart_dma.rs
Normal file
46
examples/stm32h5/src/bin/usart_dma.rs
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use core::fmt::Write;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use defmt::*;
|
||||
use embassy_executor::Executor;
|
||||
use embassy_stm32::dma::NoDma;
|
||||
use embassy_stm32::interrupt;
|
||||
use embassy_stm32::usart::{Config, Uart};
|
||||
use heapless::String;
|
||||
use static_cell::StaticCell;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn main_task() {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
|
||||
let config = Config::default();
|
||||
let irq = interrupt::take!(UART7);
|
||||
let mut usart = Uart::new(p.UART7, p.PF6, p.PF7, irq, p.GPDMA1_CH0, NoDma, config);
|
||||
|
||||
for n in 0u32.. {
|
||||
let mut s: String<128> = String::new();
|
||||
core::write!(&mut s, "Hello DMA World {}!\r\n", n).unwrap();
|
||||
|
||||
usart.write(s.as_bytes()).await.ok();
|
||||
|
||||
info!("wrote DMA");
|
||||
}
|
||||
}
|
||||
|
||||
static EXECUTOR: StaticCell<Executor> = StaticCell::new();
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
info!("Hello World!");
|
||||
|
||||
let executor = EXECUTOR.init(Executor::new());
|
||||
|
||||
executor.run(|spawner| {
|
||||
unwrap!(spawner.spawn(main_task()));
|
||||
})
|
||||
}
|
||||
58
examples/stm32h5/src/bin/usart_split.rs
Normal file
58
examples/stm32h5/src/bin/usart_split.rs
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::*;
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::dma::NoDma;
|
||||
use embassy_stm32::interrupt;
|
||||
use embassy_stm32::peripherals::{GPDMA1_CH1, UART7};
|
||||
use embassy_stm32::usart::{Config, Uart, UartRx};
|
||||
use embassy_sync::blocking_mutex::raw::ThreadModeRawMutex;
|
||||
use embassy_sync::channel::Channel;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn writer(mut usart: Uart<'static, UART7, NoDma, NoDma>) {
|
||||
unwrap!(usart.blocking_write(b"Hello Embassy World!\r\n"));
|
||||
info!("wrote Hello, starting echo");
|
||||
|
||||
let mut buf = [0u8; 1];
|
||||
loop {
|
||||
unwrap!(usart.blocking_read(&mut buf));
|
||||
unwrap!(usart.blocking_write(&buf));
|
||||
}
|
||||
}
|
||||
|
||||
static CHANNEL: Channel<ThreadModeRawMutex, [u8; 8], 1> = Channel::new();
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(spawner: Spawner) -> ! {
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
info!("Hello World!");
|
||||
|
||||
let config = Config::default();
|
||||
let irq = interrupt::take!(UART7);
|
||||
let mut usart = Uart::new(p.UART7, p.PF6, p.PF7, irq, p.GPDMA1_CH0, p.GPDMA1_CH1, config);
|
||||
unwrap!(usart.blocking_write(b"Type 8 chars to echo!\r\n"));
|
||||
|
||||
let (mut tx, rx) = usart.split();
|
||||
|
||||
unwrap!(spawner.spawn(reader(rx)));
|
||||
|
||||
loop {
|
||||
let buf = CHANNEL.recv().await;
|
||||
info!("writing...");
|
||||
unwrap!(tx.write(&buf).await);
|
||||
}
|
||||
}
|
||||
|
||||
#[embassy_executor::task]
|
||||
async fn reader(mut rx: UartRx<'static, UART7, GPDMA1_CH1>) {
|
||||
let mut buf = [0; 8];
|
||||
loop {
|
||||
info!("reading...");
|
||||
unwrap!(rx.read(&mut buf).await);
|
||||
CHANNEL.send(buf).await;
|
||||
}
|
||||
}
|
||||
128
examples/stm32h5/src/bin/usb_serial.rs
Normal file
128
examples/stm32h5/src/bin/usb_serial.rs
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
#![no_std]
|
||||
#![no_main]
|
||||
#![feature(type_alias_impl_trait)]
|
||||
|
||||
use defmt::{panic, *};
|
||||
use embassy_executor::Spawner;
|
||||
use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale};
|
||||
use embassy_stm32::time::Hertz;
|
||||
use embassy_stm32::usb::{Driver, Instance};
|
||||
use embassy_stm32::{interrupt, pac, Config};
|
||||
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
|
||||
use embassy_usb::driver::EndpointError;
|
||||
use embassy_usb::Builder;
|
||||
use futures::future::join;
|
||||
use {defmt_rtt as _, panic_probe as _};
|
||||
|
||||
#[embassy_executor::main]
|
||||
async fn main(_spawner: Spawner) {
|
||||
let mut config = Config::default();
|
||||
config.rcc.hsi = None;
|
||||
config.rcc.hsi48 = true; // needed for usb
|
||||
config.rcc.hse = Some(Hse {
|
||||
freq: Hertz(8_000_000),
|
||||
mode: HseMode::BypassDigital,
|
||||
});
|
||||
config.rcc.pll1 = Some(Pll {
|
||||
source: PllSource::Hse,
|
||||
prediv: 2,
|
||||
mul: 125,
|
||||
divp: Some(2), // 250mhz
|
||||
divq: None,
|
||||
divr: None,
|
||||
});
|
||||
config.rcc.ahb_pre = AHBPrescaler::Div2;
|
||||
config.rcc.apb1_pre = APBPrescaler::Div4;
|
||||
config.rcc.apb2_pre = APBPrescaler::Div2;
|
||||
config.rcc.apb3_pre = APBPrescaler::Div4;
|
||||
config.rcc.sys = Sysclk::Pll1P;
|
||||
config.rcc.voltage_scale = VoltageScale::Scale0;
|
||||
let p = embassy_stm32::init(config);
|
||||
|
||||
info!("Hello World!");
|
||||
|
||||
unsafe {
|
||||
pac::RCC.ccipr4().write(|w| {
|
||||
w.set_usbsel(pac::rcc::vals::Usbsel::HSI48);
|
||||
});
|
||||
}
|
||||
|
||||
// Create the driver, from the HAL.
|
||||
let irq = interrupt::take!(USB_DRD_FS);
|
||||
let driver = Driver::new(p.USB, irq, p.PA12, p.PA11);
|
||||
|
||||
// Create embassy-usb Config
|
||||
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
|
||||
config.manufacturer = Some("Embassy");
|
||||
config.product = Some("USB-serial example");
|
||||
config.serial_number = Some("12345678");
|
||||
|
||||
// Required for windows compatiblity.
|
||||
// https://developer.nordicsemi.com/nRF_Connect_SDK/doc/1.9.1/kconfig/CONFIG_CDC_ACM_IAD.html#help
|
||||
config.device_class = 0xEF;
|
||||
config.device_sub_class = 0x02;
|
||||
config.device_protocol = 0x01;
|
||||
config.composite_with_iads = true;
|
||||
|
||||
// Create embassy-usb DeviceBuilder using the driver and config.
|
||||
// It needs some buffers for building the descriptors.
|
||||
let mut device_descriptor = [0; 256];
|
||||
let mut config_descriptor = [0; 256];
|
||||
let mut bos_descriptor = [0; 256];
|
||||
let mut control_buf = [0; 64];
|
||||
|
||||
let mut state = State::new();
|
||||
|
||||
let mut builder = Builder::new(
|
||||
driver,
|
||||
config,
|
||||
&mut device_descriptor,
|
||||
&mut config_descriptor,
|
||||
&mut bos_descriptor,
|
||||
&mut control_buf,
|
||||
);
|
||||
|
||||
// Create classes on the builder.
|
||||
let mut class = CdcAcmClass::new(&mut builder, &mut state, 64);
|
||||
|
||||
// Build the builder.
|
||||
let mut usb = builder.build();
|
||||
|
||||
// Run the USB device.
|
||||
let usb_fut = usb.run();
|
||||
|
||||
// Do stuff with the class!
|
||||
let echo_fut = async {
|
||||
loop {
|
||||
class.wait_connection().await;
|
||||
info!("Connected");
|
||||
let _ = echo(&mut class).await;
|
||||
info!("Disconnected");
|
||||
}
|
||||
};
|
||||
|
||||
// Run everything concurrently.
|
||||
// If we had made everything `'static` above instead, we could do this using separate tasks instead.
|
||||
join(usb_fut, echo_fut).await;
|
||||
}
|
||||
|
||||
struct Disconnected {}
|
||||
|
||||
impl From<EndpointError> for Disconnected {
|
||||
fn from(val: EndpointError) -> Self {
|
||||
match val {
|
||||
EndpointError::BufferOverflow => panic!("Buffer overflow"),
|
||||
EndpointError::Disabled => Disconnected {},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
async fn echo<'d, T: Instance + 'd>(class: &mut CdcAcmClass<'d, Driver<'d, T>>) -> Result<(), Disconnected> {
|
||||
let mut buf = [0; 64];
|
||||
loop {
|
||||
let n = class.read_packet(&mut buf).await?;
|
||||
let data = &buf[..n];
|
||||
info!("data: {:x}", data);
|
||||
class.write_packet(data).await?;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue