From 642465a7da64333b9339283f3b3a14cb04bd349e Mon Sep 17 00:00:00 2001
From: Bruno Bousquet <21108660+brunob45@users.noreply.github.com>
Date: Tue, 28 May 2024 20:20:15 -0400
Subject: [PATCH] add stm32f446 files
---
examples/stm32f4/.cargo/config.toml | 6 +++--
examples/stm32f4/.vscode/launch.json | 33 +++++++++++++++++++++++
examples/stm32f4/.vscode/tasks.json | 21 +++++++++++++++
examples/stm32f4/Cargo.toml | 2 +-
examples/stm32f4/openocd.cfg | 5 ++++
examples/stm32f4/openocd.gdb | 40 ++++++++++++++++++++++++++++
6 files changed, 104 insertions(+), 3 deletions(-)
create mode 100644 examples/stm32f4/.vscode/launch.json
create mode 100644 examples/stm32f4/.vscode/tasks.json
create mode 100644 examples/stm32f4/openocd.cfg
create mode 100644 examples/stm32f4/openocd.gdb
diff --git a/examples/stm32f4/.cargo/config.toml b/examples/stm32f4/.cargo/config.toml
index 16efa8e6f..f5a4af51a 100644
--- a/examples/stm32f4/.cargo/config.toml
+++ b/examples/stm32f4/.cargo/config.toml
@@ -1,9 +1,11 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# replace STM32F429ZITx with your chip as listed in `probe-rs chip list`
-runner = "probe-rs run --chip STM32F429ZITx"
+# runner = "probe-rs run --chip STM32F429ZITx"
+runner = "arm-none-eabi-gdb -q -x openocd.gdb"
[build]
-target = "thumbv7em-none-eabi"
+# target = "thumbv7em-none-eabi"
+target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
[env]
DEFMT_LOG = "trace"
diff --git a/examples/stm32f4/.vscode/launch.json b/examples/stm32f4/.vscode/launch.json
new file mode 100644
index 000000000..59f98070d
--- /dev/null
+++ b/examples/stm32f4/.vscode/launch.json
@@ -0,0 +1,33 @@
+{
+ /*
+ * Requires the Rust Language Server (rust-analyzer) and Cortex-Debug extensions
+ * https://marketplace.visualstudio.com/items?itemName=rust-lang.rust-analyzer
+ * https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug
+ */
+ "version": "0.2.0",
+ "configurations": [
+ {
+ /* Configuration for the STM32F446 Discovery board */
+ "type": "cortex-debug",
+ "request": "launch",
+ "name": "Debug (OpenOCD)",
+ "servertype": "openocd",
+ "cwd": "${workspaceRoot}",
+ "preLaunchTask": "Cargo Build (debug)",
+ "runToEntryPoint": "main",
+ "executable": "./target/thumbv7em-none-eabihf/debug/multiprio",
+ /* Run `cargo build --example itm` and uncomment this line to run itm example */
+ // "executable": "./target/thumbv7em-none-eabihf/debug/examples/itm",
+ "device": "STM32F446RET6",
+ "configFiles": [
+ "interface/stlink.cfg",
+ "target/stm32f4x.cfg"
+ ],
+ "postLaunchCommands": [
+ "monitor arm semihosting enable"
+ ],
+ "postRestartCommands": [],
+ "postResetCommands": [],
+ }
+ ]
+}
\ No newline at end of file
diff --git a/examples/stm32f4/.vscode/tasks.json b/examples/stm32f4/.vscode/tasks.json
new file mode 100644
index 000000000..3cbed84b4
--- /dev/null
+++ b/examples/stm32f4/.vscode/tasks.json
@@ -0,0 +1,21 @@
+{
+ "version": "2.0.0",
+ "tasks": [
+ {
+ "type": "cargo",
+ "command": "build",
+ "problemMatcher": [
+ "$rustc"
+ ],
+ "args": [
+ "--bin",
+ "multiprio"
+ ],
+ "group": {
+ "kind": "build",
+ "isDefault": true
+ },
+ "label": "Cargo Build (debug)",
+ }
+ ]
+}
\ No newline at end of file
diff --git a/examples/stm32f4/Cargo.toml b/examples/stm32f4/Cargo.toml
index 1eb1ae6db..ee7594c95 100644
--- a/examples/stm32f4/Cargo.toml
+++ b/examples/stm32f4/Cargo.toml
@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
[dependencies]
# Change stm32f429zi to your chip name, if necessary.
-embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f429zi", "unstable-pac", "memory-x", "time-driver-any", "exti", "chrono"] }
+embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32f446re", "unstable-pac", "memory-x", "time-driver-any", "exti", "chrono"] }
embassy-sync = { version = "0.5.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.5.0", path = "../../embassy-executor", features = ["task-arena-size-32768", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
embassy-time = { version = "0.3.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
diff --git a/examples/stm32f4/openocd.cfg b/examples/stm32f4/openocd.cfg
new file mode 100644
index 000000000..e41d52b1a
--- /dev/null
+++ b/examples/stm32f4/openocd.cfg
@@ -0,0 +1,5 @@
+# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
+
+source [find interface/stlink.cfg]
+
+source [find target/stm32f4x.cfg]
diff --git a/examples/stm32f4/openocd.gdb b/examples/stm32f4/openocd.gdb
new file mode 100644
index 000000000..7795319fb
--- /dev/null
+++ b/examples/stm32f4/openocd.gdb
@@ -0,0 +1,40 @@
+target extended-remote :3333
+
+# print demangled symbols
+set print asm-demangle on
+
+# set backtrace limit to not have infinite backtrace loops
+set backtrace limit 32
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break HardFault
+break rust_begin_unwind
+# # run the next few lines so the panic message is printed immediately
+# # the number needs to be adjusted for your panic handler
+# commands $bpnum
+# next 4
+# end
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
+load
+
+# start the process but immediately halt the processor
+stepi