diff --git a/embassy-stm32/src/pwr/h7.rs b/embassy-stm32/src/pwr/h7.rs
index b298408a..37b049a8 100644
--- a/embassy-stm32/src/pwr/h7.rs
+++ b/embassy-stm32/src/pwr/h7.rs
@@ -35,11 +35,21 @@ impl Power {
             // RM0433 Rev 7 6.8.4. This is partially enforced by dropping
             // `self` at the end of this method, but of course we cannot
             // know what happened between the previous POR and here.
+            #[cfg(pwr_h7)]
             PWR.cr3().modify(|w| {
                 w.set_scuen(true);
                 w.set_ldoen(true);
                 w.set_bypass(false);
             });
+
+            #[cfg(pwr_h7smps)]
+            PWR.cr3().modify(|w| {
+                // hardcode "Direct SPMS" for now, this is what works on nucleos with the
+                // default solderbridge configuration.
+                w.set_sden(true);
+                w.set_ldoen(false);
+            });
+
             // Validate the supply configuration. If you are stuck here, it is
             // because the voltages on your board do not match those specified
             // in the D3CR.VOS and CR3.SDLEVEL fields. By default after reset
diff --git a/embassy-stm32/src/pwr/mod.rs b/embassy-stm32/src/pwr/mod.rs
index 0fe7030e..5b563d72 100644
--- a/embassy-stm32/src/pwr/mod.rs
+++ b/embassy-stm32/src/pwr/mod.rs
@@ -1,4 +1,4 @@
-#[cfg_attr(pwr_h7, path = "h7.rs")]
+#[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
 mod _version;
 
 pub use _version::*;
diff --git a/stm32-data b/stm32-data
index b10a0dd9..32ca7902 160000
--- a/stm32-data
+++ b/stm32-data
@@ -1 +1 @@
-Subproject commit b10a0dd9101038d9f93402565e9b9675f15c0871
+Subproject commit 32ca79020ec7523fe4c3fcfc02006cb1ea637a19