NaxdyOrg/embassy
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Update u5.rs

Browse source 
Update comments on p and q divider values to correctly describe what the clock outputs are used for.
This commit is contained in:
Tyler 2024-01-03 11:04:48 -06:00 committed by GitHub
parent 31bf127807
commit 727906fa04
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 8 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
embassy-stm32/src/rcc/u5.rs
View file

@ -45,17 +45,15 @@ pub struct PllConfig {
/// The multiplied clock – `source` divided by `m` times `n` – must be between 128 and 544
/// MHz. The upper limit may be lower depending on the `Config { voltage_range }`.
pub n: Plln,
/// The divider for the P output.
///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
/// `Config { voltage_range }`.
/// The divider for the P output.
///
/// The P output is one of several options
/// that can be used to feed the SAI/MDF/ADF Clock mux's.
pub p: Plldiv,
/// The divider for the Q output.
///
/// When used to drive the system clock, `source` divided by `m` times `n` divided by `r`
/// must not exceed 160 MHz. System clocks above 55 MHz require a non-default
/// `Config { voltage_range }`.
/// The divider for the Q output.
///
/// The Q ouput is one of severals options that can be used to feed the 48MHz clocks
/// and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux's.
pub q: Plldiv,
/// The divider for the R output.
///