Merge #1294
1294: Add support for `QSPI` in `stm32` r=Dirbaio a=Mirror0 Implemented with help of Tomasz Grześ <tomasz.grzes@gmail.com>. Tested only on stm32f777zi. Co-authored-by: Mateusz Butkiewicz <mateusz@github.butkiewicz.dev>
This commit is contained in:
bors[bot]
GitHub
commit
754bb802ba
4 changed files with 641 additions and 1 deletions
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@ -427,6 +427,12 @@ fn main() {
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(("sdmmc", "D6"), quote!(crate::sdmmc::D6Pin)),
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(("sdmmc", "D6"), quote!(crate::sdmmc::D7Pin)),
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(("sdmmc", "D8"), quote!(crate::sdmmc::D8Pin)),
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(("quadspi", "BK1_IO0"), quote!(crate::qspi::D0Pin)),
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(("quadspi", "BK1_IO1"), quote!(crate::qspi::D1Pin)),
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(("quadspi", "BK1_IO2"), quote!(crate::qspi::D2Pin)),
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(("quadspi", "BK1_IO3"), quote!(crate::qspi::D3Pin)),
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(("quadspi", "CLK"), quote!(crate::qspi::SckPin)),
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(("quadspi", "BK1_NCS"), quote!(crate::qspi::NSSPin)),
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].into();
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for p in METADATA.peripherals {
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@ -507,6 +513,7 @@ fn main() {
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(("dcmi", "PSSI"), quote!(crate::dcmi::FrameDma)),
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// SDMMCv1 uses the same channel for both directions, so just implement for RX
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(("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
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(("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
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]
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.into();
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@ -48,6 +48,8 @@ pub mod crc;
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))]
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pub mod flash;
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pub mod pwm;
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#[cfg(quadspi)]
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pub mod qspi;
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#[cfg(rng)]
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pub mod rng;
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#[cfg(sdmmc)]
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@ -60,7 +62,6 @@ pub mod usart;
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pub mod usb;
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#[cfg(otg)]
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pub mod usb_otg;
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#[cfg(iwdg)]
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pub mod wdg;
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294
embassy-stm32/src/qspi/enums.rs
Normal file
294
embassy-stm32/src/qspi/enums.rs
Normal file
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@ -0,0 +1,294 @@
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub(crate) enum QspiMode {
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IndirectWrite,
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IndirectRead,
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AutoPolling,
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MemoryMapped,
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}
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impl Into<u8> for QspiMode {
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fn into(self) -> u8 {
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match self {
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QspiMode::IndirectWrite => 0b00,
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QspiMode::IndirectRead => 0b01,
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QspiMode::AutoPolling => 0b10,
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QspiMode::MemoryMapped => 0b11,
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}
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}
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}
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#[allow(dead_code)]
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#[derive(Copy, Clone)]
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pub enum QspiWidth {
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NONE,
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SING,
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DUAL,
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QUAD,
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}
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impl Into<u8> for QspiWidth {
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fn into(self) -> u8 {
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match self {
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QspiWidth::NONE => 0b00,
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QspiWidth::SING => 0b01,
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QspiWidth::DUAL => 0b10,
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QspiWidth::QUAD => 0b11,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum MemorySize {
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_1KiB,
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_2KiB,
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_4KiB,
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_8KiB,
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_16KiB,
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_32KiB,
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_64KiB,
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_128KiB,
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_256KiB,
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_512KiB,
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_1MiB,
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_2MiB,
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_4MiB,
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_8MiB,
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_16MiB,
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_32MiB,
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_64MiB,
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_128MiB,
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_256MiB,
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_512MiB,
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_1GiB,
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_2GiB,
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_4GiB,
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Other(u8),
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}
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impl Into<u8> for MemorySize {
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fn into(self) -> u8 {
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match self {
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MemorySize::_1KiB => 9,
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MemorySize::_2KiB => 10,
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MemorySize::_4KiB => 11,
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MemorySize::_8KiB => 12,
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MemorySize::_16KiB => 13,
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MemorySize::_32KiB => 14,
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MemorySize::_64KiB => 15,
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MemorySize::_128KiB => 16,
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MemorySize::_256KiB => 17,
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MemorySize::_512KiB => 18,
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MemorySize::_1MiB => 19,
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MemorySize::_2MiB => 20,
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MemorySize::_4MiB => 21,
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MemorySize::_8MiB => 22,
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MemorySize::_16MiB => 23,
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MemorySize::_32MiB => 24,
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MemorySize::_64MiB => 25,
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MemorySize::_128MiB => 26,
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MemorySize::_256MiB => 27,
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MemorySize::_512MiB => 28,
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MemorySize::_1GiB => 29,
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MemorySize::_2GiB => 30,
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MemorySize::_4GiB => 31,
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MemorySize::Other(val) => val,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum AddressSize {
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_8Bit,
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_16Bit,
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_24bit,
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_32bit,
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}
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impl Into<u8> for AddressSize {
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fn into(self) -> u8 {
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match self {
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AddressSize::_8Bit => 0b00,
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AddressSize::_16Bit => 0b01,
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AddressSize::_24bit => 0b10,
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AddressSize::_32bit => 0b11,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum ChipSelectHightTime {
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_1Cycle,
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_2Cycle,
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_3Cycle,
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_4Cycle,
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_5Cycle,
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_6Cycle,
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_7Cycle,
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_8Cycle,
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}
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impl Into<u8> for ChipSelectHightTime {
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fn into(self) -> u8 {
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match self {
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ChipSelectHightTime::_1Cycle => 0,
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ChipSelectHightTime::_2Cycle => 1,
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ChipSelectHightTime::_3Cycle => 2,
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ChipSelectHightTime::_4Cycle => 3,
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ChipSelectHightTime::_5Cycle => 4,
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ChipSelectHightTime::_6Cycle => 5,
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ChipSelectHightTime::_7Cycle => 6,
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ChipSelectHightTime::_8Cycle => 7,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum FIFOThresholdLevel {
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_1Bytes,
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_2Bytes,
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_3Bytes,
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_4Bytes,
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_5Bytes,
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_6Bytes,
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_7Bytes,
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_8Bytes,
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_9Bytes,
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_10Bytes,
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_11Bytes,
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_12Bytes,
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_13Bytes,
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_14Bytes,
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_15Bytes,
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_16Bytes,
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_17Bytes,
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_18Bytes,
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_19Bytes,
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_20Bytes,
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_21Bytes,
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_22Bytes,
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_23Bytes,
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_24Bytes,
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_25Bytes,
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_26Bytes,
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_27Bytes,
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_28Bytes,
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_29Bytes,
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_30Bytes,
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_31Bytes,
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_32Bytes,
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}
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impl Into<u8> for FIFOThresholdLevel {
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fn into(self) -> u8 {
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match self {
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FIFOThresholdLevel::_1Bytes => 0,
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FIFOThresholdLevel::_2Bytes => 1,
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FIFOThresholdLevel::_3Bytes => 2,
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FIFOThresholdLevel::_4Bytes => 3,
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FIFOThresholdLevel::_5Bytes => 4,
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FIFOThresholdLevel::_6Bytes => 5,
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FIFOThresholdLevel::_7Bytes => 6,
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FIFOThresholdLevel::_8Bytes => 7,
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FIFOThresholdLevel::_9Bytes => 8,
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FIFOThresholdLevel::_10Bytes => 9,
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FIFOThresholdLevel::_11Bytes => 10,
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FIFOThresholdLevel::_12Bytes => 11,
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FIFOThresholdLevel::_13Bytes => 12,
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FIFOThresholdLevel::_14Bytes => 13,
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FIFOThresholdLevel::_15Bytes => 14,
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FIFOThresholdLevel::_16Bytes => 15,
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FIFOThresholdLevel::_17Bytes => 16,
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FIFOThresholdLevel::_18Bytes => 17,
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FIFOThresholdLevel::_19Bytes => 18,
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FIFOThresholdLevel::_20Bytes => 19,
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FIFOThresholdLevel::_21Bytes => 20,
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FIFOThresholdLevel::_22Bytes => 21,
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FIFOThresholdLevel::_23Bytes => 22,
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FIFOThresholdLevel::_24Bytes => 23,
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FIFOThresholdLevel::_25Bytes => 24,
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FIFOThresholdLevel::_26Bytes => 25,
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FIFOThresholdLevel::_27Bytes => 26,
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FIFOThresholdLevel::_28Bytes => 27,
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FIFOThresholdLevel::_29Bytes => 28,
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FIFOThresholdLevel::_30Bytes => 29,
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FIFOThresholdLevel::_31Bytes => 30,
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FIFOThresholdLevel::_32Bytes => 31,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum DummyCycles {
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_0,
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_1,
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_2,
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_3,
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_4,
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_5,
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_6,
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_7,
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_8,
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_9,
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_10,
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_11,
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_12,
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_13,
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_14,
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_15,
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_16,
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_17,
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_18,
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_19,
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_20,
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_21,
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_22,
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_23,
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_24,
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_25,
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_26,
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_27,
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_28,
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_29,
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_30,
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_31,
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}
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impl Into<u8> for DummyCycles {
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fn into(self) -> u8 {
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match self {
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DummyCycles::_0 => 0,
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DummyCycles::_1 => 1,
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DummyCycles::_2 => 2,
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DummyCycles::_3 => 3,
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DummyCycles::_4 => 4,
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DummyCycles::_5 => 5,
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DummyCycles::_6 => 6,
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DummyCycles::_7 => 7,
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DummyCycles::_8 => 8,
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DummyCycles::_9 => 9,
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DummyCycles::_10 => 10,
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DummyCycles::_11 => 11,
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DummyCycles::_12 => 12,
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DummyCycles::_13 => 13,
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DummyCycles::_14 => 14,
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DummyCycles::_15 => 15,
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DummyCycles::_16 => 16,
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DummyCycles::_17 => 17,
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DummyCycles::_18 => 18,
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DummyCycles::_19 => 19,
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DummyCycles::_20 => 20,
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DummyCycles::_21 => 21,
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DummyCycles::_22 => 22,
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DummyCycles::_23 => 23,
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DummyCycles::_24 => 24,
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DummyCycles::_25 => 25,
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DummyCycles::_26 => 26,
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DummyCycles::_27 => 27,
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DummyCycles::_28 => 28,
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DummyCycles::_29 => 29,
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DummyCycles::_30 => 30,
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DummyCycles::_31 => 31,
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}
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}
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}
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338
embassy-stm32/src/qspi/mod.rs
Normal file
338
embassy-stm32/src/qspi/mod.rs
Normal file
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@ -0,0 +1,338 @@
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#![macro_use]
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pub mod enums;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use enums::*;
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use crate::dma::TransferOptions;
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use crate::gpio::sealed::AFType;
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use crate::gpio::AnyPin;
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use crate::pac::quadspi::Quadspi as Regs;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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pub struct TransferConfig {
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/// Instraction width (IMODE)
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pub iwidth: QspiWidth,
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/// Address width (ADMODE)
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pub awidth: QspiWidth,
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/// Data width (DMODE)
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pub dwidth: QspiWidth,
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/// Instruction Id
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pub instruction: u8,
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/// Flash memory address
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pub address: Option<u32>,
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/// Number of dummy cycles (DCYC)
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pub dummy: DummyCycles,
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/// Length of data
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pub data_len: Option<usize>,
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}
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impl Default for TransferConfig {
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fn default() -> Self {
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Self {
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iwidth: QspiWidth::NONE,
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awidth: QspiWidth::NONE,
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dwidth: QspiWidth::NONE,
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instruction: 0,
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address: None,
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dummy: DummyCycles::_0,
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data_len: None,
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}
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}
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}
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pub struct Config {
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/// Flash memory size representend as 2^[0-32], as reasonable minimum 1KiB(9) was chosen.
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/// If you need other value the whose predefined use `Other` variant.
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pub memory_size: MemorySize,
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/// Address size (8/16/24/32-bit)
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pub address_size: AddressSize,
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/// Scalar factor for generating CLK [0-255]
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pub prescaler: u8,
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/// Number of bytes to trigger FIFO threshold flag.
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pub fifo_threshold: FIFOThresholdLevel,
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/// Minimum number of cycles that chip select must be high between issued commands
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pub cs_high_time: ChipSelectHightTime,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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memory_size: MemorySize::Other(0),
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address_size: AddressSize::_24bit,
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prescaler: 128,
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fifo_threshold: FIFOThresholdLevel::_17Bytes,
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cs_high_time: ChipSelectHightTime::_5Cycle,
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}
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}
|
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}
|
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#[allow(dead_code)]
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pub struct Qspi<'d, T: Instance, Dma> {
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_peri: PeripheralRef<'d, T>,
|
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sck: Option<PeripheralRef<'d, AnyPin>>,
|
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d0: Option<PeripheralRef<'d, AnyPin>>,
|
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d1: Option<PeripheralRef<'d, AnyPin>>,
|
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d2: Option<PeripheralRef<'d, AnyPin>>,
|
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d3: Option<PeripheralRef<'d, AnyPin>>,
|
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nss: Option<PeripheralRef<'d, AnyPin>>,
|
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dma: PeripheralRef<'d, Dma>,
|
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config: Config,
|
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}
|
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|
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impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
|
||||
pub fn new(
|
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peri: impl Peripheral<P = T> + 'd,
|
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
|
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
|
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
|
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
|
||||
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
config: Config,
|
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) -> Self {
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into_ref!(peri, d0, d1, d2, d3, sck, nss);
|
||||
|
||||
unsafe {
|
||||
sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
|
||||
sck.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
nss.set_as_af(nss.af_num(), AFType::OutputPushPull);
|
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nss.set_speed(crate::gpio::Speed::VeryHigh);
|
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d0.set_as_af(d0.af_num(), AFType::OutputPushPull);
|
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d0.set_speed(crate::gpio::Speed::VeryHigh);
|
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d1.set_as_af(d1.af_num(), AFType::OutputPushPull);
|
||||
d1.set_speed(crate::gpio::Speed::VeryHigh);
|
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d2.set_as_af(d2.af_num(), AFType::OutputPushPull);
|
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d2.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d3.set_as_af(d3.af_num(), AFType::OutputPushPull);
|
||||
d3.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
}
|
||||
|
||||
Self::new_inner(
|
||||
peri,
|
||||
Some(d0.map_into()),
|
||||
Some(d1.map_into()),
|
||||
Some(d2.map_into()),
|
||||
Some(d3.map_into()),
|
||||
Some(sck.map_into()),
|
||||
Some(nss.map_into()),
|
||||
dma,
|
||||
config,
|
||||
)
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
d0: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d1: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d2: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d3: Option<PeripheralRef<'d, AnyPin>>,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
nss: Option<PeripheralRef<'d, AnyPin>>,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, dma);
|
||||
|
||||
T::enable();
|
||||
unsafe {
|
||||
T::REGS.cr().write(|w| w.set_fthres(config.fifo_threshold.into()));
|
||||
|
||||
while T::REGS.sr().read().busy() {}
|
||||
|
||||
T::REGS.cr().write(|w| {
|
||||
w.set_prescaler(config.prescaler);
|
||||
w.set_en(true);
|
||||
});
|
||||
T::REGS.dcr().write(|w| {
|
||||
w.set_fsize(config.memory_size.into());
|
||||
w.set_csht(config.cs_high_time.into());
|
||||
w.set_ckmode(false);
|
||||
});
|
||||
}
|
||||
|
||||
Self {
|
||||
_peri: peri,
|
||||
sck,
|
||||
d0,
|
||||
d1,
|
||||
d2,
|
||||
d3,
|
||||
nss,
|
||||
dma,
|
||||
config,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn command(&mut self, transaction: TransferConfig) {
|
||||
unsafe {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
}
|
||||
|
||||
pub fn blocking_read(&mut self, buf: &mut [u8], transaction: TransferConfig) {
|
||||
unsafe {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
let current_ar = T::REGS.ar().read().address();
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectRead.into());
|
||||
});
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(current_ar);
|
||||
});
|
||||
|
||||
for idx in 0..len {
|
||||
while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
|
||||
buf[idx] = *(T::REGS.dr().ptr() as *mut u8);
|
||||
}
|
||||
}
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
}
|
||||
|
||||
pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) {
|
||||
unsafe {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectWrite.into());
|
||||
});
|
||||
|
||||
for idx in 0..len {
|
||||
while !T::REGS.sr().read().ftf() {}
|
||||
*(T::REGS.dr().ptr() as *mut u8) = buf[idx];
|
||||
}
|
||||
}
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
}
|
||||
|
||||
pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig)
|
||||
where
|
||||
Dma: QuadDma<T>,
|
||||
{
|
||||
unsafe {
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
let request = self.dma.request();
|
||||
let options = TransferOptions::default();
|
||||
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectRead.into());
|
||||
});
|
||||
let current_ar = T::REGS.ar().read().address();
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(current_ar);
|
||||
});
|
||||
|
||||
self.dma
|
||||
.start_read(request, T::REGS.dr().ptr() as *mut u8, buf, options);
|
||||
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(true));
|
||||
|
||||
while self.dma.is_running() {}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig)
|
||||
where
|
||||
Dma: QuadDma<T>,
|
||||
{
|
||||
unsafe {
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
let request = self.dma.request();
|
||||
let options = TransferOptions::default();
|
||||
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectWrite.into());
|
||||
});
|
||||
|
||||
self.dma
|
||||
.start_write(request, buf, T::REGS.dr().ptr() as *mut u8, options);
|
||||
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(true));
|
||||
|
||||
while self.dma.is_running() {}
|
||||
}
|
||||
}
|
||||
|
||||
fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig) {
|
||||
unsafe {
|
||||
T::REGS.fcr().modify(|v| {
|
||||
v.set_csmf(true);
|
||||
v.set_ctcf(true);
|
||||
v.set_ctef(true);
|
||||
v.set_ctof(true);
|
||||
});
|
||||
|
||||
while T::REGS.sr().read().busy() {}
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
T::REGS.dlr().write(|v| v.set_dl(len as u32 - 1));
|
||||
}
|
||||
|
||||
T::REGS.ccr().write(|v| {
|
||||
v.set_fmode(fmode.into());
|
||||
v.set_imode(transaction.iwidth.into());
|
||||
v.set_instruction(transaction.instruction);
|
||||
v.set_admode(transaction.awidth.into());
|
||||
v.set_adsize(self.config.address_size.into());
|
||||
v.set_dmode(transaction.dwidth.into());
|
||||
v.set_abmode(QspiWidth::NONE.into());
|
||||
v.set_dcyc(transaction.dummy.into());
|
||||
});
|
||||
|
||||
if let Some(addr) = transaction.address {
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(addr);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use super::*;
|
||||
|
||||
pub trait Instance {
|
||||
const REGS: Regs;
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Instance: Peripheral<P = Self> + sealed::Instance + RccPeripheral {}
|
||||
|
||||
pin_trait!(SckPin, Instance);
|
||||
pin_trait!(D0Pin, Instance);
|
||||
pin_trait!(D1Pin, Instance);
|
||||
pin_trait!(D2Pin, Instance);
|
||||
pin_trait!(D3Pin, Instance);
|
||||
pin_trait!(NSSPin, Instance);
|
||||
|
||||
dma_trait!(QuadDma, Instance);
|
||||
|
||||
foreach_peripheral!(
|
||||
(quadspi, $inst:ident) => {
|
||||
impl sealed::Instance for peripherals::$inst {
|
||||
const REGS: Regs = crate::pac::$inst;
|
||||
}
|
||||
|
||||
impl Instance for peripherals::$inst {}
|
||||
};
|
||||
);
|
||||
Loading…
Reference in a new issue